ARMv8.2 adds new instructions AT S1E1RP and AT S1E1WP to Aarch64. This
patch adds support for the instructions, making them available when
-march=armv8.2-a is selected.
gas/testsuite/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/sysreg-2.d: Update for new tests for AT S1E1RP and
AT S1E1WP.
* gas/aarch64/sysreg-2.s: Add tests for AT S1E1RP and AT S1E1WP.
opcodes/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-opc.c (aarch64_sys_regs_at): Add "s1e1rp" and "s1e1wp".
(aarch64_sys_ins_reg_supported_p): Add ARMv8.2 system register
feature test for "s1e1rp" and "s1e1wp".
Change-Id: I09e1044b629ab0a34b03c423e8d4e71ff92daad4
HP-UX and SGI/IRIX are no longer supported. Remove references
throughout.
AFAICS from the sources, "catch fork" seems to be supported in
multiple Unix systems -- just remove the "only works on xxx" remarks.
Update the list of supported shared library types.
gdb/doc/ChangeLog:
* gdb.texinfo (Threads): Remove mention of SGI.
(Forks): Remove mention of HP-UX.
(Breakpoints): Remove mention of HP-UX.
(Set Watchpoints) <hardware watchpoints>: Don't mention HP-UX.
Reword in terms of architectures.
(Set Catchpoints) <catch exec, catch fork, catch vfork>: Don't
mention supported systems.
(Convenience Vars): Don't mention HP-UX.
(Jumping): Remove mention of HP-UX in comment.
(Files) <shared libraries>: Update supported shared library types
list. Remove mention of HP-UX.
(Native): Remove HP-UX subsection.
(SVR4 Process Information): Remove mention of HP-UX.
I think these references to "spaces" came from the original multi-exec
submission that exposed "symbol spaces" to the user and had a
different UI, and then survived a global find/replace.
gdb/testsuite/ChangeLog:
2015-12-10 Pedro Alves <palves@redhat.com>
* gdb.multi/base.exp: Remove stale "spaces" references.
ARMv8.2 adds the new system instruction DC CVAP. This patch adds support
for the instruction to binutils, enabled when -march=armv8.2-a is
selected.
gas/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* config/tc-aarch64.c (parse_sys_ins_reg): Add check of
architectural support for system register.
gas/testsuite/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/sysreg-2.d: Add tests for dc instruction.
* gas/aarch64/sysreg-2.s: Add uses of dc instruction.
include/opcode/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* aarch64.h (aarch64_sys_ins_reg_supported_p): Declare.
opcodes/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap".
(aarch64_sys_ins_reg_supported_p): New.
Change-Id: I3158b97d9bbee9644c2d0e2986db807412ef1053
ARMv8.2 adds the new system instruction DC CVAP. This patch series adds
support for this instruction to binutils, enabled when -march=armv8.2-a
is selected.
The AArch64 binutils record of some system registers uses a boolean
value to hold the single flag currently supported for them. To allow
these registers to be limited to specific architectures, the first patch
in this series replaces the boolean flag with a bitset and feature test.
include/opcode/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* aarch64.h (aarch64_sys_ins_reg): Replace has_xt with flags.
(aarch64_sys_ins_reg_has_xt): Declare.
opcodes/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt
with aarch64_sys_ins_reg_has_xt.
(aarch64_ext_sysins_op): Likewise.
* aarch64-opc.c (operand_general_constraint_met_p): Likewise.
(F_HASXT): New.
(aarch64_sys_regs_ic): Update for changes to aarch64_sys_ins_reg.
(aarch64_sys_regs_dc): Likewise.
(aarch64_sys_regs_at): Likewise.
(aarch64_sys_regs_tlbi): Likewise.
(aarch64_sys_ins_reg_has_xt): New.
Change-Id: I363637a6c3f54d7ffff953b3a0734e8139cae819
Several of the gdb.multi tests use the "nowarnings" option to suppress
warnings. The warnings in question all come from missing headers,
like e.g.:
src/gdb/testsuite/gdb.multi/multi-arch-exec.c:28:3: warning: incompatible implicit declaration of built-in function 'exit' [enabled by default]
exit (1);
^
There's no point in trying to avoid to include standard headers. In
gdb.base/hangout.c's case, it's even dangerous, as that file calls
printf. In order to compile a call to a variatic function correctly,
a declaration must be visible.
gdb/testsuite/ChangeLog:
2015-12-10 Pedro Alves <palves@redhat.com>
* gdb.multi/base.exp: Don't use nowarnings.
* gdb.multi/bkpt-multi-exec.exp: Don't use nowarnings.
* gdb.multi/hangout.c: Include stdio.h.
* gdb.multi/hello.c: Include stdlib.h.
* gdb.multi/multi-arch-exec.c: Include stdlib.h.
* gdb.multi/multi-arch-exec.exp: Don't use nowarnings.
* gdb.multi/multi-arch.exp: Don't use nowarnings.
When creating a dummy BFD for an IR file, the output BFD is used as
a template for the new BFD, when it needs to be the input BFD passed
into the function when not dealing with a BFD plugin.
On most targets this is not an issue as the input and output formats
are the same anyway, but on MinGW targets, there are two variant
formats used (pe-i386/pe-x86-64 and pei-i386/pei-x86-64) which are
similar but not interchangeable here.
PR ld/18199
* plugin.c (plugin_get_ir_dummy_bfd): Use srctemplate as the
template when calling bfd_create if it does not use the BFD
plugin target vector.
ARMv8.2 adds a new control bit PSTATE.UAO. This patch adds support for
this bit to binutils, following the same basic pattern as for
PSTATE.PAN. The new control bit is only available when -march=armv8.2-a
is specified.
gas/testsuite/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/uao-directive.d: New.
* gas/aarch64/uao.d: New.
* gas/aarch64/uao.s: New.
opcodes/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-opc.c (aarch64_sys_regs): Add "uao".
(aarch64_sys_reg_supported_p): Add comment. Add checks for "uao".
(aarch64_pstatefields): Add "uao".
(aarch64_pstatefield_supported_p): Add checks for "uao".
Change-Id: Id571628ac5227b78aaf1876e85d15d7b6c0a2896
gas/ChangeLog:
2015-12-10 Jose E. Marchesi <jose.marchesi@oracle.com>
* doc/c-sparc.texi (Sparc-Regs): Document the %dN and %qN notation
for floating-point registers.
Before, on systems that did not support PTRACE_EVENT_CLONE, both GDB and
GDBServer coordinated with libthread_db.so to insert breakpoints at magic
locations in libpthread.so, in order to break at thread creation and
thread death.
Support for thread events was removed from GDBServer as patch:
https://sourceware.org/ml/gdb-patches/2015-11/msg00466.html
This patch removes support for thread events in GDB.
No regressions found on Ubuntu 14.04 x86_64.
gdb/ChangeLog:
* breakpoint.c (remove_thread_event_breakpoints): Remove.
* breakpoint.h (remove_thread_event_breakpoints): Remove
declaration.
* linux-nat.c (in_pid_list_p): Remove.
(lin_lwp_attach_lwp): Remove.
* linux-nat.h (lin_lwp_attach_lwp): Remove declaration.
* linux-thread-db.c (thread_db_use_events): Remove.
(struct thread_db_info) <td_create_bp_addr>: Remove.
<td_death_bp_addr>: Likewise.
<td_ta_event_addr_p>: Likewise.
<td_ta_set_event_p>: Likewise.
<td_ta_clear_event_p>: Likewise.
<td_ta_event_getmsg_p>: Likewise.
<td_thr_event_enable_p>: Likewise.
(attach_thread): Likewise.
(detach_thread): Likewise.
(have_threads_callback): Likewise.
(have_threads): Likewise.
(enable_thread_event): Likewise.
(enable_thread_event_reporting): Likewise.
(try_thread_db_load_1): Remove td_ta_event_addr, td_ta_set_event,
td_ta_clear_event, td_ta_event_getmsg, td_thr_event_enable
initializations.
(try_thread_db_load_1): Remove enable_thread_event_reporting call.
(disable_thread_event_reporting): Remove.
(record_thread): Adapt to thread_db_use_event removal.
(detach_thread): Remove.
(thread_db_detach): Adapt to thread_db_use_event removal.
(check_event): Remove.
(thread_db_wait): Adapt to thread events support removal.
(thread_db_mourn_inferior): Likewise.
(find_new_threads_callback): Likewise.
(find_new_threads_once): Likewise.
(thread_db_update_thread_list): Likewise.
The ARMv8.2 RAS extension adds a number of new registers. This patch
adds the registers and makes them available whenever the RAS extension
is enabled, as it is when -march=armv8.2-a is selected.
The new registers are:
erridr_el1, errselr_el1, erxfr_el1, erxctlr, erxaddr_el1,
erxmisc0_el1, erxmisc1_el1, vsesr_el2, disr_el1 and
vdisr_el2.
gas/testsuite/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/sysreg-2.d: Add tests for new registers.
* gas/aarch64/sysreg-2.s: Likewise. Also replace some spaces with
tabs.
opcodes/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-opc.c (aarch64_sys_regs): Add "vsesr_el2", "erridr_el1",
"errselr_el1", "erxfr_el1", "erxctlr", "erxaddr_el1",
"erxmisc0_el1", "erxmisc1_el1", "disr_el1" and "vdisr_el2".
(aarch64_sys_reg_supported_p): Add architecture feature tests for
new registers.
Change-Id: I8a01a0f0ee7987f89eead32650f6afcc749b3c74
The ARMv8.2 RAS extension adds a new barrier instruction ESB as an alias
and the preferred form of HINT 16.
This patch adds an architectural feature flag for the RAS extension and
includes it in the features selected enabled by -march=armv8.2-a. It
also adds the ESB instruction, making it available whenever the RAS
feature is enabled.
Because ESB is the preferred form and because the target architecture
isn't available to the disassembler, HINT 16 will be disassembled as ESB
even when the target has no support for the RAS extension.
gas/testsuite/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/system-2.d: New.
* gas/aarch64/system-2.s: New.
* gas/aarch64/system.d: Adjust expected output for HINT 16.
include/opcode/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* aarch64.h (AARCH64_FEATURE_RAS): New.
(AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_RAS.
opcodes/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-tbl.h (aarch64_feature_ras): New.
(RAS): New.
(aarch64_opcode_table): Add "esb".
Change-Id: Id4713917da15cca3b977284f43febd1c9b3d9faf
ARMv8.1 includes CRC as a required extension but this isn't reflected in
the features enabled by -march=armv8.1-a. The FP16 feature modifier also
clashes with AARCH64_FEATURE_V8_1 and the list of features for ARMv8.2
is missing ARMv8.1 features.
This patch enables +crc for -march values of armv8.1-a and later. It
also fixes the values for AARCH64_FEATURE_F16 and makes
AARCH64_ARCH_V8_2 and superset of AARCH64_ARCH_V8_2.
gas/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* doc/c-aarch64.texi (AArch64 Extensions): Update entry for crc.
include/opcode
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* aarch64.h (AARCH64_FEATURE_F16): Fix clash with
AARCH64_FEATURE_V8_1.
(AARCH64_ARCH_V8_1): Add AARCH64_FEATURE_CRC.
(AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_CRC and
AARCH64_FEATURE_V8_1.
Change-Id: I8af5369f6df2430b28f6cec92870d2a4d14a7431
Commit fc58fa65d4 (gdb/doc: Restructure frame command documentation)
reordered the sections in the 'Examining the Stack' chapter, but
missed updating the menu:
src/gdb/doc/gdb.texinfo:6968: warning: node next `Backtrace' in menu `Frame Filter Management' and in sectioning `Selection' differ
src/gdb/doc/gdb.texinfo:7167: warning: node prev `Selection' in menu `Frame Filter Management' and in sectioning `Backtrace' differ
src/gdb/doc/gdb.texinfo:7252: warning: node `Frame Filter Management' is next for `Frame Info' in sectioning but not in menu
src/gdb/doc/gdb.texinfo:7317: warning: node `Selection' is next for `Frame Filter Management' in menu but not in sectioning
src/gdb/doc/gdb.texinfo:7317: warning: node prev `Frame Filter Management' in menu `Backtrace' and in sectioning `Frame Info' differ
gdb/doc/ChangeLog:
2015-12-10 Pedro Alves <palves@redhat.com>
* gdb.texinfo (Stack): Reorder menu.
It is possible to use multiple base addresses within a single address
range series, within the .debug_ranges section. The following is a
simplified example for 32-bit addresses:
.section ".debug_ranges"
.4byte 0xffffffff
.4byte BASE_1
.4byte START_OFFSET_1
.4byte END_OFFSET_1
.4byte START_OFFSET_2
.4byte END_OFFSET_2
.4byte 0xffffffff
.4byte BASE_2
.4byte START_OFFSET_3
.4byte END_OFFSET_3
.4byte 0
.4byte 0
In this example START/END 1 and 2 are relative to BASE_1, while
START/END 3 are relative to BASE_2.
Currently gdb does not correctly parse this DWARF, resulting in
corrupted address range information. This commit fixes this issue, and
adds a new test to cover this case.
In order to support testing of this feature extensions were made to the
testsuite dwarf assembler, additional functionality was added to the
.debug_line generation function, and a new function for generating the
.debug_ranges section was added.
gdb/ChangeLog:
* dwarf2read.c (dwarf2_ranges_read): Unify and fix base address
reading code.
gdb/testsuite/ChangeLog:
* gdb.dwarf2/dw2-ranges-base.c: New file.
* gdb.dwarf2/dw2-ranges-base.exp: New file.
* lib/dwarf.exp (namespace eval Dwarf): Add new variables to
support additional line table, and debug ranges generation.
(Dwarf::ranges): New function, generate .debug_ranges.
(Dwarf::lines): Support generating simple line table programs.
(Dwarf::assemble): Initialise new namespace variables.
There's a set of legacy command line arguments that the arc assembler
still accepts, however, these arguments not longer have any effect on
the assembler.
Currently we return false from md_parse_option for all of these
arguments, with the result that the assembler terminates with an error
message.
We should return true indicating that the argument has been accepted,
even though we ignore it.
gas/ChangeLog:
* config/tc-arc.c (md_parse_option): Return 1 in order to accept
dummy arguments.
This patch fixes the following failures for rl78-elf:
FAIL: gdb.base/vla-datatypes.exp: print int_vla
FAIL: gdb.base/vla-datatypes.exp: print unsigned_int_vla
FAIL: gdb.base/vla-datatypes.exp: print double_vla
FAIL: gdb.base/vla-datatypes.exp: print float_vla
FAIL: gdb.base/vla-datatypes.exp: print long_vla
FAIL: gdb.base/vla-datatypes.exp: print unsigned_long_vla
FAIL: gdb.base/vla-datatypes.exp: print char_vla
FAIL: gdb.base/vla-datatypes.exp: print short_vla
FAIL: gdb.base/vla-datatypes.exp: print unsigned_short_vla
FAIL: gdb.base/vla-datatypes.exp: print unsigned_char_vla
FAIL: gdb.base/vla-datatypes.exp: print foo_vla
FAIL: gdb.base/vla-datatypes.exp: print bar_vla
FAIL: gdb.base/vla-datatypes.exp: print vla_struct_object
FAIL: gdb.base/vla-datatypes.exp: print vla_union_object
FAIL: gdb.base/vla-ptr.exp: print td_vla
FAIL: gdb.mi/mi-vla-c99.exp: evaluate complete vla
The first failure in this bunch occurs due to printing an incorrect
result for a variable length array:
print int_vla
$1 = {-1, -1, -1, -1, -1}
The result should actually be this:
$1 = {0, 2, 4, 6, 8}
When I started examining this bug, I found that printing an
individual array element worked correctly. E.g. "print int_vla[2]"
resulted in 4 being printed. I have not looked closely to see why
this is the case.
I found that evaluation of the location expression for int_vla was
causing problems. This is the relevant DWARF entry for int_vla:
<2><15a>: Abbrev Number: 10 (DW_TAG_variable)
<15b> DW_AT_name : (indirect string, offset: 0xbf): int_vla
<15f> DW_AT_decl_file : 1
<160> DW_AT_decl_line : 35
<161> DW_AT_type : <0x393>
<165> DW_AT_location : 4 byte block: 86 7a 94 2 (DW_OP_breg22 (r22): -6; DW_OP_deref_size: 2)
I found that DW_OP_breg22 was providing a correct result.
DW_OP_deref_size was fetching the correct value from memory. However,
the value being fetched should be considered a pointer.
DW_OP_deref_size zero extends the fetched value prior to pushing
it onto the evaluation stack. (The DWARF-4 document specifies this
action; so GDB is faithfully implementing the DWARF-4 specification.)
However, zero extending the pointer is not sufficient for converting
that value to an address for rl78 and (perhaps) other architectures
which define a `pointer_to_address' method. (I suspect that m32c
would have the same problem.)
Ideally, we would perform the pointer to address conversion in
DW_OP_deref_size. We don't, however, know the type of the object
that the address refers to in DW_OP_deref_size. I can't think
of a way to infer the type at that point in the code.
Before proceeding, I should note that there are two other DWARF
operations that could be used in place of DW_OP_deref_size. One of
these is DW_OP_GNU_deref_type. Current GDB implements this operation,
but as is obvious from the name, it is non-standard DWARF. The other
operation is DW_OP_xderef_size. Even though it's part of DWARF-2
through DWARF-4 specifications, it's not presently implemented in GDB.
Present day GCC does not output dwarf expressions containing this
operation either. [Of the two, I like DW_OP_GNU_deref_type better.
Using it avoids the need to specify an "address space identifier".
(GCC, GDB, and other non-free tools all need to agree on the meanings
of these identifiers.)]
Back to the bug analysis...
The closest consumer of the DW_OP_deref_size result is the
DWARF_VALUE_MEMORY case in dwarf2_evaluate_loc_desc_full. At that
location, we do know the object type to which the address is intended
to refer. I added code to perform a pointer to address conversion at
this location. (See the patch.)
I do have some misgivings regarding this patch. As noted earlier, it
would really be better to perform the pointer to address conversion in
DW_OP_deref_size. I can't, however, think of a way to make this work.
Changing GCC to output one of the other aforementioned operations might
be preferable but, as noted earlier, these solutions have problems as
well. Long term, I think it'd be good to have something like
DW_OP_GNU_deref_type become part of the standard. If that can't or
won't happen, we'll need to implement DW_OP_xderef_size.
But until that happens, this patch will work for expressions in which
DW_OP_deref_size occurs last. It should even work for dereferences
followed by adding an offset. I don't think it'll work for more than
one dereference in the same expression.
gdb/ChangeLog:
* dwarf2loc.c (dwarf2_evaluate_loc_desc_full): Perform a pointer
to address conversion for DWARF_VALUE_MEMORY.
This change eliminates some failures on simulator targets and makes
the test run a bit quicker too - without this change, we have to wait
for timeouts.
gdb/testsuite/ChangeLog:
* gdb.base/async.exp (proc test_background): Add case
for asynchronous execution not supported.
This set of patches add support for the zero-padded hexadecimal format for
varobj's, defined as "zero-hexadecimal". We currently only support regular
non-zero-padded hexadecimal.
Talking with IDE developers, they would like to have this option that is
already available to GDB's print/x commands, in the CLI, as 'z'.
gdb/ChangeLog:
2015-12-09 Luis Machado <lgustavo@codesourcery.com>
* gdb/mi/mi-cmd-var.c (mi_parse_format): Handle new "zero-hexadecimal"
format.
* gdb/varobj.c (varobj_format_string): Add "zero-hexadecimal" entry.
(format_code): Add 'z' entry.
(varobj_set_display_format): Handle FORMAT_ZHEXADECIMAL.
* gdb/varobj.h (varobj_display_formats) <FORMAT_ZHEXADECIMAL>: New enum
field.
* NEWS: Add new note to MI changes citing the new zero-hexadecimal
format for -var-set-format.
gdb/doc/ChangeLog:
2015-12-09 Luis Machado <lgustavo@codesourcery.com>
* gdb.texinfo (GDB/MI Variable Objects): Update text to mention
-var-set-format's new zero-hexadecimal format.
gdb/testsuite/ChangeLog:
2015-12-09 Luis Machado <lgustavo@codesourcery.com>
* gdb.mi/mi-var-display.exp: Add new checks for the zero-hexadecimal
format and change test names to make them unique.
The SPARC Refence Manual documents the %dN and %qN syntax to
refer to double and quad-precision floating-point registers,
respectively. See OSA2015 Appendix C, Assembly Language Syntax,
C1.1 Register Names.
This patch adds support for these names to GAS. This eases the
porting of software from Solaris to GNU/Linux, as these register
names have been supported by the Solaris linker for a long time
and many assembler require that support.
gas/ChangeLog:
2015-12-09 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (sparc_ip): Support %dN and %qN notation for
double and quad-precision floating-point registers.
When `info float` is used on an AMD64 system, GDB prints
floating-point values of x87 registers with raw contents like
0x361a867a8e0527397ce0 or 0xc4f988454a1ddd3cfdab wrongly.
This happens due to truncation to double, after which the former
becomes 0.0, and the latter becomes negative infinity. This is caused
by failed detection of x86-64 host, which results in setting
gdb_host_{float,double,long_double}_format to zeros.
This commit fixes this misdetection, and adds a test to make sure
future commits don't introduce a regression here.
gdb/ChangeLog:
2015-12-09 Ruslan Kabatsayev <b7.10110111@gmail.com>
PR gdb/18702
* configure.host: Fix detection of x86_64 host when setting
floatformats.
gdb/testsuite/ChangeLog:
2015-12-09 Ruslan Kabatsayev <b7.10110111@gmail.com>
Pedro Alves <pedro@redhat.com>
PR gdb/18702
Add checking of floatformats setup on x86_64 hosts.
* gdb.arch/i386-float.S (main): Load bigval and smallval.
(smallval, bigval): New labels/constants.
* gdb.arch/i386-float.exp: Use with_test_prefix and test "info
float" after loading bigval and smallval.
In an fixed position executable, the entry code does not need to be
PIC and can thus lose a dependency on r12.
* powerpc.cc (Target_powerpc::Relocate::relocate): Edit ELFv2
entry code.
(Target_powerpc::relocate_relocs): Edit relocs to suit.
Some linker code editing needs to change multiple insns. In some
cases multiple relocations are involved and it is not sufficient to
make the changes independently as relocations are processed, because
doing so might lead to a partial edit. So in order to safely edit we
need all the relocations available in relocate(). Also, to emit
edited relocs corresponding to the edited code sequence we need some
way to pass information from relocate() to relocate_relocs(),
particularly if the edit depends on insns. We can't modify input
relocs in relocate() as they are mmapped PROT_READ, nor it is
particularly clean to write relocs to the output at that stage. So
add a Relocatable_relocs* field to relinfo to mark edited relocs.
Given that relocate is passed the raw reloc pointer, it makes sense to
remove the rel/rela parameter and r_type too. However, that means the
mips relocate() needs to know whether SHT_REL or SHT_RELA relocs are
being processed. So add a rel_type for mips, which also has the
benefit of removing relocate() overloading there.
This patch adds the infrastructure without making use of it.
Note that relinfo->rr will be NULL if not outputting relocations.
* object.h (struct Relocate_info): Add "rr".
* reloc.h (Relocatable_relocs::set_strategy): New accessor.
* reloc.cc (Sized_relobj_file::do_relocate_sections): Init
relinfo.rr for relocate_section and relocate_relocs.
* powerpc.cc (relocate): Add rel_type and preloc parameters.
Delete rela and r_type params, instead recalculate these from
preloc.
(relocate_relocs): Delete Relocatable_relocs* param, instead
use relinfo->rr.
* aarch64.cc: Likewise.
* arm.cc: Likewise.
* i386.cc: Likewise.
* mips.cc: Likewise.
* s390.cc: Likewise.
* sparc.cc: Likewise.
* target.h: Likewise.
* tilegx.cc: Likewise.
* x86_64.cc: Likewise.
* testsuite/testfile.cc: Likewise.
* target-reloc.h (relocate_section): Adjust to suit.
(apply_relocation, relocate_relocs): Likewise.
While not allowed, this certainly shouldn't result in confusing the
programmer (by skipping lines in unexpected ways): Without returning,
demand_empty_rest_of_line() (at the end of the function) will demand
the _next_ line to be empty, and without the conditional we would
ignore the next line.
.file directives may be used to identify the scope of local symbols,
the purpose of which gets subverted when re-ordering them. Only allow
the first of them to be moved to the first position.
gdb/ChangeLog:
* NEWS: Announce this enhancement and the corresponding new
option.
gdb/doc/ChangeLog:
* gdb.texinfo (Ada Mode Into): Move overloading support
description to its own node.
(Overloading support for Ada): New node.
Various fixes to linker relaxation. In general, we need to support
relaxing every branch, even if we don't relax it in the assembler,
so we can optionally defer relaxation to the linker.
* elf32-rl78.c (rl78_offset_for_reloc): Add more relocs.
(rl78_elf_relax_section): Add bc/bz/bnc/bnz/bh/bnh. Fix reloc
choices.
* config/rl78-parse.y: Make all branches relaxable via
rl78_linkrelax_branch().
* config/tc-rl78.c (rl78_linkrelax_branch): Mark all relaxable
branches with relocs.
(options): Add OPTION_NORELAX.
(md_longopts): Add -mnorelax.
(md_parse_option): Support OPTION_NORELAX.
(op_type_T): Add bh, sk, call, and br.
(rl78_opcode_type): Likewise.
(rl78_relax_frag): Fix not-relaxing logic. Add sk.
(md_convert_frag): Fix relocation handling.
(tc_gen_reloc): Strip relax relocs when not linker relaxing.
(md_apply_fix): Defer overflow handling for anything that needs a
PLT, to the linker.
* config/tc-rl78.h (TC_FORCE_RELOCATION): Force all relocations to
the linker when linker relaxing.
* doc/c-rl78.texi (norelax): Add.
In commit 6085d6f6, Z0 packet is disabled in aarch64 GDBserver if
the inferior is 32-bit or there may be multiple inferiors, because
Z0 packet isn't supported for arm then. Recently, Z0 packet
is supported in arm target, so we don't have such limitation in
aarch64 GDBserver, that is to say, aarch64 GDBserver can use Z0
packet in multi-arch/multi-inferior debugging when the inferior's
arch is arm.
Part of this patch is to revert 6085d6f6, and the rest of the patch
is to move some breakpoint related arm_* functions into
linux-aarch32-low.c in order to share them between arm and aarch64.
This patch is regression tested on aarch64-linux for debugging both
aarch64 programs and arm programs respectively.
gdb/gdbserver:
2015-12-07 Yao Qi <yao.qi@linaro.org>
* configure.srv: Append arm.o to srv_tgtobj for
aarch64*-*-linux* target.
* linux-aarch32-low.c (arm_abi_breakpoint): New macro. Moved
from linux-arm-low.c.
(arm_eabi_breakpoint, arm_breakpoint): Likewise.
(arm_breakpoint_len, thumb_breakpoint): Likewise.
(thumb_breakpoint_len, thumb2_breakpoint): Likewise.
(thumb2_breakpoint_len): Likewise.
(arm_is_thumb_mode, arm_breakpoint_at): Likewise.
(arm_breakpoint_kinds): Likewise.
(arm_breakpoint_kind_from_pc): Likewise.
(arm_sw_breakpoint_from_kind): Likewise.
(arm_breakpoint_kind_from_current_state): Likewise.
* linux-aarch32-low.h (arm_breakpoint_kind_from_pc): Declare.
(arm_sw_breakpoint_from_kind): Declare.
(arm_breakpoint_kind_from_current_state): Declare.
(arm_breakpoint_at): Declare.
* linux-aarch64-low.c (aarch64_sw_breakpoint_from_kind): Call
arm_sw_breakpoint_from_kind if process is 32-bit.
(aarch64_breakpoint_kind_from_pc): New function.
(aarch64_breakpoint_kind_from_current_state): New function.
(the_low_target): Initialize fields breakpoint_kind_from_pc
and breakpoint_kind_from_current_state.
* linux-arm-low.c (arm_breakpoint_kinds): Move to
linux-aarch32-low.c.
(arm_abi_breakpoint, arm_eabi_breakpoint): Likewise.
(arm_breakpoint, arm_breakpoint_len): Likewise.
(thumb_breakpoint, thumb_breakpoint_len): Likewise.
(thumb2_breakpoint, thumb2_breakpoint_len): Likewise.
(arm_is_thumb_mode): Likewise.
(arm_breakpoint_at): Likewise.
(arm_breakpoint_kind_from_pc): Likewise.
(arm_sw_breakpoint_from_kind): Likewise.
(arm_breakpoint_kind_from_current_state): Likewise.
Revert:
2015-08-04 Yao Qi <yao.qi@linaro.org>
* linux-aarch64-low.c (aarch64_supports_z_point_type): Return
0 for Z_PACKET_SW_BP if it may be used in multi-arch debugging.
* server.c (extended_protocol): Remove "static".
* server.h (extended_protocol): Declare it.
* elf32-rx.c (elf32_rx_relax_delete_bytes): Add extra parameter -
the start of the relocs for the section. Delete code to load in
the relocs.
(elf32_rx_relax_section): Do not free the loaded relocs.
So far, trying to evaluate an expression involving a function call for
which GDB could find multiple function candidates outputs a menu so that
the user can select the one to run. For instance, with the two
following functions:
type New_Integer is new Integer;
function F (I : Integer) return Boolean;
function F (I : New_Integer) return Boolean;
Then we get the following GDB session:
(gdb) print f(1)
Multiple matches for f
[0] cancel
[1] foo.f at foo.adb:23
[2] foo.f at foo.adb.28
>
While the source location information is sufficient in order to
determine which one to select, one has to look for them in source files,
which is not convenient.
This commit tunes this menu in order to also include the list of formal
and return types (if any) in each entry. The above then becomes:
(gdb) print f(1)
Multiple matches for f
[0] cancel
[1] foo.f (integer) return boolean at foo.adb:23
[2] foo.f (foo.new_integer) return boolean at foo.adb.28
>
Since this output is more verbose than previously, this change also
introduces an option (set/show ada print-signatures) to get the original
output.
gdb/ChangeLog:
* ada-lang.c (print_signatures): New.
(ada_print_symbol_signature): New.
(user_select_syms): Add signatures to the output of candidate
symbols using ada_print_symbol_signature.
(_initialize_ada_language): Add a "set/show ada
print-signatures" boolean option.
gdb/testsuite/ChangeLog:
* gdb.ada/fun_overload_menu.exp: New testcase.
* gdb.ada/fun_overload_menu/foo.adb: New testcase.
Tested on x86_64-linux, no regression.
* msp430-sim.c (sim_open): Check for needed memory at address
0x500 not 0x200.
(get_op): Add support for F5 hardware multiply addresses.
(put_op): Likewise.
This fixes some cases where the linker would incorrectly error on plt
relocs to local ifunc symbols. I've also tidied plt and ifunc
handling for ppc64, where check_relocs was allowing for the
possibility of plt calls via addr14/addr24 relocs but relocate_section
was not.
* elf32-ppc.c (ppc_elf_check_relocs): Don't error on local ifunc
plt call. Wrap long lines.
(ppc_elf_relocate_section): Wrap long lines.
* elf64-ppc.c (ppc64_elf_check_relocs): Don't error on local ifunc
plt calls. Move __tls_get_addr checks later. Don't create plt
for addr14/addr24 relocs.
(ppc64_elf_gc_sweep_hook): Adjust to suit check_relocs changes.
(ppc64_elf_relocate_section): Correct local ifunc handling for
PLT64, PLT32 and PLT16 relocs.
On 32-bit targets, memory requested for program/section headers on a
fuzzed binary can wrap to 0. A bfd_alloc of zero bytes actually
returns a one byte allocation rather than a NULL pointer. This then
leads to buffer overflows.
Making this check unconditional triggers an extremely annoying gcc-5
warning.
PR19323
* elfcode.h (elf_object_p): Check for ridiculous e_shnum and
e_phnum values.
Add a new relocation that marks large-model entry code, for edit back
to medium-model.
include/elf/
* ppc64.h (R_PPC64_ENTRY): Define.
bfd/
* reloc.c (BFD_RELOC_PPC64_ENTRY): New.
* elf64-ppc.c (reloc_howto_type ppc64_elf_howto_raw): Add
entry for R_PPC64_ENTRY.
(LD_R2_0R12, ADD_R2_R2_R12, LIS_R2, ADDIS_R2_R12): Define.
(ppc64_elf_reloc_type_lookup): Handle R_PPC64_ENTRY.
(ppc64_elf_relocate_section): Edit code at R_PPC64_ENTTY. Use
new insn defines.
* libbfd.h: Regenerate.
* bfd-in2.h: Regenerate.
