Commit Graph

7771 Commits

Author SHA1 Message Date
Andrew Burgess
bb65a718b6 gas/arc: Don't rely on bfd list of cpu type for cpu selection
In the ARC assembler, when a cpu type is specified using the .cpu
directive, we rely on the bfd list of arc machine types in order to
validate the cpu name passed in.

This validation is only used in order to check that the cpu type passed
to the .cpu directive matches any machine type selected earlier on the
command line.  Once that initial check has passed a full check is
performed using the assemblers internal list of know cpu types.

The problem is that the assembler knows about more cpu types than bfd,
some cpu types known by the assembler are actually aliases for a base
cpu type plus a specific set of assembler extensions.  One such example
is NPS400, though more could be added later.

This commit removes the need for the assembler to use the bfd list of
machine types for validation.  Instead the error checking, to ensure
that any value passed to a '.cpu' directive matches any earlier command
line selection, is moved into the function arc_select_cpu.

I have taken the opportunity to bundle the 4 separate static globals
that describe the currently selected machine type into a single
structure (called selected_cpu).

gas/ChangeLog:

	* config/tc-arc.c (arc_target): Delete.
	(arc_target_name): Delete.
	(arc_features): Delete.
	(arc_mach_type): Delete.
	(mach_type_specified_p): Delete.
	(enum mach_selection_type): New enum.
	(mach_selection_mode): New static global.
	(selected_cpu): New static global.
	(arc_eflag): Rename to ...
	(arc_initial_eflag): ...this, and make const.
	(arc_select_cpu): Update comment, new parameter, check how
	previous machine type selection was made, and record this
	selection.  Use selected_cpu instead of old globals.
	(arc_option): Remove use of arc_get_mach, instead use
	arc_select_cpu to validate machine type selection.  Use
	selected_cpu over old globals.
	(allocate_tok): Use selected_cpu over old globals.
	(find_opcode_match): Likewise.
	(assemble_tokens): Likewise.
	(arc_cons_fix_new): Likewise.
	(arc_extinsn): Likewise.
	(arc_extcorereg): Likewise.
	(md_begin): Update default machine type selection, use
	selected_cpu over old globals.
	(md_parse_option): Update machine type selection option handling,
	use selected_cpu over old globals.
	* testsuite/gas/arc/nps400-0.s: Add .cpu directive.

bfd/ChangeLog:

	* cpu-arc.c (arc_get_mach): Delete.
2016-10-27 12:28:20 +01:00
Alan Modra
2a3a749076 Revert "bison warning fixes"
This reverts commit 95e61695c1.  People
still want to use older versions of bison, apparently.

	Revert 2016-10-06  Alan Modra  <amodra@gmail.com>
	* config/rl78-parse.y: Do use old %name-prefix syntax.
	* config/rx-parse.y: Likewise.
2016-10-26 11:45:50 +10:30
H.J. Lu
b5cefccad8 X86: Remove pcommit instruction
Remove x86 pcommit instruction support, which has been deprecated:

https://software.intel.com/en-us/blogs/2016/09/12/deprecate-pcommit-instruction

gas/

	* config/tc-i386.c (cpu_arch): Remove .pcommit.
	* doc/c-i386.texi: Likewise.
	* testsuite/gas/i386/i386.exp: Remove pcommit tests.
	* testsuite/gas/i386/pcommit-intel.d: Removed.
	* testsuite/gas/i386/pcommit.d: Likewise.
	* testsuite/gas/i386/pcommit.s: Likewise.
	* testsuite/gas/i386/x86-64-pcommit-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-pcommit.d: Likewise.
	* testsuite/gas/i386/x86-64-pcommit.s: Likewise.

opcodes/

	* i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
	(prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
	(rm_table): Update the RM_0FAE_REG_7 entry.
	* i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
	(cpu_flags): Remove CpuPCOMMIT.
	* i386-opc.h (CpuPCOMMIT): Removed.
	(i386_cpu_flags): Remove cpupcommit.
	* i386-opc.tbl: Remove pcommit.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
2016-10-21 12:16:32 -07:00
H.J. Lu
9889cbb14e Check invalid mask registers
In 32-bit, the REX_B bit in the 3-byte VEX prefix is ignored and the
the highest bit in VEX.vvvv is either 1 or ignored.  In 64-bit, we
need to check invalid mask registers.

gas/

	PR binutis/20705
	* testsuite/gas/i386/i386.exp: Run x86-64-opcode-bad.
	* testsuite/gas/i386/x86-64-opcode-bad.d: New file.
	* testsuite/gas/i386/x86-64-opcode-bad.s: Likewise.

opcodes/

	PR binutis/20705
	* i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
	the highest bit in VEX.vvvv for the 3-byte VEX prefix in
	32-bit mode.  Don't check vex.register_specifier in 32-bit
	mode.
	(OP_E_register): Check invalid mask registers.
	(OP_G): Likewise.
	(OP_VEX): Likewise.
2016-10-20 15:26:23 -07:00
Renlin Li
008a97eff0 [GAS][ARM]Generate unpredictable warning for pc used in data processing instructions with register-shifted register operand.
gas/

2016-10-19  Renlin Li  <renlin.li@arm.com>

	* config/tc-arm.c (encode_arm_shift): Generate unpredictable warning
	for register-shifted register instructions.
	* testsuite/gas/arm/shift-bad-pc.d: New.
	* testsuite/gas/arm/shift-bad-pc.l: New.
	* testsuite/gas/arm/shift-bad-pc.s: New.
2016-10-19 11:27:35 +01:00
Cupertino Miranda
8cae7a47b1 Fixed matching in newly added test.
gas/ChangeLog:

    2016-10-17  Cupertino Miranda  <cmiranda@synopsys.com>
	* testsuite/arc/dis-inv.d: Fixed target match.
2016-10-17 16:51:37 +02:00
Cupertino Miranda
decf5bd157 Removed pseudo invalid instructions opcodes.
The disassember was generating invXXX instructions for cases when in reality we
had llockd or scondd instrutions.

opcodes/ChangeLog:

    Cupertino Miranda  <cmiranda@synopsys.com>
	arc-tbl.h: Removed any "inv.+" instructions from the table.

gas/ChangeLog:

    Cupertino Miranda  <cmiranda@synopsys.com>
        testsuite/arc/dis-inv.s: Test to validate patch.
        testsuite/arc/dis-inv.d: Likewise.
2016-10-17 15:27:51 +02:00
Claudiu Zissulescu
e5b06ef06b [ARC] Disassembler: fix LIMM detection for short instructions.
The ARC (short) instructions are using a special register number to
indicate is the instruction uses a long immediate (LIMM).  In the case
of short instruction, this LIMM indicator depends on the ISA version
used. Thus, for ARCv1 processors, the LIMM indicator is 0x3E, the same
value used in "long" instructions.  However, for the ARCv2 processors,
this LIMM indicator is 0x1E.

This patch fixes the LIMM detection for ARCv1 ISA and adds two tests.

gas/
2016-10-13  Claudiu Zissulescu  <claziss@synopsys.com>

	* testsuite/gas/arc/shortlimm_a7.d: New file.
	* testsuite/gas/arc/shortlimm_a7.s: Likewise.
	* testsuite/gas/arc/shortlimm_hs.d: Likewise.
	* testsuite/gas/arc/shortlimm_hs.s: Likewise.

include/
2016-10-13  Claudiu Zissulescu  <claziss@synopsys.com>

	* opcode/arc.h (ARC_OPCODE_ARCV2): New define.

opcodes/
2016-10-13  Claudiu Zissulescu  <claziss@synopsys.com>

        * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
	usage on ISA basis.
2016-10-14 13:52:15 +02:00
Nick Clifton
a24bb4f0cc Enhance objdump so that it will use .got, .plt and .plt.got section symbols when disassembling, and it will use dynamic relocs to interpret entries in the PLT and GOT.
binutils * objdump.c (is_significant_symbol_name): New function.
	(remove_useless_symbols): Do not remove significanr symbols.
	(find_symbol_for_address): If an exact match for the specified
	address has not been found, try scanning the dynamic relocs to see
	if one of these matches the address.  If so, use the symbol
	associated with the reloc.
	(objdump_print_addr_with_symbol): Do not print offsets to symbols
	with no value.
	(disassemble_section): Only use dynamic relocs if the user
	requested this.
	(disassemble_data): Always load dynamic relocs if they are
	available.

ld	* ld-aarch64/emit-relocs-515-be.d: Adjust output to match change
	in objdump.
	* ld-aarch64/emit-relocs-515.d: Likewise.
	* ld-aarch64/emit-relocs-516-be.d: Likewise.
	* ld-aarch64/emit-relocs-516.d: Likewise.
	* ld-aarch64/farcall-b-plt.d: Likewise.
	* ld-aarch64/farcall-bl-plt.d: Likewise.
	* ld-aarch64/gc-plt-relocs.d: Likewise.
	* ld-aarch64/tls-desc-ie.d: Likewise.
	* ld-aarch64/tls-tiny-desc.d: Likewise.
	* ld-aarch64/tls-tiny-gd.d: Likewise.
	* ld-aarch64/tls-tiny-ie.d: Likewise.
	* ld-arm/arm-app-abs32.d: Likewise.
	* ld-arm/arm-app.d: Likewise.
	* ld-arm/arm-lib-plt32.d: Likewise.
	* ld-arm/arm-lib.d: Likewise.
	* ld-arm/armthumb-lib.d: Likewise.
	* ld-arm/cortex-a8-fix-b-plt.d: Likewise.
	* ld-arm/cortex-a8-fix-bcc-plt.d: Likewise.
	* ld-arm/cortex-a8-fix-bl-plt.d: Likewise.
	* ld-arm/cortex-a8-fix-bl-rel-plt.d: Likewise.
	* ld-arm/cortex-a8-fix-blx-plt.d: Likewise.
	* ld-arm/farcall-mixed-app-v5.d: Likewise.
	* ld-arm/farcall-mixed-app.d: Likewise.
	* ld-arm/farcall-mixed-app2.d: Likewise.
	* ld-arm/farcall-mixed-lib-v4t.d: Likewise.
	* ld-arm/farcall-mixed-lib.d: Likewise.
	* ld-arm/ifunc-10.dd: Likewise.
	* ld-arm/ifunc-14.dd: Likewise.
	* ld-arm/ifunc-15.dd: Likewise.
	* ld-arm/ifunc-3.dd: Likewise.
	* ld-arm/ifunc-4.dd: Likewise.
	* ld-arm/ifunc-9.dd: Likewise.
	* ld-arm/long-plt-format.d: Likewise.
	* ld-arm/mixed-app-v5.d: Likewise.
	* ld-arm/mixed-app.d: Likewise.
	* ld-arm/mixed-lib.d: Likewise.
	* ld-arm/tls-lib-loc.d: Likewise.
	* ld-cris/dso-pltdis1.d: Likewise.
	* ld-cris/dso-pltdis2.d: Likewise.
	* ld-cris/dso12-pltdis.d: Likewise.
	* ld-elf/symbolic-func.r: Likewise.
	* ld-frv/fdpic-pie-1.d: Likewise.
	* ld-frv/fdpic-pie-2.d: Likewise.
	* ld-frv/fdpic-pie-6.d: Likewise.
	* ld-frv/fdpic-pie-7.d: Likewise.
	* ld-frv/fdpic-pie-8.d: Likewise.
	* ld-frv/fdpic-shared-1.d: Likewise.
	* ld-frv/fdpic-shared-2.d: Likewise.
	* ld-frv/fdpic-shared-3.d: Likewise.
	* ld-frv/fdpic-shared-4.d: Likewise.
	* ld-frv/fdpic-shared-5.d: Likewise.
	* ld-frv/fdpic-shared-6.d: Likewise.
	* ld-frv/fdpic-shared-7.d: Likewise.
	* ld-frv/fdpic-shared-8.d: Likewise.
	* ld-frv/fdpic-shared-local-2.d: Likewise.
	* ld-frv/fdpic-shared-local-8.d: Likewise.
	* ld-frv/fdpic-static-1.d: Likewise.
	* ld-frv/fdpic-static-2.d: Likewise.
	* ld-frv/fdpic-static-6.d: Likewise.
	* ld-frv/fdpic-static-7.d: Likewise.
	* ld-frv/fdpic-static-8.d: Likewise.
	* ld-frv/tls-dynamic-2.d: Likewise.
	* ld-frv/tls-initial-shared-2.d: Likewise.
	* ld-frv/tls-relax-shared-2.d: Likewise.
	* ld-frv/tls-shared-2.d: Likewise.
	* ld-i386/plt-nacl.pd: Likewise.
	* ld-i386/plt-pic-nacl.pd: Likewise.
	* ld-i386/plt-pic.pd: Likewise.
	* ld-i386/plt.pd: Likewise.
	* ld-i386/pr19636-1d-nacl.d: Likewise.
	* ld-i386/pr19636-1d.d: Likewise.
	* ld-i386/pr19636-2c-nacl.d: Likewise.
	* ld-i386/pr19636-2c.d: Likewise.
	* ld-ifunc/ifunc-21-x86-64.d: Likewise.
	* ld-ifunc/ifunc-22-x86-64.d: Likewise.
	* ld-ifunc/pr17154-i386.d: Likewise.
	* ld-ifunc/pr17154-x86-64.d: Likewise.
	* ld-m68k/plt1-68020.d: Likewise.
	* ld-m68k/plt1-cpu32.d: Likewise.
	* ld-m68k/plt1-isab.d: Likewise.
	* ld-m68k/plt1-isac.d: Likewise.
	* ld-metag/shared.d: Likewise.
	* ld-metag/stub_pic_app.d: Likewise.
	* ld-metag/stub_pic_shared.d: Likewise.
	* ld-metag/stub_shared.d: Likewise.
	* ld-s390/tlsbin_64.dd: Likewise.
	* ld-s390/tlspic_64.dd: Likewise.
	* ld-tic6x/shlib-1.dd: Likewise.
	* ld-tic6x/shlib-1b.dd: Likewise.
	* ld-tic6x/shlib-1rb.dd: Likewise.
	* ld-tic6x/shlib-app-1.dd: Likewise.
	* ld-tic6x/shlib-app-1b.dd: Likewise.
	* ld-tic6x/shlib-app-1r.dd: Likewise.
	* ld-tic6x/shlib-app-1rb.dd: Likewise.
	* ld-tic6x/shlib-noindex.dd: Likewise.
	* ld-vax-elf/export-class-data.dd: Likewise.
	* ld-vax-elf/plt-local-lib.dd: Likewise.
	* ld-vax-elf/plt-local.dd: Likewise.
	* ld-x86-64/bnd-ifunc-2.d: Likewise.
	* ld-x86-64/bnd-plt-1.d: Likewise.
	* ld-x86-64/gotpcrel1.dd: Likewise.
	* ld-x86-64/libno-plt-1b.dd: Likewise.
	* ld-x86-64/load1c-nacl.d: Likewise.
	* ld-x86-64/load1c.d: Likewise.
	* ld-x86-64/load1d-nacl.d: Likewise.
	* ld-x86-64/load1d.d: Likewise.
	* ld-x86-64/mov1a.d: Likewise.
	* ld-x86-64/mov1b.d: Likewise.
	* ld-x86-64/mov1c.d: Likewise.
	* ld-x86-64/mov1d.d: Likewise.
	* ld-x86-64/mov2a.d: Likewise.
	* ld-x86-64/mov2b.d: Likewise.
	* ld-x86-64/mov2c.d: Likewise.
	* ld-x86-64/mov2d.d: Likewise.
	* ld-x86-64/mpx3.dd: Likewise.
	* ld-x86-64/mpx4.dd: Likewise.
	* ld-x86-64/no-plt-1a.dd: Likewise.
	* ld-x86-64/no-plt-1b.dd: Likewise.
	* ld-x86-64/no-plt-1c.dd: Likewise.
	* ld-x86-64/no-plt-1e.dd: Likewise.
	* ld-x86-64/no-plt-1f.dd: Likewise.
	* ld-x86-64/no-plt-1g.dd: Likewise.
	* ld-x86-64/plt-main-bnd.dd: Likewise.
	* ld-x86-64/plt-nacl.pd: Likewise.
	* ld-x86-64/plt.pd: Likewise.
	* ld-x86-64/pr18591.d: Likewise.
	* ld-x86-64/pr19609-1c.d: Likewise.
	* ld-x86-64/pr19609-1e.d: Likewise.
	* ld-x86-64/pr19609-1j.d: Likewise.
	* ld-x86-64/pr19609-1l.d: Likewise.
	* ld-x86-64/pr19609-1m.d: Likewise.
	* ld-x86-64/pr19609-5b.d: Likewise.
	* ld-x86-64/pr19609-5c.d: Likewise.
	* ld-x86-64/pr19609-5e.d: Likewise.
	* ld-x86-64/pr19609-6b.d: Likewise.
	* ld-x86-64/pr19609-7b.d: Likewise.
	* ld-x86-64/pr19609-7d.d: Likewise.
	* ld-x86-64/pr19636-2d.d: Likewise.
	* ld-x86-64/pr20093-1.d: Likewise.
	* ld-x86-64/pr20093-2.d: Likewise.
	* ld-x86-64/pr20253-1b.d: Likewise.
	* ld-x86-64/pr20253-1d.d: Likewise.
	* ld-x86-64/pr20253-1f.d: Likewise.
	* ld-x86-64/pr20253-1h.d: Likewise.
	* ld-x86-64/pr20253-1j.d: Likewise.
	* ld-x86-64/pr20253-1l.d: Likewise.
	* ld-x86-64/protected3.d: Likewise.
	* ld-x86-64/tlsbin.dd: Likewise.
	* ld-x86-64/tlsbin2.dd: Likewise.
	* ld-x86-64/tlsbindesc.dd: Likewise.
	* ld-x86-64/tlsdesc-nacl.pd: Likewise.
	* ld-x86-64/tlsdesc.dd: Likewise.
	* ld-x86-64/tlsdesc.pd: Likewise.
	* ld-x86-64/tlsgd10.dd: Likewise.
	* ld-x86-64/tlsgd5.dd: Likewise.
	* ld-x86-64/tlsgd6.dd: Likewise.
	* ld-x86-64/tlsgd8.dd: Likewise.
	* ld-x86-64/tlsgdesc.dd: Likewise.
	* ld-x86-64/tlspic.dd: Likewise.
	* ld-x86-64/tlspic2.dd: Likewise.

2016-10-11  Nick Clifton  <nickc@redhat.com>

	PR ld/20535
	* emultempl/elf32.em (_search_needed): Add support for pseudo
	environment variables supported by ld.so.  Namely $ORIGIN, $LIB
	and $PLATFORM.
	* configure.ac: Add getauxval to list AC_CHECK_FUNCS list.
	* config.in: Regenerate.
	* configure: Regenerate.

2016-10-11  Alan Modra  <amodra@gmail.com>

	* ldlang.c (lang_do_assignments_1): Descend into output section
	statements that do not yet have bfd sections.  Set symbol section
	temporarily for symbols defined in such statements to the undefined
	section.  Don't error on data or reloc statements until final phase.
	* ldexp.c (exp_fold_tree_1 <etree_assign>): Handle bfd_und_section
	in expld.section.
	* testsuite/ld-mmix/bpo-10.d: Adjust.
	* testsuite/ld-mmix/bpo-11.d: Adjust.

2016-10-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* emulparams/elf64_s390.sh: Move binary start to 16M.
	* testsuite/ld-s390/tlsbin_64.dd: Adjust testcases accordingly.
	* testsuite/ld-s390/tlsbin_64.rd: Likewise.

2016-10-07  Alan Modra  <amodra@gmail.com>

	* ldexp.c (MAX): Define.
	(exp_unop, exp_binop, exp_trinop): Alloc at least enough for
	etree_type.value.

2016-10-07  Alan Modra  <amodra@gmail.com>

	* testsuite/lib/ld-lib.exp (is_generic_elf): New, extracted from..
	* testsuite/ld-elf/elf.exp: ..here.

2016-10-06  Ludovic Court?s  <ludo@gnu.org>

	* emulparams/elf32bmipn32-defs.sh: Shift quote of
	"x$EMULATION_NAME" to the left to work around
	<http://ftp.gnu.org/gnu/bash/bash-4.2-patches/bash42-007>.

2016-10-06  Alan Modra  <amodra@gmail.com>

	* lexsup.c: Spell fall through comments consistently and add
	missing fall through comments.

2016-10-06  Alan Modra  <amodra@gmail.com>

	* plugin.c (asymbol_from_plugin_symbol): Avoid compiler warning
	by adding return.

2016-10-04  Alan Modra  <amodra@gmail.com>

	* ld.texinfo (Expression Section): Update result of arithmetic
	expressions.
	* ldexp.c (arith_result_section): New function.
	(fold_binary): Use it.

2016-10-04  Alan Modra  <amodra@gmail.com>

	* ldexp.c (exp_value_fold): New function.
	(exp_unop, exp_binop, exp_trinop): Use it.

2016-09-30  Alan Modra  <amodra@gmail.com>

	* scripttempl/v850.sc: Don't reference __ctbp, __ep, __gp when
	not relocating.
	* scripttempl/v850_rh850.sc: Likewise.

2016-09-30  Alan Modra  <amodra@gmail.com>

	PR ld/20528
	* testsuite/ld-elf/pr20528a.d: xfail generic elf targets.  Allow
	multiple .text sections for hppa-linux.
	* testsuite/ld-elf/pr20528b.d: Likewise.

2016-09-30  Alan Modra  <amodra@gmail.com>

	* ldmain.c (default_bfd_error_handler): New function pointer.
	(ld_bfd_error_handler): New function.
	(main): Arrange to call it on bfd errors/warnings.
	(ld_bfd_assert_handler): Enable tail call.

2016-09-30  Alan Modra  <amodra@gmail.com>

	* ldlang.c (ignore_bfd_errors): Update params.

2016-09-29  H.J. Lu  <hongjiu.lu@intel.com>

	PR ld/20528
	* emultempl/elf32.em (gld${EMULATION_NAME}_place_orphan): Don't
	merge 2 sections with different SHF_EXCLUDE.
	* testsuite/ld-elf/pr20528a.d: New file.
	* testsuite/ld-elf/pr20528a.s: Likewise.
	* testsuite/ld-elf/pr20528b.d: Likewise.
	* testsuite/ld-elf/pr20528b.s: Likewise.

2016-09-28  Christophe Lyon  <christophe.lyon@linaro.org>

	PR ld/20608
	* testsuite/ld-arm/arm-elf.exp: Handle new testcase.
	* testsuite/ld-arm/farcall-mixed-app2.d: New file.
	* testsuite/ld-arm/farcall-mixed-app2.r: Likewise.
	* testsuite/ld-arm/farcall-mixed-app2.s: Likewise.
	* testsuite/ld-arm/farcall-mixed-app2.sym: Likewise.

2016-09-26  Vlad Zakharov  <vzakhar@synopsys.com>

	* Makefile.in: Regenerate.
	* configure: Likewise.

2016-09-26  Alan Modra  <amodra@gmail.com>

	* testsuite/ld-powerpc/attr-gnu-4-4.s: Delete.
	* testsuite/ld-powerpc/attr-gnu-4-14.d: Delete.
	* testsuite/ld-powerpc/attr-gnu-4-24.d: Delete.
	* testsuite/ld-powerpc/attr-gnu-4-34.d: Delete.
	* testsuite/ld-powerpc/attr-gnu-4-41.d: Delete.
	* testsuite/ld-powerpc/attr-gnu-4-32.d: Adjust expected warning.
	* testsuite/ld-powerpc/attr-gnu-8-23.d: Likewise.
	* testsuite/ld-powerpc/attr-gnu-4-01.d: Adjust expected output.
	* testsuite/ld-powerpc/attr-gnu-4-02.d: Likewise.
	* testsuite/ld-powerpc/attr-gnu-4-03.d: Likewise.
	* testsuite/ld-powerpc/attr-gnu-4-10.d: Likewise.
	* testsuite/ld-powerpc/attr-gnu-4-11.d: Likewise.
	* testsuite/ld-powerpc/attr-gnu-4-20.d: Likewise.
	* testsuite/ld-powerpc/attr-gnu-4-22.d: Likewise.
	* testsuite/ld-powerpc/attr-gnu-4-33.d: Likewise.
	* testsuite/ld-powerpc/attr-gnu-8-11.d: Likewise.
	* testsuite/ld-powerpc/powerpc.exp: Don't run deleted tests.

2016-09-23  Akihiko Odaki  <akihiko.odaki.4i@stu.hosei.ac.jp>

	PR ld/20595
	* testsuite/ld-arm/unwind-4.d: Add -q option to linker command
	line and -r option to objdump command line.  Match emitted relocs
	to make sure that superflous relocs are not generated.

2016-09-23  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* emulparams/elf64_s390.sh: Change TEXT_START_ADDR to 256MB.
	* testsuite/ld-s390/tlsbin_64.dd: Adjust testcase accordingly.
	* testsuite/ld-s390/tlsbin_64.rd: Likewise.

2016-09-22  Nick Clifton  <nickc@redhat.com>

	* emultempl/elf32.em (_try_needed): In verbose mode, report failed
	attempts to find a needed library.

2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>

	* testsuite/ld-aarch64/emit-relocs-28.d: Expect spaces after ","
	in addresses.
	* testsuite/ld-aarch64/emit-relocs-301-be.d: Likewise.
	* testsuite/ld-aarch64/emit-relocs-301.d: Likewise.
	* testsuite/ld-aarch64/emit-relocs-302-be.d: Likewise.
	* testsuite/ld-aarch64/emit-relocs-302.d: Likewise.
	* testsuite/ld-aarch64/emit-relocs-310-be.d: Likewise.
	* testsuite/ld-aarch64/emit-relocs-310.d: Likewise.
	* testsuite/ld-aarch64/emit-relocs-313.d: Likewise.
	* testsuite/ld-aarch64/emit-relocs-515-be.d: Likewise.
	* testsuite/ld-aarch64/emit-relocs-515.d: Likewise.
	* testsuite/ld-aarch64/emit-relocs-516-be.d: Likewise.
	* testsuite/ld-aarch64/emit-relocs-516.d: Likewise.
	* testsuite/ld-aarch64/emit-relocs-531.d: Likewise.
	* testsuite/ld-aarch64/emit-relocs-532.d: Likewise.
	* testsuite/ld-aarch64/emit-relocs-533.d: Likewise.
	* testsuite/ld-aarch64/emit-relocs-534.d: Likewise.
	* testsuite/ld-aarch64/emit-relocs-535.d: Likewise.
	* testsuite/ld-aarch64/emit-relocs-536.d: Likewise.
	* testsuite/ld-aarch64/emit-relocs-537.d: Likewise.
	* testsuite/ld-aarch64/emit-relocs-538.d: Likewise.
	* testsuite/ld-aarch64/erratum835769.d: Likewise.
	* testsuite/ld-aarch64/erratum843419.d: Likewise.
	* testsuite/ld-aarch64/farcall-b-plt.d: Likewise.
	* testsuite/ld-aarch64/farcall-bl-plt.d: Likewise.
	* testsuite/ld-aarch64/gc-plt-relocs.d: Likewise.
	* testsuite/ld-aarch64/ifunc-21.d: Likewise.
	* testsuite/ld-aarch64/ifunc-7c.d: Likewise.
	* testsuite/ld-aarch64/tls-desc-ie.d: Likewise.
	* testsuite/ld-aarch64/tls-large-desc-be.d: Likewise.
	* testsuite/ld-aarch64/tls-large-desc.d: Likewise.
	* testsuite/ld-aarch64/tls-large-ie-be.d: Likewise.
	* testsuite/ld-aarch64/tls-large-ie.d: Likewise.
	* testsuite/ld-aarch64/tls-relax-all.d: Likewise.
	* testsuite/ld-aarch64/tls-relax-gd-ie.d: Likewise.
	* testsuite/ld-aarch64/tls-relax-gdesc-ie-2.d: Likewise.
	* testsuite/ld-aarch64/tls-relax-gdesc-ie.d: Likewise.
	* testsuite/ld-aarch64/tls-relax-large-desc-ie-be.d: Likewise.
	* testsuite/ld-aarch64/tls-relax-large-desc-ie.d: Likewise.
	* testsuite/ld-aarch64/tls-tiny-desc.d: Likewise.
	* testsuite/ld-aarch64/tls-tiny-gd.d: Likewise.

gas	* gas/arm/tls.d: Adjust output to match change in objdump.
2016-10-11 13:50:10 +01:00
Jiong Wang
93562a343c [AArch64] PR target/20666, fix wrong encoding of new introduced BFC pseudo
opcode/
	PR target/20666
	* aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.

gas/
	* testsuite/gas/aarch64/alias-2.d: Update expected results.
2016-10-11 11:24:44 +01:00
Andreas Krebbel
969b385b5f MIPS64: Adjust cfi* testcases.
The CFI* testcases fail on MIPS64 because the augmentation string does
not match the regexp. This is because MIPS64 doesn't use the default of
4 for DWARF2_FDE_RELOC_SIZE which ends up as "b" in the augmentation
string. MIPS64 uses the address size which is 8 resulting in "c".

Adding c to the regexp fixes a couple of them. Others also need
adjustments in the FDE header lines due to different
sizes/offsets.

gas/ChangeLog:

2016-10-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* testsuite/gas/cfi/cfi-common-1.d: Adjust regexps for mips64.
	* testsuite/gas/cfi/cfi-common-2.d: Likewise.
	* testsuite/gas/cfi/cfi-common-3.d: Likewise.
	* testsuite/gas/cfi/cfi-common-4.d: Likewise.
	* testsuite/gas/cfi/cfi-common-5.d: Likewise.
	* testsuite/gas/cfi/cfi-common-7.d: Likewise.
	* testsuite/gas/cfi/cfi-common-8.d: Likewise.
	* testsuite/gas/cfi/cfi-common-9.d: Likewise.
	* testsuite/gas/cfi/cfi-mips-1.d: Likewise.
2016-10-10 14:06:35 +02:00
Alan Modra
b6f80bb873 Auto-generated dependencies for rx-parse.o and rl78-parse.o
I noticed a while ago that the rx-elf gas gprel test regressed for no
apparent reason.  It turns out that the problem was rx-parse.y using
BFD_RELOC_RX_* values, which may change when other targets add new
relocs.  If rx-parse.o doesn't depend on bfd.h, it won't be recompiled.

	* Makefile.am (EXTRA_as_new_SOURCES): Add config/rl78-parse.y and
	config/rx-parse.y.  Move config/bfin-parse.y.
	(bfin-parse.@OBJEXT@, rl78-parse.@OBJEXT@, rx-parse.@OBJEXT@): Delete.
	($(srcdir)/config/rl78-defs.h): New rule.
	* Makefile.in: Regenerate.
2016-10-08 14:45:01 +10:30
Jiong Wang
362c0c4d9c [AArch64] PR target/20667, fix disassembler for the "special" optional SYS_Rt operand for "ic"/"tlbi"
gas/
	PR target/20667
	* testsuite/gas/aarch64/sys-rt-reg.s: Test source for instructions
	using SYS_Rt reg.
	* testsuite/gas/aarch64/sys-rt-reg.d: New testcase.

opcodes/
	PR target/20667
	* aarch64-opc.c (aarch64_print_operand): Always print operand if
	it's available.
2016-10-07 10:55:56 +01:00
Claudiu Zissulescu
08ec958fe0 [ARC] Fix parsing leave_s and enter_s mnemonics.
gas/
2016-10-06  Claudiu Zissulescu  <claziss@synopsys.com>

	* testsuite/gas/arc/leave_enter.d: New file.
	* testsuite/gas/arc/leave_enter.s: Likewise.
	* testsuite/gas/arc/regnames.d: Likewise.
	* testsuite/gas/arc/regnames.s: Likewise.
	* config/tc-arc.c (arc_parse_name): Don't match reg names against
	confirmed symbol names.
2016-10-06 17:01:59 +02:00
Alan Modra
fcddde94ee -Wimplicit-fallthrough dodgy fixes
The comment logically belongs inside the preprocessor conditional,
but gcc's -Wimplicit-fallthrough loses track of it.  Revert when/if
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=77817 is fixed.

	* app.c (do_scrub_chars): Move fall through comment.
	* expr.c (operand): Likewise.
2016-10-06 22:49:38 +10:30
Matthew Fortune
3d3424e9a8 Refine .cfi_sections check to only consider compact eh_frame
The .cfi_sections directive can be safely used multiple times
with different sections named at any time unless the compact form
of exception handling is requested after CFI information has
been emitted.  Only the compact form of CFI information changes
the way in which CFI is generated and therefore cannot be
retrospectively requested after generating CFI information.

gas/

	PR gas/20648
	* dw2gencfi.c (dot_cfi_sections): Refine the check for
	inconsistent .cfi_sections to only consider compact vs non
	compact forms.
	* testsuite/gas/cfi/cfi-common-9.d: New file.
	* testsuite/gas/cfi/cfi-common-9.s: New file.
	* testsuite/gas/cfi/cfi.exp: Run new test.
2016-10-06 12:46:09 +01:00
Alan Modra
1a0670f374 -Wimplicit-fallthrough warning fixes
Comment changes.

bfd/
	* coff-h8300.c: Spell fall through comments consistently.
	* coffgen.c: Likewise.
	* elf32-hppa.c: Likewise.
	* elf32-ppc.c: Likewise.
	* elf32-score.c: Likewise.
	* elf32-score7.c: Likewise.
	* elf64-ppc.c: Likewise.
	* elfxx-aarch64.c: Likewise.
	* elfxx-mips.c: Likewise.
	* cpu-ns32k.c: Add missing fall through comments.
	* elf-m10300.c: Likewise.
	* elf32-arm.c: Likewise.
	* elf32-avr.c: Likewise.
	* elf32-bfin.c: Likewise.
	* elf32-frv.c: Likewise.
	* elf32-i386.c: Likewise.
	* elf32-microblaze.c: Likewise.
	* elf32-nds32.c: Likewise.
	* elf32-ppc.c: Likewise.
	* elf32-rl78.c: Likewise.
	* elf32-rx.c: Likewise.
	* elf32-s390.c: Likewise.
	* elf32-sh.c: Likewise.
	* elf32-tic6x.c: Likewise.
	* elf64-ia64-vms.c: Likewise.
	* elf64-ppc.c: Likewise.
	* elf64-s390.c: Likewise.
	* elf64-x86-64.c: Likewise.
	* elflink.c: Likewise.
	* elfnn-aarch64.c: Likewise.
	* elfnn-ia64.c: Likewise.
	* ieee.c: Likewise.
	* oasys.c: Likewise.
	* pdp11.c: Likewise.
	* srec.c: Likewise.
	* versados.c: Likewise.
opcodes/
	* aarch64-opc.c: Spell fall through comments consistently.
	* i386-dis.c: Likewise.
	* aarch64-dis.c: Add missing fall through comments.
	* aarch64-opc.c: Likewise.
	* arc-dis.c: Likewise.
	* arm-dis.c: Likewise.
	* i386-dis.c: Likewise.
	* m68k-dis.c: Likewise.
	* mep-asm.c: Likewise.
	* ns32k-dis.c: Likewise.
	* sh-dis.c: Likewise.
	* tic4x-dis.c: Likewise.
	* tic6x-dis.c: Likewise.
	* vax-dis.c: Likewise.
binutils/
	* dlltool.c: Spell fall through comments consistently.
	* objcopy.c: Likewise.
	* readelf.c: Likewise.
	* dwarf.c: Add missing fall through comments.
	* elfcomm.c: Likewise.
	* sysinfo.y: Likewise.
	* readelf.c: Likewise.  Also remove extraneous comments.
gas/
	* app.c: Add missing fall through comments.
	* dw2gencfi.c: Likewise.
	* expr.c: Likewise.
	* config/tc-alpha.c: Likewise.
	* config/tc-arc.c: Likewise.
	* config/tc-arm.c: Likewise.
	* config/tc-cr16.c: Likewise.
	* config/tc-crx.c: Likewise.
	* config/tc-dlx.c: Likewise.
	* config/tc-h8300.c: Likewise.
	* config/tc-hppa.c: Likewise.
	* config/tc-i370.c: Likewise.
	* config/tc-i386.c: Likewise.
	* config/tc-i960.c: Likewise.
	* config/tc-ia64.c: Likewise.
	* config/tc-m68hc11.c: Likewise.
	* config/tc-m68k.c: Likewise.
	* config/tc-mep.c: Likewise.
	* config/tc-metag.c: Likewise.
	* config/tc-microblaze.c: Likewise.
	* config/tc-mips.c: Likewise.
	* config/tc-ns32k.c: Likewise.
	* config/tc-rx.c: Likewise.
	* config/tc-score.c: Likewise.
	* config/tc-score7.c: Likewise.
	* config/tc-sh.c: Likewise.
	* config/tc-tic4x.c: Likewise.
	* config/tc-vax.c: Likewise.
	* config/tc-xstormy16.c: Likewise.
	* config/tc-z80.c: Likewise.
	* config/tc-z8k.c: Likewise.
	* config/obj-elf.c: Likewise.
	* config/tc-i386.c: Likewise.
	* depend.c: Spell fall through comments consistently.
	* config/tc-arm.c: Likewise.
	* config/tc-d10v.c: Likewise.
	* config/tc-i960.c: Likewise.
	* config/tc-ia64.c: Likewise.
	* config/tc-m68k.c: Likewise.
	* config/tc-mcore.c: Likewise.
	* config/tc-mep.c: Likewise.
	* config/tc-ns32k.c: Likewise.
	* config/tc-visium.c: Likewise.
	* config/tc-xstormy16.c: Likewise.
	* config/tc-z8k.c: Likewise.
gprof/
	* gprof.c: Add missing fall through comments.
ld/
	* lexsup.c: Spell fall through comments consistently and add
	missing fall through comments.
2016-10-06 10:13:15 +10:30
Alan Modra
1e0f0b4d01 -Wimplicit-fallthrough noreturn fixes
binutils/
	* cxxfilt.c (usage): Add ATTRIBUTE_NORETURN.
	* elfedit.c (usage): Likewise.
	* nm.c (usage): Likewise.
	* objcopy.c (copy_usage, strip_usage): Likewise.
	* srconv.c (show_usage): Likewise.
	* strings.c (usage): Likewise.
	* sysdump.c (show_usage): Likewise.
	* srconv.c: Remove unneeded forward function declarations.
	* strings.c: Likewise.
	* sysdump.c: Likewise.
gas/
	* as.h (as_assert): Add ATTRIBUTE_NORETURN.
2016-10-06 09:40:30 +10:30
Alan Modra
2b80414579 -Wimplicit-fallthrough error fixes
Well, not all are errors, but a little more substantive than just
fiddling with comments.

bfd/
	* coffcode.h (coff_slurp_symbol_table): Revert accidental commit
	made 2015-01-08.
	* elf32-nds32.c (nds32_elf_grok_psinfo): Add missing break.
	* reloc.c (bfd_default_reloc_type_lookup): Add missing breaks.
opcodes/
	* arc-ext.c (create_map): Add missing break.
	* msp430-decode.opc (encode_as): Likewise.
	* msp430-decode.c: Regenerate.
binutils/
	* coffdump.c (dump_coff_where): Add missing break.
	* stabs.c (stab_xcoff_builtin_type): Likewise.
gas/
	* config/tc-arc.c (find_opcode_match): Add missing break.
	* config/tc-i960.c (get_cdisp): Likewise.
	* config/tc-metag.c (parse_swap, md_apply_fix): Likewise.
	* config/tc-mt.c (md_parse_option): Likewise.
	* config/tc-nds32.c (nds32_apply_fix): Likewise.
	* config/tc-hppa.c (pa_ip): Assert rather than testing last
	condition of multiple if statements.
	* config/tc-s390.c (s390_exp_compare): Return 0 on error.
	* config/tc-tic4x.c (tic4x_operand_parse): Add as_bad and break
	out of case rather than falling into next case.  Formatting.
ld/
	* plugin.c (asymbol_from_plugin_symbol): Avoid compiler warning
	by adding return.
2016-10-06 09:39:56 +10:30
Alan Modra
95e61695c1 bison warning fixes
* config/rl78-parse.y: Don't use deprecated %name-prefix.
	* config/rx-parse.y: Likewise.
2016-10-06 09:36:33 +10:30
Jiong Wang
744ce3025e [AArch64] PR target/20553, fix opcode mask for SIMD multiply by element
opcode/
	PR target/20553
        * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.

gas/
        * testsuite/gas/aarch64/advsimd-fp16.s (indexed_elem): New high index
        testcases for H and S variants.  New low index testcases for D variant.
        * testsuite/gas/aarch64/advsimd-fp16.d: Update expected results.
2016-09-30 14:16:54 +01:00
Andreas Krebbel
084303b8c6 Add .cfi_val_offset GAS command.
This patch adds support for .cfi_val_offset GAS pseudo command which
maps to DW_CFA_val_offset and DW_CFA_val_offset_sf.

gas/ChangeLog:

2016-09-29  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* doc/as.texinfo: Add docu for .cfi_val_offset.
	* dw2gencfi.c (cfi_add_CFA_val_offset): New function.
	(dot_cfi): Add case for DW_CFA_val_offset.
	(output_cfi_insn): Likewise.
	(cfi_pseudo_table): Add entry for cfi_val_offset.
	* dw2gencfi.h: Add prototype for cfi_add_CFA_val_offset.
	* testsuite/gas/cfi/cfi-common-8.d: New test.
	* testsuite/gas/cfi/cfi-common-8.s: New test.
	* testsuite/gas/cfi/cfi.exp: Run cfi-common-8 testcase.

binutils/ChangeLog:

2016-09-29  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* dwarf.c (display_debug_frames): Adjust output line.
2016-09-29 16:33:25 +02:00
Alan Modra
a5721ba270 Disallow 3-operand cmp[l][i] for ppc64
cmp[l][o] get an optional L field only when generating 32-bit code.
dcbf, tlbie and tlbiel keep their optional L field, ditto for R field
of tbegin.  cmprb, tsr., wlcr[all] and mtsle all change to a
compulsory L field.

L field of dcbf and wclr is 2 bits.

	PR 20641
include/
	* opcode/ppc.h (PPC_OPERAND_OPTIONAL32): Define.
opcodes/
	* ppc-opc.c (L): Make compulsory.
	(LOPT): New, optional form of L.
	(HTM_R): Define as LOPT.
	(L0, L1): Delete.
	(L32OPT): New, optional for 32-bit L.
	(L2OPT): New, 2-bit L for dcbf.
	(SVC_LEC): Update.
	(L2): Define.
	(insert_l0, extract_l0, insert_l1, extract_l2): Delete.
	(powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
	<dcbf>: Use L2OPT.
	<tlbiel, tlbie>: Use LOPT.
	<wclr, wclrall>: Use L2.
gas/
	* config/tc-ppc.c (md_assemble): Handle PPC_OPERAND_OPTIONAL32.
	* testsuite/gas/ppc/power8.s: Provide tbegin. operand.
	* testsuite/gas/ppc/power9.d: Update cmprb disassembly.
2016-09-29 15:12:47 +09:30
Trevor Saunders
78fb7e37eb tc-xtensa.c: fixup xg_reverse_shift_count typo
gas/ChangeLog:

2016-09-26  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* config/tc-xtensa.c (xg_reverse_shift_count): Pass cnt_arg instead of
	cnt_argp to concat.
2016-09-26 12:55:56 -04:00
Vlad Zakharov
c5da193232 When building target binaries, ensure that the warning flags selected for the command line match the target compiler.
bfd	* warning.m4 (AC_EGREP_CPP_FOR_BUILD): Introduce macro
	to verify CC_FOR_BUILD compiler.
	(AM_BINUTILS_WARNINGS): Introduce ac_cpp_for_build variable
	and add CC_FOR_BUILD compiler checks.
	* Makefile.in: Regenerate.
	* configure: Likewise.
	* doc/Makefile.in: Likewise.

binutils	* Makefile.am: Replace AM_CLFAGS with AM_CFLAGS_FOR_BUILD
	when building with CC_FOR_BUILD compiler.
	* Makefile.in: Regenerate.
	* configure: Likewise.
	* doc/Makefile.in: Likewise.

gas	* Makefile.in: Regenerate.
	* configure: Likewise.
	* doc/Makefile.in: Likewise.

gold	* Makefile.in: Regenerate.
	* configure: Likewise.
	* testsuite/Makefile.in: Likewise.

gprof	* Makefile.in: Regenerate.
	* configure: Likewise.

ld	* Makefile.in: Regenerate.
	* configure: Likewise.

opcodes	* Makefile.in: Regenerate.
	* configure: Likewise.
2016-09-26 16:36:08 +01:00
Alan Modra
005d79fd61 PowerPC .gnu.attributes
This patch extends Tag_GNU_Power_ABI_FP to cover long double ABIs,
makes the assembler warn about undefined tag values, and removes
similar warnings from the linker.  I think it is better to not
warn in the linker about undefined tag values as future extensions to
the tags then won't result in likely bogus warnings.  This is
consistent with the fact that an older linker won't warn on an
entirely new tag.

include/
	* elf/ppc.h (Tag_GNU_Power_ABI_FP): Comment.
bfd/
	* elf-bfd.h (_bfd_elf_ppc_merge_fp_attributes): Declare.
	* elf32-ppc.c (_bfd_elf_ppc_merge_fp_attributes): New function.
	(ppc_elf_merge_obj_attributes): Use it.  Don't copy first file
	attributes, merge them.  Don't warn about undefined tag bits,
	or copy unknown values to output.
	* elf64-ppc.c (ppc64_elf_merge_private_bfd_data): Call
	_bfd_elf_ppc_merge_fp_attributes.
binutils/
	* readelf.c (display_power_gnu_attribute): Catch truncated section
	for all powerpc attributes.  Display long double ABI.  Don't
	capitalize words, except for names.  Show known bits of tag values
	when some unknown bits are present.  Whitespace fixes.
gas/
	* config/tc-ppc.c (ppc_elf_gnu_attribute): New function.
	(md_pseudo_table <ELF>): Handle "gnu_attribute".
ld/
	* testsuite/ld-powerpc/attr-gnu-4-4.s: Delete.
	* testsuite/ld-powerpc/attr-gnu-4-14.d: Delete.
	* testsuite/ld-powerpc/attr-gnu-4-24.d: Delete.
	* testsuite/ld-powerpc/attr-gnu-4-34.d: Delete.
	* testsuite/ld-powerpc/attr-gnu-4-41.d: Delete.
	* testsuite/ld-powerpc/attr-gnu-4-32.d: Adjust expected warning.
	* testsuite/ld-powerpc/attr-gnu-8-23.d: Likewise.
	* testsuite/ld-powerpc/attr-gnu-4-01.d: Adjust expected output.
	* testsuite/ld-powerpc/attr-gnu-4-02.d: Likewise.
	* testsuite/ld-powerpc/attr-gnu-4-03.d: Likewise.
	* testsuite/ld-powerpc/attr-gnu-4-10.d: Likewise.
	* testsuite/ld-powerpc/attr-gnu-4-11.d: Likewise.
	* testsuite/ld-powerpc/attr-gnu-4-20.d: Likewise.
	* testsuite/ld-powerpc/attr-gnu-4-22.d: Likewise.
	* testsuite/ld-powerpc/attr-gnu-4-33.d: Likewise.
	* testsuite/ld-powerpc/attr-gnu-8-11.d: Likewise.
	* testsuite/ld-powerpc/powerpc.exp: Don't run deleted tests.
2016-09-26 18:04:57 +09:30
Thomas Preud'homme
870dd155d6 Remove legacy basepri_mask MRS/MSR special reg
2016-09-22  Thomas Preud'homme  <thomas.preudhomme@arm.com>

gas/
	* config/tc-arm.c (v7m_psrs): Remove BASEPRI_MASK MRS/MSR special
	register and redundant basepri_max.
2016-09-22 11:30:24 +01:00
Richard Sandiford
ad43e107eb [AArch64] Print spaces after commas in addresses
I got an off-list request to make the AArch64 disassembler print
spaces after commas in addresses.  This patch does that.

The same code is used to print operands in "did you mean" errors,
so to keep things consistent, the patch also prints spaces between
operands in those messages.

opcodes/
	* aarch64-opc.c (print_immediate_offset_address): Print spaces
	after commas in addresses.
	(aarch64_print_operand): Likewise.

gas/
	* config/tc-aarch64.c (print_operands): Print spaces between
	operands.
	* testsuite/gas/aarch64/ilp32-basic.d: Expect spaces after ","
	in addresses.
	* testsuite/gas/aarch64/ldst-reg-imm-post-ind.d: Likewise.
	* testsuite/gas/aarch64/ldst-reg-imm-pre-ind.d: Likewise.
	* testsuite/gas/aarch64/ldst-reg-pair.d: Likewise.
	* testsuite/gas/aarch64/ldst-reg-reg-offset.d: Likewise.
	* testsuite/gas/aarch64/ldst-reg-uns-imm.d: Likewise.
	* testsuite/gas/aarch64/ldst-reg-unscaled-imm.d: Likewise.
	* testsuite/gas/aarch64/reloc-insn.d: Likewise.
	* testsuite/gas/aarch64/sve.d: Likewise.
	* testsuite/gas/aarch64/symbol.d: Likewise.
	* testsuite/gas/aarch64/system.d: Likewise.
	* testsuite/gas/aarch64/tls-desc.d: Likewise.
	* testsuite/gas/aarch64/sve-invalid.l: Expect spaces after ","
	in suggested alternatives.
	* testsuite/gas/aarch64/verbose-error.l: Likewise.

ld/
	* testsuite/ld-aarch64/emit-relocs-28.d: Expect spaces after ","
	in addresses.
	* testsuite/ld-aarch64/emit-relocs-301-be.d: Likewise.
	* testsuite/ld-aarch64/emit-relocs-301.d: Likewise.
	* testsuite/ld-aarch64/emit-relocs-302-be.d: Likewise.
	* testsuite/ld-aarch64/emit-relocs-302.d: Likewise.
	* testsuite/ld-aarch64/emit-relocs-310-be.d: Likewise.
	* testsuite/ld-aarch64/emit-relocs-310.d: Likewise.
	* testsuite/ld-aarch64/emit-relocs-313.d: Likewise.
	* testsuite/ld-aarch64/emit-relocs-515-be.d: Likewise.
	* testsuite/ld-aarch64/emit-relocs-515.d: Likewise.
	* testsuite/ld-aarch64/emit-relocs-516-be.d: Likewise.
	* testsuite/ld-aarch64/emit-relocs-516.d: Likewise.
	* testsuite/ld-aarch64/emit-relocs-531.d: Likewise.
	* testsuite/ld-aarch64/emit-relocs-532.d: Likewise.
	* testsuite/ld-aarch64/emit-relocs-533.d: Likewise.
	* testsuite/ld-aarch64/emit-relocs-534.d: Likewise.
	* testsuite/ld-aarch64/emit-relocs-535.d: Likewise.
	* testsuite/ld-aarch64/emit-relocs-536.d: Likewise.
	* testsuite/ld-aarch64/emit-relocs-537.d: Likewise.
	* testsuite/ld-aarch64/emit-relocs-538.d: Likewise.
	* testsuite/ld-aarch64/erratum835769.d: Likewise.
	* testsuite/ld-aarch64/erratum843419.d: Likewise.
	* testsuite/ld-aarch64/farcall-b-plt.d: Likewise.
	* testsuite/ld-aarch64/farcall-bl-plt.d: Likewise.
	* testsuite/ld-aarch64/gc-plt-relocs.d: Likewise.
	* testsuite/ld-aarch64/ifunc-21.d: Likewise.
	* testsuite/ld-aarch64/ifunc-7c.d: Likewise.
	* testsuite/ld-aarch64/tls-desc-ie.d: Likewise.
	* testsuite/ld-aarch64/tls-large-desc-be.d: Likewise.
	* testsuite/ld-aarch64/tls-large-desc.d: Likewise.
	* testsuite/ld-aarch64/tls-large-ie-be.d: Likewise.
	* testsuite/ld-aarch64/tls-large-ie.d: Likewise.
	* testsuite/ld-aarch64/tls-relax-all.d: Likewise.
	* testsuite/ld-aarch64/tls-relax-gd-ie.d: Likewise.
	* testsuite/ld-aarch64/tls-relax-gdesc-ie-2.d: Likewise.
	* testsuite/ld-aarch64/tls-relax-gdesc-ie.d: Likewise.
	* testsuite/ld-aarch64/tls-relax-large-desc-ie-be.d: Likewise.
	* testsuite/ld-aarch64/tls-relax-large-desc-ie.d: Likewise.
	* testsuite/ld-aarch64/tls-tiny-desc.d: Likewise.
	* testsuite/ld-aarch64/tls-tiny-gd.d: Likewise.
2016-09-21 17:11:52 +01:00
Richard Sandiford
ab3b8fcfdb [AArch64] Use "must" rather than "should" in error messages
One of the review comments from the SVE series was that it would
be better to use "must" rather than "should" in error messages.
I think this patch fixes all cases in the AArch64 code.
It also uses "must be" instead of "expected to be".

opcodes/
	* aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
	rather than "should be" or "expected to be" in error messages.

gas/
	* config/tc-aarch64.c (output_operand_error_record): Use "must be"
	rather than "should be" or "expected to be" in error messages.
	(parse_operands): Likewise.
	* testsuite/gas/aarch64/diagnostic.l: Likewise.
	* testsuite/gas/aarch64/legacy_reg_names.l: Likewise.
	* testsuite/gas/aarch64/sve-invalid.l: Likewise.
	* testsuite/gas/aarch64/sve-reg-diagnostic.l: Likewise.
2016-09-21 17:11:04 +01:00
Richard Sandiford
bb7eff5206 [AArch64] Add SVE condition codes
SVE defines new names for existing NZCV conditions, to reflect the
result of instructions like PTEST.  This patch adds support for these
names.

The patch also adds comments to the disassembly output to show the
alternative names of a condition code.  For example:

	cinv	x0, x1, cc

becomes:

     	cinv	x0, x1, cc  // cc = lo, ul, last

and:

	b.cc	f0 <...>

becomes:

     	b.cc	f0 <...>  // b.lo, b.ul, b.last

Doing this for the SVE names follows the practice recommended by the
SVE specification and is definitely useful when reading SVE code.
If the feeling is that it's too distracting elsewhere, we could add
an option to turn it off.

include/
	* opcode/aarch64.h (aarch64_cond): Bump array size to 4.

opcodes/
	* aarch64-dis.c (remove_dot_suffix): New function, split out from...
	(print_mnemonic_name): ...here.
	(print_comment): New function.
	(print_aarch64_insn): Call it.
	* aarch64-opc.c (aarch64_conds): Add SVE names.
	(aarch64_print_operand): Print alternative condition names in
	a comment.

gas/
	* config/tc-aarch64.c (opcode_lookup): Search for the end of
	a condition name, rather than assuming that it will have exactly
	2 characters.
	(parse_operands): Likewise.
	* testsuite/gas/aarch64/alias.d: Add new condition-code comments
	to the expected output.
	* testsuite/gas/aarch64/beq_1.d: Likewise.
	* testsuite/gas/aarch64/float-fp16.d: Likewise.
	* testsuite/gas/aarch64/int-insns.d: Likewise.
	* testsuite/gas/aarch64/no-aliases.d: Likewise.
	* testsuite/gas/aarch64/programmer-friendly.d: Likewise.
	* testsuite/gas/aarch64/reloc-insn.d: Likewise.
	* testsuite/gas/aarch64/b_c_1.d, testsuite/gas/aarch64/b_c_1.s:
	New test.

ld/
	* testsuite/ld-aarch64/emit-relocs-280.d: Match branch comments.
	* testsuite/ld-aarch64/weak-undefined.d: Likewise.
2016-09-21 17:09:59 +01:00
Richard Sandiford
f2a5c4f5af Fix misplaced ChangeLog 2016-09-21 17:08:58 +01:00
Richard Sandiford
bc33f5f961 [AArch64][SVE 32/32] Add SVE tests
This patch adds new tests for SVE.  It also extends diagnostic.[sl] with
checks for some inappropriate uses of MUL and MUL VL in base AArch64
instructions.

gas/testsuite/
	* gas/aarch64/diagnostic.s, gas/aarch64/diagnostic.l: Add tests for
	invalid uses of MUL VL and MUL in base AArch64 instructions.
	* gas/aarch64/sve-add.s, gas/aarch64/sve-add.d, gas/aarch64/sve-dup.s,
	gas/aarch64/sve-dup.d, gas/aarch64/sve-invalid.s,
	gas/aarch64/sve-invalid.d, gas/aarch64/sve-invalid.l,
	gas/aarch64/sve-reg-diagnostic.s, gas/aarch64/sve-reg-diagnostic.d,
	gas/aarch64/sve-reg-diagnostic.l, gas/aarch64/sve.s,
	gas/aarch64/sve.d: New tests.
2016-09-21 16:59:07 +01:00
Richard Sandiford
c0890d2628 [AArch64][SVE 31/32] Add SVE instructions
This patch adds the SVE instruction definitions and associated OP_*
enum values.

include/
	* opcode/aarch64.h (AARCH64_FEATURE_SVE): New macro.
	(OP_MOV_P_P, OP_MOV_Z_P_Z, OP_MOV_Z_V, OP_MOV_Z_Z, OP_MOV_Z_Zi)
	(OP_MOVM_P_P_P, OP_MOVS_P_P, OP_MOVZS_P_P_P, OP_MOVZ_P_P_P)
	(OP_NOTS_P_P_P_Z, OP_NOT_P_P_P_Z): New aarch64_ops.

opcodes/
	* aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
	(OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
	(OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
	(OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
	(OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
	(OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
	(OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
	(OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
	(OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
	(OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
	(OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
	(OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
	(OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
	(OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
	(OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
	(OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
	(OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
	(OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
	(OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
	(OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
	(OP_SVE_XWU, OP_SVE_XXU): New macros.
	(aarch64_feature_sve): New variable.
	(SVE): New macro.
	(_SVE_INSN): Likewise.
	(aarch64_opcode_table): Add SVE instructions.
	* aarch64-opc.h (extract_fields): Declare.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis.c (extract_fields): Make global.
	(do_misc_decoding): Handle the new SVE aarch64_ops.
	* aarch64-dis-2.c: Regenerate.

gas/
	* doc/c-aarch64.texi: Document the "sve" feature.
	* config/tc-aarch64.c (REG_TYPE_R_Z_BHSDQ_VZP): New register type.
	(get_reg_expected_msg): Handle it.
	(parse_operands): When parsing operands of an SVE instruction,
	disallow immediates that match REG_TYPE_R_Z_BHSDQ_VZP.
	(aarch64_features): Add an entry for SVE.
2016-09-21 16:58:48 +01:00
Richard Sandiford
047cd301d4 [AArch64][SVE 29/32] Add new SVE core & FP register operands
SVE uses some new fields to store W, X and scalar FP registers.
This patch adds corresponding operands.

include/
	* opcode/aarch64.h (AARCH64_OPND_SVE_Rm): New aarch64_opnd.
	(AARCH64_OPND_SVE_Rn_SP, AARCH64_OPND_SVE_VZn, AARCH64_OPND_SVE_Vd)
	(AARCH64_OPND_SVE_Vm, AARCH64_OPND_SVE_Vn): Likewise.

opcodes/
	* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
	and FP register operands.
	* aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
	(FLD_SVE_Vn): New aarch64_field_kinds.
	* aarch64-opc.c (fields): Add corresponding entries.
	(aarch64_print_operand): Handle the new SVE core and FP register
	operands.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-asm-2.c: Likewise.
	* aarch64-dis-2.c: Likewise.

gas/
	* config/tc-aarch64.c (parse_operands): Handle the new SVE core
	and FP register operands.
2016-09-21 16:57:43 +01:00
Richard Sandiford
165d495085 [AArch64][SVE 28/32] Add SVE FP immediate operands
This patch adds support for the new SVE floating-point immediate
operands.  One operand uses the same 8-bit encoding as base AArch64,
but in a different position.  The others use a single bit to select
between two values.

One of the single-bit operands is a choice between 0 and 1, where 0
is not a valid 8-bit encoding.  I think the cleanest way of handling
these single-bit immediates is therefore to use the IEEE float encoding
itself as the immediate value and select between the two possible values
when encoding and decoding.

As described in the covering note for the patch that added F_STRICT,
we get better error messages by accepting unsuffixed vector registers
and leaving the qualifier matching code to report an error.  This means
that we carry on parsing the other operands, and so can try to parse FP
immediates for invalid instructions like:

	fcpy	z0, #2.5

In this case there is no suffix to tell us whether the immediate should
be treated as single or double precision.  Again, we get better error
messages by picking one (arbitrary) immediate size and reporting an error
for the missing suffix later.

include/
	* opcode/aarch64.h (AARCH64_OPND_SVE_FPIMM8): New aarch64_opnd.
	(AARCH64_OPND_SVE_I1_HALF_ONE, AARCH64_OPND_SVE_I1_HALF_TWO)
	(AARCH64_OPND_SVE_I1_ZERO_ONE): Likewise.

opcodes/
	* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
	immediate operands.
	* aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
	* aarch64-opc.c (fields): Add corresponding entry.
	(operand_general_constraint_met_p): Handle the new SVE FP immediate
	operands.
	(aarch64_print_operand): Likewise.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
	(ins_sve_float_zero_one): New inserters.
	* aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
	(aarch64_ins_sve_float_half_two): Likewise.
	(aarch64_ins_sve_float_zero_one): Likewise.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
	(ext_sve_float_zero_one): New extractors.
	* aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
	(aarch64_ext_sve_float_half_two): Likewise.
	(aarch64_ext_sve_float_zero_one): Likewise.
	* aarch64-dis-2.c: Regenerate.

gas/
	* config/tc-aarch64.c (double_precision_operand_p): New function.
	(parse_operands): Use it to calculate the dp_p input to
	parse_aarch64_imm_float.  Handle the new SVE FP immediate operands.
2016-09-21 16:57:22 +01:00
Richard Sandiford
e950b34539 [AArch64][SVE 27/32] Add SVE integer immediate operands
This patch adds the new SVE integer immediate operands.  There are
three kinds:

- simple signed and unsigned ranges, but with new widths and positions.

- 13-bit logical immediates.  These have the same form as in base AArch64,
  but at a different bit position.

  In the case of the "MOV Zn.<T>, #<limm>" alias of DUPM, the logical
  immediate <limm> is not allowed to be a valid DUP immediate, since DUP
  is preferred over DUPM for constants that both instructions can handle.

- a new 9-bit arithmetic immediate, of the form "<imm8>{, LSL #8}".
  In some contexts the operand is signed and in others it's unsigned.
  As an extension, we allow shifted immediates to be written as a single
  integer, e.g. "#256" is equivalent to "#1, LSL #8".  We also use the
  shiftless form as the preferred disassembly, except for the special
  case of "#0, LSL #8" (a redundant encoding of 0).

include/
	* opcode/aarch64.h (AARCH64_OPND_SIMM5): New aarch64_opnd.
	(AARCH64_OPND_SVE_AIMM, AARCH64_OPND_SVE_ASIMM)
	(AARCH64_OPND_SVE_INV_LIMM, AARCH64_OPND_SVE_LIMM)
	(AARCH64_OPND_SVE_LIMM_MOV, AARCH64_OPND_SVE_SHLIMM_PRED)
	(AARCH64_OPND_SVE_SHLIMM_UNPRED, AARCH64_OPND_SVE_SHRIMM_PRED)
	(AARCH64_OPND_SVE_SHRIMM_UNPRED, AARCH64_OPND_SVE_SIMM5)
	(AARCH64_OPND_SVE_SIMM5B, AARCH64_OPND_SVE_SIMM6)
	(AARCH64_OPND_SVE_SIMM8, AARCH64_OPND_SVE_UIMM3)
	(AARCH64_OPND_SVE_UIMM7, AARCH64_OPND_SVE_UIMM8)
	(AARCH64_OPND_SVE_UIMM8_53): Likewise.
	(aarch64_sve_dupm_mov_immediate_p): Declare.

opcodes/
	* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
	integer immediate operands.
	* aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
	(FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
	(FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
	* aarch64-opc.c (fields): Add corresponding entries.
	(operand_general_constraint_met_p): Handle the new SVE integer
	immediate operands.
	(aarch64_print_operand): Likewise.
	(aarch64_sve_dupm_mov_immediate_p): New function.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
	(ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
	* aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
	(aarch64_ins_limm): ...here.
	(aarch64_ins_inv_limm): New function.
	(aarch64_ins_sve_aimm): Likewise.
	(aarch64_ins_sve_asimm): Likewise.
	(aarch64_ins_sve_limm_mov): Likewise.
	(aarch64_ins_sve_shlimm): Likewise.
	(aarch64_ins_sve_shrimm): Likewise.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
	(ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
	* aarch64-dis.c (decode_limm): New function, split out from...
	(aarch64_ext_limm): ...here.
	(aarch64_ext_inv_limm): New function.
	(decode_sve_aimm): Likewise.
	(aarch64_ext_sve_aimm): Likewise.
	(aarch64_ext_sve_asimm): Likewise.
	(aarch64_ext_sve_limm_mov): Likewise.
	(aarch64_top_bit): Likewise.
	(aarch64_ext_sve_shlimm): Likewise.
	(aarch64_ext_sve_shrimm): Likewise.
	* aarch64-dis-2.c: Regenerate.

gas/
	* config/tc-aarch64.c (parse_operands): Handle the new SVE integer
	immediate operands.
2016-09-21 16:56:57 +01:00
Richard Sandiford
98907a7049 [AArch64][SVE 26/32] Add SVE MUL VL addressing modes
This patch adds support for addresses of the form:

       [<base>, #<offset>, MUL VL]

This involves adding a new AARCH64_MOD_MUL_VL modifier, which is
why I split it out from the other addressing modes.

For LD2, LD3 and LD4, the offset must be a multiple of the structure
size, so for LD3 the possible values are 0, 3, 6, ....  The patch
therefore extends value_aligned_p to handle non-power-of-2 alignments.

include/
	* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4xVL): New aarch64_opnd.
	(AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, AARCH64_OPND_SVE_ADDR_RI_S4x3xVL)
	(AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, AARCH64_OPND_SVE_ADDR_RI_S6xVL)
	(AARCH64_OPND_SVE_ADDR_RI_S9xVL): Likewise.
	(AARCH64_MOD_MUL_VL): New aarch64_modifier_kind.

opcodes/
	* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
	operands.
	* aarch64-opc.c (aarch64_operand_modifiers): Initialize
	the AARCH64_MOD_MUL_VL entry.
	(value_aligned_p): Cope with non-power-of-two alignments.
	(operand_general_constraint_met_p): Handle the new MUL VL addresses.
	(print_immediate_offset_address): Likewise.
	(aarch64_print_operand): Likewise.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
	(ins_sve_addr_ri_s9xvl): New inserters.
	* aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
	(aarch64_ins_sve_addr_ri_s6xvl): Likewise.
	(aarch64_ins_sve_addr_ri_s9xvl): Likewise.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
	(ext_sve_addr_ri_s9xvl): New extractors.
	* aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
	(aarch64_ext_sve_addr_ri_s4xvl): Likewise.
	(aarch64_ext_sve_addr_ri_s6xvl): Likewise.
	(aarch64_ext_sve_addr_ri_s9xvl): Likewise.
	* aarch64-dis-2.c: Regenerate.

gas/
	* config/tc-aarch64.c (SHIFTED_NONE, SHIFTED_MUL_VL): New
	parse_shift_modes.
	(parse_shift): Handle SHIFTED_MUL_VL.
	(parse_address_main): Add an imm_shift_mode parameter.
	(parse_address, parse_sve_address): Update accordingly.
	(parse_operands): Handle MUL VL addressing modes.
2016-09-21 16:56:15 +01:00
Richard Sandiford
4df068de52 [AArch64][SVE 25/32] Add support for SVE addressing modes
This patch adds most of the new SVE addressing modes and associated
operands.  A follow-on patch adds MUL VL, since handling it separately
makes the changes easier to read.

The patch also introduces a new "operand-dependent data" field to the
operand flags, based closely on the existing one for opcode flags.
For SVE this new field needs only 2 bits, but it could be widened
in future if necessary.

include/
	* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_U6): New aarch64_opnd.
	(AARCH64_OPND_SVE_ADDR_RI_U6x2, AARCH64_OPND_SVE_ADDR_RI_U6x4)
	(AARCH64_OPND_SVE_ADDR_RI_U6x8, AARCH64_OPND_SVE_ADDR_RR)
	(AARCH64_OPND_SVE_ADDR_RR_LSL1, AARCH64_OPND_SVE_ADDR_RR_LSL2)
	(AARCH64_OPND_SVE_ADDR_RR_LSL3, AARCH64_OPND_SVE_ADDR_RX)
	(AARCH64_OPND_SVE_ADDR_RX_LSL1, AARCH64_OPND_SVE_ADDR_RX_LSL2)
	(AARCH64_OPND_SVE_ADDR_RX_LSL3, AARCH64_OPND_SVE_ADDR_RZ)
	(AARCH64_OPND_SVE_ADDR_RZ_LSL1, AARCH64_OPND_SVE_ADDR_RZ_LSL2)
	(AARCH64_OPND_SVE_ADDR_RZ_LSL3, AARCH64_OPND_SVE_ADDR_RZ_XTW_14)
	(AARCH64_OPND_SVE_ADDR_RZ_XTW_22, AARCH64_OPND_SVE_ADDR_RZ_XTW1_14)
	(AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, AARCH64_OPND_SVE_ADDR_RZ_XTW2_14)
	(AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, AARCH64_OPND_SVE_ADDR_RZ_XTW3_14)
	(AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, AARCH64_OPND_SVE_ADDR_ZI_U5)
	(AARCH64_OPND_SVE_ADDR_ZI_U5x2, AARCH64_OPND_SVE_ADDR_ZI_U5x4)
	(AARCH64_OPND_SVE_ADDR_ZI_U5x8, AARCH64_OPND_SVE_ADDR_ZZ_LSL)
	(AARCH64_OPND_SVE_ADDR_ZZ_SXTW, AARCH64_OPND_SVE_ADDR_ZZ_UXTW):
	Likewise.

opcodes/
	* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
	address operands.
	* aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
	(FLD_SVE_xs_22): New aarch64_field_kinds.
	(OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
	(get_operand_specific_data): New function.
	* aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
	FLD_SVE_xs_14 and FLD_SVE_xs_22.
	(operand_general_constraint_met_p): Handle the new SVE address
	operands.
	(sve_reg): New array.
	(get_addr_sve_reg_name): New function.
	(aarch64_print_operand): Handle the new SVE address operands.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
	(ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
	(ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
	* aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
	(aarch64_ins_sve_addr_rr_lsl): Likewise.
	(aarch64_ins_sve_addr_rz_xtw): Likewise.
	(aarch64_ins_sve_addr_zi_u5): Likewise.
	(aarch64_ins_sve_addr_zz): Likewise.
	(aarch64_ins_sve_addr_zz_lsl): Likewise.
	(aarch64_ins_sve_addr_zz_sxtw): Likewise.
	(aarch64_ins_sve_addr_zz_uxtw): Likewise.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
	(ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
	(ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
	* aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
	(aarch64_ext_sve_addr_ri_u6): Likewise.
	(aarch64_ext_sve_addr_rr_lsl): Likewise.
	(aarch64_ext_sve_addr_rz_xtw): Likewise.
	(aarch64_ext_sve_addr_zi_u5): Likewise.
	(aarch64_ext_sve_addr_zz): Likewise.
	(aarch64_ext_sve_addr_zz_lsl): Likewise.
	(aarch64_ext_sve_addr_zz_sxtw): Likewise.
	(aarch64_ext_sve_addr_zz_uxtw): Likewise.
	* aarch64-dis-2.c: Regenerate.

gas/
	* config/tc-aarch64.c (REG_TYPE_SVE_BASE, REG_TYPE_SVE_OFFSET): New
	register types.
	(get_reg_expected_msg): Handle them.
	(aarch64_addr_reg_parse): New function, split out from
	aarch64_reg_parse_32_64.  Handle Z registers too.
	(aarch64_reg_parse_32_64): Call it.
	(parse_address_main): Add base_qualifier, offset_qualifier,
	base_type and offset_type parameters.  Handle SVE base and offset
	registers.
	(parse_address): Update call to parse_address_main.
	(parse_sve_address): New function.
	(parse_operands): Parse the new SVE address operands.
2016-09-21 16:55:49 +01:00
Richard Sandiford
2442d8466e [AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALED
Some SVE instructions count the number of elements in a given vector
pattern and allow a scale factor of [1, 16] to be applied to the result.
This scale factor is written ", MUL #n", where "MUL" is a new operator.
E.g.:

	UQINCD	X0, POW2, MUL #2

This patch adds support for this kind of operand.

All existing operators were shifts of some kind, so there was a natural
range of [0, 63] regardless of context.  This was then narrowered further
by later checks (e.g. to [0, 31] when used for 32-bit values).

In contrast, MUL doesn't really have a natural context-independent range.
Rather than pick one arbitrarily, it seemed better to make the "shift"
amount a full 64-bit value and leave the range test to the usual
operand-checking code.  I've rearranged the fields of aarch64_opnd_info
so that this doesn't increase the size of the structure (although I don't
think its size is critical anyway).

include/
	* opcode/aarch64.h (AARCH64_OPND_SVE_PATTERN_SCALED): New
	aarch64_opnd.
	(AARCH64_MOD_MUL): New aarch64_modifier_kind.
	(aarch64_opnd_info): Make shifter.amount an int64_t and
	rearrange the fields.

opcodes/
	* aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
	AARCH64_OPND_SVE_PATTERN_SCALED.
	* aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
	* aarch64-opc.c (fields): Add a corresponding entry.
	(set_multiplier_out_of_range_error): New function.
	(aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
	(operand_general_constraint_met_p): Handle
	AARCH64_OPND_SVE_PATTERN_SCALED.
	(print_register_offset_address): Use PRIi64 to print the
	shift amount.
	(aarch64_print_operand): Likewise.  Handle
	AARCH64_OPND_SVE_PATTERN_SCALED.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-asm.h (ins_sve_scale): New inserter.
	* aarch64-asm.c (aarch64_ins_sve_scale): New function.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis.h (ext_sve_scale): New inserter.
	* aarch64-dis.c (aarch64_ext_sve_scale): New function.
	* aarch64-dis-2.c: Regenerate.

gas/
	* config/tc-aarch64.c (SHIFTED_MUL): New parse_shift_mode.
	(parse_shift): Handle it.  Reject AARCH64_MOD_MUL for all other
	shift modes.  Skip range tests for AARCH64_MOD_MUL.
	(process_omitted_operand): Handle AARCH64_OPND_SVE_PATTERN_SCALED.
	(parse_operands): Likewise.
2016-09-21 16:55:22 +01:00
Richard Sandiford
245d2e3fe8 [AArch64][SVE 23/32] Add SVE pattern and prfop operands
The SVE instructions have two enumerated operands: one to select a
vector pattern and another to select a prefetch operation.  The latter
is a cut-down version of the base AArch64 prefetch operation.

Both types of operand can also be specified as raw enum values such as #31.
Reserved values can only be specified this way.

If it hadn't been for the pattern operand, I would have been tempted
to use the existing parsing for prefetch operations and add extra
checks for SVE.  However, since the patterns needed new enum parsing
code anyway, it seeemed cleaner to reuse it for the prefetches too.

Because of the small number of enum values, I don't think we'd gain
anything by using hash tables.

include/
	* opcode/aarch64.h (AARCH64_OPND_SVE_PATTERN): New aarch64_opnd.
	(AARCH64_OPND_SVE_PRFOP): Likewise.
	(aarch64_sve_pattern_array): Declare.
	(aarch64_sve_prfop_array): Likewise.

opcodes/
	* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
	AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
	* aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
	(FLD_SVE_prfop): Likewise.
	* aarch64-opc.c: Include libiberty.h.
	(aarch64_sve_pattern_array): New variable.
	(aarch64_sve_prfop_array): Likewise.
	(fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
	(aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
	AARCH64_OPND_SVE_PRFOP.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Likewise.
	* aarch64-opc-2.c: Likewise.

gas/
	* config/tc-aarch64.c (parse_enum_string): New function.
	(po_enum_or_fail): New macro.
	(parse_operands): Handle AARCH64_OPND_SVE_PATTERN and
	AARCH64_OPND_SVE_PRFOP.
2016-09-21 16:54:53 +01:00
Richard Sandiford
d50c751e00 [AArch64][SVE 22/32] Add qualifiers for merging and zeroing predication
This patch adds qualifiers to represent /z and /m suffixes on
predicate registers.

include/
	* opcode/aarch64.h (AARCH64_OPND_QLF_P_Z): New aarch64_opnd_qualifier.
	(AARCH64_OPND_QLF_P_M): Likewise.

opcodes/
	* aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
	AARCH64_OPND_QLF_P_[ZM].
	(aarch64_print_operand): Print /z and /m where appropriate.

gas/
	* config/tc-aarch64.c (vector_el_type): Add NT_zero and NT_merge.
	(parse_vector_type_for_operand): Assert that the skipped character
	is a '.'.
	(parse_predication_for_operand): New function.
	(parse_typed_reg): Parse /z and /m suffixes for predicate registers.
	(vectype_to_qualifier): Handle NT_zero and NT_merge.
2016-09-21 16:54:30 +01:00
Richard Sandiford
f11ad6bc0f [AArch64][SVE 21/32] Add Zn and Pn registers
This patch adds the Zn and Pn registers, and associated fields and
operands.

include/
	* opcode/aarch64.h (AARCH64_OPND_CLASS_SVE_REG): New
	aarch64_operand_class.
	(AARCH64_OPND_CLASS_PRED_REG): Likewise.
	(AARCH64_OPND_SVE_Pd, AARCH64_OPND_SVE_Pg3, AARCH64_OPND_SVE_Pg4_5)
	(AARCH64_OPND_SVE_Pg4_10, AARCH64_OPND_SVE_Pg4_16)
	(AARCH64_OPND_SVE_Pm, AARCH64_OPND_SVE_Pn, AARCH64_OPND_SVE_Pt)
	(AARCH64_OPND_SVE_Za_5, AARCH64_OPND_SVE_Za_16, AARCH64_OPND_SVE_Zd)
	(AARCH64_OPND_SVE_Zm_5, AARCH64_OPND_SVE_Zm_16, AARCH64_OPND_SVE_Zn)
	(AARCH64_OPND_SVE_Zn_INDEX, AARCH64_OPND_SVE_ZnxN)
	(AARCH64_OPND_SVE_Zt, AARCH64_OPND_SVE_ZtxN): New aarch64_opnds.

opcodes/
	* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
	* aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
	(FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
	(FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
	(FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
	* aarch64-opc.c (fields): Add corresponding entries here.
	(operand_general_constraint_met_p): Check that SVE register lists
	have the correct length.  Check the ranges of SVE index registers.
	Check for cases where p8-p15 are used in 3-bit predicate fields.
	(aarch64_print_operand): Handle the new SVE operands.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
	* aarch64-asm.c (aarch64_ins_sve_index): New function.
	(aarch64_ins_sve_reglist): Likewise.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
	* aarch64-dis.c (aarch64_ext_sve_index): New function.
	(aarch64_ext_sve_reglist): Likewise.
	* aarch64-dis-2.c: Regenerate.

gas/
	* config/tc-aarch64.c (NTA_HASVARWIDTH): New macro.
	(AARCH64_REG_TYPES): Add ZN and PN.
	(get_reg_expected_msg): Handle them.
	(parse_vector_type_for_operand): Add a reg_type parameter.
	Skip the width for Zn and Pn registers.
	(parse_typed_reg): Extend vector handling to Zn and Pn.  Update the
	call to parse_vector_type_for_operand.  Set HASVARTYPE for Zn and Pn,
	expecting the width to be 0.
	(parse_vector_reg_list): Restrict error about [BHSD]nn operands to
	REG_TYPE_VN.
	(vectype_to_qualifier): Use S_[BHSD] qualifiers for NTA_HASVARWIDTH.
	(parse_operands): Handle the new Zn and Pn operands.
	(REGSET16): New macro, split out from...
	(REGSET31): ...here.
	(reg_names): Add Zn and Pn entries.
2016-09-21 16:53:54 +01:00
Richard Sandiford
0c608d6b62 [AArch64][SVE 20/32] Add support for tied operands
SVE has some instructions in which the same register appears twice
in the assembly string, once as an input and once as an output.
This patch adds a general mechanism for that.

The patch needs to add new information to the instruction entries.
One option would have been to extend the flags field of the opcode
to 64 bits (since we already rely on 64-bit integers being available
on the host).  However, the *_INSN macros mean that it's easy to add
new information as top-level fields without affecting the existing
table entries too much.  Going for that option seemed to give slightly
neater code.

include/
	* opcode/aarch64.h (aarch64_opcode): Add a tied_operand field.
	(AARCH64_OPDE_UNTIED_OPERAND): New aarch64_operand_error_kind.

opcodes/
	* aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
	(_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
	(V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
	* aarch64-opc.c (aarch64_match_operands_constraint): Check for
	tied operands.

gas/
	* config/tc-aarch64.c (output_operand_error_record): Handle
	AARCH64_OPDE_UNTIED_OPERAND.
2016-09-21 16:52:30 +01:00
Richard Sandiford
4989adac84 [AArch64][SVE 13/32] Add an F_STRICT flag
SVE predicate operands can appear in three forms:

1. unsuffixed: "Pn"
2. with a predication type: "Pn/[ZM]"
3. with a size suffix: "Pn.[BHSD]"

No variation is allowed: unsuffixed operands cannot have a (redundant)
suffix, and the suffixes can never be dropped.  Unsuffixed Pn are used
in LDR and STR, but they are also used for Pg operands in cases where
the result is scalar and where there is therefore no choice to be made
between "merging" and "zeroing".  This means that some Pg operands have
suffixes and others don't.

It would be possible to use context-sensitive parsing to handle
this difference.  The tc-aarch64.c code would then raise an error
if the wrong kind of suffix is used for a particular instruction.

However, we get much more user-friendly error messages if we parse
all three forms for all SVE instructions and record the suffix as a
qualifier.  The normal qualifier matching code can then report cases
where the wrong kind of suffix is used.  This is a slight extension
of existing usage, which really only checks for the wrong choice of
suffix within a particular kind of suffix.

The only catch is a that a "NIL" entry in the qualifier list
specifically means "no suffix should be present" (case 1 above).
NIL isn't a wildcard here.  It also means that an instruction that
requires all-NIL qualifiers can fail to match (because a suffix was
supplied when it shouldn't have been); this requires a slight change
to find_best_match.

This patch adds an F_STRICT flag to select this behaviour.
The flag will be set for all SVE instructions.  The behaviour
for other instructions doesn't change.

include/
	* opcode/aarch64.h (F_STRICT): New flag.

opcodes/
	* aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.

gas/
	* config/tc-aarch64.c (find_best_match): Simplify, allowing an
	instruction with all-NIL qualifiers to fail to match.
2016-09-21 16:51:00 +01:00
Richard Sandiford
73866052f2 [AArch64][SVE 12/32] Remove boolean parameters from parse_address_main
In the review of the original version of this series, Richard didn't
like the use of boolean parameters to parse_address_main.  I think we
can just get rid of them and leave the callers to check the addressing
modes.  As it happens, the handling of ADDR_SIMM9{,_2} already did this
for relocation operators (i.e. it used parse_address_reloc and then
rejected relocations).

The callers are already set up to reject invalid register post-indexed
addressing, so we can simply remove the accept_reg_post_index parameter
without adding any more checks.  This again creates a corner case where:

	.equ	x2, 1
	ldr	w0, [x1], x2

was previously an acceptable way of writing "ldr w0, [x1], #1" but
is now rejected.

Removing the "reloc" parameter means that two cases need to check
explicitly for relocation operators.

ADDR_SIMM9_2 appers to be unused.  I'll send a separate patch
to remove it.

This patch makes parse_address temporarily equivalent to
parse_address_main, but later patches in the series will need
to keep the distinction.

gas/
	* config/tc-aarch64.c (parse_address_main): Remove reloc and
	accept_reg_post_index parameters.  Parse relocations and register
	post indexes unconditionally.
	(parse_address): Remove accept_reg_post_index parameter.
	Update call to parse_address_main.
	(parse_address_reloc): Delete.
	(parse_operands): Call parse_address instead of parse_address_main.
	Update existing callers of parse_address and make them check
	inst.reloc.type where appropriate.
	* testsuite/gas/aarch64/diagnostic.s: Add tests for relocations
	in ADDR_SIMPLE, SIMD_ADDR_SIMPLE, ADDR_SIMM7 and ADDR_SIMM9 addresses.
	Also test for invalid uses of post-index register addressing.
	* testsuite/gas/aarch64/diagnostic.l: Update accordingly.
2016-09-21 16:49:31 +01:00
Richard Sandiford
e1b988bba6 [AArch64][SVE 11/32] Tweak aarch64_reg_parse_32_64 interface
aarch64_reg_parse_32_64 is currently used to parse address registers,
among other things.  It returns two bits of information about the
register: whether it's W rather than X, and whether it's a zero register.

SVE adds addressing modes in which the base or offset can be a vector
register instead of a scalar, so a choice between W and X is no longer
enough.  It's more convenient to pass the type of register around as
a qualifier instead.

As it happens, two callers of aarch64_reg_parse_32_64 already wanted
the information in the form of a qualifier, so the change feels pretty
natural even without SVE.

Also, the function took two parameters to control whether {W}SP
and (W|X)ZR should be accepted.  We tend to get slightly better
error messages by accepting them regardless and getting the caller
to do the check, rather than potentially treating "xzr", "sp" etc.
as constants.  This is easier to do if the function returns the
reg_entry rather than just the register number.

This does create a corner case where:

	.equ	sp, 1
	ldr	w0, [x0, sp]

was previously an acceptable way of writing "ldr w0, [x0, #1]",
but I don't think it's important to continue supporting that.
We already rejected things like:

	.equ	sp, 1
	add	x0, x1, sp

To ensure these new error messages "win" when matching against
several candidate instruction entries, we need to use the same
address-parsing code for all addresses, including ADDR_SIMPLE
and SIMD_ADDR_SIMPLE.  The next patch also relies on this.

Finally, aarcch64_check_reg_type was written in a pretty
conservative way.  It should always be equivalent to a single
bit test.

gas/
	* config/tc-aarch64.c (REG_TYPE_R_Z, REG_TYPE_R_SP): New register
	types.
	(get_reg_expected_msg): Handle them and REG_TYPE_R64_SP.
	(aarch64_check_reg_type): Simplify.
	(aarch64_reg_parse_32_64): Return the reg_entry instead of the
	register number.  Return the type as a qualifier rather than an
	"isreg32" boolean.  Remove reject_sp, reject_rz and isregzero
	parameters.
	(parse_shifter_operand): Update call to aarch64_parse_32_64_reg.
	Use get_reg_expected_msg.
	(parse_address_main): Likewise.  Use aarch64_check_reg_type.
	(po_int_reg_or_fail): Replace reject_sp and reject_rz parameters
	with a reg_type parameter.  Update call to aarch64_parse_32_64_reg.
	Use aarch64_check_reg_type to test the result.
	(parse_operands): Update after the above changes.  Parse ADDR_SIMPLE
	addresses normally before enforcing the syntax restrictions.
	* testsuite/gas/aarch64/diagnostic.s: Add tests for a post-index
	zero register and for a stack pointer index.
	* testsuite/gas/aarch64/diagnostic.l: Update accordingly.
	Also update existing diagnostic messages after the above changes.
	* testsuite/gas/aarch64/illegal-lse.l: Update the error message
	for 32-bit register bases.
2016-09-21 16:49:24 +01:00
Richard Sandiford
874d7e6ef9 [AArch64][SVE 10/32] Move range check out of parse_aarch64_imm_float
Since some SVE constants are no longer explicitly tied to the 8-bit
FP immediate format, it seems better to move the range checks out of
parse_aarch64_imm_float and into the callers.

gas/
	* config/tc-aarch64.c (parse_aarch64_imm_float): Remove range check.
	(parse_operands): Check the range of 8-bit FP immediates here instead.
2016-09-21 16:49:15 +01:00
Richard Sandiford
6a9deabec4 [AArch64][SVE 09/32] Improve error messages for invalid floats
Previously:

        fmov d0, #2

would give an error:

        Operand 2 should be an integer register

whereas the user probably just forgot to add the ".0" to make:

        fmov d0, #2.0

This patch reports an invalid floating point constant unless the
operand is obviously a register.

The FPIMM8 handling is only relevant for SVE.  Without it:

        fmov z0, z1

would try to parse z1 as an integer immediate zero (the res2 path),
whereas it's more likely that the user forgot the predicate.  This is
tested by the final patch.

gas/
	* config/tc-aarch64.c (parse_aarch64_imm_float): Report a specific
	low-severity error for registers.
	(parse_operands): Report an invalid floating point constant for
	if parsing an FPIMM8 fails, and if no better error has been
	recorded.
	* testsuite/gas/aarch64/diagnostic.s,
	testsuite/gas/aarch64/diagnostic.l: Add tests for integer operands
	to FMOV.
2016-09-21 16:49:07 +01:00
Richard Sandiford
04a3379ace [AArch64][SVE 08/32] Generalise aarch64_double_precision_fmovable
SVE has single-bit floating-point constants that don't really
have any relation to the AArch64 8-bit floating-point encoding.
(E.g. one of the constants selects between 0 and 1.)  The easiest
way of representing them in the aarch64_opnd_info seemed to be
to use the IEEE float representation directly, rather than invent
some new scheme.

This patch paves the way for that by making the code that converts IEEE
doubles to IEEE floats accept any value in the range of an IEEE float,
not just zero and 8-bit floats.  It leaves the range checking to the
caller (which already handles it).

gas/
	* config/tc-aarch64.c (aarch64_double_precision_fmovable): Rename
	to...
	(can_convert_double_to_float): ...this.  Accept any double-precision
	value that converts to single precision without loss of precision.
	(parse_aarch64_imm_float): Update accordingly.
2016-09-21 16:48:59 +01:00
Richard Sandiford
1799c0d064 [AArch64][SVE 07/32] Replace hard-coded uses of REG_TYPE_R_Z_BHSDQ_V
To remove parsing ambiguities and to avoid register names being
accidentally added to the symbol table, the immediate parsing
routines reject things like:

	.equ	x0, 0
	add	v0.4s, v0.4s, x0

An explicit '#' must be used instead:

	.equ	x0, 0
	add	v0.4s, v0.4s, #x0

Of course, it wasn't possible to predict what other register
names might be added in future, so this behaviour was restricted
to the register names that were defined at the time.  For backwards
compatibility, we should continue to allow things like:

	.equ	p0, 0
	add	v0.4s, v0.4s, p0

even though p0 is now an SVE register.

However, it seems reasonable to extend the x0 behaviour above to
SVE registers when parsing SVE instructions, especially since none
of the SVE immediate formats are relocatable.  Doing so removes the
same parsing ambiguity for SVE instructions as the x0 behaviour removes
for base AArch64 instructions.

As a prerequisite, we then need to be able to tell the parsing routines
which registers to reject.  This patch changes the interface to make
that possible, although the set of rejected registers doesn't change
at this stage.

gas/
	* config/tc-aarch64.c (parse_immediate_expression): Add a
	reg_type parameter.
	(parse_constant_immediate): Likewise, and update calls.
	(parse_aarch64_imm_float): Likewise.
	(parse_big_immediate): Likewise.
	(po_imm_nc_or_fail): Update accordingly, passing down a new
	imm_reg_type variable.
	(po_imm_of_fail): Likewise.
	(parse_operands): Likewise.
2016-09-21 16:48:50 +01:00