Commit Graph

2229 Commits

Author SHA1 Message Date
Jim Wilson
645a2c5b46 RISC-V: Add 2 missing privileged registers.
gas/
	* testsuite/gas/riscv/priv-reg.s: Add missing stval and mtval.
	* testsuite/gas/riscv/priv-reg.d: Likewise.

	include/
	* opcode/riscv-opc.h (CSR_SBADADDR): Rename to CSR_STVAL.  Rename
	DECLARE_CSR entry.  Add alias to map sbadaddr to CSR_STVAL.
	(CSR_MBADADDR): Rename to CSR_MTVAL.  Rename DECLARE_CSR entry.
	Add alias to map mbadaddr to CSR_MTVAL.
2018-01-04 14:17:53 -08:00
Alan Modra
219d1afa89 Update year range in copyright notice of binutils files 2018-01-03 17:49:56 +10:30
Alan Modra
1e56386871 ChangeLog rotation 2018-01-03 17:49:42 +10:30
Joel Brobecker
e2882c8578 Update copyright year range in all GDB files
gdb/ChangeLog:

        Update copyright year range in all GDB files
2018-01-02 07:38:06 +04:00
Jim Wilson
d9be0c189a RISC-V: Add missing privileged spec registers.
gas/
	* testsuite/gas/riscv/priv-reg.d, testsuite/gas/riscv/priv-reg.s: New.

	include/
	* opcode/riscv-opc.h (DECLARE_CSR): Add missing privileged registers.
	Sort to match privileged spec documentation order.
	(DECLARE_CSR_ALIAS): Add ubadaddr, and comments.
2017-12-28 13:21:46 -08:00
Tamar Christina
00c2093f69 Correct disassembly of dot product instructions.
Dot products deviate from the normal disassembly rules for lane indexed
instruction. Their canonical representation is in the form of:

v0.2s, v0.8b, v0.4b[0] instead of v0.2s, v0.8b, v0.b[0] to try to denote
that these instructions select 4x 1 byte elements instead of a single 1 byte
element.

Previously we were disassembling them following the normal rules, this patch
corrects the disassembly.

gas/

	PR gas/22559
	* config/tc-aarch64.c (vectype_to_qualifier): Support AARCH64_OPND_QLF_S_4B.
	* gas/testsuite/gas/aarch64/dotproduct.d: Update disassembly.

include/

	PR gas/22559
	* aarch64.h (aarch64_opnd_qualifier): Add AARCH64_OPND_QLF_S_4B.

opcodes/

	PR gas/22559
	* aarch64-asm.c (aarch64_ins_reglane): Change AARCH64_OPND_QLF_S_B to
	AARCH64_OPND_QLF_S_4B
	* aarch64-dis.c (aarch64_ext_reglane): Change AARCH64_OPND_QLF_S_B to
	AARCH64_OPND_QLF_S_4B
	* aarch64-opc.c (aarch64_opnd_qualifiers): Add 4b variant.
	* aarch64-tbl.h (QL_V2DOT): Change S_B to S_4B.
2017-12-19 12:21:12 +00:00
Tamar Christina
a3b3345ae6 Add support for V_4B so we can properly reject it.
Previously parse_vector_type_for_operand was changed to allow the use of 4b
register size for indexed lane instructions. However this had the unintended
side effect of also allowing 4b for normal vector registers.

Because this support was only partial the rest of the tool silently treated
4b as 8b and continued. This patch adds full support for 4b so it can be
properly distinguished from 8b and the correct errors are generated.

With this patch you still can't encode any instruction which actually requires
v<num>.4b but such instructions don't exist so to prevent needing a workaround
in get_vreg_qualifier_from_value this was just omitted.

gas/

	PR gas/22529
	* config/tc-aarch64.c (vectype_to_qualifier): Support AARCH64_OPND_QLF_V_4B.
	* gas/testsuite/gas/aarch64/pr22529.s: New.
	* gas/testsuite/gas/aarch64/pr22529.d: New.
	* gas/testsuite/gas/aarch64/pr22529.l: New.

include/

	PR gas/22529
	* opcode/aarch64.h (aarch64_opnd_qualifier): Add AARCH64_OPND_QLF_V_4B.

opcodes/

	PR gas/22529
	* aarch64-opc.c (aarch64_opnd_qualifiers): Add 4b variant.
2017-12-19 12:19:15 +00:00
Stephen Crane
c4e648430f Add plugin API for processing plugin-added input files
Gold plugins may wish to further process an input file added by a plugin. For
example, the plugin may need to assign a unique segment for sections in a
plugin-generated input file. This patch adds a plugin callback that the linker
will call when reading symbols from a new input file added after the
all_symbols_read event (i.e. an input file added by a plugin).

2017-12-11  Stephen Crane  <sjc@immunant.com>

	* plugin-api.h: Add new plugin hook to allow processing of input
	files added by a plugin.
	(ld_plugin_new_input_handler): New function hook type.
	(ld_plugin_register_new_input): New interface.
	(LDPT_REGISTER_NEW_INPUT_HOOK): New enum val.
	(tv_register_new_input): New member.

	* plugin.cc (Plugin::load): Include hooks for register_new_input
	in transfer vector.
	(Plugin::new_input): New function.
	(register_new_input): New function.
	(Plugin_manager::claim_file): Call Plugin::new_input if in
	replacement phase.
	* plugin.h (Plugin::set_new_input_handler): New function.
	* testsuite/plugin_new_section_layout.c: New plugin to test
	new_input plugin API.
	* testsuite/plugin_final_layout.sh: Add new input test.
	* testsuite/Makefile.am (plugin_layout_new_file): New test case.
	* testsuite/Makefile.in: Regenerate.
2017-12-11 14:58:38 -08:00
Peter Bergner
0f873fd58b Use consistent types for holding instructions, instruction masks, etc.
include/
	* opcode/ppc.h (PPC_INT_FMT): Define.
	(struct powerpc_opcode) <opcode>: Update type.
	(struct powerpc_opcode) <mask>: Likewise.
	(struct powerpc_opcode) <bitm>: Likewise.
	(struct powerpc_opcode) <insert>: Likewise.
	(struct powerpc_opcode) <extract>: Likewise.
	(ppc_optional_operand_value): Likewise.

gas/
	* config/tc-ppc.c (last_insn): Update type.
	(insn_validate) <omask, mask>: Likewise.
	(ppc_setup_opcodes) <mask, right_bit>: Likewise.
	<PRINT_OPCODE_TABLE>: Update types and printf format specifiers.
	(ppc_insert_operand): Update return and argument types and remove
	unneeded type casts.
	<min, max, right, tmp>: Update type.
	(md_assemble): Remove unneeded type casts.
	<insn, val, tmp_insn>: Update type.

opcodes/
	* opcodes/ppc-dis.c (disassemble_init_powerpc): Fix white space.
	(operand_value_powerpc): Update return and argument type.
	<value, top>: Update type.
	(skip_optional_operands): Update argument type.
	(lookup_powerpc): Likewise.
	(lookup_vle): Likewise.
	<table_opcd, table_mask, insn2>: Update type.
	(lookup_spe2): Update argument type.
	<table_opcd, table_mask, insn2>: Update type.
	(print_insn_powerpc) <insn, value>: Update type.
	Use PPC_INT_FMT for printing instructions and operands.
	* opcodes/ppc-opc.c (insert_arx, extract_arx, insert_ary, extract_ary,
	insert_rx, extract_rx, insert_ry, extract_ry, insert_bat, extract_bat,
	insert_bba, extract_bba, insert_bdm, extract_bdm, insert_bdp,
	extract_bdp, valid_bo_pre_v2, valid_bo_post_v2, valid_bo, insert_bo,
	extract_bo, insert_boe, extract_boe, insert_dcmxs, extract_dcmxs,
	insert_dxd, extract_dxd, insert_dxdn, extract_dxdn, insert_fxm,
	extract_fxm, insert_li20, extract_li20, insert_ls, extract_ls,
	insert_esync, extract_esync, insert_mbe, extract_mbe, insert_mb6,
	extract_mb6, extract_nb, insert_nbi, insert_nsi, extract_nsi,
	insert_ral, extract_ral, insert_ram, extract_ram, insert_raq,
	extract_raq, insert_ras, extract_ras, insert_rbs, extract_rbs,
	insert_rbx, extract_rbx, insert_sci8, extract_sci8, insert_sci8n,
	extract_sci8n, insert_sd4h, extract_sd4h, insert_sd4w, extract_sd4w,
	insert_oimm, extract_oimm, insert_sh6, extract_sh6, insert_spr,
	extract_spr, insert_sprg, extract_sprg, insert_tbr, extract_tbr,
	insert_xt6, extract_xt6, insert_xtq6, extract_xtq6, insert_xa6,
	extract_xa6, insert_xb6, extract_xb6, insert_xb6s, extract_xb6s,
	insert_xc6, extract_xc6, insert_dm, extract_dm, insert_vlesi,
	extract_vlesi, insert_vlensi, extract_vlensi, insert_vleui,
	extract_vleui, insert_vleil, extract_vleil, insert_evuimm1_ex0,
	extract_evuimm1_ex0, insert_evuimm2_ex0, extract_evuimm2_ex0,
	insert_evuimm4_ex0, extract_evuimm4_ex0, insert_evuimm8_ex0,
	extract_evuimm8_ex0, insert_evuimm_lt8, extract_evuimm_lt8,
	insert_evuimm_lt16, extract_evuimm_lt16, insert_rD_rS_even,
	extract_rD_rS_even, insert_off_lsp, extract_off_lsp, insert_off_spe2,
	extract_off_spe2, insert_Ddd, extract_Ddd): Update types.
	(OP, OPTO, OPL, OPVUP, OPVUPRT, A, AFRALFRC_MASK, B, BD8, BD8IO, BD15,
	BD24, BBO, Y_MASK  , AT1_MASK, AT2_MASK, BBOCB, C_LK, C, CTX, UCTX,
	DX, EVSEL, IA16, I16A, I16L, IM7, LI20, MME, MD, MDS, SC, SC_MASK,
	SCI8, SCI8BF, SD4, SE_IM5, SE_R, SE_RR, VX, VX_LSP, VX_RA_CONST,
	VX_RB_CONST, VX_SPE_CRFD, VX_SPE2_CLR, VX_SPE2_SPLATB, VX_SPE2_OCTET,
	VX_SPE2_DDHH, VX_SPE2_HH, VX_SPE2_EVMAR, VX_SPE2_EVMAR_MASK, VXA,
	VXR, VXASH, X, EX, XX2, XX3, XX3RC, XX4, Z, XWRA_MASK, XLRT_MASK,
	XRLARB_MASK, XLRAND_MASK, XRTLRA_MASK, XRTLRARB_MASK, XRTARARB_MASK,
	XRTBFRARB_MASK, XOPL, XOPL2, XRCL, XRT, XRTRA, XCMP_MASK, XCMPL_MASK,
	XTO, XTLB, XSYNC, XEH_MASK, XDSS, XFL, XISEL, XL, XLO, XLYLK, XLOCB,
	XMBAR, XO, XOPS, XS, XFXM, XSPR, XUC, XW, APU): Update types in casts.
2017-12-01 11:20:15 -06:00
H.J. Lu
276da9b31b Re-apply "elf: Properly compute offsets of note descriptor and next note"
CORE PT_NOTE segments may have p_align values of 0 or 1.  gABI specifies
that PT_NOTE alignment should be aligned to 4 bytes for 32-bit objects
and to 8 bytes for 64-bit objects.  If segment alignment is less than 4,
we use 4 byte alignment.
2017-11-24 14:52:15 -08:00
Simon Marchi
4e25ac038e Revert "elf: Properly compute offsets of note descriptor and next note"
This reverts commit 650444eb54.

With this patch, running the GDB test case gdb.base/auxv.exp is stuck in
an infinite loop, consuming memory to the point that it renders the
machine unusable. I am reverting it so we can take our time to
investigate while not killing all the developers' machines.
2017-11-24 15:43:51 -05:00
H.J. Lu
650444eb54 elf: Properly compute offsets of note descriptor and next note
According to gABI, in a note entry, the note name field, not note name
size, is padded for the note descriptor.  And the note descriptor field,
not note descriptor size, is padded for the next note entry.  Also notes
are aligned to 4 bytes in 32-bit objects and 8 bytes in 64-bit objects.
Since on Linux, .note.ABI-tag and .note.gnu.build-id notes are always
aligned to 4 bytes, we need to use alignment of note section or note
segment, instead of assuming alignment based on ELF file class.

Tested on i686 and x86-64.

bfd/

	PR binutils/22444
	* elf.c (elf_read_notes): Add an argument for note aligment.
	(elf_parse_notes): Likewise.
	(_bfd_elf_make_section_from_shdr): Pass section aligment to
	elf_parse_notes.
	(bfd_section_from_phdr): Pass segment aligment to elf_read_notes.
	(elf_parse_notes): Add an argument for note aligment.  Use
	ELF_NOTE_DESC_OFFSET to get the offset of the note descriptor.
	Use ELF_NOTE_NEXT_OFFSET to get the offset of the next note
	entry.
	(elf_read_notes): Add an argument for note aligment and pass it
	to elf_parse_notes.

binutils/

	PR binutils/22444
	* readelf.c (process_notes_at): Use ELF_NOTE_DESC_OFFSET to get
	the offset of the note descriptor.  Use ELF_NOTE_NEXT_OFFSET to
	get the offset of the next note entry.

include/

	PR binutils/22444
	* elf/external.h (ELF_ALIGN_UP): New.
	(ELF_NOTE_DESC_OFFSET): Likewise.
	(ELF_NOTE_NEXT_OFFSET): Likewise.
2017-11-24 06:41:52 -08:00
Tamar Christina
d0f7791c66 Add new AArch64 FP16 FM{A|S} instructions.
This patch separates the new FP16 instructions backported from Armv8.4-a to Armv8.2-a
into a new flag order to distinguish them from the rest of the already existing optional
FP16 instructions in Armv8.2-a.

The new flag "+fp16fml" is available from Armv8.2-a and implies +fp16 and is mandatory on
Armv8.4-a.

gas/

	* config/tc-aarch64.c (fp16fml): New.
	* doc/c-aarch64.texi (fp16fml): New.
	* testsuite/gas/aarch64/armv8_2-a-crypto-fp16.d (fp16): Make fp16fml.
	* testsuite/gas/aarch64/armv8_3-a-crypto-fp16.d (fp16): Make fp16fml.

include/

	* opcode/aarch64.h: (AARCH64_FEATURE_F16_FML): New.
	(AARCH64_ARCH_V8_4): Enable AARCH64_FEATURE_F16_FML by default.

opcodes/

	* aarch64-tbl.h (aarch64_feature_fp_16_v8_2): Require AARCH64_FEATURE_F16_FML
	and AARCH64_FEATURE_F16.
2017-11-16 16:27:35 +00:00
Tamar Christina
01f4802036 Separate the new FP16 instructions backported from Armv8.4-a to Armv8.2-a into a new flag order to distinguish them from the rest of the already existing optional FP16 instructions in Armv8.2-a.
The new flag "+fp16fml" is available from Armv8.2-a and implies +fp16 and is mandatory
from Armv8.4-a.

gas/

	* config/tc-arm.c (arm_ext_fp16_fml, fp16fml): New.
	(do_neon_fmac_maybe_scalar_long): Use arm_ext_fp16_fml.
	* doc/c-arm.texi (fp16, fp16fml): New.
	* testsuite/gas/arm/armv8_2-a-fp16.d (fp16): Make fp16fml.
	* testsuite/gas/arm/armv8_3-a-fp16.d (fp16): Make fp16fml.
	* testsuite/gas/arm/armv8_2-a-fp16-illegal.d (fp16): Make fp16fml.
	* testsuite/gas/arm/armv8_2-a-fp16-thumb2.d (fp16): Make fp16fml.

include/

	* opcode/arm.h: (ARM_EXT2_FP16_FML): New.
	(ARM_AEXT2_V8_4A): Add ARM_EXT2_FP16_FML.
2017-11-15 15:56:23 +00:00
Jan Beulich
5be87c8fa7 PE: don't corrupt section flags when linking from ELF objects
Linking EFI executables from ELF object files can result in corrupted
COFF section flags if the section's alignment is too high. Issue a
diagnostic in that case, erroring out if this is not a final link, and
make sure only in-range values get written to the output image.

While doing this also make tic80 use the generic alignment macros
instead of custom #ifdef-ary.

No testsuite regressions for the range of COFF/PE targets that actually
cross-build in the first place on x86-64-linux.
2017-11-13 12:26:12 +01:00
Tamar Christina
981b557a48 Enable the Dot Product extension by default for Armv8.4-a.
include/

	* opcode/aarch64.h (AARCH64_ARCH_V8_4): Enable DOTPROD.

gas/testsuite

	* gas/aarch64/dotproduct_armv8_4.s: New.
	* gas/aarch64/dotproduct_armv8_4.d: New.
2017-11-09 16:29:31 +00:00
Tamar Christina
f42f1a1d6c Adds the new Fields and Operand types for the new instructions in Armv8.4-a.
gas/
	* config/tc-aarch64.c (process_omitted_operand):
	Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2
	and AARCH64_OPND_IMM_2.
	(parse_operands): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2,
	AARCH64_OPND_IMM_2, AARCH64_OPND_MASK
	and AARCH64_OPND_ADDR_OFFSET.

include/
	* opcode/aarch64.h:
	(aarch64_opnd): Add AARCH64_OPND_Va, AARCH64_OPND_MASK,
	AARCH64_OPND_IMM_2, AARCH64_OPND_ADDR_OFFSET
	and AARCH64_OPND_SM3_IMM2.
	(aarch64_insn_class): Add cryptosm3 and cryptosm4.
	(arch64_feature_set): Make uint64_t.

opcodes/
	* aarch64-asm.h (ins_addr_offset): New.
	* aarch64-asm.c (aarch64_ins_reglane): Add cryptosm3.
	(aarch64_ins_addr_offset): New.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis.h (ext_addr_offset): New.
	* aarch64-dis.c (aarch64_ext_reglane): Add cryptosm3.
	(aarch64_ext_addr_offset): New.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc.h (aarch64_field_kind): Add FLD_imm6_2,
	FLD_imm4_2 and FLD_SM3_imm2.
	* aarch64-opc.c (fields): Add FLD_imm6_2,
	FLD_imm4_2 and FLD_SM3_imm2.
	(operand_general_constraint_met_p): Add AARCH64_OPND_ADDR_OFFSET.
	(aarch64_print_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2,
	AARCH64_OPND_MASK, AARCH64_OPND_IMM_2 and AARCH64_OPND_ADDR_OFFSET.
	* aarch64-opc-2.c (Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2): New.
	* aarch64-tbl.h
	(aarch64_opcode_table): Add Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2.
2017-11-09 16:29:04 +00:00
Tamar Christina
b6b9ca0c3e Split the ARM Crypto ISA extensions for AES and SHA1+2 into their own options (+aes and +sha2). The reason for the split is because with the introduction of Armv8.4-a the implementation of AES has explicitly been made independent of the implementation of the other crypto extensions.
gas	* config/tc-aarch64.c (aarch64_arch_option_table): Add armv8.4-a.
	(aarch64_features):	Added SM4 and SHA3.

include	* opcode/aarch64.h:
	(AARCH64_FEATURE_V8_4, AARCH64_FEATURE_SM4): New.
	(AARCH64_ARCH_V8_4, AARCH64_FEATURE_SHA3): New.

opcodes	* aarch64-tbl.h
	(aarch64_feature_v8_4, aarch64_feature_crypto_v8_2): New.
	(aarch64_feature_sm4, aarch64_feature_sha3): New.
	(aarch64_feature_fp_16_v8_2): New.
	(ARMV8_4, SHA3, SM4, CRYPTO_V8_2, FP_F16_V8_2): New.
	(V8_4_INSN, CRYPTO_V8_2_INSN): New.
	(SHA3_INSN, SM4_INSN, FP16_V8_2_INSN): New.
2017-11-09 11:21:31 +00:00
Nick Clifton
21b81e67c7 Change the type of the aarch64_feature_set typedef to unsigned long long so that it will work on 32-bit hosts.
* opcode/aarch64.h (aarch64_feature_set): Change type to unsigned
	long long.
2017-11-09 10:28:32 +00:00
Nick Clifton
c0e7cef715 Split the AArch64 Crypto instructions for AES and SHA1+2 into their own options (+aes and +sha2).
The new options are:

	+aes: Enables the AES instructions of Armv8-a,
	      enabled by default with +crypto.

	+sha2: Enables the SHA1 and SHA2 instructions of Armv8-a,
	       enabled by default with +crypto.

These options have been turned on by default when +crypto
is used, as such no breakage is expected.

The reason for the split is because with the introduction of Armv8.4-a
the implementation of AES has explicitly been made independent of the
implementation of the other crypto extensions. Backporting the split does
not break any of the previous requirements and so is safe to do.

gas	* config/tc-aarch64.c
	(aarch64_features): Include AES and SHA2 in CRYPTO.
	Add SHA2 and AES.

include	* opcode/aarch64.h:
	(AARCH64_FEATURE_SHA2, AARCH64_FEATURE_AES): New.

opcodes	* aarch64-tbl.h (aarch64_feature_crypto): Add AES and SHA2.
	(aarch64_feature_sha2, aarch64_feature_aes): New.
	(SHA2, AES): New.
	(AES_INSN, SHA2_INSN): New.
	(pmull, pmull2, aese, aesd, aesmc, aesimc): Change to AES_INS.
	(sha1h, sha1su1, sha256su0, sha1c, sha1p,
	 sha1m, sha1su0, sha256h, sha256h2, sha256su1):
	Change to SHA2_INS.
2017-11-08 14:30:53 +00:00
Jiong Wang
dec41383ff Adds command line support for Armv8.4-A, via the new command line option -march=armv8.4-a. Add support for "+dotprod" ARM feature (required for ARMv8.4-A). Add assembler and disassembler support for new FP16 instructions introduced in Armv8.4-A
gas	* config/tc-arm.c (arm_extensions):
	(arm_archs): New entry for "armv8.4-a".
	Add FPU_ARCH_DOTPROD_NEON_VFP_ARMV8.
	(arm_ext_v8_2): New variable.
	(enum arm_reg_type): New enumeration REG_TYPE_NSD.
	(reg_expected_msgs): New entry for REG_TYPE_NSD.
	(parse_typed_reg_or_scalar): Handle REG_TYPE_NSD.
	(parse_scalar): Support REG_TYPE_VFS.
	(enum operand_parse_code): New enumerations OP_RNSD and OP_RNSD_RNSC.
	(parse_operands): Handle OP_RNSD and OP_RNSD_RNSC.
	(NEON_SHAPE_DEF): New entries for DHH and DHS.
	(neon_scalar_for_fmac_fp16_long): New function to generate Rm encoding
	for new FP16 instructions in ARMv8.2-A.
	(do_neon_fmac_maybe_scalar_long): New function to encode new FP16
	instructions in ARMv8.2-A.
	(do_neon_vfmal): Wrapper function for vfmal.
	(do_neon_vfmsl): Wrapper function for vfmsl.
	(insns): New entries for vfmal and vfmsl.
	* doc/c-arm.texi (-march): Document "armv8.4-a".
	* testsuite/gas/arm/dotprod-mandatory.d: New test.
	* testsuite/gas/arm/armv8_2-a-fp16.s: New test source.
	* testsuite/gas/arm/armv8_2-a-fp16-illegal.s: New test source.
	* testsuite/gas/arm/armv8_2-a-fp16.d: New test.
	* testsuite/gas/arm/armv8_3-a-fp16.d: New test.
	* testsuite/gas/arm/armv8_4-a-fp16.d: New test.
	* testsuite/gas/arm/armv8_2-a-fp16-thumb2.d: New test.
	* testsuite/gas/arm/armv8_2-a-fp16-illegal.d: New test.
	* testsuite/gas/arm/armv8_2-a-fp16-illegal.l: New error file.

opcodes	* arm-dis.c (coprocessor_opcodes): New entries for ARMv8.2-A new
	FP16 instructions, including vfmal.f16 and vfmsl.f16.

include	* opcode/arm.h (ARM_AEXT2_V8_4A): Include Dot Product feature.
	(ARM_EXT2_V8_4A): New macro.
	(ARM_AEXT2_V8_4A): Likewise.
	(ARM_ARCH_V8_4A): Likewise.
2017-11-08 13:15:12 +00:00
Palmer Dabbelt
1270b047fd RISC-V: Add satp as an alias for sptbr
The RISC-V privileged ISA changed the name of sptbr (Supervisor Page
Table Base Register) to satp (Supervisor Address Translation and
Protection) to reflect the fact it could be used for more than just
paging.  This patch adds an alias, as they're the same register.

include/ChangeLog

2017-11-06  Palmer Dabbelt  <palmer@dabbelt.com>

        * opcode/riscv-opc.h (sptbr): Rename to satp.
        (CSR_SPTBR): Rename to CSR_SATP.
        (sptbr): Alias to CSR_SATP.

gas/ChangeLog

2017-11-06  Palmer Dabbelt  <palmer@dabbelt.com>

        * testsuite/gas/riscv/satp.d: New test.
        testsuite/gas/riscv/satp.s: Likewise.
        testsuite/gas/riscv/riscv.exp: Likewise.
        config/tc-riscv.c (md_begin): Handle CSR aliases.
2017-11-07 09:00:37 -08:00
Tamar Christina
0198d5e6fc This patch similarly to the AArch64 one enables Dot Product support by default for the Cortex-A55 and Cortex-A75 which have hardware support for these instructions.
gas	* config/tc-arm.c (arm_cpus):
	Change FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
	into FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD.

include	* opcode/arm.h (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD):
	New macro.
2017-11-07 10:17:21 +00:00
Siddhesh Poyarekar
c05e0c5af3 aarch64: Remove AARCH64_FEATURE_F16 from AARCH64_ARCH_V8_2
The FP16 feature is optional in ARMv8.2, so it is wrong to add it to
the default AARCH64_ARCH_V8_2 feature flags.  This patch makes the
behaviour consistent with that of gcc, which also does not assume FP16
for ARMv8.2.

include/

	* opcode/aarch64.h (AARCH64_ARCH_V8_2): Drop
	AARCH64_FEATURE_F16.
2017-11-02 22:49:32 +05:30
James Bowman
81b42bcab1 FT32B is a new FT32 family member. It has a code compression scheme, which requires the use of linker relaxations. The change is quite large, so submission is in several parts.
Part 2 adds a relaxation pass, which actually implements the code compression scheme.

bfd	* archures.c: Add bfd_mach_ft32b.
	* cpu-ft32.c: Add arch_info_struct.
	* elf32-ft32.c: Add R_FT32_RELAX, SC0, SC1,
	DIFF32. (ft32_elf_relocate_section): Add clauses
	for R_FT32_SC0, SC1, DIFF32.  (ft32_reloc_shortable,
	elf32_ft32_is_diff_reloc, elf32_ft32_adjust_diff_reloc_value,
	elf32_ft32_adjust_reloc_if_spans_insn,
	elf32_ft32_relax_delete_bytes, elf32_ft32_relax_is_branch_target,
	ft32_elf_relax_section): New function.
	* reloc.c: Add BFD_RELOC_FT32_RELAX, SC0, SC1, DIFF32.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Regenerate.

gas	* config/tc-ft32.c (md_assemble): add relaxation reloc
	BFD_RELOC_FT32_RELAX.  (md_longopts): Add "norelax" and
	"no-relax". (md_apply_fix): Add reloc BFD_RELOC_FT32_DIFF32.
	(relaxable_section, ft32_validate_fix_sub, ft32_force_relocation,
	ft32_allow_local_subtract): New function.
	* config/tc-ft32.h: remove unused MD_PCREL_FROM_SECTION.
	* testsuite/gas/ft32/insnsc.s: New test exercising all FT32B
	shortcodes.

include	* elf/ft32.h: Add R_FT32_RELAX, SC0, SC1, DIFF32.
2017-11-01 15:33:24 +00:00
Alan Modra
e5d70d6b5a PR22348, conflicting global vars in crx and cr16
include/
	PR 22348
	* opcode/cr16.h (instruction): Delete.
	(cr16_words, cr16_allWords, cr16_currInsn): Delete.
	* opcode/crx.h (crx_cst4_map): Rename from cst4_map.
	(crx_cst4_maps): Rename from cst4_maps.
	(crx_no_op_insn): Rename from no_op_insn.
	(instruction): Delete.
opcodes/
	PR 22348
	* cr16-dis.c (cr16_cinvs, instruction, cr16_currInsn): Make static.
	(cr16_words, cr16_allWords, processing_argument_number): Likewise.
	(imm4flag, size_changed): Likewise.
	* crx-dis.c (crx_cinvs, NUMCINVS, instruction, currInsn): Likewise.
	(words, allWords, processing_argument_number): Likewise.
	(cst4flag, size_changed): Likewise.
	* crx-opc.c (crx_cst4_map): Rename from cst4_map.
	(crx_cst4_maps): Rename from cst4_maps.
	(crx_no_op_insn): Rename from no_op_insn.
gas/
	PR 22348
	* config/tc-crx.c (instruction, output_opcode): Make static.
	(relocatable, ins_parse, cur_arg_num): Likewise.
	(parse_insn): Adjust for renamed opcodes globals.
	(check_range): Likewise
2017-10-25 22:14:58 +10:30
Andrew Waterman
3342be5dab RISC-V: Only relax to C.LUI when imm != 0 and rd != 0/2
This matches the ISA specification.  This also adds two tests: one to
make sure the assembler rejects invalid 'c.lui's, and one to make sure
we only relax valid 'c.lui's.

bfd/ChangeLog

2017-10-24  Andrew Waterman  <andrew@sifive.com>

        * elfnn-riscv.c (_bfd_riscv_relax_lui): Don't relax to c.lui
        when rd is x0.

include/ChangeLog

2017-10-24  Andrew Waterman  <andrew@sifive.com>

        * opcode/riscv.h (VALID_RVC_LUI_IMM): c.lui can't load the
        immediate 0.

gas/ChangeLog

2017-10-24  Andrew Waterman  <andrew@sifive.com>

        * testsuite/gas/riscv/c-lui-fail.d: New testcase.
        gas/testsuite/gas/riscv/c-lui-fail.l: Likewise.
        gas/testsuite/gas/riscv/c-lui-fail.s: Likewise.
        gas/testsuite/gas/riscv/riscv.exp: Likewise.

ld/ChangeLog

2017-10-24  Andrew Waterman  <andrew@sifive.com>

        * ld/testsuite/ld-riscv-elf/c-lui.d: New testcase.
        ld/testsuite/ld-riscv-elf/c-lui.s: Likewise.
        ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp: New test suite.
2017-10-24 08:02:46 -07:00
James Bowman
3b4b0a629a FT32: support for FT32B processor - part 1
FT32B is a new FT32 family member. It has a code
compression scheme, which requires the use of linker
relaxations. The change is quite large, so submission
is in several parts.

Part 1 adds a 15-bit instruction field, and CPU-specific functions for
the code compression that are used in binutils and GDB.

bfd/ChangeLog:

2017-10-12  James Bowman  <james.bowman@ftdichip.com>

	* bfd-in2.h: Regenerate.
	* libbfd.h: Regenerate.
	* elf32-ft32.c: Add HOWTO R_FT32_15.
	* reloc.c: Add BFD_RELOC_FT32_15.

gas/ChangeLog:

2017-10-12  James Bowman  <james.bowman@ftdichip.com>

	* config/tc-ft32.c (md_assemble): Replace FT32_FLD_K8 with
	K15.
	(md_apply_fix, tc_gen_reloc): Add BFD_RELOC_FT32_15.

include/ChangeLog:

2017-10-12  James Bowman  <james.bowman@ftdichip.com>

	* elf/ft32.h: Add R_FT32_15.
	* opcode/ft32.h: Replace FT32_FLD_K8 with K15.
	(ft32_shortcode, sc_compar, ft32_split_shortcode,
	ft32_merge_shortcode, ft32_merge_shortcode): New functions.

opcodes/ChangeLog:

2017-10-12  James Bowman  <james.bowman@ftdichip.com>

	* opcodes/ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15.
	* opcodes/ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with
	K15. Add jmpix pattern.

sim/ChangeLog:

2017-10-12  James Bowman  <james.bowman@ftdichip.com>

	* sim/ft32/interp.c (step_once): Replace FT32_FLD_K8 with K15.
2017-10-12 18:41:29 -07:00
John Baldwin
12c4bd7f53 Handle FreeBSD-specific AT_EHDRFLAGS and AT_HWCAP auxiliary vector types.
FreeBSD recently added two additional ELF auxiliary vectors.  FreeBSD's
AT_HWCAP uses a different number compared to AT_HWCAP on Linux as the
numerical value was already in use for a different vector on FreeBSD.

include/ChangeLog:

	* elf/common.h (AT_FREEBSD_EHDRFLAGS, AT_FREEBSD_HWCAP): Define.

gdb/ChangeLog:

	* fbsd-tdep.c (fbsd_print_auxv_entry): Handle AT_EHDRFLAGS and
	AT_HWCAP.
2017-10-05 09:50:01 -07:00
Alexandre Oliva
9f27220911 LVU: dump loclists with locviews
When dumping location lists, also dump locview lists that may be
interspersed with them, and bring view pairs next to the corresponding
location list entries.

This patch supports DW_AT_GNU_locviews as a separate attribute for
DWARF4- loc_lists and split (dwo) loclists, as well as DWARF5
loclists.

It also supports, in DWARF5 loclists, the proposed
DW_LLE_GNU_view_pair loclist entry type proposed for DWARF6.


The tests use 32-bit DWARF, even on 64-bit targets, resolving offsets
to constants so as to reduce the risk that relocations be created for
them, or that the offsets be rejected as nonconstants.


The patch also adds an xfail to an unrelated test, namely dw5, so that
no unexpected fails remain on nds32*-elf, one of the tested targets.


Reviewed-by: Alan Modra <amodra@gmail.com>


for  include/ChangeLog

	* dwarf2.def (DW_AT_GNU_locviews): New.
	* dwarf2.h (enum dwarf_location_list_entry_type): Add
	DW_LLE_GNU_view_pair.
	(DW_LLE_view_pair): Define.

for  binutils/ChangeLog

	* dwarf.h (debug_info): Add loc_views and num_loc_views.
	* dwarf.c (vm1): New constant.
	(print_dwarf_view): New function.
	(read_and_display_attr_value): Support DW_AT_GNU_locviews.
	(process_debug_info): Keep num_loc_offsets and num_loc_views
	in sync.
	(display_view_pair_list): New function.
	(display_loc_list_dwo): Take vstart_ptr; update it.  Dump
	location view pairs before the range they apply to, when a
	viewlist augments the loc list.
	(display_loc_list): Likewise.  Check view numbers in range
	tests.
	(display_loclists_list): Likewise.  Handle view pair entries,
	and warn on trailing ones.
	(loc_views): New variable.
	(loc_offsets_compar): Compare loc_views if loc_offsets are the
	same.
	(display_debug_loc): Check and sort loc_views too.  Accept
	loc_view as expected_start.  Skip if lists and views are the
	same.  Dump locview list separately in order, and pass the
	locview list base to each list dump function.  Warn and skip
	overlap and hole checking if we find loclists and locviews to
	not be adjacent.
	* testsuite/binutils-all/locview-1.s: New.
	* testsuite/binutils-all/readelf.locview-1: New.
	* testsuite/binutils-all/locview-2.s: New.
	* testsuite/binutils-all/readelf.locview-2: New.
	* testsuite/binutils-all/readelf.exp: Run new tests.  Fix
	option spelling in pr18374 fail message.  XFAIL dw5 test on
	nds32*-elf.
2017-09-22 17:05:51 -03:00
Pedro Alves
26a67918a5 Sync libiberty/ & include/ with GCC
Note this brings in the interface files for libcc1/G++ as well, which
we will be needing in GDB soon anyway.  That commit renamed a method
in the C interface and that required a small update to GDB's compile/
code, which I've included that in this patch to keep the tree
building.

include/ChangeLog:
2017-09-15  Pedro Alves  <palves@redhat.com>

	* ansidecl.h (DISABLE_COPY_AND_ASSIGN): New macro.

	2017-09-12  Jiong Wang  <jiong.wang@arm.com>

	* dwarf2.def (DW_CFA_AARCH64_negate_ra_state): New DW_CFA_DUP.
	* dwarf2.h (DW_CFA_DUP): New define.

	2017-08-21  Richard Biener  <rguenther@suse.de>

	* simple-object.h (simple_object_copy_lto_debug_sections): New
	function.

	2017-05-18  Martin Liska  <mliska@suse.cz>

	* ansidecl.h: Define CONSTEXPR macro.

	2017-05-24  Nathan Sidwell  <nathan@acm.org>

	* libiberty.h (ASTRDUP): Adjust cast to avoid warning.

	2017-01-30  Alexandre Oliva <aoliva@redhat.com>

	Introduce C++ support in libcc1.
	* gcc-c-fe.def (int_type_v0): Rename from...
	(int_type): ... this.  Introduce new version.
	(float_type_v0): Rename from...
	(float_type): ... this.  Introduce new version.
	(char_type): New.
	* gcc-c-interface.h (gcc_c_api_version): Add GCC_C_FE_VERSION_1.
	(gcc_type_array): Move...
	* gcc-interface.h: ... here.
	* gcc-cp-fe.def: New.
	* gcc-cp-interface.h: New.

	2016-04-29  Oleg Endo  <olegendo@gcc.gnu.org>

	* longlong.h (umul_ppmm): Remove SHMEDIA checks.
	(__umulsidi3, count_leading_zeros): Remove SHMEDIA implementations.

	2017-09-15  Yao Qi  <yao.qi@linaro.org>
	    Pedro Alves  <palves@redhat.com>

	* ansidecl.h (DISABLE_COPY_AND_ASSIGN): New macro.

	2017-09-12  Jiong Wang  <jiong.wang@arm.com>

	* dwarf2.def (DW_CFA_AARCH64_negate_ra_state): New DW_CFA_DUP.
	* dwarf2.h (DW_CFA_DUP): New define.

	2017-08-21  Richard Biener  <rguenther@suse.de>

	* simple-object.h (simple_object_copy_lto_debug_sections): New
	function.

	2017-05-18  Martin Liska  <mliska@suse.cz>

	* ansidecl.h: Define CONSTEXPR macro.

	2017-05-24  Nathan Sidwell  <nathan@acm.org>

	* libiberty.h (ASTRDUP): Adjust cast to avoid warning.

	2017-01-30  Alexandre Oliva <aoliva@redhat.com>

	Introduce C++ support in libcc1.
	* gcc-c-fe.def (int_type_v0): Rename from...
	(int_type): ... this.  Introduce new version.
	(float_type_v0): Rename from...
	(float_type): ... this.  Introduce new version.
	(char_type): New.
	* gcc-c-interface.h (gcc_c_api_version): Add GCC_C_FE_VERSION_1.
	(gcc_type_array): Move...
	* gcc-interface.h: ... here.
	* gcc-cp-fe.def: New.
	* gcc-cp-interface.h: New.

	2016-04-29  Oleg Endo  <olegendo@gcc.gnu.org>

	* longlong.h (umul_ppmm): Remove SHMEDIA checks.
	(__umulsidi3, count_leading_zeros): Remove SHMEDIA implementations.

libiberty/ChangeLog:
2017-09-15  Nathan Sidwell  <nathan@acm.org>

	PR demangler/82195
	* cp-demangle.c (d_name): Add 'toplevel' parm.  Pass to	...
	(d_local_name): ... here.  Parse trailing function args on nested
	local_name.
	(d_encoding, d_special_name, d_class_enum_type): Adjust d_name calls.
	* testsuite/demangle-expected: Add tests.

2017-09-15  Richard Biener  <rguenther@suse.de>

	PR lto/81968
	* simple-object-elf.c (simple_object_elf_copy_lto_debug_sections):
	Iterate marking dependent sections necessary.

2017-09-15  Nathan Sidwell  <nathan@acm.org>

	* cp-demangle.c (is_fnqual_component_type): Reimplement using
	FNQUAL_COMPONENT_CASE.
	(d_encoding): Hold bare_function_type in local var.
	(d_local_name): Build name in both cases and build result once.
	Collapse switch-if to single conditional.
	(d_local_name):

	* testsuite/demangle-expected: Realign blank lines with tests.

2017-09-12  Jiong Wang  <jiong.wang@arm.com>

	* dwarfnames.c (DW_CFA_DUP): New define.

gdb/ChangeLog:
2017-09-15  Pedro Alves  <palves@redhat.com>

	* compile/compile-c-types.c (convert_enum, convert_int)
	(convert_float): Adjust to refer to int_type_v0 and float_type_v0.
2017-09-15 17:40:33 +01:00
Kuan-Lin Chen
4ec521f238 nds32: Rename __BIT() to N32_BIT(). 2017-09-11 13:46:27 +08:00
Alexander Fedotov-B55613
83eef88358 Missing relocation R_PPC_VLE_ADDR20 and add VLE flag to details in readelf
include/
	* elf/ppc.h (R_PPC_VLE_ADDR20): New relocation.
bfd/
	* elf32-ppc.c (ppc_elf_howto_raw): Add R_PPC_VLE_ADDR20.
	(ppc_elf_check_relocs): Handle it.
	(ppc_elf_vle_split20): New function.
	(ppc_elf_relocate_section): Handle R_PPC_VLE_ADDR20.
binutils/
	* readelf.c (get_elf_section_flags): Add VLE.
	(process_section_headers): Add VLE key to details.
gas/
	* config/tc-ppc.c (md_parse_option): Handle "mno-vle" flag.
	(ppc_elf_section_letter): New function.
	* config/tc-ppc.h (md_elf_section_letter): New.
	* testsuite/gas/elf/section10.d: Adjust for VLE.
2017-09-05 08:42:27 +09:30
Alexander Fedotov
7408194835 [PowerPC VLE] Add SPE2 and EFS2 instructions support
include/
	* opcode/ppc.h:
	(spe2_opcodes, spe2_num_opcodes): New.
	(PPC_OPCODE_SPE2): New define.
	(PPC_OPCODE_EFS2): Likewise.
	(SPE2_XOP): Likewise.
	(SPE2_XOP_TO_SEG): Likewise.
opcodes/
	* ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
	PPC_OPCODE_EFS2 flag to "e200z4" entry.
	New entries efs2 and spe2.
	Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
	(SPE2_OPCD_SEGS): New macro.
	(spe2_opcd_indices): New.
	(disassemble_init_powerpc): Handle SPE2 opcodes.
	(lookup_spe2): New function.
	(print_insn_powerpc): call lookup_spe2.
	* ppc-opc.c (insert_evuimm1_ex0): New function.
	(extract_evuimm1_ex0): Likewise.
	(insert_evuimm_lt8): Likewise.
	(extract_evuimm_lt8): Likewise.
	(insert_off_spe2): Likewise.
	(extract_off_spe2): Likewise.
	(insert_Ddd): Likewise.
	(extract_Ddd): Likewise.
	(DD): New operand.
	(EVUIMM_LT8): Likewise.
	(EVUIMM_LT16): Adjust.
	(MMMM): New operand.
	(EVUIMM_1): Likewise.
	(EVUIMM_1_EX0): Likewise.
	(EVUIMM_2): Adjust.
	(NNN): New operand.
	(VX_OFF_SPE2): Likewise.
	(BBB): Likewise.
	(DDD): Likewise.
	(VX_MASK_DDD): New mask.
	(HH): New operand.
	(VX_RA_CONST): New macro.
	(VX_RA_CONST_MASK): Likewise.
	(VX_RB_CONST): Likewise.
	(VX_RB_CONST_MASK): Likewise.
	(VX_OFF_SPE2_MASK): Likewise.
	(VX_SPE_CRFD): Likewise.
	(VX_SPE_CRFD_MASK VX): Likewise.
	(VX_SPE2_CLR): Likewise.
	(VX_SPE2_CLR_MASK): Likewise.
	(VX_SPE2_SPLATB): Likewise.
	(VX_SPE2_SPLATB_MASK): Likewise.
	(VX_SPE2_OCTET): Likewise.
	(VX_SPE2_OCTET_MASK): Likewise.
	(VX_SPE2_DDHH): Likewise.
	(VX_SPE2_DDHH_MASK): Likewise.
	(VX_SPE2_HH): Likewise.
	(VX_SPE2_HH_MASK): Likewise.
	(VX_SPE2_EVMAR): Likewise.
	(VX_SPE2_EVMAR_MASK): Likewise.
	(PPCSPE2): Likewise.
	(PPCEFS2): Likewise.
	(vle_opcodes): Add EFS2 and some missing SPE opcodes.
	(powerpc_macros): Map old SPE instructions have new names
	with the same opcodes. Add SPE2 instructions which just are
	mapped to SPE2.
	(spe2_opcodes): Add SPE2 opcodes.
gas/
	* config/tc-ppc.c:
	(md_parse_option): Add mspe2 switch.
	(md_show_usage): Document -mspe2.
	(ppc_setup_opcodes): Handle spe2_opcodes.
	* doc/as.texinfo: Document -mspe2.
	* doc/c-ppc.texi: Likewise.
	* testsuite/gas/ppc/efs.d: New file.
	* testsuite/gas/ppc/efs.s: Likewise.
	* testsuite/gas/ppc/efs2.d: Likewise.
	* testsuite/gas/ppc/efs2.s: Likewise.
	* testsuite/gas/ppc/ppc.exp: Run new tests.
	* testsuite/gas/ppc/spe.d: New file.
	* testsuite/gas/ppc/spe.s: Likewise.
	* testsuite/gas/ppc/spe2-checks.d: Likewise.
	* testsuite/gas/ppc/spe2-checks.l: Likewise.
	* testsuite/gas/ppc/spe2-checks.s: Likewise.
	* testsuite/gas/ppc/spe2.d: Likewise.
	* testsuite/gas/ppc/spe2.s: Likewise.
	* testsuite/gas/ppc/spe_ambiguous.d: Likewise.
	* testsuite/gas/ppc/spe_ambiguous.s: Likewise.
2017-08-24 17:30:31 +09:30
Jan Kratochvil
6e41ddec97 compile: Add 'set compile-gcc'
As discussed in
	How to use compile & execute function in GDB
	https://sourceware.org/ml/gdb/2015-04/msg00026.html

GDB currently searches for compilers on /usr/bin/ARCH-OS-gcc and
chooses a match from there.  However, it is not currently possible for
the user to override which compiler to use.  This is what this patch
implements.

It is also a sync between GCC's and GDB's interfaces.

gdb/ChangeLog
2017-08-23  Jan Kratochvil  <jan.kratochvil@redhat.com>

	* NEWS (Changes since GDB 7.9): Add set compile-gcc and show
	compile-gcc.
	* compile/compile.c (compile_gcc, show_compile_gcc): New.
	(compile_to_object): Implement compile_gcc.
	(_initialize_compile): Install "set compile-gcc".  Initialize
	compile_gcc.

gdb/doc/ChangeLog
2017-08-23  Jan Kratochvil  <jan.kratochvil@redhat.com>

	* gdb.texinfo (Compiling and Injecting Code): Add to subsection
	"Compiler search for the compile command" descriptions of set
	compile-gcc and show compile-gcc.

include/ChangeLog
2017-08-23  Jan Kratochvil  <jan.kratochvil@redhat.com>

	* gcc-interface.h (enum gcc_base_api_version): Update comment for
	GCC_FE_VERSION_1.
	(struct gcc_base_vtable): Rename set_arguments to set_arguments_v0.
	Add set_arguments, set_triplet_regexp and set_driver_filename.
2017-08-23 11:16:35 -04:00
Jan Kratochvil
e68c32d53e compile: set debug compile: Display GCC driver filename
As discussed in
	How to use compile & execute function in GDB
	https://sourceware.org/ml/gdb/2015-04/msg00026.html

GDB currently searches for compilers on /usr/bin/ARCH-OS-gcc and
chooses a match from there.  However, it is not currently possible for
the user to display which compiler was selected.  Up until now, GDB's
compiler interface was not up-to-date with GCC's one, which means that
it wasn't possible to obtain this information.  This patch implements
the mechanisms necessary for that.

gdb/ChangeLog
2017-08-23  Jan Kratochvil  <jan.kratochvil@redhat.com>

	* compile/compile.c (compile_to_object): Conditionally call
	set_verbose.  Conditionally call compile or compile_v0.

include/ChangeLog
2017-08-23  Jan Kratochvil  <jan.kratochvil@redhat.com>

	* gcc-interface.h (enum gcc_base_api_version): Add
	GCC_FE_VERSION_1.
	(struct gcc_base_vtable): Rename compile to compile_v0.  Update
	comment for compile.  New methods set_verbose and compile.
2017-08-23 11:15:03 -04:00
Alexander Fedotov
e3c2f928b8 [PowerPC VLE] Add LSP (Lightweight Signal Processing) instruction support
include/
	* opcode/ppc.h (PPC_OPCODE_LSP): New define.
opcodes/
	* ppc-opc.c (insert_evuimm2_ex0): New function.
	(extract_evuimm2_ex0): Likewise.
	(insert_evuimm4_ex0): Likewise.
	(extract_evuimm4_ex0): Likewise.
	(insert_evuimm8_ex0): Likewise.
	(extract_evuimm8_ex0): Likewise.
	(insert_evuimm_lt16): Likewise.
	(extract_evuimm_lt16): Likewise.
	(insert_rD_rS_even): Likewise.
	(extract_rD_rS_even): Likewise.
	(insert_off_lsp): Likewise.
	(extract_off_lsp): Likewise.
	(RD_EVEN): New operand.
	(RS_EVEN): Likewise.
	(RSQ): Adjust.
	(EVUIMM_LT16): New operand.
	(HTM_SI): Adjust.
	(EVUIMM_2_EX0): New operand.
	(EVUIMM_4): Adjust.
	(EVUIMM_4_EX0): New operand.
	(EVUIMM_8): Adjust.
	(EVUIMM_8_EX0): New operand.
	(WS): Adjust.
	(VX_OFF): New operand.
	(VX_LSP): New macro.
	(VX_LSP_MASK): Likewise.
	(VX_LSP_OFF_MASK): Likewise.
	(PPC_OPCODE_LSP): Likewise.
	(vle_opcodes): Add LSP opcodes.
	* ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
gas/
	* testsuite/gas/ppc/lsp-checks.d,
	* testsuite/gas/ppc/lsp-checks.l,
	* testsuite/gas/ppc/lsp-checks.s: New test.
	* testsuite/gas/ppc/lsp.d,
	* testsuite/gas/ppc/lsp.s: New test.
	* testsuite/gas/ppc/ppc.exp: Run new tests.
2017-08-21 23:29:13 +09:30
Gustavo Romero
66c3b5f87c Add new NT_PPC_* available since Linux 4.8
Add new note types available since Linux 4.8 to elf/common.h and
make the 'readelf' tool aware of it.

include/
	* elf/common.h (NT_PPC_TAR): New macro.
	(NT_PPC_PPR): Likewise.
	(NT_PPC_DSCR): Likewise.
	(NT_PPC_EBB): Likewise.
	(NT_PPC_PMU): Likewise.
	(NT_PPC_TM_CGPR): Likewise.
	(NT_PPC_TM_CFPR): Likewise.
	(NT_PPC_TM_CVMX): Likewise.
	(NT_PPC_TM_CVSX): Likewise.
	(NT_PPC_TM_SPR): Likewise.
	(NT_PPC_TM_CTAR): Likewise.
	(NT_PPC_TM_CPPR): Likewise.
	(NT_PPC_TM_CDSCR): Likewise.
binutils/
	* readelf.c (get_note_type): Handle PPC note types available
	since Linux 4.8.
2017-08-16 07:45:28 +09:30
H.J. Lu
a4819f54c0 Treat common symbol as undefined for --no-define-common
When --no-define-common is used to build shared library, treat common
symbol as undefined so that common symbols that are referenced from a
shared library to be assigned addresses only in the main program.  This
eliminates the unused duplicate space in the shared library, and also
prevents any possible confusion over resolving to the wrong duplicate
when there are many dynamic modules with specialized search paths for
runtime symbol resolution.

--no-define-common is only allowed when building a shared library.

bfd/

	PR ld/21903:
	* elflink.c (elf_link_add_object_symbols): Treat common symbol
	as undefined for --no-define-common.

include/

	PR ld/21903:
	* bfdlink.h (bfd_link_info): Add inhibit_common_definition.

ld/

	PR ld/21903:
	* ld.h (command_line): Remove inhibit_common_definition.
	* ldgram.y: Replace command_line.inhibit_common_definition with
	link_info.inhibit_common_definition.
	* ldlang.c (lang_common): Likewise.
	* lexsup.c (parse_args): Likewise.
	* ldmain.c (main): Only allow --no-define-common with -shared.
	* testsuite/ld-elf/pr21903.s: New file.
	* testsuite/ld-elf/pr21903a.d: Likewise.
	* testsuite/ld-elf/pr21903b.d: Likewise.
	* testsuite/ld-elf/pr21903c.d: Likewise.
	* testsuite/ld-elf/pr21903d.d: Likewise.
	* testsuite/ld-elf/pr21903e.d: Likewise.
2017-08-06 08:19:04 -07:00
Nick Clifton
c48a4d9834 Fix compile time error when using ansidecl.h with an old version of GCC.
PR 21850
	* ansidecl.h (OVERRIDE): Protect check of __cplusplus value with
	#idef __cplusplus.
2017-07-31 15:08:32 +01:00
Claudiu Zissulescu
7179e0e6b2 [ARC] Add SJLI instruction.
include/
2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>

	* opcode/arc.h (SJLI): Add.

opcode/
2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-opc.c (extract_uimm12_20): New function.
	(UIMM12_20): New operand.
	(SIMM3_5_S): Adjust.
	* arc-tbl.h (sjli): Add new instruction.
2017-07-19 09:56:55 +02:00
John Eric Martin
684d5a10b1 [ARC] Add JLI support.
The following relocation types were added to GCC/binutils:

ARC_JLI_SECTOFF is a relocation type in Metaware that is now used by
GCC as well to adjust the index of function calls to functions with
attribute jli_call_always.

bfd/
2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
	    John Eric Martin  <John.Martin@emmicro-us.com>

	* bfd-in2.h: Regenerate.
	* libbfd.h: Regenerate.
	* elf32-arc.c (JLI): Define.
	* reloc.c: Add JLI relocations.

gas/
2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>

	* testsuite/gas/arc/jli-1.d: New file.
	* testsuite/gas/arc/jli-1.s: Likewise.
	* testsuite/gas/arc/taux.d: Update for jli_base.

include/
2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
	    John Eric Martin  <John.Martin@emmicro-us.com>

	* elf/arc-reloc.def: Add JLI relocs howto.
	* opcode/arc-func.h (replace_jli): New function.

ld/
2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
	    John Eric Martin  <John.Martin@emmicro-us.com>

	* emulparams/arcelf.sh (JLI_START_TABLE): Define.
	* scripttempl/elfarc.sc: Handle jlitab section.
	* scripttempl/elfarcv2.sc: Likewise.
	* testsuite/ld-arc/arc.exp: Add JLI test.
	* testsuite/ld-arc/jli-script.ld: New file.
	* testsuite/ld-arc/jli-simple.dd: Likewise.
	* testsuite/ld-arc/jli-simple.rd: Likewise.
	* testsuite/ld-arc/jli-simple.s: Likewise.
	* testsuite/ld/testsuite/ld-arc/jli-overflow.s: Likewise.
	* testsuite/ld/testsuite/ld-arc/jli-overflow.d: Likewise.
	* testsuite/ld/testsuite/ld-arc/jli-overflow.err: Likewise.

opcode/
2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
	    John Eric Martin  <John.Martin@emmicro-us.com>

	* arc-opc.c (UIMM10_6_S_JLIOFF): Define.
	(UIMM3_23): Adjust accordingly.
	* arc-regs.h: Add/correct jli_base register.
	* arc-tbl.h (jli_s): Likewise.
2017-07-19 09:56:55 +02:00
Yuri Chornovian
de194d8575 Fix spelling typos. 2017-07-18 16:58:14 +01:00
Ravi Bangoria
0f6329bd7f binutils/objdump: Fix disassemble for huge elf sections
When elf section size is beyond unsigned int max value, objdump fails
to disassemble from that section. Ex on PowerPC,

  $ objdump -h /proc/kcore
    Idx  Name   Size       VMA
      4  load2  100000000  c000000000000000

Here, size of load2 section is 0x100000000. Also note that, 0xc00....
address range is kernel space for PowerPC. Now let's try to disassemble
do_sys_open() using /proc/kcore.

  $ cat /proc/kallsyms | grep -A1 -w do_sys_open
    c00000000036c000 T do_sys_open
    c00000000036c2d0 T SyS_open

Before patch:

  $ objdump -d --start-address=0xc00000000036c000 --stop-address=0xc00000000036c2d0 /proc/kcore
    /proc/kcore:    file format elf64-powerpcle

    Disassembly of section load2:

    c00000000036c000 <load2+0x36c000>:
    c00000000036c000:    Address 0xc00000000036c000 is out of bounds.

Fix this by changing type of 'buffer_length' from unsigned int to
size_t. After patch:

  $ objdump -d --start-address=0xc00000000036c000 --stop-address=0xc00000000036c2d0 /proc/kcore
    /proc/kcore:    file format elf64-powerpcle

    Disassembly of section load2:

    c00000000036c000 <load2+0x36c000>:
    c00000000036c000: fc 00 4c 3c     addis   r2,r12,252
    c00000000036c004: 00 53 42 38     addi    r2,r2,21248
    c00000000036c008: a6 02 08 7c     mflr    r0

include/
	* dis-asm.h (struct disassemble_info): Change type of buffer_length
	field to size_t.
opcodes/
	* dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
	max_addr_offset and octets variables to size_t.
2017-07-14 22:51:01 +09:30
John Baldwin
0b9305edf1 Recognize the recently-added FreeBSD core dump note for LWP info.
This core dump note contains the same information returned by the
ptrace PT_LWPINFO operation for each LWP belonging to a process.

binutils/ChangeLog:

	* readelf.c (get_freebsd_elfcore_note_type): Handle
	NT_FREEBSD_PTLWPINFO.

include/ChangeLog:

	* elf/common.h (NT_FREEBSD_PTLWPINFO): Define.
2017-07-07 16:10:47 -07:00
Jan Kratochvil
de837d77bc Import include/+libiberty/ r249883 from upstream GCC.
include/ChangeLog
2017-07-02  Jan Kratochvil  <jan.kratochvil@redhat.com>

	* dwarf2.def (DW_IDX_compile_unit, DW_IDX_type_unit, DW_IDX_die_offset)
	(DW_IDX_parent, DW_IDX_type_hash, DW_IDX_lo_user, DW_IDX_hi_user)
	(DW_IDX_GNU_internal, DW_IDX_GNU_external): New.
	* dwarf2.h (DW_IDX, DW_IDX_DUP, DW_FIRST_IDX, DW_END_IDX): New.
	(enum dwarf_name_index_attribute): Remove.
	(get_DW_IDX_name): New declaration.

libiberty/ChangeLog
2017-07-02  Jan Kratochvil  <jan.kratochvil@redhat.com>

	* dwarfnames.c (DW_FIRST_IDX, DW_END_IDX, DW_IDX, DW_IDX_DUP): New.
2017-07-02 22:09:52 +02:00
Georg-Johann Lay
32f76c6773 Add support for a __gcc_isr pseudo isntruction to the AVR assembler.
PR gas/21683
include * opcode/avr.h (AVR_INSN): Add one for __gcc_isr.

gas * doc/c-avr.texi (AVR Options) <-mgcc-isr>: Document it.
    (AVR Pseudo Instructions): New node.
    * config/tc-avr.h (md_pre_output_hook): Define to avr_pre_output_hook.
    (md_undefined_symbol): Define to avr_undefined_symbol.
    (avr_pre_output_hook, avr_undefined_symbol): New protos.
    * config/tc-avr.c (struc-symbol.h): Include it.
    (ISR_CHUNK_Done, ISR_CHUNK_Prologue, ISR_CHUNK_Epilogue): New enums.
    (avr_isr, avr_gccisr_opcode)
    (avr_no_sreg_hash, avr_no_sreg): New static variables.
    (avr_opt_s) <have_gccisr>: Add field.
    (avr_opt): Add initializer for have_gccisr.
    (enum options) <OPTION_HAVE_GCCISR>: Add enum.
    (md_longopts) <"mgcc-isr">: Add entry.
    (md_show_usage): Document -mgcc-isr.
    (md_parse_option) [OPTION_HAVE_GCCISR]: Handle it.
    (md_undefined_symbol): Remove.
    (avr_undefined_symbol, avr_pre_output_hook): New fuctions.
    (md_begin) <avr_no_sreg_hash, avr_gccisr_opcode>: Initialize them.
    (avr_operand) <pregno>: Add argument and set *pregno if function
    is called for a register constraint.
    [N]: Handle constraint.
    (avr_operands) <avr_operand>: Pass 5th parameter to calls.
    [avr_opt.have_gccisr]: Call avr_update_gccisr.  Call
    avr_gccisr_operands instead of avr_operands.
    (avr_update_gccisr, avr_emit_insn, avr_patch_gccisr_frag)
    (avr_gccisr_operands, avr_check_gccisr_done): New static functions.
    * testsuite/gas/avr/gccisr-01.d: New test.
    * testsuite/gas/avr/gccisr-01.s: New test.
    * testsuite/gas/avr/gccisr-02.d: New test.
    * testsuite/gas/avr/gccisr-02.s: New test.
    * testsuite/gas/avr/gccisr-03.d: New test.
    * testsuite/gas/avr/gccisr-03.s: New test.
2017-06-30 16:37:39 +01:00
Maciej W. Rozycki
9785fc2a4d MIPS: Fix XPA base and Virtualization ASE instruction handling
Correct a commit 7d64c587c1 ("Add support for the MIPS eXtended
Physical Address (XPA) ASE.") bug, causing XPA base and Virtualization
ASE instructions to be wrongly always enabled with the selection of the
MIPS32r2 or higher ISA.

For example this source assembles successfully as shown below:

$ cat xpa.s
	mfhc0	$2, $1
$ as -32 -mips32 -o xpa.o xpa.s
xpa.s: Assembler messages:
xpa.s:1: Error: opcode not supported on this processor: mips32 (mips32) `mfhc0 $2,$1'
$ as -32 -mips32r2 -o xpa.o xpa.s
$ objdump -d xpa.o

xpa.o:     file format elf32-tradbigmips

Disassembly of section .text:

00000000 <.text>:
   0:	40420800 	mfhc0	v0,c0_random
	...
$

To address this issue remove the I33 (INSN_ISA32R2) marking from all XPA
instructions in the opcode table.  Additionally, for XPA Virtualization
ASE instructions implement an XPAVZ (ASE_XPA_VIRT) combination ASE flag
and use it in place of IVIRT|XPA (ASE_VIRT|ASE_XPA).

Now the same source is correctly rejected unless the `-mxpa' option is
also used:

$ as -32 -mips32r2 -o xpa.o xpa.s
xpa.s: Assembler messages:
xpa.s:1: Error: opcode not supported on this processor: mips32r2 (mips32r2) `mfhc0 $2,$1'
$ as -32 -mips32r2 -mxpa -o xpa.o xpa.s
$

Add test cases for XPA base and XPA Virtualization ASE instructions.

Parts of this change by Andrew Bennett.

	include/
	* opcode/mips.h (ASE_XPA_VIRT): New macro.

	opcodes/
	* mips-dis.c (mips_calculate_combination_ases): Handle the
	ASE_XPA_VIRT flag.
	(parse_mips_ase_option): New function.
	(parse_mips_dis_option): Factor out ASE option handling to the
	new function.  Call `mips_calculate_combination_ases'.
	* mips-opc.c (XPAVZ): New macro.
	(mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
	"mfhgc0", "mthc0" and "mthgc0".

	gas/
	* config/tc-mips.c (mips_set_ase): Handle the ASE_XPA_VIRT flag.
	* testsuite/gas/mips/xpa.d: Remove `xpa' from `-M' in `objdump'
	flags.  Add `-mvirt' to `as' flags.
	* testsuite/gas/mips/xpa-err.d: New test.
	* testsuite/gas/mips/xpa-virt-err.d: New test.
	* testsuite/gas/mips/xpa-err.l: New stderr output.
	* testsuite/gas/mips/xpa-virt-err.l: New stderr output.
	* testsuite/gas/mips/xpa-err.s: New test source.
	* testsuite/gas/mips/xpa-virt-err.s: New test source.
	* testsuite/gas/mips/mips.exp: Run the new tests.

	binutils/
	* testsuite/binutils-all/mips/mips-xpa-virt-1.d: New test.
	* testsuite/binutils-all/mips/mips-xpa-virt-2.d: New test.
	* testsuite/binutils-all/mips/mips-xpa-virt-3.d: New test.
	* testsuite/binutils-all/mips/mips-xpa-virt-4.d: New test.
	* testsuite/binutils-all/mips/mips-xpa-virt.s: New test source.
	* testsuite/binutils-all/mips/mips.exp: Run the new tests.
2017-06-30 07:21:55 +01:00
Andreas Arnez
88ab90e860 S390: Support guarded-storage core note sections
Newer Linux kernel versions offer two new register sets in support of the
z/Architecture's guarded storage facility: NT_S390_GS_CB, the
"guarded-storage registers", and NT_S390_GS_BC, the "guarded-storage
broadcast control block".  This patch adds support for the respective core
notes sections to binutils.

bfd/ChangeLog:
	* elf-bfd.h (elfcore_write_s390_gs_cb): Add prototype.
	(elfcore_write_s390_gs_bc): Likewise.
	* elf.c (elfcore_grok_s390_gs_cb): New function.
	(elfcore_grok_s390_gs_bc): New function.
	(elfcore_grok_note): Call them.
	(elfcore_write_s390_gs_cb): New function.
	(elfcore_write_s390_gs_bc): New function.
	(elfcore_write_register_note): Call them.

binutils/ChangeLog:
	* readelf.c (get_note_type): Add NT_S390_GS_CB and NT_S390_GS_BC.

include/ChangeLog:
	* elf/common.h (NT_S390_GS_CB): New macro.
	(NT_S390_GS_BC): Likewise.
2017-06-29 10:30:09 +02:00
Tamar Christina
65a55fbbd9 [AArch64] Add dot product support for AArch64 to binutils
gas/
	* config/tc-aarch64.c (aarch64_reg_parse_32_64): Accept 4B.
	(aarch64_features): Added dotprod.
	* doc/c-aarch64.texi: Added dotprod.
	* testsuite/gas/aarch64/dotproduct.d: New.
	* testsuite/gas/aarch64/dotproduct.s: New.

opcodes/
	* aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
	* aarch64-dis.c (aarch64_ext_reglane): Likewise.
	* aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
	(aarch64_feature_dotprod, DOT_INSN): New.
	(udot, sdot): New.
	* aarch64-dis-2.c: Regenerated.

include/
	* opcode/aarch64.h: (AARCH64_FEATURE_DOTPROD): New.
	(aarch64_insn_class): Added dotprod.
2017-06-28 11:09:01 +01:00