Commit Graph

2229 Commits

Author SHA1 Message Date
Jiong Wang
c604a79ad4 [ARM] Assembler and disassembler support Dot Product Extension
This patch add assembler and disassembler support for new Dot Product
  Extension.

  The support can be enabled through the new "+dotprod" extension.

include/
	* opcode/arm.h (FPU_NEON_EXT_DOTPROD): New macro.
	(FPU_ARCH_DOTPROD_NEON_VFP_ARMV8): New macro.

gas/
	* config/tc-arm.c (fpu_neon_ext_dotprod): New variable.
	(neon_scalar_for_mul): Improve comments.
	(do_neon_dotproduct): New function to encode Dot Product instructions.
	(do_neon_dotproduct_s): Wrapper function for signed Dot Product
	instructions.
	(do_neon_dotproduct_u): Wrapper function for unsigned Dot Product
	instructions.
	(insns): New entries for vsdot and vudot.
	(arm_extensions): New entry for "dotprod".
	* doc/c-arm.texi: Document new "dotprod" extension.
	* testsuite/gas/arm/dotprod.s: New test source.
	* testsuite/gas/arm/dotprod-illegal.s: New test source.
	* testsuite/gas/arm/dotprod.d: New test.
	* testsuite/gas/arm/dotprod-thumb2.d: New test.
	* testsuite/gas/arm/dotprod-illegal.d: New test.
	* testsuite/gas/arm/dotprod-legacy-arch.d: New test.
	* testsuite/gas/arm/dotprod-illegal.l: New error file.
	* testsuite/gas/arm/dotprod-legacy-arch.l: New error file.

opcodes/
	* arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
2017-06-28 11:00:55 +01:00
Maciej W. Rozycki
38bf472a15 MIPS: Add Imagination interAptiv MR2 MIPS32r3 processor support
Add support for the Imagination interAptiv MR2 MIPS32r3 processor with
the MIPS16e2 ASE as per documentation, including in particular:

1. Support for implementation-specific interAptiv MR2 COPYW and UCOPYW
   MIPS16e2 instructions[1], for assembly and disassembly,

2. Support for implementation-specific interAptiv MR2 SAVE and RESTORE
   regular MIPS instructions[2], for assembly and disassembly,

3. ELF binary file annotation for the interAptiv MR2 MIPS architecture
   extension.

4. Support for interAptiv MR2 architecture selection for assembly, in
   the form of the `-march=interaptiv-mr2' command-line option and its
   corresponding `arch=interaptiv-mr2' setting for the `.set' and
   `.module' pseudo-ops.

5. Support for interAptiv MR2 architecture selection for disassembly,
   in the form of the `mips:interaptiv-mr2' target architecture, for
   use e.g. with the `-m' command-line option for `objdump'.

Parts of this change by Matthew Fortune and Andrew Bennett.

References:

[1] "MIPS32 interAptiv Multiprocessing System Software User's Manual",
    Imagination Technologies Ltd., Document Number: MD00904, Revision
    02.01, June 15, 2016, Section 24.3 "MIPS16e2 Implementation Specific
    Instructions", pp. 878-883

[2] same, Chapter 25 "Implementation-specific Instructions", pp. 911-917

	include/
	* elf/mips.h (E_MIPS_MACH_IAMR2): New macro.
	(AFL_EXT_INTERAPTIV_MR2): Likewise.
	* opcode/mips.h: Document new operand codes defined.
	(INSN_INTERAPTIV_MR2): New macro.
	(INSN_CHIP_MASK): Adjust accordingly.
	(CPU_INTERAPTIV_MR2): New macro.
	(cpu_is_member) <CPU_INTERAPTIV_MR2>: New case.
	(MIPS16_ALL_ARGS): Rename to...
	(MIPS_SVRS_ALL_ARGS): ... this.
	(MIPS16_ALL_STATICS): Rename to...
	(MIPS_SVRS_ALL_STATICS): ... this.

	bfd/
	* archures.c (bfd_mach_mips_interaptiv_mr2): New macro.
	* cpu-mips.c (I_interaptiv_mr2): New enum value.
	(arch_info_struct): Add "mips:interaptiv-mr2" entry.
	* elfxx-mips.c (_bfd_elf_mips_mach) <E_MIPS_MACH_IAMR2>: New
	case.
	(mips_set_isa_flags) <bfd_mach_mips_interaptiv_mr2>: Likewise.
	(bfd_mips_isa_ext) <bfd_mach_mips_interaptiv_mr2>: Likewise.
	(print_mips_isa_ext) <AFL_EXT_INTERAPTIV_MR2>: Likewise.
	(mips_mach_extensions): Add `bfd_mach_mipsisa32r3' and
	`bfd_mach_mips_interaptiv_mr2' entries.
	* bfd-in2.h: Regenerate.

	opcodes/
	* mips-formats.h (INT_BIAS): New macro.
	(INT_ADJ): Redefine in INT_BIAS terms.
	* mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
	(mips_print_save_restore): New function.
	(print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
	(validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
	call.
	(print_insn_args): Handle OP_SAVE_RESTORE_LIST.
	(print_mips16_insn_arg): Call `mips_print_save_restore' for
	OP_SAVE_RESTORE_LIST handling, factored out from here.
	* mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
	(RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
	(mips_builtin_opcodes): Add "restore" and "save" entries.
	* mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
	(IAMR2): New macro.
	(mips16_opcodes): Add "copyw" and "ucopyw" entries.

	binutils/
	* readelf.c (get_machine_flags) <E_MIPS_MACH_IAMR2>: New case.
	(print_mips_isa_ext) <AFL_EXT_INTERAPTIV_MR2>: Likewise.
	* NEWS: Mention Imagination interAptiv MR2 processor support.

	gas/
	* config/tc-mips.c (validate_mips_insn): Handle
	OP_SAVE_RESTORE_LIST specially.
	(mips_encode_save_restore, mips16_encode_save_restore): New
	functions.
	(match_save_restore_list_operand): Factor out SAVE/RESTORE
	operand insertion into the instruction word or halfword to these
	new functions.
	(mips_cpu_info_table): Add "interaptiv-mr2" entry.

	* doc/c-mips.texi (MIPS Options): Add `interaptiv-mr2' to the
	`-march=' argument list.
2017-06-28 02:07:36 +01:00
Kuan-Lin Chen
a6cbf936e3 RISC-V: Use pc-relative relocation for FDE initial location
The symbol address in .eh_frame may be adjusted in
_bfd_elf_discard_section_eh_frame, and the content of .eh_frame will be
adjusted in _bfd_elf_write_section_eh_frame. Therefore, we cannot insert
a relocation whose addend symbol is in .eh_frame. Othrewise, the value
may be adjusted twice.

bfd/ChangeLog
2017-06-26  Kuan-Lin Chen  <rufus@andestech.com>

	* elfnn-riscv.c (perform_relocation): Support the new
	R_RISCV_32_PCREL relocation.
	(riscv_elf_relocate_section): Likewise.
	* elfxx-riscv.c (howto_table): Likewise.
	(riscv_reloc_map): Likewise.
	* bfd-in2.h (BFD_RELOC_RISCV_32_PCREL): New relocation.
	* libbfd.h: Regenerate.

gas/ChangeLog
2017-06-26  Kuan-Lin Chen  <rufus@andestech.com>

	* config/tc-riscv.c (md_apply_fix) [BFD_RELOC_32]: Convert to a
	R_RISCV_32_PCREL relocation.

include/ChangeLog
2017-06-26  Kuan-Lin Chen  <rufus@andestech.com>

	* elf/riscv.h (R_RISCV_32_PCREL): New.
2017-06-26 18:26:40 -07:00
Andreas Krebbel
fd52715cfa Add pgste marker changelog 2017-06-26 11:07:17 +02:00
Thomas Preud'homme
ced40572e4 [ARM] Add support for ARMv8-R in assembler and readelf
=== Context ===

This patch is part of a patch series to add support for ARMv8-R
architecture. Its purpose is to add support for ARMv8-R in GAS:
instructions, build attributes and readelf.

=== Patch description ===

Although some differences exist for system registers, from GAS point of
view ARMv8-R supports the same instructions as ARMv8-A Aarch32 state
and a subset of its extensions. This patch therefore introduce a new
feature bit to distinguish the availability of the pan, ras and rdma
extensions between ARMv8-A and ARMv8-R and allow crypto, fp and simd
extensions to be used by ARMv8-R.

Most of the changes are then in the testsuite to (i) rename source files
and error output to be shared between ARMv8-A and ARMv8-R, (ii) rename
files with expected output for ARMv8-A build attributes and (iii) add
new files with expected output for ARMv8-R build attributes.

2017-06-24  Thomas Preud'homme  <thomas.preudhomme@arm.com>

binutils/
	* readelf.c (arm_attr_tag_CPU_arch): Fill value for ARMv8-R.

gas/
	* NEWS: Mention support for ARMv8-R architecture.
	* config/tc-arm.c (arm_archs): Add entry for ARMv8-R.
	(arm_extensions): Restrict pan, ras and rdma extension to
	ARMv8-A and make crypto, fp and simd extensions available to
	ARMv8-R.
	(cpu_arch_ver): Add entry for ARMv8-R.
	(aeabi_set_public_attributes): Update gas_assert for Tag_DIV_use
	logic.
	* testsuite/gas/arm/armv8-a+fp.s: Rename into ...
	* testsuite/gas/arm/armv8-ar+fp.s: This.  Remove .arch directive.
	* testsuite/gas/arm/armv8-a+fp.d: Specify source to assemble and
	architecture to assemble for.
	* testsuite/gas/arm/armv8-r+fp.d: New.
	* testsuite/gas/arm/armv8-a+simd.s: Rename into ...
	* testsuite/gas/arm/armv8-ar+simd.s: This.  Remove .arch directive.
	* testsuite/gas/arm/armv8-a+simd.d: Specify source to assemble and
	architecture to assemble for.
	* testsuite/gas/arm/armv8-r+simd.d: New.
	* testsuite/gas/arm/armv8-a-bad.s: Rename into ...
	* testsuite/gas/arm/armv8-ar-bad.s: This.  Remove .arch directive.
	* testsuite/gas/arm/armv8-a-bad.l: Rename into ...
	* testsuite/gas/arm/armv8-ar-bad.l: This.  Decrement line number by 1.
	* testsuite/gas/arm/armv8-a-bad.d: Specify source to assemble,
	architecture to assemble for and adjust error output file.
	* testsuite/gas/arm/armv8-r-bad.d: New.
	* testsuite/gas/arm/armv8-a-barrier.s: Rename into ...
	* testsuite/gas/arm/armv8-ar-barrier.s: This.
	* testsuite/gas/arm/armv8-a-barrier-arm.d: Adjust source.
	* testsuite/gas/arm/armv8-a-barrier-thumb.d: Likewise.
	* testsuite/gas/arm/armv8-r-barrier-arm.d: New.
	* testsuite/gas/arm/armv8-r-barrier-thumb.d: New.
	* testsuite/gas/arm/armv8-a-it-bad.s: Rename into ...
	* testsuite/gas/arm/armv8-ar-it-bad.s: This.  Remove .arch directive.
	* testsuite/gas/arm/armv8-a-it-bad.l: Rename into ...
	* testsuite/gas/arm/armv8-ar-it-bad.l: This.  Decrement line number
	by 1.
	* testsuite/gas/arm/armv8-a-it-bad.d: Specify source to assemble,
	architecture to assemble for and adjust error output file.
	* testsuite/gas/arm/armv8-r-it-bad.d: New.
	* testsuite/gas/arm/armv8-a.s: Rename into ...
	* testsuite/gas/arm/armv8-ar.s: This.  Remove .arch directive.
	* testsuite/gas/arm/armv8-a.d: Specify source to assemble and
	architecture to assemble for.
	* testsuite/gas/arm/armv8-r.d: New.
	* testsuite/gas/arm/attr-march-armv8-r+crypto.d: New.
	* testsuite/gas/arm/attr-march-armv8-r+fp.d: New.
	* testsuite/gas/arm/attr-march-armv8-r+simd.d: New.
	* testsuite/gas/arm/attr-march-armv8-r.d: New.
	* testsuite/gas/arm/crc32.s: Rename into ...
	* testsuite/gas/arm/crc32-armv8-ar.s: This.
	* testsuite/gas/arm/crc32.d: Rename into ...
	* testsuite/gas/arm/crc32-armv8-a.d: This.  Specify source to assemble.
	* testsuite/gas/arm/crc32-armv8-r.d: New.
	* testsuite/gas/arm/crc32-bad.s: Rename into ...
	* testsuite/gas/arm/crc32-armv8-ar-bad.s: This.
	* testsuite/gas/arm/crc32-bad.d: Rename into ...
	* testsuite/gas/arm/crc32-armv8-a-bad.d: This.  Specify source to
	assemble.
	* testsuite/gas/arm/crc32-armv8-r-bad.d: New.
	* testsuite/gas/arm/mask_1.s: Rename into ...
	* testsuite/gas/arm/mask_1-armv8-ar.s: This.
	* testsuite/gas/arm/mask_1.d: Rename into ...
	* testsuite/gas/arm/mask_1-armv8-a.d: This.  Specify source to
	assemble.
	* testsuite/gas/arm/mask_1-armv8-r.d: new.

include/
	* elf/arm.h (TAG_CPU_ARCH_V8R): New macro.
	* opcode/arm.h (ARM_EXT2_V8A): New macro.
	(ARM_AEXT2_V8A): Rename into ...
	(ARM_AEXT2_V8AR): This.
	(ARM_AEXT2_V8A): New macro.
	(ARM_AEXT_V8R): New macro.
	(ARM_AEXT2_V8R): New macro.
	(ARM_ARCH_V8R): New macro.
2017-06-24 10:37:47 +01:00
Thomas Preud'homme
173205ca33 [ARM] Remove ARMv6S-M special casing
=== Context ===

This patch is part of a patch series to add support for ARMv8-R
architecture. Its purpose is to remove special casing for ARMv6S-M
autodetection.

=== Motivation ===

Currently, SWI and SVC mnemonics are enabled for ARMv4T and successor
architectures with extra checks in the handler function (do_t_swi) to
give an error message when ARMv6-M is targeted and some more special
casing in aeabi_set_public_attributes. This was made to exclude these
mnemonics for ARMv6-M unless the OS extension is in use.

However this logic is superfluous: there is already code to check
whether an instruction is available based on the feature bit it is part
of and whether the targeted architecture has that feature bit. This
patch aims at removing that unneeded complexity.

=== Patch description ===

The OS extension is already limited to the ARMv6-M architecture so all
this patch does is redefined availability of the ARM_EXT_OS feature bit
to not be present for ARM_ARCH_V6M. ARM_ARCH_V6SM does not need any
change either because it already includes ARM_EXT_OS.

The patch also make sure that the error message that was given by
do_t_swi when SWI/SVC is unavailable is still the same by detecting the
situation in md_assemble.

2017-06-24  Thomas Preud'homme  <thomas.preudhomme@arm.com>

gas/
	* config/tc-arm.c (arm_ext_v6m): Delete.
	(arm_ext_v7m): Delete.
	(arm_ext_m): Remove ARM_EXT_OS from the set of feature defined M
	profile.
	(arm_arch_v6m_only): Delete.
	(do_t_swi): Remove special case for ARMv6S-M.
	(md_assemble): Display error message previously in do_t_swi when
	SVC is not available.
	(insns): Guard swi and svc by arm_ext_os for Thumb mode.
	(aeabi_set_public_attributes): Remove special case for ARMv6S-M.

include/
	* opcode/arm.h (ARM_AEXT_V4TxM): Add ARM_EXT_OS bit to the set.
	(ARM_AEXT_V4T): Likewise.
	(ARM_AEXT_V5TxM): Likewise.
	(ARM_AEXT_V5T): Likewise.
	(ARM_AEXT_V6M): Mask off ARM_EXT_OS bit.
2017-06-24 10:26:41 +01:00
Andreas Krebbel
b4cbbe8f72 S/390: Add support for pgste marker
This patch adds a new S/390 specific segment type: PT_S390_PGSTE.  For
binaries marked with that segment the kernel will allocate 4k page
tables.  The only user so far will be qemu.

ld/ChangeLog:

2017-06-23  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* Makefile.in: Add s390.em as build dependency.
	* emulparams/elf64_s390.sh (EXTRA_EM_FILE): Add s390.em.
	* emultempl/s390.em: New file.
	* gen-doc.texi: Add documentation for --s390-pgste option.
	* ld.texinfo: Likewise.

include/ChangeLog:

2017-06-23  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* elf/s390.h (PT_S390_PGSTE): Define macro.

binutils/ChangeLog:

2017-06-23  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* readelf.c (get_s390_segment_type): Add support for the new
	segment type PT_S390_PGSTE.
	(get_segment_type): Call get_s390_segment_type.

elfcpp/ChangeLog:

2017-06-23  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* elfcpp.h (enum PT): Add PT_S390_PGSTE to enum.

bfd/ChangeLog:

2017-06-23  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* elf-s390.h: New file.
	* elf64-s390.c (struct elf_s390_link_hash_table): Add params
	field.
	(elf_s390_additional_program_headers): New function.
	(elf_s390_modify_segment_map): New function.
	(bfd_elf_s390_set_options): New function.
	(elf_backend_additional_program_headers)
	(elf_backend_modify_segment_map): Add macro definitions.
2017-06-23 08:00:46 +02:00
H.J. Lu
48580982ef x86: Support Intel Shadow Stack with SHSTK property
To support Intel Shadow Stack (SHSTK) in Intel Control-flow Enforcement
Technology (CET) instructions:

https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf

 #define GNU_PROPERTY_X86_FEATURE_1_SHSTK (1U << 1)

is added to GNU program properties to indicate that all executable sections
are compatible with SHSTK where return address popped from shadow stack
always matches return address popped from normal stack.

GNU_PROPERTY_X86_FEATURE_1_SHSTK is set on output only if it is set on all
relocatable inputs.

bfd/

	* elf32-i386.c (elf_i386_merge_gnu_properties): If info->shstk
	is set, turn on GNU_PROPERTY_X86_FEATURE_1_SHSTK.
	(elf_i386_link_setup_gnu_properties): If info->shstk is set,
	turn on GNU_PROPERTY_X86_FEATURE_1_IBT.
	* elf64-x86-64.c (elf_x86_64_merge_gnu_properties): If
	info->shstk is set, turn on GNU_PROPERTY_X86_FEATURE_1_SHSTK.
	(elf_x86_64_link_setup_gnu_properties): If info->shstk is set,
	turn on GNU_PROPERTY_X86_FEATURE_1_IBT.

binutils/

	* readelf.c (decode_x86_feature): Decode
	GNU_PROPERTY_X86_FEATURE_1_SHSTK.
	* testsuite/binutils-all/i386/shstk.d: New file.
	* testsuite/binutils-all/i386/shstk.s: Likewise.
	* testsuite/binutils-all/x86-64/shstk-x32.d: Likewise.
	* testsuite/binutils-all/x86-64/shstk.d: Likewise.
	* testsuite/binutils-all/x86-64/shstk.s: Likewise.

include/

	* bfdlink.h (bfd_link_info): Add shstk.
	* elf/common.h (GNU_PROPERTY_X86_FEATURE_1_SHSTK): New.

ld/

	* NEWS: Mention -z shstk and GNU_PROPERTY_X86_FEATURE_1_SHSTK.
	* emulparams/cet.sh (PARSE_AND_LIST_OPTIONS_CET): Add "-z shstk".
	(PARSE_AND_LIST_ARGS_CASE_Z_CET): Support "-z shstk".
	* ld.texinfo: Document -z shstk.
	* testsuite/ld-i386/i386.exp: Run SHSTK tests.
	* testsuite/ld-x86-64/x86-64.exp: Likewise.
	* testsuite/ld-i386/property-x86-shstk.s: New file.
	* testsuite/ld-i386/property-x86-shstk1a.d: Likewise.
	* testsuite/ld-i386/property-x86-shstk1b.d: Likewise.
	* testsuite/ld-i386/property-x86-shstk2.d: Likewise.
	* testsuite/ld-i386/property-x86-shstk3a.d: Likewise.
	* testsuite/ld-i386/property-x86-shstk3b.d: Likewise.
	* testsuite/ld-i386/property-x86-shstk4.d: Likewise.
	* testsuite/ld-i386/property-x86-shstk5.d: Likewise.
	* testsuite/ld-x86-64/property-x86-shstk.s: Likewise.
	* testsuite/ld-x86-64/property-x86-shstk1a-x32.d: Likewise.
	* testsuite/ld-x86-64/property-x86-shstk1a.d: Likewise.
	* testsuite/ld-x86-64/property-x86-shstk1b-x32.d: Likewise.
	* testsuite/ld-x86-64/property-x86-shstk1b.d: Likewise.
	* testsuite/ld-x86-64/property-x86-shstk2-x32.d: Likewise.
	* testsuite/ld-x86-64/property-x86-shstk2.d: Likewise.
	* testsuite/ld-x86-64/property-x86-shstk3a-x32.d: Likewise.
	* testsuite/ld-x86-64/property-x86-shstk3a.d: Likewise.
	* testsuite/ld-x86-64/property-x86-shstk3b-x32.d: Likewise.
	* testsuite/ld-x86-64/property-x86-shstk3b.d: Likewise.
	* testsuite/ld-x86-64/property-x86-shstk4-x32.d: Likewise.
	* testsuite/ld-x86-64/property-x86-shstk4.d: Likewise.
	* testsuite/ld-x86-64/property-x86-shstk5-x32.d: Likewise.
	* testsuite/ld-x86-64/property-x86-shstk5.d: Likewise.
2017-06-22 05:50:31 -07:00
H.J. Lu
ee2fdd6f36 x86: Support Intel IBT with IBT property and IBT-enable PLT
To support IBT in Intel Control-flow Enforcement Technology (CET)
instructions:

https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf

 #define GNU_PROPERTY_X86_FEATURE_1_AND 0xc0000002

 #define GNU_PROPERTY_X86_FEATURE_1_IBT (1U << 0)

are added to GNU program properties to indicate that all executable
sections are compatible with IBT when ENDBR instruction starts each
valid target where an indirect branch instruction can land.

GNU_PROPERTY_X86_FEATURE_1_IBT is set on output only if it is set on
all relocatable inputs.

The followings changes are made to the Procedure Linkage Table (PLT):

1. For 64-bit x86-64,  PLT is changed to

PLT0:  push       GOT[1]
       bnd jmp    *GOT[2]
       nop
...
PLTn:  endbr64
       push       namen_reloc_index
       bnd jmp    PLT0

together with the second PLT section:

PLTn:  endbr64
       bnd jmp   *GOT[namen_index]
       nop

BND prefix is also added so that IBT-enabled PLT is compatible with MPX.

2. For 32-bit x86-64 (x32) and i386,  PLT is changed to

PLT0:  push       GOT[1]
       jmp        *GOT[2]
       nop
...
PLTn:  endbr64                                 # endbr32 for i386.
       push       namen_reloc_index
       jmp        PLT0

together with the second PLT section:

PLTn:  endbr64                                 # endbr32 for i386.
       jmp       *GOT[namen_index]
       nop

BND prefix isn't used since MPX isn't supported on x32 and BND registers
aren't used in parameter passing on i386.

GOT is an array of addresses.  Initially, GOT[namen_index] is filled
with the address of the ENDBR instruction of the corresponding entry
in the first PLT section.  The function, namen, is called via the
ENDBR instruction in the second PLT entry.  GOT[namen_index] is updated
to the actual address of the function, namen, at run-time.

2 linker command line options are added:

1. -z ibtplt: Generate IBT-enabled PLT.
2. -z ibt: Generate GNU_PROPERTY_X86_FEATURE_1_IBT in GNU program
properties as well as IBT-enabled PLT.

bfd/

	* elf32-i386.c (elf_i386_lazy_ibt_plt0_entry): New.
	(elf_i386_lazy_ibt_plt_entry): Likewise.
	(elf_i386_pic_lazy_ibt_plt0_entry): Likewise.
	(elf_i386_non_lazy_ibt_plt_entry): Likewise.
	(elf_i386_pic_non_lazy_ibt_plt_entry): Likewise.
	(elf_i386_eh_frame_lazy_ibt_plt): Likewise.
	(elf_i386_lazy_plt_layout): Likewise.
	(elf_i386_non_lazy_plt_layout): Likewise.
	(elf_i386_link_hash_entry): Add plt_second.
	(elf_i386_link_hash_table): Add plt_second and
	plt_second_eh_frame.
	(elf_i386_allocate_dynrelocs): Use the second PLT if needed.
	(elf_i386_size_dynamic_sections): Use .plt.got unwind info for
	the second PLT.  Check the second PLT.
	(elf_i386_relocate_section): Use the second PLT to resolve
	PLT reference if needed.
	(elf_i386_finish_dynamic_symbol): Fill and use the second PLT if
	needed.
	(elf_i386_finish_dynamic_sections): Set sh_entsize on the
	second PLT.  Generate unwind info for the second PLT.
	(elf_i386_plt_type): Add plt_second.
	(elf_i386_get_synthetic_symtab): Support the second PLT.
	(elf_i386_parse_gnu_properties): Support
	GNU_PROPERTY_X86_FEATURE_1_AND.
	(elf_i386_merge_gnu_properties): Support
	GNU_PROPERTY_X86_FEATURE_1_AND.  If info->ibt is set, turn
	on GNU_PROPERTY_X86_FEATURE_1_IBT
	(elf_i386_link_setup_gnu_properties): If info->ibt is set,
	turn on GNU_PROPERTY_X86_FEATURE_1_IBT.  Use IBT-enabled PLT
	for info->ibtplt, info->ibt or GNU_PROPERTY_X86_FEATURE_1_IBT
	is set on all relocatable inputs.
	* elf64-x86-64.c (elf_x86_64_lazy_ibt_plt_entry): New.
	(elf_x32_lazy_ibt_plt_entry): Likewise.
	(elf_x86_64_non_lazy_ibt_plt_entry): Likewise.
	(elf_x32_non_lazy_ibt_plt_entry): Likewise.
	(elf_x86_64_eh_frame_lazy_ibt_plt): Likewise.
	(elf_x32_eh_frame_lazy_ibt_plt): Likewise.
	(elf_x86_64_lazy_ibt_plt): Likewise.
	(elf_x32_lazy_ibt_plt): Likewise.
	(elf_x86_64_non_lazy_ibt_plt): Likewise.
	(elf_x32_non_lazy_ibt_plt): Likewise.
	(elf_x86_64_get_synthetic_symtab): Support the second PLT.
	(elf_x86_64_parse_gnu_properties): Support
	GNU_PROPERTY_X86_FEATURE_1_AND.
	(elf_x86_64_merge_gnu_properties): Support
	GNU_PROPERTY_X86_FEATURE_1_AND.  If info->ibt is set, turn
	on GNU_PROPERTY_X86_FEATURE_1_IBT
	(elf_x86_64_link_setup_gnu_properties): If info->ibt is set,
	turn on GNU_PROPERTY_X86_FEATURE_1_IBT.  Use IBT-enabled PLT
	for info->ibtplt, info->ibt or GNU_PROPERTY_X86_FEATURE_1_IBT
	is set on all relocatable inputs.

binutils/

	* readelf.c (decode_x86_feature): New.
	(print_gnu_property_note): Call decode_x86_feature on
	GNU_PROPERTY_X86_FEATURE_1_AND.
	* testsuite/binutils-all/i386/empty.d: New file.
	* testsuite/binutils-all/i386/empty.s: Likewise.
	* testsuite/binutils-all/i386/ibt.d: Likewise.
	* testsuite/binutils-all/i386/ibt.s: Likewise.
	* testsuite/binutils-all/x86-64/empty-x32.d: Likewise.
	* testsuite/binutils-all/x86-64/empty.d: Likewise.
	* testsuite/binutils-all/x86-64/empty.s: Likewise.
	* testsuite/binutils-all/x86-64/ibt-x32.d: Likewise.
	* testsuite/binutils-all/x86-64/ibt.d: Likewise.
	* testsuite/binutils-all/x86-64/ibt.s: Likewise.

include/

	* bfdlink.h (bfd_link_info): Add ibtplt and ibt.
	* elf/common.h (GNU_PROPERTY_X86_FEATURE_1_AND): New.
	(GNU_PROPERTY_X86_FEATURE_1_IBT): Likewise.

ld/

	* Makefile.am (ELF_X86_DEPS): Add $(srcdir)/emulparams/cet.sh.
	* Makefile.in: Regenerated.
	* NEWS: Mention GNU_PROPERTY_X86_FEATURE_1_IBT, -z ibtplt
	and -z ibt.
	* emulparams/cet.sh: New file.
	* testsuite/ld-i386/ibt-plt-1.d: Likewise.
	* testsuite/ld-i386/ibt-plt-1.s: Likewise.
	* testsuite/ld-i386/ibt-plt-2.s: Likewise.
	* testsuite/ld-i386/ibt-plt-2a.d: Likewise.
	* testsuite/ld-i386/ibt-plt-2b.d: Likewise.
	* testsuite/ld-i386/ibt-plt-2c.d: Likewise.
	* testsuite/ld-i386/ibt-plt-2d.d: Likewise.
	* testsuite/ld-i386/ibt-plt-3.s: Likewise.
	* testsuite/ld-i386/ibt-plt-3a.d: Likewise.
	* testsuite/ld-i386/ibt-plt-3b.d: Likewise.
	* testsuite/ld-i386/ibt-plt-3c.d: Likewise.
	* testsuite/ld-i386/ibt-plt-3d.d: Likewise.
	* testsuite/ld-i386/plt-main-ibt.dd: Likewise.
	* testsuite/ld-i386/plt-pie-ibt.dd: Likewise.
	* testsuite/ld-i386/property-x86-empty.s: Likewise.
	* testsuite/ld-i386/property-x86-ibt.s: Likewise.
	* testsuite/ld-i386/property-x86-ibt1a.d: Likewise.
	* testsuite/ld-i386/property-x86-ibt1b.d: Likewise.
	* testsuite/ld-i386/property-x86-ibt2.d: Likewise.
	* testsuite/ld-i386/property-x86-ibt3a.d: Likewise.
	* testsuite/ld-i386/property-x86-ibt3b.d: Likewise.
	* testsuite/ld-i386/property-x86-ibt4.d: Likewise.
	* testsuite/ld-i386/property-x86-ibt5.d: Likewise.
	* testsuite/ld-x86-64/ibt-plt-1-x32.d: Likewise.
	* testsuite/ld-x86-64/ibt-plt-1.d: Likewise.
	* testsuite/ld-x86-64/ibt-plt-1.s: Likewise.
	* testsuite/ld-x86-64/ibt-plt-2.s: Likewise.
	* testsuite/ld-x86-64/ibt-plt-2a-x32.d: Likewise.
	* testsuite/ld-x86-64/ibt-plt-2a.d: Likewise.
	* testsuite/ld-x86-64/ibt-plt-2b-x32.d: Likewise.
	* testsuite/ld-x86-64/ibt-plt-2b.d: Likewise.
	* testsuite/ld-x86-64/ibt-plt-2c-x32.d: Likewise.
	* testsuite/ld-x86-64/ibt-plt-2c.d: Likewise.
	* testsuite/ld-x86-64/ibt-plt-2d-x32.d: Likewise.
	* testsuite/ld-x86-64/ibt-plt-2d.d: Likewise.
	* testsuite/ld-x86-64/ibt-plt-3.s: Likewise.
	* testsuite/ld-x86-64/ibt-plt-3a-x32.d: Likewise.
	* testsuite/ld-x86-64/ibt-plt-3a.d: Likewise.
	* testsuite/ld-x86-64/ibt-plt-3b-x32.d: Likewise.
	* testsuite/ld-x86-64/ibt-plt-3b.d: Likewise.
	* testsuite/ld-x86-64/ibt-plt-3c-x32.d: Likewise.
	* testsuite/ld-x86-64/ibt-plt-3c.d: Likewise.
	* testsuite/ld-x86-64/ibt-plt-3d-x32.d: Likewise.
	* testsuite/ld-x86-64/ibt-plt-3d.d: Likewise.
	* testsuite/ld-x86-64/plt-main-ibt-now.rd: Likewise.
	* testsuite/ld-x86-64/plt-main-ibt-x32.dd: Likewise.
	* testsuite/ld-x86-64/plt-main-ibt.dd: Likewise.
	* testsuite/ld-x86-64/property-x86-empty.s: Likewise.
	* testsuite/ld-x86-64/property-x86-ibt.s: Likewise.
	* testsuite/ld-x86-64/property-x86-ibt1a-x32.d: Likewise.
	* testsuite/ld-x86-64/property-x86-ibt1a.d: Likewise.
	* testsuite/ld-x86-64/property-x86-ibt1b-x32.d: Likewise.
	* testsuite/ld-x86-64/property-x86-ibt1b.d: Likewise.
	* testsuite/ld-x86-64/property-x86-ibt2-x32.d: Likewise.
	* testsuite/ld-x86-64/property-x86-ibt2.d: Likewise.
	* testsuite/ld-x86-64/property-x86-ibt3a-x32.d: Likewise.
	* testsuite/ld-x86-64/property-x86-ibt3a.d: Likewise.
	* testsuite/ld-x86-64/property-x86-ibt3b-x32.d: Likewise.
	* testsuite/ld-x86-64/property-x86-ibt3b.d: Likewise.
	* testsuite/ld-x86-64/property-x86-ibt4-x32.d: Likewise.
	* testsuite/ld-x86-64/property-x86-ibt4.d: Likewise.
	* testsuite/ld-x86-64/property-x86-ibt5-x32.d: Likewise.
	* testsuite/ld-x86-64/property-x86-ibt5.d: Likewise.
	* emulparams/elf32_x86_64.sh: Source emulparams/cet.sh.
	(TINY_READONLY_SECTION): Add .plt.sec.
	* emulparams/elf_i386.sh: Likewise.
	* emulparams/elf_x86_64.sh: Source emulparams/cet.sh.
	* ld.texinfo: Document -z ibtplt and -z ibt.
	* testsuite/ld-i386/i386.exp: Run IBT and IBT PLT tests.
	* testsuite/ld-x86-64/x86-64.exp: Likewise.
	* testsuite/ld-x86-64/pr21481b.S (check): Updated for x32.
2017-06-22 05:44:53 -07:00
Thomas Preud'homme
2c6b98ea6f [ARM] Rework Tag_CPU_arch build attribute value selection
=== Context ===

This patch is part of a patch series to add support for ARMv8-R
architecture. Its purpose is to rework the Tag_CPU_arch build attribute
value selection to (i) match architecture or CPU if specified by user
without any need for hack and (ii) match an architecture with all the
features used if in autodetection mode or return an error.

=== Motivation ===

Currently, Tag_CPU_arch build attribute value selection assumes that an
architecture is always a superset of architectures released earlier. As
such, the logic is to browse architectures in chronological order of
release and selecting the Tag_CPU_arch value of the last one to
contribute a feature used[1]/requested[2] not contributed by earlier
architectures.

[1] in case of autodetection mode
[2] otherwise, ie. in case of -mcpu/-march or associated directives

This logic fails the two objectives mentionned in the Context section.
First, due to the assumption it does an architecture can be selected
while not having all the features used/requested which fails the second
objective. Second, not doing an exact match when an architecture or CPU
is selected by the user means the wrong value is chosen when a later
architecture provides a subset of the feature bits of an earlier
architecture. This is the case for the implementation of ARMv8-R (see
later patch).

An added benefit of this patch is that it is possible to easily generate
more consistent build attribute by setting the feature bits from the
architecture matched in aeabi_set_public_attributes in autodetection
mode. This is better done as a separate patch because lots of testcase'
expected results must then be updated accordingly.

=== Patch description ===

The patch changes the main logic for Tag_CPU_arch and
Tag_CPU_arch_profile
values selection to:
- look for an exact match in case an architecture or CPU was specified
  on the command line or in a directive
- select the first released architecture that provides a superset of the
  feature used in the autodetection case
- select the most featureful architecture in case of -march=all
The array cpu_arch_ver is updated to include all architectures in order
to make the first point work.

Note that when looking for an exact match, the architecture with
selected extension is tried first and then only the architecture. This
is because some architectures are exactly equivalent to an earlier
architecture with its extensions selected. ARMv6S-M (= ARMv6-M + OS
extension) and ARMv6KZ (ARMv6K + security extension) are two such
examples.

Other adjustments are also necessary in aeabi_set_public_attributes to
make this change work.

1) The logic to set Tag_ARM_ISA_use and Tag_THUMB_ISA_use must check the
absence of feature bit used/requested to decide whether to give the
default value for empty files (see EABI attribute defaults test). It was
previously checking that arch == 0 which would only happen if no feature
bit could be matched by any architecture, ie there is no feature bit to
match.

2) A fallback to a superset match must exist when no_cpu_selected ()
returns true. This is because aeabi_set_public_attributes is called
again after relaxation and at this point selected_cpu is set from the
previous execution of that function. There is therefore no way to check
whether the user specified an architecture or CPU.

3) Tag_CPU_arch lines are removed from expected output when the
detected architecture should be pre-ARMv4, since 0 is the Tag_CPU_arch
value for pre-ARMv4 architectures and default value for an absent entry
is 0.

2017-06-21  Thomas Preud'homme  <thomas.preudhomme@arm.com>

gas/
	* config/tc-arm.c (fpu_any): Defined from FPU_ANY.
	(cpu_arch_ver): Add all architectures and sort by release date.
	(have_ext_for_needed_feat_p): New.
	(get_aeabi_cpu_arch_from_fset): New.
	(aeabi_set_public_attributes): Call above function to determine
	Tag_CPU_arch and Tag_CPU_arch_profile values.  Adapt Tag_ARM_ISA_use
	and Tag_THUMB_ISA_use selection logic to check absence of feature bit
	accordingly.
	* testsuite/gas/arm/attr-march-armv1.d: Fix expected Tag_CPU_arch build
	attribute value.
	* testsuite/gas/arm/attr-march-armv2.d: Likewise.
	* testsuite/gas/arm/attr-march-armv2a.d: Likewise.
	* testsuite/gas/arm/attr-march-armv2s.d: Likewise.
	* testsuite/gas/arm/attr-march-armv3.d: Likewise.
	* testsuite/gas/arm/attr-march-armv3m.d: Likewise.
	* testsuite/gas/arm/pr12198-2.d: Likewise.

include/
	* opcode/arm.h (FPU_ANY): New macro.
2017-06-21 16:42:01 +01:00
Alan Modra
7dba9362c1 Rewrite __start and __stop symbol handling
This arranges for __start and __stop symbols to be defined before
garbage collection, for all target formats.  That should allow the
COFF and PE --gc-sections to keep a singleton orphan input section,
a feature lost by 2017-06-13 commit cbd0eecf26.  The fancier ELF
treatment of keeping all input sections associated with a __start or
__stop symbol, from 2015-10-23 commit 1cce69b9dc, is retained.

.startof. and .sizeof. symbols are deliberately not defined before
garbage collection, so these won't affect garbage collection of
sections.

The patch also ensures __start, __stop, .startof. and .sizeof. symbols
are defined before target size_dynamic_sections is called, albeit
with a preliminary value, so that target code doesn't need to cope
with a symbol changing from undefined at size_dynamic_sections to
defined at relocate_section.

Also, a number of problems with the testcases have been fixed.

	PR ld/20022
	PR ld/21557
	PR ld/21562
	PR ld/21571
include/
	* bfdlink.h (struct bfd_link_hash_entry): Delete undef.section.
bfd/
	* targets.c (struct bfd_target): Add _bfd_define_start_stop.
	(BFD_JUMP_TABLE_LINK): Likewise.
	* elf-bfd.h (bfd_elf_define_start_stop): Declare.
	* elflink.c (_bfd_elf_gc_mark_rsec): Update comment.
	(bfd_elf_define_start_stop): New function.
	* linker.c (bfd_generic_define_start_stop): New function.
	* coff64-rs6000.c (rs6000_xcoff64_vec, rs6000_xcoff64_aix_vec): Init
	new field.
	* aout-adobe.c (aout_32_bfd_define_start_stop): Define.
	* aout-target.h (MY_bfd_define_start_stop): Define.
	* aout-tic30.c (MY_bfd_define_start_stop): Define.
	* binary.c (binary_bfd_define_start_stop): Define.
	* bout.c (b_out_bfd_define_start_stop): Define.
	* coff-alpha.c (_bfd_ecoff_bfd_define_start_stop): Define.
	* coff-mips.c (_bfd_ecoff_bfd_define_start_stop): Define.
	* coff-rs6000.c (_bfd_xcoff_bfd_define_start_stop): Define.
	* coffcode.h (coff_bfd_define_start_stop): Define.
	* elfxx-target.h (bfd_elfNN_bfd_define_start_stop): Define.
	* i386msdos.c (msdos_bfd_define_start_stop): Define.
	* i386os9k.c (os9k_bfd_define_start_stop): Define.
	* ieee.c (ieee_bfd_define_start_stop): Define.
	* ihex.c (ihex_bfd_define_start_stop): Define.
	* libbfd-in.h (_bfd_nolink_bfd_define_start_stop): Define.
	* mach-o-target.c (bfd_mach_o_bfd_define_start_stop): Define.
	* mmo.c (mmo_bfd_define_start_stop): Define.
	* nlm-target.h (nlm_bfd_define_start_stop): Define.
	* oasys.c (oasys_bfd_define_start_stop): Define.
	* pef.c (bfd_pef_bfd_define_start_stop): Define.
	* plugin.c (bfd_plugin_bfd_define_start_stop): Define.
	* ppcboot.c (ppcboot_bfd_define_start_stop): Define.
	* som.c (som_bfd_define_start_stop): Define.
	* srec.c (srec_bfd_define_start_stop): Define.
	* tekhex.c (tekhex_bfd_define_start_stop): Define.
	* versados.c (versados_bfd_define_start_stop): Define.
	* vms-alpha.c (vms_bfd_define_start_stop): Define.
	(alpha_vms_bfd_define_start_stop): Define.
	* xsym.c (bfd_sym_bfd_define_start_stop): Define.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Regenerate.
ld/
	* emultempl/elf32.em (gld${EMULATION_NAME}_after_open): Don't set
	__start/__stop syms here.
	* ldlang.c (lang_set_startof): Delete.
	(start_stop_syms, start_stop_count, start_stop_alloc): New vars.
	(lang_define_start_stop, lang_init_start_stop, foreach_start_stop,
	undef_start_stop, lang_undef_start_stop, lang_init_startof_sizeof,
	set_start_stop, lang_finalize_start_stop): New functions.
	(lang_process): Call _start_stop functions.
	* testsuite/ld-elf/pr21562a.d: Use xfail rather than notarget.
	Correct typos and list of xfail targets.
	* testsuite/ld-elf/pr21562b.d: Likewise.
	* testsuite/ld-elf/pr21562c.d: Likewise.
	* testsuite/ld-elf/pr21562d.d: Likewise.
	* testsuite/ld-elf/pr21562e.d: Likewise.
	* testsuite/ld-elf/pr21562f.d: Likewise.
	* testsuite/ld-elf/pr21562g.d: Likewise.
	* testsuite/ld-elf/pr21562h.d: Likewise.
	* testsuite/ld-elf/pr21562i.d: Likewise.
	* testsuite/ld-elf/pr21562j.d: Likewise.
	* testsuite/ld-elf/pr21562k.d: Likewise.
	* testsuite/ld-elf/pr21562l.d: Likewise.
	* testsuite/ld-elf/pr21562m.d: Likewise.
	* testsuite/ld-elf/pr21562n.d: Likewise.
	* testsuite/ld-elf/sizeofa.d: Likewise.  Adjust to pass for generic ELF.
	* testsuite/ld-elf/sizeofb.d: Likewise.
	* testsuite/ld-elf/startofa.d: Likewise.
	* testsuite/ld-elf/startofb.d: Likewise.
2017-06-16 23:38:28 +09:30
Yao Qi
6394c60699 Don't use print_insn_XXX in GDB
This is a follow-up to

  [PATCH 0/6] Unify the disassembler selection in gdb and objdump
  https://sourceware.org/ml/binutils/2017-05/msg00192.html

that is, opcodes is able to select the right disassembler, so gdb
doesn't have to select them.  Instead, gdb can just use
default_print_insn.  As a result, these print_insn_XXX are not used
out of opcodes, so this patch also moves their declarations from
include/dis-asm.h to opcodes/disassemble.h.  With this change,
GDB doesn't use any print_insn_XXX directly any more.

gdb:

2017-06-14  Yao Qi  <yao.qi@linaro.org>

	* aarch64-tdep.c (aarch64_gdb_print_insn): Call
	default_print_insn instead of print_insn_aarch64.
	* arm-tdep.c (gdb_print_insn_arm): Call
	default_print_insn instead of print_insn_big_arm
	and print_insn_little_arm.
	* i386-tdep.c (i386_print_insn): Call default_print_insn
	instead of print_insn_i386.
	* ia64-tdep.c (ia64_print_insn): Call
	default_print_insn instead of print_insn_ia64.
	* mips-tdep.c (gdb_print_insn_mips): Call
	default_print_insn instead of print_insn_big_mips
	and print_insn_little_mips.
	* spu-tdep.c (gdb_print_insn_spu): Call default_print_insn
	instead of print_insn_spu.

include:

2017-06-14  Yao Qi  <yao.qi@linaro.org>

	* dis-asm.h (print_insn_aarch64): Move it to opcodes/disassemble.h.
	(print_insn_big_arm, print_insn_big_mips): Likewise.
	(print_insn_i386, print_insn_ia64): Likewise.
	(print_insn_little_arm, print_insn_little_mips): Likewise.
	(print_insn_spu): Likewise.

opcodes:

2017-06-14  Yao Qi  <yao.qi@linaro.org>

	* aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
	* arm-dis.c: Likewise.
	* ia64-dis.c: Likewise.
	* mips-dis.c: Likewise.
	* spu-dis.c: Likewise.
	* disassemble.h (print_insn_aarch64): New declaration, moved from
	include/dis-asm.h.
	(print_insn_big_arm, print_insn_big_mips): Likewise.
	(print_insn_i386, print_insn_ia64): Likewise.
	(print_insn_little_arm, print_insn_little_mips): Likewise.
2017-06-14 16:29:01 +01:00
Andrew Burgess
7bdf4127c3 ld: Allow section groups to be resolved as part of a relocatable link
This commit adds a new linker feature: the ability to resolve section
groups as part of a relocatable link.

Currently section groups are automatically resolved when performing a
final link, and are carried through when performing a relocatable link.
By carried through this means that one copy of each section group (from
all the copies that might be found in all the input files) is placed
into the output file.  Sections that are part of a section group will
not match input section specifiers within a linker script and are
forcibly kept as separate sections.

There is a slight resemblance between section groups and common
section.  Like section groups, common sections are carried through when
performing a relocatable link, and resolved (allocated actual space)
only at final link time.

However, with common sections there is an ability to force the linker to
allocate space for the common sections when performing a relocatable
link, there's currently no such ability for section groups.

This commit adds such a mechanism.  This new facility can be accessed in
two ways, first there's a command line switch --force-group-allocation,
second, there's a new linker script command FORCE_GROUP_ALLOCATION.  If
one of these is used when performing a relocatable link then the linker
will resolve the section groups as though it were performing a final
link, the section group will be deleted, and the members of the group
will be placed like normal input sections.  If there are multiple copies
of the group (from multiple input files) then only one copy of the group
members will be placed, the duplicate copies will be discarded.

Unlike common sections that have the --no-define-common command line
flag, and INHIBIT_COMMON_ALLOCATION linker script command there is no
way to prevent group resolution during a final link, this is because the
ELF gABI specifically prohibits the presence of SHT_GROUP sections in a
fully linked executable.  However, the code as written should make
adding such a feature trivial, setting the new resolve_section_groups
flag to false during a final link should work as you'd expect.

bfd/ChangeLog:

	* elf.c (_bfd_elf_make_section_from_shdr): Don't initially mark
	SEC_GROUP sections as SEC_EXCLUDE.
	(bfd_elf_set_group_contents): Replace use of abort with an assert.
	(assign_section_numbers): Use resolve_section_groups flag instead
	of relocatable link type.
	(_bfd_elf_init_private_section_data): Use resolve_section_groups
	flag instead of checking the final_link flag for part of the
	checks in here.  Fix white space as a result.
	* elflink.c (elf_link_input_bfd): Use resolve_section_groups flag
	instead of relocatable link type.
	(bfd_elf_final_link): Likewise.

include/ChangeLog:

	* bfdlink.h (struct bfd_link_info): Add new resolve_section_groups
	flag.

ld/ChangeLog:

	* ld.h (struct args_type): Add force_group_allocation field.
	* ldgram.y: Add support for FORCE_GROUP_ALLOCATION.
	* ldlex.h: Likewise.
	* ldlex.l: Likewise.
	* lexsup.c: Likewise.
	* ldlang.c (unique_section_p): Check resolve_section_groups flag
	not the relaxable link flag.
	(lang_add_section): Discard section groups when we're resolving
	groups.  Clear the SEC_LINK_ONCE flag if we're resolving section
	groups.
	* ldmain.c (main): Initialise resolve_section_groups flag in
	link_info based on command line flags.
	* testsuite/ld-elf/group11.d: New file.
	* testsuite/ld-elf/group12.d: New file.
	* testsuite/ld-elf/group12.ld: New file.
	* NEWS: Mention new features.
	* ld.texinfo (Options): Document --force-group-allocation.
	(Miscellaneous Commands): Document FORCE_GROUP_ALLOCATION.
2017-06-06 09:53:38 +01:00
Alan Modra
f378ab099d PPC64_OPT_LOCALENTRY
ELFv2 functions with localentry:0 are those with a single entry point,
ie. global entry == local entry, and that have no requirement on r2 or
r12, and guarantee r2 is unchanged on return.  Such an external
function can be called via the PLT without saving r2 or restoring it
on return, avoiding a common load-hit-store for small functions.   The
optimization is attractive.  The TOC pointer load-hit-store is a major
reason why calls to small functions that need no register saves, or
with shrink-wrap, no register saves on a fast path, are slow on
powerpc64le.

To be safe, this optimization needs ld.so support to check that the
run-time matches link-time function implementation.  If a function
in a shared library with st_other localentry non-zero is called
without saving and restoring r2, r2 will be trashed on return, leading
to segfaults.  For that reason the optimization does not happen for
weak functions since a weak definition is a fairly solid hint that the
function will likely be overridden.  I'm also not enabling the
optimization by default unless glibc-2.26 is detected, which should
have the ld.so checks implemented.

bfd/
	* elf64-ppc.c (struct ppc_link_hash_table): Add has_plt_localentry0.
	(ppc64_elf_merge_symbol_attribute): Merge localentry bits from
	dynamic objects.
	(is_elfv2_localentry0): New function.
	(ppc64_elf_tls_setup): Default params->plt_localentry0.
	(plt_stub_size): Adjust size for tls_get_addr_opt stub.
	(build_tls_get_addr_stub): Use a simpler stub when r2 is not saved.
	(ppc64_elf_size_stubs): Leave stub_type as ppc_stub_plt_call for
	optimized localentry:0 stubs.
	(ppc64_elf_build_stubs): Save r2 in ELFv2 __glink_PLTresolve.
	(ppc64_elf_relocate_section): Leave nop unchanged for optimized
	localentry:0 stubs.
	(ppc64_elf_finish_dynamic_sections): Set PPC64_OPT_LOCALENTRY in
	DT_PPC64_OPT.
	* elf64-ppc.h (struct ppc64_elf_params): Add plt_localentry0.
include/
	* elf/ppc64.h (PPC64_OPT_LOCALENTRY): Define.
ld/
	* emultempl/ppc64elf.em (params): Init plt_localentry0 field.
	(enum ppc64_opt): New, replacing OPTION_* defines.  Add
	OPTION_PLT_LOCALENTRY, and OPTION_NO_PLT_LOCALENTRY.
	(PARSE_AND_LIST_*): Support --plt-localentry and --no-plt-localentry.
	* testsuite/ld-powerpc/elfv2so.d: Update.
	* testsuite/ld-powerpc/powerpc.exp (TLS opt 5): Use --no-plt-localentry.
	* testsuite/ld-powerpc/tlsopt5.d: Update.
2017-06-01 22:47:32 +09:30
Eli Zaretskii
b9c6833008 Fix MinGW compilation warnings due to environ.h
include/ChangeLog:

2017-05-31  Eli Zaretskii <eliz@gnu.org>

	* environ.h: Add #ifndef guard.
2017-05-31 09:35:07 +03:00
Anton Kolesov
940171d086 [ARC] Add arc-cpu.def with processor definitions
This patch extracts ARC CPU definitions from gas/config/tc-arc.c (cpu_types)
into a separate file arc-cpu.def.  This will allow reuse of CPU type definition
in multiple places where it might be needed, for example in disassembler.  This
will help ensure that gas and disassembker use same option values for CPUs.

arc-cpu.def file relies on preprocessor macroses which are defined somewhere
else.  This for example multiple C files to include arc-cpu.def, but define
different macroses, therefore creating different structures.

include/ChangeLog:
yyyy-mm-dd  Anton Kolesov  <anton.kolesov@synopsys.com>

	* elf/arc-cpu.def: New file.

gas/ChangeLog:
yyyy-mm-dd  Anton Kolesov  <anton.kolesov@synopsys.com>

	* config/tc-arc.c (cpu_types): Include arc-cpu.def

Signed-off-by: Anton Kolesov <Anton.Kolesov@synopsys.com>
2017-05-30 16:52:28 +03:00
Andreas Krebbel
a09f258601 S/390: Improve error checking for optional operands
So far we only had an instruction flag which made an arbitrary number
of operands optional.  This limits error checking capabilities for
instructions marked that way.  With this patch the optparm flag only
allows a single optional parameter and another one is added (optparm2)
allowing 2 optional arguments.  Hopefully we won't need more than that
in the future. So far there will be only a single use of optparm2.

gas/ChangeLog:

2017-05-30  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* config/tc-s390.c (md_gather_operands): Support new optparm2
	instruction flag.

include/ChangeLog:

2017-05-30  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* opcode/s390.h: Add new instruction flags optparm2.

opcodes/ChangeLog:

2017-05-30  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* s390-dis.c (s390_print_insn_with_opcode): Support new optparm2
	instruction flag.
	* s390-mkopc.c (main): Recognize the new instruction flag when
	parsing instruction list.
2017-05-30 10:22:25 +02:00
Andreas Krebbel
bfcfbe611b S/390: Remove optional operand flag.
The per operand optional flag hasn't been used for quite some time.
Cleanup some remains.

include/ChangeLog:

2017-05-30  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* opcode/s390.h: Remove S390_OPERAND_OPTIONAL.

gas/ChangeLog:

2017-05-30  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* config/tc-s390.c (md_gather_operands): Remove code dealing with
	S390_OPERAND_OPTIONAL.
2017-05-30 10:19:59 +02:00
Yao Qi
88c1242dc0 Move print_insn_XXX to an opcodes internal header
With the changes done in previous patches, print_insn_XXX functions
don't have to be external visible out of opcodes, because both gdb
and objdump select disassemblers through a single interface.

This patch moves these print_insn_XXX declarations from
include/dis-asm.h to opcodes/disassemble.h, which is a new header
added by this patch.

include:

2017-05-24  Yao Qi  <yao.qi@linaro.org>

	* dis-asm.h: Move some function declarations to
	opcodes/disassemble.h.

opcodes:

2017-05-24  Yao Qi  <yao.qi@linaro.org>

	* alpha-dis.c: Include disassemble.h, don't include
	dis-asm.h.
	* avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
	* crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
	* disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
	* fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
	* hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
	* i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
	* iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
	* m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
	* m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
	* metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
	* moxie-dis.c, msp430-dis.c, mt-dis.c:
	* nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
	* or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
	* ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
	* rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
	* sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
	* tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
	* tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
	* v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
	* w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
	* xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
	* z80-dis.c, z8k-dis.c: Likewise.
	* disassemble.h: New file.
2017-05-24 17:23:52 +01:00
Yao Qi
003ca0fd22 Refactor disassembler selection
Nowadays, opcodes/disassemble.c:disassembler selects the proper
disassembler according to ABFD only.  However, it actually
selects disassemblers according to arch, mach, endianess, and
abfd.  This patch adds them to the parameters of disassembler,
so that its caller can still select disassemblers in case that
abfd is NULL (a typical case in GDB).

There isn't any functionality change.

binutils:

2017-05-24  Yao Qi  <yao.qi@linaro.org>

	* objdump.c (disassemble_data): Caller update.

include:

2017-05-24  Yao Qi  <yao.qi@linaro.org>

	* dis-asm.h (disassembler): Update declaration.

opcodes:

2017-05-24  Yao Qi  <yao.qi@linaro.org>

	* disassemble.c (disassembler): Add arguments a, big and mach.
	Use them.

sim/common:

2017-05-24  Yao Qi  <yao.qi@linaro.org>

	* sim-trace.c (trace_disasm): Caller update.
2017-05-24 17:23:52 +01:00
claziss
575dcd27f8 [ARC] Update MAX_INSN_FLGS.
It is required to parse instructions like ldb.x.a.di.

include/
2017-05-23  Claudiu Zissulescu <claziss@synopsys.com>

	* opcode/arc.h (MAX_INSN_FLGS): Update to 4.
2017-05-23 12:18:10 +02:00
H.J. Lu
04ef582ace x86: Add NOTRACK prefix support
For register indirect branches, NOTRACK prefix (0x3e), which is also
the DS segment register prefix, can be used to ignore the CET indirect
branch track.

gas/

	* config/tc-i386.c (REX_PREFIX): Changed to 7.
	(NOTRACK_PREFIX): New.
	(MAX_PREFIXES): Changed to 8.
	(_i386_insn): Add notrack_prefix.
	(PREFIX_GROUP): Add PREFIX_DS.
	(add_prefix): Return PREFIX_DS for DS_PREFIX_OPCODE.
	(md_assemble): Check if NOTRACK prefix is supported.
	(parse_insn): Set notrack_prefix and issue an error for
	other prefixes after NOTRACK prefix.
	* testsuite/gas/i386/i386.exp: Run tests for NOTRACK prefix.
	* testsuite/gas/i386/notrack-intel.d: New file.
	* testsuite/gas/i386/notrack.d: Likewise.
	* testsuite/gas/i386/notrack.s: Likewise.
	* testsuite/gas/i386/notrackbad.l: Likewise.
	* testsuite/gas/i386/notrackbad.s: Likewise.
	* testsuite/gas/i386/x86-64-notrack-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-notrack.d: Likewise.
	* testsuite/gas/i386/x86-64-notrack.s: Likewise.
	* testsuite/gas/i386/x86-64-notrackbad.l: Likewise.
	* testsuite/gas/i386/x86-64-notrackbad.s: Likewise.

include/

	* include/opcode/i386.h (NOTRACK_PREFIX_OPCODE): New.

opcodes/

	* i386-dis.c (NOTRACK_Fixup): New.
	(NOTRACK): Likewise.
	(NOTRACK_PREFIX): Likewise.
	(last_active_prefix): Likewise.
	(reg_table): Use NOTRACK on indirect call and jmp.
	(ckprefix): Set last_active_prefix.
	(prefix_name): Return "notrack" for NOTRACK_PREFIX.
	* i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
	* i386-opc.h (NoTrackPrefixOk): New.
	(i386_opcode_modifier): Add notrackprefixok.
	* i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
	Add notrack.
	* i386-tbl.h: Regenerated.
2017-05-22 11:02:58 -07:00
Jose E. Marchesi
6451799480 binutils: support for the SPARC M8 processor
This patch adds support for the new SPARC M8 processor (implementing OSA
2017) to binutils.

New instructions:

- Dictionary Unpack

  + dictunpack

- Partitioned Compare with shifted result

  + Signed variants:   fpcmp{le,gt,eq,ne}{8,16,32}shl
  + Unsigned variants: fpcmpu{le,gt}{8,16,32}shl

- Partitioned Dual-Equal compared, with shifted result

  + fpcmpde{8,16,32}shl

- Partitioned Unsigned Range Compare, with shifted result

  + fpcmpur{8,16,32}shl

- 64-bit shifts on Floating-Point registers

  + fps{ll,ra,rl}64x

- Misaligned loads and stores

  + ldm{sh,uh,sw,uw,x,ux}
  + ldm{sh,uh,sw,uw,x,ux}a
  + ldmf{s,d}
  + ldmf{s,d}a

  + stm{h,w,x}
  + stm{h,w,x}a
  + stmf{s,d}
  + stmf{s,d}a

- Oracle Numbers

  + on{add,sub,mul,div}

- Reverse Bytes/Bits

  + revbitsb
  + revbytes{h,w,x}

- Run-Length instructions

  + rle_burst
  + rle_length

- New crypto instructions

  + sha3

- Instruction to read the new register %entropy

  + rd %entropy

New Alternate Address Identifiers:

- 0x24, #ASI_CORE_COMMIT_COUNT
- 0x24, #ASI_CORE_SELECT_COUNT
- 0x48, #ASI_ARF_ECC_REG
- 0x53, #ASI_ITLB_PROBE
- 0x58, #ASI_DSFAR
- 0x5a, #ASI_DTLB_PROBE_PRIMARY
- 0x5b, #ASI_DTLB_PROBE_REAL
- 0x64, #ASI_CORE_SELECT_COMMIT_NHT

The new assembler command-line options for selecting the M8 architecture
are:

-Av9m8 or -Asparc6 for 64-bit binaries.
-Av8plusm8 for 32-bit (v8+) binaries.

The corresponding disassembler command-line options are:

-msparc:v9m8 for 64-bit binaries.
-msparc:v8plusm8 for 32-bit (v8+) binaries.

Tested for regressions in the following targets:
sparc-aout sparc-linux sparc-vxworks sparc64-linux

bfd/ChangeLog:

2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* archures.c (bfd_mach_sparc_v9m8): Define.
	(bfd_mach_sparc_v8plusm8): Likewise.
	(bfd_mach_sparc_v9_p): Adjust to M8.
	(bfd_mach_sparc_64bit_p): Likewise.
	* aoutx.h (machine_type): Handle bfd_mach_sparc_v9m8 and
	bfd_mach_sparc_v8plusm8.
	* bfd-in2.h: Regenerated.
	* cpu-sparc.c (arch_info_struct): Entries for sparc:v9m8 and
	sparc:v8plusm8.
	* elfxx-sparc.c (_bfd_sparc_elf_object_p): Handle
	bfd_mach_sparc_v8plusm8 and bfd_mach_sparc_v9m8 using the new hw
	capabilities ONADDSUB, ONMUL, ONDIV, DICTUNP, FPCPSHL, RLE and
	SHA3.
	* elf32-sparc.c (elf32_sparc_final_write_processing): Handle
	bfd_mach_sparc_v8plusm8.

binutils/ChangeLog:

2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* NEWS: Mention the SPARC M8 support.

gas/ChangeLog:

2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* config/tc-sparc.c (sparc_arch_table): Entries for `sparc6',
	`v9m8' and `v8plusm8'.
	(sparc_md_end): Handle SPARC_OPCODE_ARCH_M8.
	(get_hwcap_name): Support the M8 hardware capabilities.
	(sparc_ip): Handle new operand types.
	* doc/c-sparc.texi (Sparc-Opts): Document -Av9m8, -Av8plusm8 and
	-Asparc6, and the corresponding -xarch aliases.
	* testsuite/gas/sparc/sparc6.s: New file.
	* testsuite/gas/sparc/sparc6.d: Likewise.
	* testsuite/gas/sparc/sparc6-diag.s: Likewise.
	* testsuite/gas/sparc/sparc6-diag.l: Likewise.
	* testsuite/gas/sparc/fpcmpshl.s: Likewise.
	* testsuite/gas/sparc/fpcmpshl.d: Likewise.
	* testsuite/gas/sparc/fpcmpshl-diag.s: Likewise.
	* testsuite/gas/sparc/fpcmpshl-diag.l: Likewise.
	* testsuite/gas/sparc/ldm-stm.s: Likewise.
	* testsuite/gas/sparc/ldm-stm.d: Likewise.
	* testsuite/gas/sparc/ldm-stm-diag.s: Likewise.
	* testsuite/gas/sparc/ldm-stm-diag.l: Likewise.
	* testsuite/gas/sparc/ldmf-stmf.s: Likewise.
	* testsuite/gas/sparc/ldmf-stmf.d: Likewise.
	* testsuite/gas/sparc/ldmf-stmf-diag.s: Likewise.
	* testsuite/gas/sparc/ldmf-stmf-diag.l: Likewise.
	* testsuite/gas/sparc/on.s: Likewise.
	* testsuite/gas/sparc/on.d: Likewise.
	* testsuite/gas/sparc/on-diag.s: Likewise.
	* testsuite/gas/sparc/on-diag.l: Likewise.
	* testsuite/gas/sparc/rle.s: Likewise.
	* testsuite/gas/sparc/rle.d: Likewise.
	* testsuite/gas/sparc/sparc.exp (gas_64_check): Run new tests.
	* testsuite/gas/sparc/rdasr.s: Add test for RDENTROPY.
	* testsuite/gas/sparc/rdasr.d: Likewise.

include/ChangeLog:

2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* elf/sparc.h (ELF_SPARC_HWCAP2_SPARC6): Define.
	(ELF_SPARC_HWCAP2_ONADDSUB): Likewise.
	(ELF_SPARC_HWCAP2_ONMUL): Likewise.
	(ELF_SPARC_HWCAP2_ONDIV): Likewise.
	(ELF_SPARC_HWCAP2_DICTUNP): Likewise.
	(ELF_SPARC_HWCAP2_FPCMPSHL): Likewise.
	(ELF_SPARC_HWCAP2_RLE): Likewise.
	(ELF_SPARC_HWCAP2_SHA3): Likewise.
	* opcode/sparc.h (sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_M8
	and adjust SPARC_OPCODE_ARCH_MAX.
	(HWCAP2_SPARC6): Define.
	(HWCAP2_ONADDSUB): Likewise.
	(HWCAP2_ONMUL): Likewise.
	(HWCAP2_ONDIV): Likewise.
	(HWCAP2_DICTUNP): Likewise.
	(HWCAP2_FPCMPSHL): Likewise.
	(HWCAP2_RLE): Likewise.
	(HWCAP2_SHA3): Likewise.
	(OPM): Likewise.
	(OPMI): Likewise.
	(ONFCN): Likewise.
	(REVFCN): Likewise.
	(SIMM10): Likewise.

opcodes/ChangeLog:

2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
	(X_IMM2): Define.
	(compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
	bfd_mach_sparc_v9m8.
	(print_insn_sparc): Handle new operand types.
	* sparc-opc.c (MASK_M8): Define.
	(v6): Add MASK_M8.
	(v6notlet): Likewise.
	(v7): Likewise.
	(v8): Likewise.
	(v9): Likewise.
	(v9a): Likewise.
	(v9b): Likewise.
	(v9c): Likewise.
	(v9d): Likewise.
	(v9e): Likewise.
	(v9v): Likewise.
	(v9m): Likewise.
	(v9andleon): Likewise.
	(m8): Define.
	(HWS_VM8): Define.
	(HWS2_VM8): Likewise.
	(sparc_opcode_archs): Add entry for "m8".
	(sparc_opcodes): Add OSA2017 and M8 instructions
	dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
	fpx{ll,ra,rl}64x,
	ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
	ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
	revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
	stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
	(asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
	ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
	ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
	ASI_CORE_SELECT_COMMIT_NHT.
2017-05-19 09:27:08 -07:00
Alan Modra
bc4e12ded1 Rename non_ir_ref to non_ir_ref_regular
Since the flag is now set only for regular object refs.

include/
	* bfdlink.h (struct bfd_link_hash_entry <non_ir_ref>): Rename to
	non_ir_ref_regular.
bfd/
	* elf-m10300.c: Rename occurrences of non_ir_ref.
	* elf32-arm.c: Likewise.
	* elf32-bfin.c: Likewise.
	* elf32-cr16.c: Likewise.
	* elf32-cris.c: Likewise.
	* elf32-d10v.c: Likewise.
	* elf32-dlx.c: Likewise.
	* elf32-fr30.c: Likewise.
	* elf32-frv.c: Likewise.
	* elf32-hppa.c: Likewise.
	* elf32-i370.c: Likewise.
	* elf32-i386.c: Likewise.
	* elf32-iq2000.c: Likewise.
	* elf32-lm32.c: Likewise.
	* elf32-m32c.c: Likewise.
	* elf32-m32r.c: Likewise.
	* elf32-m68hc1x.c: Likewise.
	* elf32-m68k.c: Likewise.
	* elf32-mcore.c: Likewise.
	* elf32-metag.c: Likewise.
	* elf32-microblaze.c: Likewise.
	* elf32-moxie.c: Likewise.
	* elf32-msp430.c: Likewise.
	* elf32-mt.c: Likewise.
	* elf32-nios2.c: Likewise.
	* elf32-or1k.c: Likewise.
	* elf32-ppc.c: Likewise.
	* elf32-rl78.c: Likewise.
	* elf32-s390.c: Likewise.
	* elf32-score.c: Likewise.
	* elf32-score7.c: Likewise.
	* elf32-sh.c: Likewise.
	* elf32-tic6x.c: Likewise.
	* elf32-tilepro.c: Likewise.
	* elf32-v850.c: Likewise.
	* elf32-vax.c: Likewise.
	* elf32-xstormy16.c: Likewise.
	* elf32-xtensa.c: Likewise.
	* elf64-alpha.c: Likewise.
	* elf64-hppa.c: Likewise.
	* elf64-ia64-vms.c: Likewise.
	* elf64-mmix.c: Likewise.
	* elf64-ppc.c: Likewise.
	* elf64-s390.c: Likewise.
	* elf64-sh64.c: Likewise.
	* elf64-x86-64.c: Likewise.
	* elflink.c: Likewise.
	* elfnn-aarch64.c: Likewise.
	* elfnn-ia64.c: Likewise.
	* elfnn-riscv.c: Likewise.
	* elfxx-mips.c: Likewise.
	* elfxx-sparc.c: Likewise.
	* elfxx-tilegx.c: Likewise.
	* linker.c: Likewise.
ld/
	* plugin.c: Rename occurrences of non_ir_ref.
2017-05-16 10:35:02 +09:30
Alan Modra
4070765b1a non_ir_ref_dynamic
dynamic_ref_after_ir_def is a little odd compared to other symbol
flags in that as the name suggests, it is set only for certain
references after a definition.  It turns out that setting a flag for
any non-ir reference from a dynamic object can be used to solve the
problem for which this flag was invented, which I think is a cleaner.
This patch does that, and sets non_ir_ref only for regular object
references.

include/
	* bfdlink.h (struct bfd_link_hash_entry): Update non_ir_ref
	comment.  Rename dynamic_ref_after_ir_def to non_ir_ref_dynamic.
ld/
	* plugin.c (is_visible_from_outside): Use non_ir_ref_dynamic.
	(plugin_notice): Set non_ir_ref for references from regular
	objects, non_ir_ref_dynamic for references from dynamic objects.
bfd/
	* elf64-ppc.c (add_symbol_adjust): Transfer non_ir_ref_dynamic.
	* elflink.c (elf_link_add_object_symbols): Update to use
	non_ir_ref_dynamic.
	(elf_link_input_bfd): Test non_ir_ref_dynamic in addition to
	non_ir_ref.
	* linker.c (_bfd_generic_link_add_one_symbol): Likewise.
2017-05-16 10:35:02 +09:30
Maciej W. Rozycki
25499ac7ee MIPS16e2: Add MIPS16e2 ASE support
Add MIPS16e2 ASE support as per the architecture specification[1],
including in particular:

1. A new ELF ASE flag to mark MIPS16e2 binaries.

2. MIPS16e2 instruction assembly support, including a relaxation update
   to use LUI rather than an LI/SLL instruction pair for loading the
   high part of 32-bit addresses.

3. MIPS16e2 instruction disassembly support, including updated rules for
   extended forms of instructions that are now subdecoded and therefore
   do not alias to the original MIPS16 ISA revision instructions even
   for encodings that are not valid in the MIPS16e2 instruction set.

Add `-mmips16e2' and `-mno-mips16e2' GAS command-line options and their
corresponding `mips16e2' and `no-mips16e2' settings for the `.set' and
`.module' pseudo-ops.  Control the availability of the MT ASE subset of
the MIPS16e2 instruction set with a combination of these controls and
the preexisting MT ASE controls.

Parts of this change by Matthew Fortune and Andrew Bennett.

References:

[1] "MIPS32 Architecture for Programmers: MIPS16e2 Application-Specific
    Extension Technical Reference Manual", Imagination Technologies
    Ltd., Document Number: MD01172, Revision 01.00, April 26, 2016

	include/
	* elf/mips.h (AFL_ASE_MIPS16E2): New macro.
	(AFL_ASE_MASK): Adjust accordingly.
	* opcode/mips.h: Document new operand codes defined.
	(mips_operand_type): Add OP_REG28 enum value.
	(INSN2_SHORT_ONLY): Update description.
	(ASE_MIPS16E2, ASE_MIPS16E2_MT): New macros.

	bfd/
	* elfxx-mips.c (print_mips_ases): Handle MIPS16e2 ASE.

	opcodes/
	* mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
	ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
	(mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
	(print_insn_arg) <OP_REG28>: Add handler.
	(validate_insn_args) <OP_REG28>: Handle.
	(print_mips16_insn_arg): Handle MIPS16 instructions that require
	32-bit encoding and 9-bit immediates.
	(print_insn_mips16): Handle MIPS16 instructions that require
	32-bit encoding and MFC0/MTC0 operand decoding.
	* mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
	<'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
	(RD_C0, WR_C0, E2, E2MT): New macros.
	(mips16_opcodes): Add entries for MIPS16e2 instructions:
	GP-relative "addiu" and its "addu" spelling, "andi", "cache",
	"di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
	"lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
	"movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
	"pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
	instructions, "swl", "swr", "sync" and its "sync_acquire",
	"sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
	"xori", "dmt", "dvpe", "emt" and "evpe".  Add split
	regular/extended entries for original MIPS16 ISA revision
	instructions whose extended forms are subdecoded in the MIPS16e2
	ISA revision: "li", "sll" and "srl".

	binutils/
	* readelf.c (print_mips_ases): Handle MIPS16e2 ASE.
	* NEWS: Mention MIPS16e2 ASE support.

	gas/
	* config/tc-mips.c (RELAX_MIPS16_ENCODE): Add `e2' flag.
	(RELAX_MIPS16_E2): New macro.
	(RELAX_MIPS16_PIC, RELAX_MIPS16_SYM32, RELAX_MIPS16_NOMACRO)
	(RELAX_MIPS16_USER_SMALL, RELAX_MIPS16_USER_EXT)
	(RELAX_MIPS16_DSLOT, RELAX_MIPS16_JAL_DSLOT)
	(RELAX_MIPS16_EXTENDED, RELAX_MIPS16_MARK_EXTENDED)
	(RELAX_MIPS16_CLEAR_EXTENDED, RELAX_MIPS16_ALWAYS_EXTENDED)
	(RELAX_MIPS16_MARK_ALWAYS_EXTENDED)
	(RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED, RELAX_MIPS16_MACRO)
	(RELAX_MIPS16_MARK_MACRO, RELAX_MIPS16_CLEAR_MACRO): Shift bits.
	(mips16_immed_extend): New prototype.
	(options): Add OPTION_MIPS16E2 and OPTION_NO_MIPS16E2 enum
	values.
	(md_longopts): Add "mmips16e2" and "mno-mips16e2" options.
	(mips_ases): Add "mips16e2" entry.
	(mips_set_ase): Handle MIPS16e2 ASE.
	(insn_insert_operand): Explicitly handle immediates with MIPS16
	instructions that require 32-bit encoding.
	(is_opcode_valid_16): Pass enabled ASE bitmask on to
	`opcode_is_member'.
	(validate_mips_insn): Explicitly handle immediates with MIPS16
	instructions that require 32-bit encoding.
	(operand_reg_mask) <OP_REG28>: Add handler.
	(match_reg28_operand): New function.
	(match_operand) <OP_REG28>: Add handler.
	(append_insn): Pass ASE_MIPS16E2 setting to RELAX_MIPS16_ENCODE.
	(match_mips16_insn): Handle MIPS16 instructions that require
	32-bit encoding and `V' and `u' operand codes.
	(mips16_ip): Allow any characters except from `.' in opcodes.
	(mips16_immed_extend): Handle 9-bit immediates.  Do not shuffle
	immediates whose width is not one of these listed.
	(md_estimate_size_before_relax): Handle MIPS16e2 relaxation.
	(mips_relax_frag): Likewise.
	(md_convert_frag): Likewise.
	(mips_convert_ase_flags): Handle MIPS16e2 ASE.

	* doc/as.texinfo (Target MIPS options): Add `-mmips16e2' and
	`-mno-mips16e2' options.
	(-mmips16e2, -mno-mips16e2): New options.
	* doc/c-mips.texi (MIPS Options): Add `-mmips16e2' and
	`-mno-mips16e2' options.
	(MIPS ASE Instruction Generation Overrides): Add `.set mips16e2'
	and `.set nomips16e2'.
2017-05-15 13:57:10 +01:00
John David Anglin
cd85e51ad3 Fix match and mask for 64-bit bb opcode. 2017-05-14 16:06:06 -04:00
Claudiu Zissulescu
53a346d823 [ARC] Object attributes.
gas/
2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>

	* testsuite/gas/arc/attr-arc600.d: New file.
	* testsuite/gas/arc/attr-arc600_mul32x16.d: Likewise.
	* testsuite/gas/arc/attr-arc600_norm.d: Likewise.
	* testsuite/gas/arc/attr-arc601.d: Likewise.
	* testsuite/gas/arc/attr-arc601_mul32x16.d: Likewise.
	* testsuite/gas/arc/attr-arc601_mul64.d: Likewise.
	* testsuite/gas/arc/attr-arc601_norm.d: Likewise.
	* testsuite/gas/arc/attr-arc700.d: Likewise.
	* testsuite/gas/arc/attr-arcem.d: Likewise.
	* testsuite/gas/arc/attr-archs.d: Likewise.
	* testsuite/gas/arc/attr-autodetect-1.d: Likewise.
	* testsuite/gas/arc/attr-autodetect-1.s: Likewise.
	* testsuite/gas/arc/attr-cpu-a601.d: Likewise.
	* testsuite/gas/arc/attr-cpu-a601.s: Likewise.
	* testsuite/gas/arc/attr-cpu-a700.d: Likewise.
	* testsuite/gas/arc/attr-cpu-a700.s: Likewise.
	* testsuite/gas/arc/attr-cpu-em.d: Likewise.
	* testsuite/gas/arc/attr-cpu-em.s: Likewise.
	* testsuite/gas/arc/attr-cpu-hs.d: Likewise.
	* testsuite/gas/arc/attr-cpu-hs.s: Likewise.
	* testsuite/gas/arc/attr-em.d: Likewise.
	* testsuite/gas/arc/attr-em4.d: Likewise.
	* testsuite/gas/arc/attr-em4_dmips.d: Likewise.
	* testsuite/gas/arc/attr-em4_fpuda.d: Likewise.
	* testsuite/gas/arc/attr-em4_fpus.d: Likewise.
	* testsuite/gas/arc/attr-hs.d: Likewise.
	* testsuite/gas/arc/attr-hs34.d: Likewise.
	* testsuite/gas/arc/attr-hs38.d: Likewise.
	* testsuite/gas/arc/attr-hs38_linux.d: Likewise.
	* testsuite/gas/arc/attr-mul64.d: Likewise.
	* testsuite/gas/arc/attr-name.d: Likewise.
	* testsuite/gas/arc/attr-name.s: Likewise.
	* testsuite/gas/arc/attr-nps400.d: Likewise.
	* testsuite/gas/arc/attr-override-mcpu.d: Likewise.
	* testsuite/gas/arc/attr-override-mcpu.s
	* testsuite/gas/arc/attr-quarkse_em.d: Likewise.
	* testsuite/gas/arc/blank.s: Likewise.
	* testsuite/gas/elf/section2.e-arc: Likewise.
	* testsuite/gas/arc/cpu-pseudop-1.d: Update test.
	* testsuite/gas/arc/cpu-pseudop-2.d: Likewise.
	* testsuite/gas/arc/nps400-0.d: Likewise.
	* testsuite/gas/elf/elf.exp: Set target_machine for ARC.
	* config/tc-arc.c (opcode/arc-attrs.h): Include.
	(ARC_GET_FLAG, ARC_SET_FLAG, streq): Define.
	(arc_attribute): Declare new function.
	(md_pseudo_table): Add arc_attribute.
	(cpu_types): Rename default cpu features.
	(selected_cpu): Set the default OSABI flag.
	(mpy_option): New variable.
	(pic_option): Likewise.
	(sda_option): Likewise.
	(tls_option): Likewise.
	(feature_type, feature_list): Remove.
	(arc_initial_eflag): Likewise.
	(attributes_set_explicitly): New variable.
	(arc_check_feature): Check also for the conflicting features.
	(arc_select_cpu): Refactor assignment of selected_cpu.eflags.
	(arc_option): Remove setting of private flags and architecture.
	(check_cpu_feature): Refactor feature names.
	(autodetect_attributes): New function.
	(assemble_tokens): Use above function.
	(md_parse_option): Refactor feature names.
	(arc_attribute): New function.
	(arc_set_attribute_int): Likewise.
	(arc_set_attribute_string): Likewise.
	(arc_stralloc): Likewise.
	(arc_set_public_attributes): Likewise.
	(arc_md_end): Likewise.
	(arc_copy_symbol_attributes): Likewise.
	(rc_convert_symbolic_attribute): Likewise.
	* config/tc-arc.h (md_end): Define.
	(CONVERT_SYMBOLIC_ATTRIBUTE): Likewise.
	(TC_COPY_SYMBOL_ATTRIBUTES): Likewise.
	* doc/c-arc.texi: Document ARC object attributes.

binutils/
2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>

	* readelf.c (decode_ARC_machine_flags): Recognize OSABI v4.
	(get_arc_section_type_name): New function.
	(get_section_type_name): Use the above function.
	(display_arc_attribute): New function.
	(process_arc_specific): Likewise.
	(process_arch_specific): Handle ARC specific information.
	* testsuite/binutils-all/strip-3.d: Consider ARC.attributes
	section.

include/
2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>

	* elf/arc.h (SHT_ARC_ATTRIBUTES): Define.
	(Tag_ARC_*): Define.
	(E_ARC_OSABI_V4): Define.
	(E_ARC_OSABI_CURRENT): Reassign it.
	(TAG_CPU_*): Define.
	* opcode/arc-attrs.h: New file.
	* opcode/arc.h (insn_subclass_t): Assign enum values.
	(insn_subclass_t): Update enum with QUARKSE1, QUARKSE2, and LL64.
	(ARC_EA, ARC_CD, ARC_LLOCK, ARC_ATOMIC, ARC_MPY, ARC_MULT)
	(ARC_NPS400, ARC_DPFP, ARC_SPFP, ARC_FPU, ARC_FPUDA, ARC_SWAP)
	(ARC_NORM, ARC_BSCAN, ARC_UIX, ARC_TSTAMP, ARC_VBFDW)
	(ARC_BARREL, ARC_DSPA, ARC_SHIFT, ARC_INTR, ARC_DIV, ARC_XMAC)
	(ARC_CRC): Delete.

bfd/
2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>

	* elf32-arc.c (FEATURE_LIST_NAME): Define.
	(CONFLICT_LIST): Likewise.
	(opcode/arc-attrs.h): Include.
	(arc_elf_print_private_bfd_data): Print OSABI v4 flag.
	(arc_extract_features): New file.
	(arc_stralloc): Likewise.
	(arc_elf_merge_attributes): Likewise.
	(arc_elf_merge_private_bfd_data): Use object attributes.
	(bfd_arc_get_mach_from_attributes): New function.
	(arc_elf_object_p): Use object attributes.
	(arc_elf_final_write_processing): Likewise.
	(elf32_arc_obj_attrs_arg_type): New function.
	(elf32_arc_obj_attrs_handle_unknown): Likewise.
	(elf32_arc_section_from_shdr): Likewise.
	(elf_backend_obj_attrs_vendor): Define.
	(elf_backend_obj_attrs_section): Likewise.
	(elf_backend_obj_attrs_arg_type): Likewise.
	(elf_backend_obj_attrs_section_type): Likewise.
	(elf_backend_obj_attrs_handle_unknown): Likewise.
	(elf_backend_section_from_shdr): Likewise.

ld/
2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>

	* testsuite/ld-arc/attr-merge-0.d: New file.
	* testsuite/ld-arc/attr-merge-0.s: Likewise.
	* testsuite/ld-arc/attr-merge-0e.s: Likewise.
	* testsuite/ld-arc/attr-merge-1.d: Likewise.
	* testsuite/ld-arc/attr-merge-1.s: Likewise.
	* testsuite/ld-arc/attr-merge-1e.s: Likewise.
	* testsuite/ld-arc/attr-merge-2.d: Likewise.
	* testsuite/ld-arc/attr-merge-2.s: Likewise.
	* testsuite/ld-arc/attr-merge-3.d: Likewise.
	* testsuite/ld-arc/attr-merge-3.s: Likewise.
	* testsuite/ld-arc/attr-merge-3e.s: Likewise.
	* testsuite/ld-arc/attr-merge-4.s: Likewise.
	* testsuite/ld-arc/attr-merge-5.d: Likewise.
	* testsuite/ld-arc/attr-merge-5a.s: Likewise.
	* testsuite/ld-arc/attr-merge-5b.s: Likewise.
	* testsuite/ld-arc/attr-merge-conflict-isa.d: Likewise.
	* testsuite/ld-arc/attr-merge-err-isa.d: Likewise.
	* testsuite/ld-arc/attr-merge-incompatible-cpu.d: Likewise.
	* testsuite/ld-arc/got-01.d: Update test.
	* testsuite/ld-arc/attr-merge-err-quarkse.d: New file.
	* testsuite/ld-arc/attr-quarkse.s: Likewise.
	* testsuite/ld-arc/attr-quarkse2.s: Likewise.

opcodes/
2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-dis.c (parse_option): Update quarkse_em option..
	* arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
	QUARKSE1.
	(dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
2017-05-10 14:42:22 +02:00
H.J. Lu
59fa66c538 Handle symbol defined in IR and referenced in DSO
We need to make an IR symbol visible if it is defined in an IR object
and referenced in a dynamic object.  When --as-needed is used, since
linker removes the IR symbol reference of the dynamic object if the
dynamic object isn't needed in the first pass, the IR definition isn't
visible to the dynamic object even if the dynamic object becomes needed
in the second pass.  Add dynamic_ref_after_ir_def to bfd_link_hash_entry
to track IR symbol which is defined in an IR object and later referenced
in a dynamic object.  dynamic_ref_after_ir_def is preserved when restoring
the symbol table for unneeded dynamic object.

bfd/

	PR ld/21382
	* elflink.c (elf_link_add_object_symbols): Preserve
	dynamic_ref_after_ir_def when restoring the symbol table for
	unneeded dynamic object.

include/

	PR ld/21382
	* bfdlink.h (bfd_link_hash_entry): Add dynamic_ref_after_ir_def.

ld/

	PR ld/21382
	* plugin.c (is_visible_from_outside): Symbol may be visible
	from outside if dynamic_ref_after_ir_def is set.
	(plugin_notice): Set dynamic_ref_after_ir_def if the symbol is
	defined in an IR object and referenced in a dynamic object.
	* testsuite/ld-plugin/lto.exp: Run PR ld/21382 tests.
	* testsuite/ld-plugin/pr21382a.c: New file.
	* testsuite/ld-plugin/pr21382b.c: Likewise.
2017-04-20 07:48:35 -07:00
Alan Modra
954b63d4c8 Implement -z dynamic-undefined-weak
-z nodynamic-undefined-weak is only implemented for x86.  (The sparc
backend has some support code but doesn't enable the option by
including ld/emulparams/dynamic_undefined_weak.sh, and since the
support looks like it may be broken I haven't enabled it.)  This patch
adds the complementary -z dynamic-undefined-weak, extends both options
to affect building of shared libraries as well as executables, and
adds support for the option on powerpc.

include/
	* bfdlink.h (struct bfd_link_info <dynamic_undefined_weak>):
	Revise comment.
bfd/
	* elflink.c (_bfd_elf_adjust_dynamic_symbol): Hide undefweak
	or make dynamic for info->dynamic_undefined_weak 0 and 1.
	* elf32-ppc.c:Formatting.
	(ensure_undefweak_dynamic): Don't make dynamic when
	info->dynamic_undefined_weak is zero.
	(allocate_dynrelocs): Discard undefweak dyn_relocs for
	info->dynamic_undefined_weak.  Discard undef dyn_relocs when
	not default visibility.  Discard undef and undefweak
	dyn_relocs earlier.
	(ppc_elf_relocate_section): Adjust to suit.
	* elf64-ppc.c: Formatting.
	(ensure_undefweak_dynamic): Don't make dynamic when
	info->dynamic_undefined_weak is zero.
	(allocate_dynrelocs): Discard undefweak dyn_relocs for
	info->dynamic_undefined_weak.  Discard them earlier.
ld/
	* ld.texinfo (dynamic-undefined-weak): Document.
	(nodynamic-undefined-weak): Document that this option now can
	be used with shared libs.
	* emulparams/dynamic_undefined_weak.sh: Support -z
	dynamic-undefined-weak.
	* emulparams/elf32ppccommon.sh: Include dynamic_undefined_weak.sh.
	* testsuite/ld-undefined/weak-undef.exp (undef_weak_so),
	(undef_weak_exe): New.  Use them.  Add -z dynamic-undefined-weak
	and -z nodynamic-undefined-weak tests.
	* Makefile.am: Update powerpc dependencies.
	* Makefile.in: Regenerate.
2017-04-19 20:39:52 +09:30
Alan Modra
c03dc33b60 Reorder PPC_OPCODE_* and set PPC_OPCODE_TMR for e6500
PPC_OPCODE_* renumbered to fill the gaps left by previous patches,
and reordered chronologically just because.  I kept PPC_OPCODE_TMR
because presumably it might be used in future APUinfo for e6500.

include/
	* opcode/ppc.h (PPC_OPCODE_*): Renumber and order chronologically.
	(PPC_OPCODE_SPE): Comment on this and other bits used for APUinfo.
opcodes/
	* ppc-dis.c (ppc_opts): Formatting.  Set PPC_OPCODE_TMR for e6500.
	* ppc-opc.c (powerpc_opcodes <mftmr, mttmr>): Remove now
	unnecessary E6500.
2017-04-11 07:43:21 +09:30
Alan Modra
ef85eab0ec Bye bye PPC_OPCODE_HTM and -mhtm
The -mhtm option is fairly useless too.

include/
	* opcode/ppc.h (PPC_OPCODE_HTM): Delete.
gas/
	* config/tc-ppc.c (md_show_usage): Delete mention of -mhtm.
	* testsuite/gas/ppc/htm.d: Pass -mpower8 and -Mpower8.
opcodes/
	* ppc-dis.c (ppc_opts): Remove PPC_OPCODE_HTM and "htm".
	* ppc-opc.c (PPCHTM): Define as PPC_OPCODE_POWER8.
2017-04-11 07:40:24 +09:30
Alan Modra
9570835e55 Bye Bye PPC_OPCODE_VSX3
This bit is also useless as it can be replaced with PPC_OPCODE_POWER9.
Defining the VSX2 and VSX3 selection based on cpu bits also lets the
assembler/disassembler distinguish between the power7 VSX opcodes and
the power8 ones.  Note that this change means -mvsx now reverts back
to just adding the power7 VSX insns.

include/
	* opcode/ppc.h (PPC_OPCODE_VSX3): Delete.
opcodes/
	* ppc-dis.c (ppc_opts): Remove PPC_OPCODE_VSX3.
	* ppc-opc.c (PPCVSX2): Define as PPC_OPCODE_POWER8.
	(PPCVSX3): Define as PPC_OPCODE_POWER9.
2017-04-11 07:36:43 +09:30
Alan Modra
9a85b496ac Bye bye PPC_OPCODE_ALTIVEC2
This bit is worse than useless.  Using it prevents the assembler and
disassembler distinguishing between opcodes added for power8 and those
added for power9.

include/
	* opcode/ppc.h (PPC_OPCODE_ALTIVEC2): Delete.
opcodes/
	* ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2.
	* ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
	(PPCVEC3): Define as PPC_OPCODE_POWER9.
2017-04-11 07:33:50 +09:30
Pip Cet
62ecb94c4a Add support for disassembling WebAssembly opcodes.
include	* dis-asm.h: Add prototypes for wasm32 disassembler.

opcodes	* Makefile.am: Add wasm32-dis.c.
	* configure.ac: Add wasm32-dis.c to wasm32 target.
	* disassemble.c: Add wasm32 disassembler code.
	* wasm32-dis.c: New file.
	* Makefile.in: Regenerate.
	* configure: Regenerate.
	* po/POTFILES.in: Regenerate.
	* po/opcodes.pot: Regenerate.

gas	* testsuite/gas/wasm32/allinsn.d: Adjust test for disassembler
	changes.
	* testsuite/gas/wasm32/disass.d: New test.
	* testsuite/gas/wasm32/disass.s: New test.
	* testsuite/gas/wasm32/disass-2.d: New test.
	* testsuite/gas/wasm32/disass-2.s: New test.
	* testsuite/gas/wasm32/reloc.d: Adjust test for changed reloc
	names.
	* testsuite/gas/wasm32/reloc.s: Update test for changed assembler
	syntax.
	* testsuite/gas/wasm32/wasm32.exp: Run new tests.  Expect allinsn
	test to succeed.
2017-04-06 17:20:02 +01:00
Pedro Alves
f995bbe8e6 -Wwrite-strings: Constify struct disassemble_info's disassembler_options field
The memory disassemble_info::disassembler_options points to is always
owned by the client.  I.e., that field is an non-owning, observing
pointer.  Thus const makes sense.

Are the include/ and opcodes/ bits OK?

Tested on x86_64 Fedora 23, built with --enable-targets=all.

include/ChangeLog:
2017-04-05  Pedro Alves  <palves@redhat.com>

	* dis-asm.h (disassemble_info) <disassembler_options>: Now a
	"const char *".
	(next_disassembler_option): Constify.

opcodes/ChangeLog:
2017-04-05  Pedro Alves  <palves@redhat.com>

	* arc-dis.c (parse_option, parse_disassembler_options): Constify.
	* arm-dis.c (parse_arm_disassembler_options): Constify.
	* ppc-dis.c (powerpc_init_dialect): Constify local.
	* vax-dis.c (parse_disassembler_options): Constify.

gdb/ChangeLog:
2017-04-05  Pedro Alves  <palves@redhat.com>

	* arm-tdep.c (show_disassembly_style_sfunc): Constify local.
	* disasm.c (set_disassembler_options): Constify local.
	* i386-tdep.c (i386_print_insn): Remove cast and FIXME comment.
2017-04-05 19:21:33 +01:00
H.J. Lu
a91e1603af Support ELF SHF_GNU_MBIND and PT_GNU_MBIND_XXX
Mark an ALLOC section, which should be placed in special memory area,
with SHF_GNU_MBIND.  Its sh_info field indicates the special memory
type.  GNU_MBIND section names start with ".mbind" so that they are
placed as orphan sections by linker.  All input GNU_MBIND sections
with the same sh_type, sh_flags and sh_info are placed in one output
GNU_MBIND section.  In executable and shared object, create a
GNU_MBIND segment for each GNU_MBIND section and its segment type is
PT_GNU_MBIND_LO plus the sh_info value.  Each GNU_MBIND segment is
aligned at page boundary.

The assembler syntax:

    .section .mbind.foo,"adx",%progbits
                          ^             0: Special memory type.
                          |
                         'd' for SHF_GNU_MBIND.

    .section .mbind.foo,"adx",%progbits,0x1
                          ^             1: Special memory type.
                          |
                         'd' for SHF_GNU_MBIND.

    .section .mbind.bar,"adG",%progbits,.foo_group,comdat,0x2
                          ^                               2: Special memory type.
                          |
                         'd' for SHF_GNU_MBIND.

bfd/

	* elf.c (get_program_header_size): Add a GNU_MBIND segment for
	each GNU_MBIND section and align GNU_MBIND section to page size.
	(_bfd_elf_map_sections_to_segments): Create a GNU_MBIND
	segment for each GNU_MBIND section.
	(_bfd_elf_init_private_section_data): Copy sh_info from input
	for GNU_MBIND section.

binutils/

	* NEWS: Mention support for ELF SHF_GNU_MBIND and
	PT_GNU_MBIND_XXX.
	* readelf.c (get_segment_type): Handle PT_GNU_MBIND_XXX.
	(get_elf_section_flags): Handle SHF_GNU_MBIND.
	(process_section_headers): Likewise.
	* testsuite/binutils-all/mbind1.s: New file.
	* testsuite/binutils-all/objcopy.exp: Run readelf test on
	mbind1.s.

gas/

	* NEWS: Mention support for ELF SHF_GNU_MBIND.
	* config/obj-elf.c (section_match): New.
	(get_section): Match both sh_info and group name.
	(obj_elf_change_section): Add argument for sh_info.  Pass both
	sh_info and group name to get_section. Issue an error for
	SHF_GNU_MBIND section without SHF_ALLOC.  Set sh_info.
	(obj_elf_parse_section_letters): Set SHF_GNU_MBIND for 'd'.
	(obj_elf_section): Support SHF_GNU_MBIND section info.
	* config/obj-elf.h (obj_elf_change_section): Add argument for
	sh_info.
	* config/tc-arm.c (start_unwind_section): Pass 0 as sh_info to
	obj_elf_change_section.
	* config/tc-ia64.c (obj_elf_vms_common): Likewise.
	* config/tc-microblaze.c (microblaze_s_data): Likewise.
	(microblaze_s_sdata): Likewise.
	(microblaze_s_rdata): Likewise.
	(microblaze_s_bss): Likewise.
	* config/tc-mips.c (s_change_section): Likewise.
	* config/tc-msp430.c (msp430_profiler): Likewise.
	* config/tc-rx.c (parse_rx_section): Likewise.
	* config/tc-tic6x.c (tic6x_start_unwind_section): Likewise.
	* doc/as.texinfo: Document 'd' for SHF_GNU_MBIND.
	* testsuite/gas/elf/elf.exp: Run section12a, section12b and
	section13.
	* testsuite/gas/elf/section10.d: Updated.
	* testsuite/gas/elf/section10.s: Likewise.
	* testsuite/gas/elf/section12.s: New file.
	* testsuite/gas/elf/section12a.d: Likewise.
	* testsuite/gas/elf/section12b.d: Likewise.
	* testsuite/gas/elf/section13.l: Likewise.
	* testsuite/gas/elf/section13.d: Likewise.
	* testsuite/gas/elf/section13.s: Likewise.

include/

	* elf/common.h (PT_GNU_MBIND_NUM): New.
	(PT_GNU_MBIND_LO): Likewise.
	(PT_GNU_MBIND_HI): Likewise.
	(SHF_GNU_MBIND): Likewise.

ld/

	* NEWS: Mention support for ELF SHF_GNU_MBIND and
	PT_GNU_MBIND_XXX.
	* emultempl/elf32.em (gld${EMULATION_NAME}_place_orphan): Place
	input GNU_MBIND sections with the same type, attributes and
	sh_info field into a single output GNU_MBIND section.
	* testsuite/ld-elf/elf.exp: Run mbind2a and mbind2b.
	* testsuite/ld-elf/mbind1.s: New file.
	* testsuite/ld-elf/mbind1a.d: Likewise.
	* testsuite/ld-elf/mbind1b.d: Likewise.
	* testsuite/ld-elf/mbind1c.d: Likewise.
	* testsuite/ld-elf/mbind2a.s: Likewise.
	* testsuite/ld-elf/mbind2b.c: Likewise.
2017-04-04 09:06:04 -07:00
Palmer Dabbelt
b52920324f RISC-V: Resurrect GP-relative disassembly hints
We missed a "_gp" when changing the GP symbol.  To make sure that
doesn't happen again, we now use the same definition everywhere (thanks,
Nick).

include/ChangeLog:

2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>

        * elf/riscv.h (RISCV_GP_SYMBOL): New define.

bfd/ChangeLog:

2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>

        * elfnn-riscv.c (GP_NAME): Delete.
        (riscv_global_pointer_value): Change GP_NAME to RISCV_GP_SYMBOL.
        (_bfd_riscv_relax_lui): Likewise.

opcodes/ChangeLog:

2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>

        * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
        RISCV_GP_SYMBOL.
2017-04-04 08:29:16 -07:00
Andrew Waterman
858f82bf7e RISC-V: Add physical memory protection CSRs
2017-03-27  Andrew Waterman  <andrew@sifive.com>

       * opcode/riscv-opc.h (CSR_PMPCFG0): New define.
       (CSR_PMPCFG1): Likewise.
       (CSR_PMPCFG2): Likewise.
       (CSR_PMPCFG3): Likewise.
       (CSR_PMPADDR0): Likewise.
       (CSR_PMPADDR1): Likewise.
       (CSR_PMPADDR2): Likewise.
       (CSR_PMPADDR3): Likewise.
       (CSR_PMPADDR4): Likewise.
       (CSR_PMPADDR5): Likewise.
       (CSR_PMPADDR6): Likewise.
       (CSR_PMPADDR7): Likewise.
       (CSR_PMPADDR8): Likewise.
       (CSR_PMPADDR9): Likewise.
       (CSR_PMPADDR10): Likewise.
       (CSR_PMPADDR11): Likewise.
       (CSR_PMPADDR12): Likewise.
       (CSR_PMPADDR13): Likewise.
       (CSR_PMPADDR14): Likewise.
       (CSR_PMPADDR15): Likewise.
       (pmpcfg0): Declare register.
       (pmpcfg1): Likewise.
       (pmpcfg2): Likewise.
       (pmpcfg3): Likewise.
       (pmpaddr0): Likewise.
       (pmpaddr1): Likewise.
       (pmpaddr2): Likewise.
       (pmpaddr3): Likewise.
       (pmpaddr4): Likewise.
       (pmpaddr5): Likewise.
       (pmpaddr6): Likewise.
       (pmpaddr7): Likewise.
       (pmpaddr8): Likewise.
       (pmpaddr9): Likewise.
       (pmpaddr10): Likewise.
       (pmpaddr11): Likewise.
       (pmpaddr12): Likewise.
       (pmpaddr13): Likewise.
       (pmpaddr14): Likewise.
       (pmpaddr15): Likewise.
2017-03-31 09:35:11 -07:00
Pip Cet
f96bd6c2d7 Add support for the WebAssembly file format and the wasm32 ELF conversion to gas and the binutils.
binutils * readelf.c: Add support for wasm32 ELF format WebAssembly files.
	(guess_is_rela): Likewise.
	(dump_relocations): Likewise.
	(is_32bit_abs_reloc): Likewise.
	(is_none_reloc_): Likewise.
	* NEWS: Mention the new support.
	* testsuite/lib/binutils-common.exp (is_elf_format): Mark wasm32
	as ELF target.
	(supports_gnu_unique): Mark wasm32 as supporting STB_GNU_UNIQUE.
	* testsuite/binutils-all/nm.exp: Mark wasm32 as requiring .size annotations.
	* testsuite/binutils-all/wasm32: New directory.
	* testsuite/binutils-all/wasm32/create-wasm.d: New file.
	* testsuite/binutils-all/wasm32/create-wasm.s: Likewise.
	* testsuite/binutils-all/wasm32/custom-section.d: Likewise.
	* testsuite/binutils-all/wasm32/custom-section.s: Likewise.
	* testsuite/binutils-all/wasm32/invalid-wasm-1.d: Likewise.
	* testsuite/binutils-all/wasm32/invalid-wasm-1.s: Likewise.
	* testsuite/binutils-all/wasm32/long-sections.d: Likewise.
	* testsuite/binutils-all/wasm32/long-sections.s: Likewise.
	* testsuite/binutils-all/wasm32/parse-wasm.d: Likewise.
	* testsuite/binutils-all/wasm32/parse-wasm.s: Likewise.
	* testsuite/binutils-all/wasm32/parse-wasm-2.d: Likewise.
	* testsuite/binutils-all/wasm32/parse-wasm-2.s: Likewise.
	* testsuite/binutils-all/wasm32/prepared-section.d: Likewise.
	* testsuite/binutils-all/wasm32/prepared-section.s: Likewise.
	* testsuite/binutils-all/wasm32/wasm32.exp: New file, run tests.

gas	* config/tc-wasm32.h: New file: Add WebAssembly assembler target.
	* config/tc-wasm32.c: New file: Add WebAssembly assembler target.
	* Makefile.am: Add WebAssembly assembler target.
	* configure.tgt: Add WebAssembly assembler target.
	* doc/c-wasm32.texi: New file: Start documenting WebAssembly
	assembler.
	* doc/all.texi: Define WASM32.
	* doc/as.texinfo: Add WebAssembly entries.
	* NEWS: Mention the new support.
	* Makefile.in: Regenerate.
	* po/gas.pot: Regenerate.
	* po/POTFILES.in: Regenerate.
	* testsuite/gas/wasm32: New directory.
	* testsuite/gas/wasm32/allinsn.d: New file.
	* testsuite/gas/wasm32/allinsn.s: New file.
	* testsuite/gas/wasm32/illegal.l: New file.
	* testsuite/gas/wasm32/illegal.s: New file.
	* testsuite/gas/wasm32/illegal-2.l: New file.
	* testsuite/gas/wasm32/illegal-2.s: New file.
	* testsuite/gas/wasm32/illegal-3.l: New file.
	* testsuite/gas/wasm32/illegal-3.s: New file.
	* testsuite/gas/wasm32/illegal-4.l: New file.
	* testsuite/gas/wasm32/illegal-4.s: New file.
	* testsuite/gas/wasm32/illegal-5.l: New file.
	* testsuite/gas/wasm32/illegal-5.s: New file.
	* testsuite/gas/wasm32/illegal-6.l: New file.
	* testsuite/gas/wasm32/illegal-6.s: New file.
	* testsuite/gas/wasm32/illegal-7.l: New file.
	* testsuite/gas/wasm32/illegal-7.s: New file.
	* testsuite/gas/wasm32/illegal-8.l: New file.
	* testsuite/gas/wasm32/illegal-8.s: New file.
	* testsuite/gas/wasm32/illegal-9.l: New file.
	* testsuite/gas/wasm32/illegal-9.s: New file.
	* testsuite/gas/wasm32/illegal-10.l: New file.
	* testsuite/gas/wasm32/illegal-10.s: New file.
	* testsuite/gas/wasm32/illegal-11.l: New file.
	* testsuite/gas/wasm32/illegal-11.s: New file.
	* testsuite/gas/wasm32/illegal-12.l: New file.
	* testsuite/gas/wasm32/illegal-12.s: New file.
	* testsuite/gas/wasm32/illegal-13.l: New file.
	* testsuite/gas/wasm32/illegal-13.s: New file.
	* testsuite/gas/wasm32/illegal-14.l: New file.
	* testsuite/gas/wasm32/illegal-14.s: New file.
	* testsuite/gas/wasm32/illegal-15.l: New file.
	* testsuite/gas/wasm32/illegal-15.s: New file.
	* testsuite/gas/wasm32/illegal-16.l: New file.
	* testsuite/gas/wasm32/illegal-16.s: New file.
	* testsuite/gas/wasm32/illegal-17.l: New file.
	* testsuite/gas/wasm32/illegal-17.s: New file.
	* testsuite/gas/wasm32/illegal-18.l: New file.
	* testsuite/gas/wasm32/illegal-18.s: New file.
	* testsuite/gas/wasm32/illegal-19.l: New file.
	* testsuite/gas/wasm32/illegal-19.s: New file.
	* testsuite/gas/wasm32/illegal-20.l: New file.
	* testsuite/gas/wasm32/illegal-20.s: New file.
	* testsuite/gas/wasm32/illegal-21.l: New file.
	* testsuite/gas/wasm32/illegal-21.s: New file.
	* testsuite/gas/wasm32/illegal-22.l: New file.
	* testsuite/gas/wasm32/illegal-22.s: New file.
	* testsuite/gas/wasm32/illegal-24.l: New file.
	* testsuite/gas/wasm32/illegal-24.s: New file.
	* testsuite/gas/wasm32/illegal-25.l: New file.
	* testsuite/gas/wasm32/illegal-25.s: New file.
	* testsuite/gas/wasm32/reloc.d: New file.
	* testsuite/gas/wasm32/reloc.s: New file.
	* testsuite/gas/wasm32/wasm32.exp: New tests for WebAssembly
	architecture.

opcodes * configure.ac: Add (empty) bfd_wasm32_arch target.
	* configure: Regenerate
	* po/opcodes.pot: Regenerate.

include	* opcode/wasm.h: New file to support wasm32 architecture.
	* elf/wasm32.h: Add R_WASM32_32 relocation.

bfd	* elf32-wasm32.c: Add relocation code, two relocs.
	* reloc.c: Add wasm32 relocations.
	* libbfd.h: Regenerate.
	* bfd-in2.h: Regenerate.
	* bfd/po/bfd.pot: Regenerate.
2017-03-30 10:57:21 +01:00
Alan Modra
52be03fd13 PowerPC -Mraw disassembly
This adds -Mraw for PowerPC objdump, a disassembler option to display
the underlying machine instruction rather than aliases.  For example,
"rlwinm" always rather than "rotlwi" when the instruction is
performing a simple rotate.

binutils/
	* doc/binutils.texi (objdump): Document PowerPC -M options.
gas/
	* config/tc-ppc.c (md_parse_option): Reject -mraw.
include/
	* opcode/ppc.h (PPC_OPCODE_RAW): Define.
	(PPC_OPCODE_*): Make them all unsigned long long constants.
opcodes/
	* ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags.  Add
	"raw" option.
	(lookup_powerpc): Don't special case -1 dialect.  Handle
	PPC_OPCODE_RAW.
	(print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
	lookup_powerpc call, pass it on second.
2017-03-29 22:55:18 +10:30
Pip Cet
8fb740dd30 Add minimal support for WebAssembly backend to the BFD library.
include * elf/wasm32.h: New file to support wasm32 architecture.

bfd * cpu-wasm32.c: New file to support wasm32 architecture.
    * elf32-wasm32.c: New file to support wasm32 architecture.
    * Makefile.am: Add wasm32 architecture.
    * archures.c: Likewise.
    * config.bfd: Likewise.
    * configure.ac: Likewise.
    * targets.c: Likewise.
2017-03-27 11:39:50 +01:00
Rinat Zelig
c0c31e91ad Implement ARC NPS-400 Ultra Ip and Miscellaneous instructions.
opcodes	* arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
	* arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR, F_NPS_M, F_NPS_CORE, F_NPS_ALL.
	(insert_nps_misc_imm_offset): New function.
	(extract_nps_misc imm_offset): New function.
	(arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
	(arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.

include * opcode/arc.h (insn_class_t): Add ULTRAIP and MISC class.

gas     * testsuite/gas/arc/nps400-12.s: New file.
        * testsuite/gas/arc/nps400-12.d: New file.
2017-03-27 11:14:30 +01:00
Andreas Krebbel
2253c8f089 S/390: Remove vx2 facility flag
This patch removes the vx2 facility flag.  It will not be used by GCC
and was a misnomer anyway.

Committed to mainline and 2.28 branch.

include/ChangeLog:

2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* opcode/s390.h (S390_INSTR_FLAG_VX2): Remove.
	(S390_INSTR_FLAG_FACILITY_MASK): Adjust value.

gas/ChangeLog:

2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* config/tc-s390.c (s390_parse_cpu): Remove S390_INSTR_FLAG_VX2
	from cpu_table.  Remove vx2, and novx2 from cpu_flags.

opcodes/ChangeLog:

2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* s390-mkopc.c (main): Remove vx2 check.
	* s390-opc.txt: Remove vx2 instruction flags.
2017-03-21 14:21:02 +01:00
Rinat Zelig
645d3342ba arc/nps400: Add cp16/cp32 instructions to opcodes library
Instructions for loading or storing 16/32B data from one address type to
another.

gas/ChangeLog

	* testsuite/gas/arc/nps400-11.s: New file.
	* testsuite/gas/arc/nps400-11.d: New file.

include/ChangeLog

	* opcode/arc.h (insn_class_t): Add DMA class.

opcodes/ChangeLog

	* arc-nps400-tbl.h: Add cp32/cp16 instructions format.
	* arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
	(insert_nps_imm_offset): New function.
	(extract_nps_imm_offset): New function.
	(insert_nps_imm_entry): New function.
	(extract_nps_imm_entry): New function.
2017-03-21 11:51:49 +00:00
Nick Clifton
a8be5506b6 Add support for a GNU BUILD note type to record the enum size.
include	* elf/common.h (GNU_BUILD_ATTRIBUTE_SHORT_ENUM): New GNU BUILD
	note type.

binutils * readelf.c (print_gnu_build_attribute_name): Add support for
	GNU_BUILD_ATTRIBUTE_SHORT_ENUM.
2017-03-16 16:44:55 +00:00
H.J. Lu
c98763221a Add DW_OP_GNU_variable_value
Sync GCC dwarf.def change

2017-03-14  Jakub Jelinek  <jakub@redhat.com>

	PR debug/77589
	* dwarf2.def (DW_OP_GNU_variable_value): New opcode.
2017-03-14 12:57:48 -07:00
Nick Clifton
c793cac124 Sync libiberty sources with GCC.
PR demangler/70909
	PR demangler/67264
	* cp-demangle.c: Fix endless recursion. Pass
	struct demangle_component as non const.
	(d_make_empty): Initialize variable.
	(d_print_comp_inner): Limit recursion.
	(d_print_comp): Decrement variable.
	* cp-demint.c (cplus_demangle_fill_component): Initialize
	variable.
	(cplus_demangle_fill_builtin_type): Likewise.
	(cplus_demangle_fill_operator): Likewise.
	* testsuite/demangle-expected: Add tests.
2017-03-13 17:49:32 +00:00
Nick Clifton
f955cccff3 Rename R_AARCH64_TLSDESC_LD64_LO12_NC to R_AARCH64_TLSDESC_LD64_LO12 and R_AARCH64_TLSDESC_ADD_LO12_NC to R_AARCH64_TLSDESC_ADD_LO12.
PR binutils/21202
include	* elf/aarch64.h (R_AARCH64_TLSDESC_LD64_LO12_NC): Rename to
	R_AARCH64_TLSDESC_LD64_LO12.
	(R_AARCH64_TLSDESC_ADD_LO12_NC): Rename to
	R_AARCH64_TLSDESC_ADD_LO12_NC.

bfd	* reloc.c (BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC): Rename to
	BFD_RELOC_AARCH64_TLSDESC_LD64_LO12.
	(BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC): Rename to
	BFD_RELOC_AARCH64_TLSDESC_ADD_LO12.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Regenerate.
	* elfnn-aarch64.c (IS_AARCH64_TLS_RELAX_RELOC): Update reloc
	names.
	(IS_AARCH64_TLSDESC_RELOC): Likewise.
	(elfNN_aarch64_howto_table): Likewise.
	(aarch64_tls_transition_without_check): Likewise.
	(aarch64_reloc_got_type): Likewise.
	(elfNN_aarch64_final_link_relocate): Likewise.
	(elfNN_aarch64_tls_relax): Likewise.
	(elfNN_aarch64_relocate_section): Likewise.
	(elfNN_aarch64_gc_sweep_hook): Likewise.
	(elfNN_aarch64_check_relocs): Likewise.
	* elfxx-aarch64.c (_bfd_aarch64_elf_put_addend): Likewise.
	(_bfd_aarch64_elf_resolve_relocation): Likewise.

gas	* config/tc-aarch64.c (reloc_table): Rename
	BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC to
	BFD_RELOC_AARCH64_TLSDESC_LD64_LO12.  Rname
	BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC to
	BFD_RELOC_AARCH64_TLSDESC_ADD_LO12.
	(md_apply_fix): Likewise.
	(aarch64_force_relocation): Likewise.
	* testsuite/gas/aarch64/tls.d: Update regexp.

ld	* testsuite/ld-aarch64/ifunc-5r-local.d: Update regexp.
2017-03-13 09:58:04 +00:00
Nick Clifton
55e22ca83a Add basic recognition of new EM_ ELF machine numbers.
include	* elf/common.h (EM_LANAI): New machine number.
	(EM_BPF): Likewise.
	(EM_WEBASSEMBLY): Likewise.
	Move low value, deprecated, numbers to their numerical
	equivalents.

binutils * readelf.c (get_machine_name): Rearrange switch table in order of
	increasing machine number.  Add missing entries.
2017-03-10 10:50:34 +00:00
H.J. Lu
1fc87489b4 Properly dump NT_GNU_PROPERTY_TYPE_0
Property type and datasz are always 4 bytes for both 32-bit and 64-bit
objects.  Property values for GNU_PROPERTY_X86_ISA_1_USED and
GNU_PROPERTY_X86_ISA_1_NEEDED are 4 bytes for both i386 and x86-64
objects.  We should also check GNU_PROPERTY_LOPROC and
GNU_PROPERTY_LOUSER.

binutils/

	PR binutils/21231
	* readelf.c (decode_x86_isa): Change argument to unsigned int.
	(print_gnu_property_note): Retrieve property type and datasz as
	4-byte integer.  Consolidate property datasz check.  Check
	GNU_PROPERTY_LOPROC and GNU_PROPERTY_LOUSER.
	* testsuite/binutils-all/i386/pr21231a.d: New file.
	* testsuite/binutils-all/i386/pr21231a.s: Likewise.
	* testsuite/binutils-all/i386/pr21231b.d: Likewise.
	* testsuite/binutils-all/i386/pr21231b.s: Likewise.
	* testsuite/binutils-all/x86-64/pr21231a.d: Likewise.
	* testsuite/binutils-all/x86-64/pr21231a.s: Likewise.
	* testsuite/binutils-all/x86-64/pr21231b.d: Likewise.
	* testsuite/binutils-all/x86-64/pr21231b.s: Likewise.

include/

	PR binutils/21231
	* elf/common.h (GNU_PROPERTY_LOPROC): New.
	(GNU_PROPERTY_HIPROC): Likewise.
	(GNU_PROPERTY_LOUSER): Likewise.
	(GNU_PROPERTY_HIUSER): Likewise.
2017-03-08 07:44:17 -08:00
Nick Clifton
9ef920e933 Add support for displaying and merging GNU_BUILD_NOTEs.
include	* elf/common.h (SHF_GNU_BUILD_NOTE): Define.
	(NT_GNU_PROPERTY_TYPE_0): Define.
	(NT_GNU_BUILD_ATTRIBUTE_OPEN): Define.
	(NT_GNU_BUILD_ATTRIBUTE_FUN): Define.
	(GNU_BUILD_ATTRIBUTE_TYPE_NUMERIC): Define.
	(GNU_BUILD_ATTRIBUTE_TYPE_STRING): Define.
	(GNU_BUILD_ATTRIBUTE_TYPE_BOOL_TRUE): Define.
	(GNU_BUILD_ATTRIBUTE_TYPE_BOOL_FALSE): Define.
	(GNU_BUILD_ATTRIBUTE_VERSION): Define.
	(GNU_BUILD_ATTRIBUTE_STACK_PROT): Define.
	(GNU_BUILD_ATTRIBUTE_RELRO): Define.
	(GNU_BUILD_ATTRIBUTE_STACK_SIZE): Define.
	(GNU_BUILD_ATTRIBUTE_TOOL): Define.
	(GNU_BUILD_ATTRIBUTE_ABI): Define.
	(GNU_BUILD_ATTRIBUTE_PIC): Define.
	(NOTE_GNU_PROPERTY_SECTION_NAME): Define.
	(GNU_BUILD_ATTRS_SECTION_NAME): Define.
	(GNU_PROPERTY_STACK_SIZE): Define.
	(GNU_PROPERTY_NO_COPY_ON_PROTECTED): Define.
	(GNU_PROPERTY_X86_ISA_1_USED): Define.
	(GNU_PROPERTY_X86_ISA_1_NEEDED): Define.
	(GNU_PROPERTY_X86_ISA_1_486): Define.
	(GNU_PROPERTY_X86_ISA_1_586): Define.
	(GNU_PROPERTY_X86_ISA_1_686): Define.
	(GNU_PROPERTY_X86_ISA_1_SSE): Define.
	(GNU_PROPERTY_X86_ISA_1_SSE2): Define.
	(GNU_PROPERTY_X86_ISA_1_SSE3): Define.
	(GNU_PROPERTY_X86_ISA_1_SSSE3): Define.
	(GNU_PROPERTY_X86_ISA_1_SSE4_1): Define.
	(GNU_PROPERTY_X86_ISA_1_SSE4_2): Define.
	(GNU_PROPERTY_X86_ISA_1_AVX): Define.
	(GNU_PROPERTY_X86_ISA_1_AVX2): Define.
	(GNU_PROPERTY_X86_ISA_1_AVX512F): Define.
	(GNU_PROPERTY_X86_ISA_1_AVX512CD): Define.
	(GNU_PROPERTY_X86_ISA_1_AVX512ER): Define.
	(GNU_PROPERTY_X86_ISA_1_AVX512PF): Define.
	(GNU_PROPERTY_X86_ISA_1_AVX512VL): Define.
	(GNU_PROPERTY_X86_ISA_1_AVX512DQ): Define.
	(GNU_PROPERTY_X86_ISA_1_AVX512BW): Define.

binutils* readelf.c (get_note_type): Add support for GNU_BUILD_NOTEs.
	(get_gnu_elf_note_type): Add support for GNU_PROPERTY_NOTEs.
	(decode_x86_isa): New function.
	(print_gnu_property_note): New function.
	(print_gnu_note): Handle GNU_PROPERTY_NOTEs.
	(print_gnu_build_attribute_description): New function.
	(print_gnu_build_attribute_name): New function.
	(process_note): Add support for GNU_BUILD_NOTEs.
	* objcopy.c (--merge-notes): New command line option.
	(copy_options): Add merge-notes.
	(copy_usage): Likewise.
	(is_merge_note_section): New function.
	(merge_gnu_build_notes): New function.
	(copy_object): Merge note sections if asked to do so.
	(skip_section): Add skip_copy parameter.  Add support for skipping
	merged note sections.
	(copy_relocations_in_section): Update call to skip_section.
	(copy_section): Likewise.
	(copy_main): Add support for merge-notes option.
	* doc/binutils.texi: Document the new option to objcopy.
	* NEWS: Mention the new feature.
	* testsuite/binutils-all/note-2-32.d: New test.  Checks note
	merging on 32-bit targets.
	* testsuite/binutils-all/note-2-32.s: New test source file.
	* testsuite/binutils-all/note-2-64.d: New test.  Like note-2-32.d
	but for 64-bit targets.
	* testsuite/binutils-all/note-2-64.s: New test source file.
	* testsuite/binutils-all/objcopy.exp: Run the new test.
2017-03-01 11:09:46 +00:00
Peter Bergner
65b48a8140 GDB: Add support for the new set/show disassembler-options commands.
This commit adds support to GDB so that it can modify the disassembler-options
value that is passed to the disassembler, similar to objdump's -M option.
Currently, the only supported targets are ARM, PowerPC and S/390, but
adding support for a new target(s) is not difficult.

include/
	* dis-asm.h (disasm_options_t): New typedef.
	(parse_arm_disassembler_option): Remove prototype.
	(set_arm_regname_option): Likewise.
	(get_arm_regnames): Likewise.
	(get_arm_regname_num_options): Likewise.
	(disassemble_init_s390): New prototype.
	(disassembler_options_powerpc): Likewise.
	(disassembler_options_arm): Likewise.
	(disassembler_options_s390): Likewise.
	(remove_whitespace_and_extra_commas): Likewise.
	(disassembler_options_cmp): Likewise.
	(next_disassembler_option): New inline function.
	(FOR_EACH_DISASSEMBLER_OPTION): New macro.

opcodes/
	* disassemble.c Include "safe-ctype.h".
	(disassemble_init_for_target): Handle s390 init.
	(remove_whitespace_and_extra_commas): New function.
	(disassembler_options_cmp): Likewise.
	* arm-dis.c: Include "libiberty.h".
	(NUM_ELEM): Delete.
	(regnames): Use long disassembler style names.
	Add force-thumb and no-force-thumb options.
	(NUM_ARM_REGNAMES): Rename from this...
	(NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
	(get_arm_regname_num_options): Delete.
	(set_arm_regname_option): Likewise.
	(get_arm_regnames): Likewise.
	(parse_disassembler_options): Likewise.
	(parse_arm_disassembler_option): Rename from this...
	(parse_arm_disassembler_options): ...to this.  Make static.
	Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
	(print_insn): Use parse_arm_disassembler_options.
	(disassembler_options_arm): New function.
	(print_arm_disassembler_options): Handle updated regnames.
	* ppc-dis.c: Include "libiberty.h".
	(ppc_opts): Add "32" and "64" entries.
	(ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
	(powerpc_init_dialect): Add break to switch statement.
	Use new FOR_EACH_DISASSEMBLER_OPTION macro.
	(disassembler_options_powerpc): New function.
	(print_ppc_disassembler_options): Use ARRAY_SIZE.
	Remove printing of "32" and "64".
	* s390-dis.c: Include "libiberty.h".
	(init_flag): Remove unneeded variable.
	(struct s390_options_t): New structure type.
	(options): New structure.
	(init_disasm): Rename from this...
	(disassemble_init_s390): ...to this.  Add initializations for
	current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
	(print_insn_s390): Delete call to init_disasm.
	(disassembler_options_s390): New function.
	(print_s390_disassembler_options): Print using information from
	struct 'options'.
	* po/opcodes.pot: Regenerate.

binutils/
	* objdump.c (main): Use remove_whitespace_and_extra_commas.

gdb/
	* NEWS: Mention new set/show disassembler-options commands.
	* doc/gdb.texinfo: Document new set/show disassembler-options commands.
	* disasm.c: Include "arch-utils.h", "gdbcmd.h" and "safe-ctype.h".
	(prospective_options): New static variable.
	(gdb_disassembler::gdb_disassembler): Initialize
	m_di.disassembler_options.
	(gdb_buffered_insn_length_init_dis): Initilize di->disassembler_options.
	(get_disassembler_options): New function.
	(set_disassembler_options): Likewise.
	(set_disassembler_options_sfunc): Likewise.
	(show_disassembler_options_sfunc): Likewise.
	(disassembler_options_completer): Likewise.
	(_initialize_disasm): Likewise.
	* disasm.h (get_disassembler_options): New prototype.
	(set_disassembler_options): Likewise.
	* gdbarch.sh (gdbarch_disassembler_options): New variable.
	(gdbarch_verify_disassembler_options): Likewise.
	* gdbarch.c: Regenerate.
	* gdbarch.h: Likewise.
	* arm-tdep.c (num_disassembly_options): Delete.
	(set_disassembly_style): Likewise.
	(arm_disassembler_options): New static variable.
	(set_disassembly_style_sfunc): Convert short style name into long
	option name.  Call set_disassembler_options.
	(show_disassembly_style_sfunc): New function.
	(arm_gdbarch_init): Call set_gdbarch_disassembler_options and
	set_gdbarch_verify_disassembler_options.
	(_initialize_arm_tdep): Delete regnames variable and update callers.
	(arm_disassembler_options): Initialize.
	(disasm_options): New variable.
	(num_disassembly_options): Rename from this...
	(num_disassembly_styles): ...to this.  Compute by scanning through
	disasm_options.
	(valid_disassembly_styles): Initialize using disasm_options.
	Remove calls to parse_arm_disassembler_option, get_arm_regnames and
	set_arm_regname_option.
	Pass show_disassembly_style_sfunc to the "disassembler" setshow command.
	* rs6000-tdep.c (powerpc_disassembler_options): New static variable.
	(rs6000_gdbarch_init): Call set_gdbarch_disassembler_options and
	set_gdbarch_verify_disassembler_options.
	* s390-tdep.c (s390_disassembler_options): New static variable.
	(s390_gdbarch_init):all set_gdbarch_disassembler_options and
	set_gdbarch_verify_disassembler_options.

gdb/testsuite/
	* gdb.arch/powerpc-power.exp: Delete test.
	* gdb.arch/powerpc-power.s: Likewise.
	* gdb.disasm/disassembler-options.exp: New test.
	* gdb.arch/powerpc-altivec.exp: Likewise.
	* gdb.arch/powerpc-altivec.s: Likewise.
	* gdb.arch/powerpc-altivec2.exp: Likewise.
	* gdb.arch/powerpc-altivec2.s: Likewise.
	* gdb.arch/powerpc-altivec3.exp: Likewise.
	* gdb.arch/powerpc-altivec3.s: Likewise.
	* gdb.arch/powerpc-power7.exp: Likewise.
	* gdb.arch/powerpc-power7.s: Likewise.
	* gdb.arch/powerpc-power8.exp: Likewise.
	* gdb.arch/powerpc-power8.s: Likewise.
	* gdb.arch/powerpc-power9.exp: Likewise.
	* gdb.arch/powerpc-power9.s: Likewise.
	* gdb.arch/powerpc-vsx.exp: Likewise.
	* gdb.arch/powerpc-vsx.s: Likewise.
	* gdb.arch/powerpc-vsx2.exp: Likewise.
	* gdb.arch/powerpc-vsx2.s: Likewise.
	* gdb.arch/powerpc-vsx3.exp: Likewise.
	* gdb.arch/powerpc-vsx3.s: Likewise.
	* gdb.arch/arm-disassembler-options.exp: Likewise.
	* gdb.arch/powerpc-disassembler-options.exp: Likewise.
	* gdb.arch/s390-disassembler-options.exp: Likewise.
2017-02-28 12:32:07 -06:00
Alan Modra
7ba71655a4 PowerPC addpcis fix
This came up because I was looking at ld/tmpdir/addpcis.o and noticed
the odd addends on REL16DX_HA.  They ought to both be -4.  The error
crept in due REL16DX_HA howto being pc-relative (as indeed it should
be), and code at gas/write.c:1001 after this comment
	      /* Make it pc-relative.  If the back-end code has not
		 selected a pc-relative reloc, cancel the adjustment
		 we do later on all pc-relative relocs.  */
*not* cancelling the pc-relative adjustment.  So I've made a dummy
non-relative split reloc so that the generic code handles this, rather
than attempting to add hacks later in md_apply_fix which would not be
very robust.  Having the new internal reloc also makes it easy to
support

 addpcis rx,sym@ha

as an equivalent to

 addpcis rx,(sym-0f)@ha
0:

The patch also fixes overflow checking, which must test whether the
addi will overflow too since @l relocs don't have any overflow check.

Lastly, since I was poking at md_apply_fix, I arranged to have the
generic gas/write.c code emit errors for subtraction expressions where
we lack reloc support.

include/
	* elf/ppc64.h (R_PPC64_16DX_HA): New.  Expand fake reloc comment.
	* elf/ppc.h (R_PPC_16DX_HA): Likewise.
bfd/
	* reloc.c (BFD_RELOC_PPC_16DX_HA): New.
	* elf64-ppc.c (ppc64_elf_howto_raw <R_PPC64_16DX_HA>): New howto.
	(ppc64_elf_reloc_type_lookup): Translate new bfd reloc.
	(ppc64_elf_ha_reloc): Correct overflow test on REL16DX_HA.
	(ppc64_elf_relocate_section): Likewise.
	* elf32-ppc.c (ppc_elf_howto_raw <R_PPC_16DX_HA>): New howto.
	(ppc_elf_reloc_type_lookup): Translate new bfd reloc.
	(ppc_elf_check_relocs): Handle R_PPC_16DX_HA to pacify gcc.
	* libbfd.h: Regenerate.
	* bfd-in2.h: Regenerate.
gas/
	* config/tc-ppc.c (md_assemble): Use BFD_RELOC_PPC_16DX_HA for addpcis.
	(md_apply_fix): Remove fx_subsy check.  Move code converting to
	pcrel reloc earlier and handle BFD_RELOC_PPC_16DX_HA.  Remove code
	emiiting errors on seeing fx_pcrel set on unexpected relocs, as
	that is done now by the generic code via..
	* config/tc-ppc.h (TC_FORCE_RELOCATION_SUB_LOCAL): ..this. Define.
	(TC_VALIDATE_FIX_SUB): Define.
ld/
	* testsuite/ld-powerpc/addpcis.d: Define ext1 and ext2 at
	limits of addpcis range.
2017-02-28 11:59:47 +10:30
Richard Sandiford
582e12bf76 [AArch64] Additional SVE instructions
This patch supports some additions to the SVE architecture prior to
its public release.

include/
	* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4x16)
	(AARCH64_OPND_SVE_IMM_ROT1, AARCH64_OPND_SVE_IMM_ROT2)
	(AARCH64_OPND_SVE_Zm3_INDEX, AARCH64_OPND_SVE_Zm3_22_INDEX)
	(AARCH64_OPND_SVE_Zm4_INDEX): New aarch64_opnds.

opcodes/
	* aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
	(OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
	(OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
	(OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
	(OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
	(OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
	(OP_SVE_V_HSD): New macros.
	(OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
	(OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
	(OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
	(aarch64_opcode_table): Add new SVE instructions.
	(aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
	for rotation operands.  Add new SVE operands.
	* aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
	(ins_sve_quad_index): Likewise.
	(ins_imm_rotate): Split into...
	(ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
	* aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
	(aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
	functions.
	(aarch64_ins_sve_addr_ri_s4): New function.
	(aarch64_ins_sve_quad_index): Likewise.
	(do_misc_encoding): Handle "MOV Zn.Q, Qm".
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
	(ext_sve_quad_index): Likewise.
	(ext_imm_rotate): Split into...
	(ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
	* aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
	(aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
	functions.
	(aarch64_ext_sve_addr_ri_s4): New function.
	(aarch64_ext_sve_quad_index): Likewise.
	(aarch64_ext_sve_index): Allow quad indices.
	(do_misc_decoding): Likewise.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
	aarch64_field_kinds.
	(OPD_F_OD_MASK): Widen by one bit.
	(OPD_F_NO_ZR): Bump accordingly.
	(get_operand_field_width): New function.
	* aarch64-opc.c (fields): Add new SVE fields.
	(operand_general_constraint_met_p): Handle new SVE operands.
	(aarch64_print_operand): Likewise.
	* aarch64-opc-2.c: Regenerate.

gas/
	* doc/c-aarch64.texi: Document that sve implies fp16, simd and compnum.
	* config/tc-aarch64.c (parse_vector_type_for_operand): Allow .q
	to be used with SVE registers.
	(parse_operands): Handle new SVE operands.
	(aarch64_features): Make "sve" require F16 rather than FP.  Also
	require COMPNUM.
	* testsuite/gas/aarch64/sve.s: Add tests for new instructions.
	Include compnum tests.
	* testsuite/gas/aarch64/sve.d: Update accordingly.
	* testsuite/gas/aarch64/sve-invalid.s: Add tests for new instructions.
	* testsuite/gas/aarch64/sve-invalid.l: Update accordingly.  Also
	update expected output for new FMOV and MOV alternatives.
2017-02-24 18:29:00 +00:00
Richard Sandiford
f482d30447 [AArch64] Add a "compnum" feature
This patch adds a named "compnum" feature for the ARMv8.3-A FCADD
and FCMLA extensions.

include/
	* opcode/aarch64.h (AARCH64_FEATURE_COMPNUM): New macro.
	(AARCH64_ARCH_V8_3): Include AARCH64_FEATURE_COMPNUM.

opcodes/
	* aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
	(aarch64_feature_compnum): ...this.
	(SIMD_V8_3): Replace with...
	(COMPNUM): ...this.
	(CNUM_INSN): New macro.
	(aarch64_opcode_table): Use it for the complex number instructions.

gas/
	* doc/c-aarch64.texi: Add a "compnum" entry.
	* config/tc-aarch64.c (aarch64_features): Likewise,
	* testsuite/gas/aarch64/advsimd-compnum.s: New test.
	* testsuite/gas/aarch64/advsimd-compnum.d: Likewise.
2017-02-24 18:27:26 +00:00
Andrew Waterman
742d14b39b Add new counter-enable CSRs
include/ChangeLog:

2017-02-22  Andrew Waterman  <andrew@sifive.com>

       * opcode/riscv-opc.h (CSR_SCOUNTEREN): New define.
       (CSR_MCOUNTEREN): Likewise.
       (scounteren): Declare register.
       (mcounteren): Likewise.
2017-02-24 09:24:58 -08:00
Andreas Krebbel
64025b4ec9 S/390: Add support for new cpu architecture - arch12.
This adds support of new instructions to the S/390 specific parts.

The important feature of the new instruction set is the support of
single and extended precision floating point vector operations.

Note: arch12 is NOT the official name of the new CPU.  It just
continues the series of archXX options supported as alternate names.
The archXX terminology refers to the edition number of the Principle
of Operations manual.  The official CPU name will be added later while
keeping support of the arch12 for backwards compatibility.

No testsuite regressions.

Committed to mainline.

Bye,

-Andreas-

opcodes/ChangeLog:

2017-02-23  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* s390-mkopc.c (main): Accept arch12 as cpu string and vx2 as
	facility.
	* s390-opc.c: Add new operand description macros, new instruction
	types, instruction masks, and new .insn instruction types.
	* s390-opc.txt: Add new arch12 instructions.

include/ChangeLog:

2017-02-23  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* opcode/s390.h (enum s390_opcode_cpu_val): New value
	S390_OPCODE_ARCH12.
	(S390_INSTR_FLAG_VX2): New macro definition.

gas/ChangeLog:

2017-02-23  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* config/tc-s390.c (s390_parse_cpu): New entry for arch12.
	* doc/as.texinfo: Document arch12 as cpu type.
	* doc/c-s390.texi: Likewise.
	* testsuite/gas/s390/s390.exp: Run arch12 specific tests.
	* testsuite/gas/s390/zarch-arch12.d: New test.
	* testsuite/gas/s390/zarch-arch12.s: New test.
	* testsuite/gas/s390/zarch-z13.d: Rename some mnemonics in the
	output patterns.
2017-02-23 18:27:38 +01:00
Sheldon Lobo
1e9d41d49f opcodes,gas: associate SPARC ASIs with an architecture level.
With this change an architecture level bump due to assembly ASIs will show
up as a warning/error depending on options passed to gas.

Tested with sparc64-linux-gnu, and it does not introduce any regressions.

gas/ChangeLog:

	Add support for associating SPARC ASIs with an architecture level.
	* config/tc-sparc.c (parse_sparc_asi): New encode SPARC ASIs.

opcodes/ChangeLog:

	Add support for associating SPARC ASIs with an architecture level.
	* include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
	* opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
	decoding of SPARC ASIs.
2017-02-23 07:53:16 -08:00
Andrew Waterman
f98d33be3a Add SFENCE.VMA instruction
include/ChangeLog:

2017-02-14  Andrew Waterman  <andrew@sifive.com>

        * opcode/riscv-opc.h (MATCH_SFENCE_VMA): New define.
        (MASK_SFENCE_VMA): Likewise.
        (sfence_vma): Declare instruction.

opcodes/ChangeLog:

2017-02-14  Andrew Waterman  <andrew@sifive.com>

        * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
        pseudoinstructions.
2017-02-15 10:35:00 -08:00
Alan Modra
7e0de605cb PowerPC register expression checks
This stops powerpc gas blithely accepting such nonsense as
"addi %f4,%cr3,%r31".

	PR 21118
gas/
	* NEWS: Mention powerpc register checks.
	* config/tc-ppc.c (struct pd_reg): Make value a short.  Add flags.
	(pre_defined_registers): Delete fpscr and pmr entries.  Set
	register type in flags.
	(cr_names): Set type in flags.
	(reg_name_search): Return pointer to struct pd_reg rather than value.
	(register_name): Adjust to suit.  Set X_md from flags.
	(ppc_parse_name): Likewise.
	(ppc_optimize_expr): New function.
	(md_assemble): Verify expresion reg flags match operand.
	* config/tc-ppc.h (md_optimize_expr): Define.
	(ppc_optimize_expr): Declare.
include/
	* opcode/ppc.h (PPC_OPERAND_*): Reassign values, regs first.
	(PPC_OPERAND_SPR, PPC_OPERAND_GQR): Define.
opcodes/
	* ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
	with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.
2017-02-14 21:12:07 +10:30
Claudiu Zissulescu
6ec7c1ae19 [ARC] Provide an interface to decode ARC instructions.
gas/
2017-02-06  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/tc-arc.c (parse_opcode_flags): Ignore implicit flags.

include/
2017-02-06  Claudiu Zissulescu  <claziss@synopsys.com>
	    Anton Kolesov  <anton.kolesov@synopsys.com>

	* opcode/arc.h (insn_class_t): Add ENTER, LEAVE, POP, PUSH, BBIT0,
	BBIT1, BI, BIH, BRCC, EI, JLI, and SUB instruction classes.
	(flag_class_t): Add F_CLASS_WB, F_CLASS_ZZ, and F_CLASS_IMPLICIT
	flag classes.

opcode/
2017-02-06  Claudiu Zissulescu  <claziss@synopsys.com>
	    Anton Kolesov  <anton.kolesov@synopsys.com>

	* arc-dis.c (arc_disassemble_info): New structure.
	(init_arc_disasm_info): New function.
	(find_format_from_table): Ignore implicit flags.
	(find_format): Update dissassembler private data.
	(print_flags): Likewise.
	(print_insn_arc): Likewise.
	(arc_opcode_to_insn_type): Consider the new added instruction
	classes.
	(arcAnalyzeInstr): Remove.
	(arc_insn_decode): New function.
	* arc-dis.h (arc_ldst_writeback_mode): New enum.
	(arc_ldst_data_size): Likewise.
	(arc_condition_code): Likewise.
	(arc_operand_kind): Likewise.
	(arc_insn_kind): New struct.
	(arc_instruction): Likewise.
	(arc_insn_decode): Declare function.
	(ARC_Debugger_OperandType): Deleted.
	(Flow): Likewise.
	(NullifyMode): Likewise.
	(allOperandsSize): Likewise.
	(arcDisState): Likewise.
	(arcAnalyzeInstr): Likewise.
	* arc-dis.c (arc_opcode_to_insn_type): Handle newly introduced
	insn_class_t enums.
	* arc-opc.c (F_SIZED): New define.
	(C_CC_EQ, C_CC_GE, C_CC_GT, C_CC_HI, C_CC_HS): Likewise.
	(C_CC_LE, C_CC_LO, C_CC_LS, C_CC_LT, C_CC_NE): Likewise.
	(C_CC_NE, C_AA_AB, C_AA_AW, C_ZZ_D, C_ZZ_H, C_ZZ_B): Likewise.
	(arc_flag_classes): Add F_CLASS_COND/F_CLASS_IMPLICIT flags.
	* opcodes/arc-tbl.h: Update instructions to include new
	F_CLASS_IMPLICIT flags.
	(bbit0, lp): Change class.
	(bbit1, bi, bih, br*, ei_s, jli_s): Likewsie
2017-02-06 11:26:13 +01:00
Dimitar Dimitrov
a1aa5e81de Clarify that include/opcode/ files are part of GNU opcodes
include/ChangeLog:
2017-01-25  Dimitar Dimitrov  <dimitar@dinux.eu>

        * opcode/hppa.h: Clarify that file is part of GNU opcodes.
        * opcode/i860.h: Ditto.
        * opcode/nios2.h: Ditto.
        * opcode/nios2r1.h: Ditto.
        * opcode/nios2r2.h: Ditto.
        * opcode/pru.h: Ditto.

opcodes/ChangeLog:
2017-01-25  Dimitar Dimitrov  <dimitar@dinux.eu>

        * pru-opc.c: Remove vague reference to a future GDB port.
2017-01-25 12:30:52 +00:00
Pedro Alves
82f252717e Fix include/ChangeLog entry format
Add missing <> around name.
2017-01-25 12:24:29 +00:00
Alan Hayward
fae1616f5f [PATCH] Add NT_ARM_SVE
* elf/common.h (NT_ARM_SVE): Define.
2017-01-24 10:38:24 +00:00
Jiong Wang
8cf50cb070 [DWARF] Sync GCC dwarf.def change on AArch64
include/
	* dwarf2.def: Sync with mainline gcc sources.
2017-01-04 14:27:52 +00:00
Szabolcs Nagy
d74d4880e2 [AArch64] Add separate feature flag for weaker release consistent load insns
The weaker release consistency support of ARMv8.3-A is allowed as an optional
extension for ARMv8.2-A, so separate command line option and feature flag is
added: -march=armv8.2-a+rcpc turns LDAPR, LDAPRB, LDAPRH instructions on.

opcodes/
	* aarch64-tbl.h (RCPC, RCPC_INSN): Define.
	(aarch64_opcode_table): Use RCPC_INSN.

include/
	* opcode/aarch64.h (AARCH64_FEATURE_RCPC): Define.
	(AARCH64_ARCH_V8_3): Update.

gas/
	* config/tc-aarch64.c (aarch64_features): Add rcpc.
	* doc/c-aarch64.texi (AArch64 Extensions): Document rcpc.
	* testsuite/gas/aarch64/ldst-exclusive-armv8_3.d: Rename to ...
	* testsuite/gas/aarch64/ldst-rcpc.d: This.
	* testsuite/gas/aarch64/ldst-exclusive-armv8_3.s: Rename to ...
	* testsuite/gas/aarch64/ldst-rcpc.s: This.
	* testsuite/gas/aarch64/ldst-rcpc-armv8_2.d: New test.
2017-01-04 12:31:08 +00:00
Kito Cheng
cc917fd93d Add support for the Q extension to the RISCV ISA.
gas    * config/tc-riscv.c (riscv_set_arch): Whitelist the "q" ISA
        extension.
        (riscv_after_parse_args): Set FLOAT_ABI_QUAD when the Q ISA is
        enabled and no other ABI is specified.

include * opcode/riscv-opc.h: Add support for the "q" ISA extension.

opcodes * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
        extension.
        * riscv-opcodes/all-opcodes: Likewise.
2017-01-03 17:42:01 +00:00
Nick Clifton
fb9b4b7e53 Sync dwarf headers with master versions in gcc repository.
* dwarf2.def: Sync with mainline gcc sources
	* dwarf2.h: Likewise.

	2016-12-21  Jakub Jelinek  <jakub@redhat.com>

	* dwarf2.def (DW_FORM_ref_sup): Renamed to ...
	(DW_FORM_ref_sup4): ... this.  New form.
	(DW_FORM_ref_sup8): New form.

	2016-10-17  Jakub Jelinek  <jakub@redhat.com>

	* dwarf2.h (enum dwarf_calling_convention): Add new DWARF5
	calling convention codes.
	(enum dwarf_line_number_content_type): New.
	(enum dwarf_location_list_entry_type): Add DWARF5 DW_LLE_*
	codes.
	(enum dwarf_source_language): Add new DWARF5 DW_LANG_* codes.
	(enum dwarf_macro_record_type): Add DWARF5 DW_MACRO_* codes.
	(enum dwarf_name_index_attribute): New.
	(enum dwarf_range_list_entry): New.
	(enum dwarf_unit_type): New.
	* dwarf2.def: Add new DWARF5 DW_TAG_*, DW_FORM_*, DW_AT_*,
	DW_OP_* and DW_ATE_* entries.

	2016-08-15  Jakub Jelinek  <jakub@redhat.com>

	* dwarf2.def (DW_AT_string_length_bit_size,
	DW_AT_string_length_byte_size): New attributes.

	2016-08-12  Alexandre Oliva <aoliva@redhat.com>

	PR debug/63240
	* dwarf2.def (DW_AT_deleted, DW_AT_defaulted): New.
	* dwarf2.h (enum dwarf_defaulted_attribute): New.
2017-01-03 15:18:52 +00:00
Alan Modra
2571583aed Update year range in copyright notice of all files. 2017-01-02 14:08:56 +10:30
Alan Modra
5c1ad6b5bb ChangeLog rotation 2017-01-02 13:55:05 +10:30
Joel Brobecker
61baf725ec update copyright year range in GDB files
This applies the second part of GDB's End of Year Procedure, which
updates the copyright year range in all of GDB's files.

gdb/ChangeLog:

        Update copyright year range in all GDB files.
2017-01-01 10:52:34 +04:00
Dimitar Dimitrov
889294f6ff PRU BFD support
include/
	* elf/common.h: Add PRU ELF.
	* elf/pru.h: New file.
	* opcode/pru.h: New file.
	* dis-asm.h (print_insn_pru): Declare.
bfd/
	* archures.c: Add bfd_arch_pru.
	* Makefile.am: Add PRU target.
	* config.bfd: Ditto.
	* configure.ac: Ditto.
	* elf-bfd.h (enum elf_target_id): Add PRU_ELF_DATA.
	* targets.c: Add pru_elf32_vec.
	* reloc.c: Add PRU relocations.
	* cpu-pru.c: New file.
	* elf32-pru.c: New file.
	* Makefile.in: Regenerate.
	* configure: Regenerate.
	* po/SRC-POTFILES.in: Regenerate.
	* bfd-in2.h: Regenerate
	* libbfd.h: Regenerate.

Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
2016-12-31 12:02:09 +10:30
Maciej W. Rozycki
5284e471d5 MIPS16: Add ASMACRO instruction support
Add ASMACRO instruction support as per the MIPS16e ASE architecture
specifications [1][2], completing MIPS16e instruction set support.

[1] "MIPS32 Architecture for Programmers, Volume IV-a: The MIPS16e
    Application-Specific Extension to the MIPS32 Architecture", MIPS
    Technologies, Inc., Document Number: MD00076, Revision 2.63, July
    16, 2013, Section 4.1 "MIPS16e Instruction Descriptions", p. 65

[2] "MIPS64 Architecture for Programmers, Volume IV-a: The MIPS16e
    Application-Specific Extension to the MIPS64 Architecture", MIPS
    Technologies, Inc., Document Number: MD00077, Revision 2.60, June
    25, 2008, Section 1.1 "MIPS16e Instruction Descriptions", p. 66

	include/
	* opcode/mips.h: Document `0', `1', `2', `3', `4' and `s'
	operand codes.

	opcodes/
	* mips16-opc.c (decode_mips16_operand): Add `0', `1', `2', `3',
	`4' and `s' operand codes.
	(mips16_opcodes): Add "asmacro" entry.

	binutils/
	* testsuite/binutils-all/mips/mips16-extend-insn.d: Update for
	ASMACRO support.

	gas/
	* testsuite/gas/mips/mips16-asmacro.d: New test.
	* testsuite/gas/mips/mips16-32@mips16-asmacro.d: New test.
	* testsuite/gas/mips/mips16-64@mips16-asmacro.d: New test.
	* testsuite/gas/mips/mips16-asmacro.s: New test source.
	* testsuite/gas/mips/mips.exp: Run the new tests.
2016-12-23 19:55:21 +00:00
Maciej W. Rozycki
d8722d7641 MIPS16: Reassign 0' and 4' operand codes
Replace `0' and `4' operand codes with `.' and `F' respectively to free
up the `0'-`4' consecutive range.  No functional change.

	gas/
	* config/tc-mips.c (mips16_macro_build): Replace `0' and `4'
	operand codes with `.' and `F' respectively.
	(mips16_macro): Likewise.

	include/
	* opcode/mips.h: Replace `0' and `4' operand codes with `.' and
	`F' respectively.

	opcodes/
	* mips16-opc.c (decode_mips16_operand): Replace `0' and `4'
	operand codes with `.' and `F' respectively.
	(mips16_opcodes): Likewise.
2016-12-23 19:37:13 +00:00
Maciej W. Rozycki
0674ee5dad MIPS16: Handle non-extensible instructions correctly
Identify non-extensible instructions in the MIPS16 opcode table and
disallow their use with the `.e' instruction size suffix in assembly and
do not interpret any EXTEND prefix present as a part of the instruction
in disassembly.

According to all versions of the MIPS16 ASE specifications the following
instructions encodings are not extensible [1][2][3][4][5][6]: I8/MOV32R,
I8/MOVR32, all RRR minor opcodes, all RR minor opcodes except from DSRA
and DSRL, and EXTEND itself, and as from revision 2.50 of the MIPS16e
ASE specifications it has been further clarified what was previously
implied, that non-extesiable instructions when preceded with an EXTEND
prefix must cause a Reserved Instruction exception [3][5].

Therefore in the presence of an EXTEND prefix none of these instructions
are supposed to be handled as extended instructions and supporting these
forms in disassembly causes confusion, and in the case of the RRR major
opcode it also clashes with the ASMACRO encoding.

References:

[1] "Product Description, MIPS16 Application-Specific Extension",
    Version 1.3, MIPS Technologies, Inc., 970130, Table 3. "MIPS16
    Instruction Set Summary", p. 5

[2] same, Table 5 "RR Minor Opcodes (RR-type instructions)", p.10

[3] "MIPS32 Architecture for Programmers, Volume IV-a: The MIPS16e
    Application-Specific Extension to the MIPS32 Architecture", MIPS
    Technologies, Inc., Document Number: MD00076, Revision 2.63, July
    16, 2013, Section 3.9 "MIPS16e Instruction Summaries", pp. 37-39

[4] same, Section 3.15 "Instruction Bit Encoding", pp. 46-49

[5] "MIPS64 Architecture for Programmers, Volume IV-a: The MIPS16e
    Application-Specific Extension to the MIPS64 Architecture", MIPS
    Technologies, Inc., Document Number: MD00077, Revision 2.60, June
    25, 2008, Section 1.9 "MIPS16e Instruction Summaries", pp. 38-41

[6] same, Section 1.15 "Instruction Bit Encoding", pp. 48-51

	include/
	* opcode/mips.h (INSN2_SHORT_ONLY): New macro.

	gas/
	* config/tc-mips.c (is_size_valid_16): Disallow a `.e' suffix
	instruction size override for INSN2_SHORT_ONLY opcode table
	entries.
	* testsuite/gas/mips/mips16-extend-swap.d: Adjust output.
	* testsuite/gas/mips/mips16-macro-e.l: Adjust error messages.
	* testsuite/gas/mips/mips16-32@mips16-macro-e.l: Adjust error
	messages.
	* testsuite/gas/mips/mips16e-32@mips16-macro-e.l: Adjust error
	messages.
	* testsuite/gas/mips/mips16-insn-e.d: New test.
	* testsuite/gas/mips/mips16-insn-t.d: New test.
	* testsuite/gas/mips/mips16-32@mips16-insn-e.d: New test.
	* testsuite/gas/mips/mips16-64@mips16-insn-e.d: New test.
	* testsuite/gas/mips/mips16e-32@mips16-insn-e.d: New test.
	* testsuite/gas/mips/mips16-32@mips16-insn-t.d: New test.
	* testsuite/gas/mips/mips16-64@mips16-insn-t.d: New test.
	* testsuite/gas/mips/mips16e-32@mips16-insn-t.d: New test.
	* testsuite/gas/mips/mips16-insn-e.l: New stderr output.
	* testsuite/gas/mips/mips16-insn-t.l: New stderr output.
	* testsuite/gas/mips/mips16-32@mips16-insn-e.l: New stderr
	output.
	* testsuite/gas/mips/mips16-64@mips16-insn-e.l: New stderr
	output.
	* testsuite/gas/mips/mips16e-32@mips16-insn-e.l: New stderr
	output.
	* testsuite/gas/mips/mips16-32@mips16-insn-t.l: New stderr
	output.
	* testsuite/gas/mips/mips16-64@mips16-insn-t.l: New stderr
	output.
	* testsuite/gas/mips/mips16e-32@mips16-insn-t.l: New stderr
	output.
	* testsuite/gas/mips/mips16-insn-e.s: New test source.
	* testsuite/gas/mips/mips16-insn-t.s: New test source.
	* testsuite/gas/mips/mips.exp: Run the new tests.

	opcodes/
	* mips-dis.c (print_insn_mips16): Disallow EXTEND prefix
	matching for INSN2_SHORT_ONLY opcode table entries.
	* mips16-opc.c (SH): New macro.
	(mips16_opcodes): Set SH in `pinfo2' for non-extensible
	instruction entries: "nop", "addu", "and", "break", "cmp",
	"daddu", "ddiv", "ddivu", "div", "divu", "dmult", "dmultu",
	"drem", "dremu", "dsllv", "dsll", "dsrav", "dsra", "dsrlv",
	"dsrl", "dsubu", "exit", "entry", "jalr", "jal", "jr", "j",
	"jalrc", "jrc", "mfhi", "mflo", "move", "mult", "multu", "neg",
	"not", "or", "rem", "remu", "sllv", "sll", "slt", "sltu",
	"srav", "sra", "srlv", "srl", "subu", "xor", "sdbbp", "seb",
	"seh", "sew", "zeb", "zeh", "zew" and "extend".

	binutils/
	* testsuite/binutils-all/mips/mips16-extend-insn.d: New test.
	* testsuite/binutils-all/mips/mips16-extend-insn.s: New test
	source.
	* testsuite/binutils-all/mips/mips.exp: Run the new tests.
2016-12-23 19:33:45 +00:00
Alan Modra
4e25adb395 Remove high bit set characters
gas/
	* doc/c-lm32.texi: Fix chars with high bit set.
	* testsuite/gas/bfin/vector2.s: Likewise.
gold/
	* arm.cc: Fix comment chars with high bit set.
include/
	* coff/pe.h: Fix comment chars with high bit set.
	* opcode/xgate.h: Likewise.
ld/
	* testsuite/ld-scripts/sysroot-prefix.exp: Fix chars with high bit set.
2016-12-21 19:18:46 +10:30
Maciej W. Rozycki
7fd5392005 MIPS16: Switch to 32-bit opcode table interpretation
Switch to 32-bit MIPS16 opcode table entry interpretation, similar to
how the microMIPS opcode table is handled, for both the `match' and
`mask' fields, removing special casing for JAL and JALX instructions and
their `a' and `i' operand codes throughout, while retaining automatic
processing of extendable opcodes in assembly and disassembly.

In assembly disallow size enforcement suffixes as appropriate: `.t' for
both 32-bit instructions and macros and `.e' for macros only, making
macro handling consistent with the microMIPS instruction set.

In disassembly fully decode EXTEND prefixes prepended to unsupported
instruction encodings (according to the ISA selection) rather than
dumping them as hexadecimal data along with the following instruction,
removing all special casing for the EXTEND prefix and making its
handling rely on its opcode table entry, except where it is considered a
part of an extendable instruction.

	include/
	* opcode/mips.h (mips_opcode_32bit_p): New inline function.

	gas/
	* config/tc-mips.c (micromips_insn_length): Use
	`mips_opcode_32bit_p'.
	(is_size_valid): Adjust description.
	(is_size_valid_16): New function.
	(validate_mips_insn): Use `mips_opcode_32bit_p' in MIPS16
	operand decoding.
	(validate_mips16_insn): Remove `a' and `i' operand code special
	casing, use `mips_opcode_32bit_p' to determine instruction
	width.
	(append_insn): Adjust forced MIPS16 instruction size
	determination.
	(match_mips16_insn): Likewise.  Don't shift the instruction's
	opcode with the `a' and `i' operand codes.  Use
	`mips_opcode_32bit_p' in operand decoding.
	(match_mips16_insns): Check for forced instruction size's
	validity.
	(mips16_ip): Don't force instruction size in the `noautoextend'
	mode.
	* testsuite/gas/mips/mips16-jal-e.d: New test.
	* testsuite/gas/mips/mips16-jal-t.d: New test.
	* testsuite/gas/mips/mips16-macro-e.d: New test.
	* testsuite/gas/mips/mips16-macro-t.d: New test.
	* testsuite/gas/mips/mips16-jal-t.l: New stderr output.
	* testsuite/gas/mips/mips16-macro-e.l: New stderr output.
	* testsuite/gas/mips/mips16-macro-t.l: New stderr output.
	* testsuite/gas/mips/mips16-jal-e.s: New test source.
	* testsuite/gas/mips/mips16-jal-t.s: New test source.
	* testsuite/gas/mips/mips16-macro-e.s: New test source.
	* testsuite/gas/mips/mips16-macro-t.s: New test source.
	* testsuite/gas/mips/mips.exp: Run the new tests.

	opcodes/
	* mips-dis.c (print_mips16_insn_arg): Always handle `extend' and
	`insn' together, with `extend' as the high-order 16 bits.
	(match_kind): New enum.
	(print_insn_mips16): Rework for 32-bit instruction matching.
	Do not dump EXTEND prefixes here.
	* mips16-opc.c (mips16_opcodes): Move "extend" entry to the end.
	Recode `match' and `mask' fields as 32-bit in absolute "jal" and
	"jalx" entries.

	binutils/
	* testsuite/binutils-all/mips/mips16-extend-noinsn.d: Adjust
	test for separate EXTEND prefix disassembly.
2016-12-20 11:56:32 +00:00
Andrew Waterman
2922d21da1 Re-work RISC-V gas flags: now we just support -mabi and -march
We've decided to standardize on two flags for RISC-V: "-march" sets the
target architecture (which determines which instructions can be
generated), and "-mabi" sets the target ABI.  We needed to rework this
because the old flag set didn't support soft-float or single-float ABIs,
and didn't support an x32-style ABI on RISC-V.

Additionally, we've changed the behavior of the -march flag: it's now a
lot stricter and only parses things we can actually understand.
Additionally, it's now lowercase-only: the rationale is that while the
RISC-V ISA manual specifies that ISA strings are case-insensitive, in
Linux-land things are usually case-sensitive.  Since this flag can be
used to determine library paths, we didn't want to bake some
case-insensitivity in there that would case trouble later.

This patch implements these two new flags and removes the old flags that
could conflict with these.  There wasn't a RISC-V release before, so we
want to just support a clean flag set.

include/
	* elf/riscv.h (EF_RISCV_SOFT_FLOAT): Don't define.
	(EF_RISCV_FLOAT_ABI, EF_RISCV_FLOAT_ABI_SOFT): Define.
	(EF_RISCV_FLOAT_ABI_SINGLE, EF_RISCV_FLOAT_ABI_DOUBLE): Define.
	(EF_RISCV_FLOAT_ABI_QUAD): Define.
bfd/
	* elfnn-riscv.c (_bfd_riscv_elf_merge_private_bfd_data): Use
	EF_RISCV_FLOAT_ABI_SOFT instead of EF_RISCV_SOFT_FLOAT.
binutils/
	* readelf.c (get_machine_flags): Use
	EF_RISCV_FLOAT_ABI_{SOFT,SINGLE,DOBULE,QUAD) instead of
	EF_RISCV_{SOFT,HARD}_FLOAT.
gas/
	* config/tc-riscv.h (xlen): Delete.
	* config/tc-riscv.c (xlen): Make static.
	(abi_xlen): New variable.
	(options): Replace OPTION_{M32,M64,MSOFT_FLOAT,MHARD_FLOAT,MRVC}
	with OPTION_MABI.
	(md_longopts): Likewise.
	(md_parse_option): Likewise.
	(riscv_elf_final_processing): Likewise.
	* doc/as.texinfo (Target RISC-V options): Likewise.
	* doc/c-riscv.texi (OPTIONS): Likewise.
	* config/tc-riscv.c (float_mode): Removed.
	(float_abi): New type, specifies the floating-point ABI.
	(riscv_set_abi): New function.
	(riscv_add_subset): Only allow lower-case ISA names and require
	them to start with "rv".
	(riscv_after_parse_args): Likewise.
opcodes/
	* riscv-dis.c (riscv_disassemble_insn): Default to the ELF's
	XLEN when none is provided.
2016-12-20 12:26:34 +10:30
Andrew Waterman
45f764234a Rework RISC-V relocations
Before this commit we didn't cleanly support CFI directives because the
internal offsets used to get relaxed which broke them.  This patch
significantly reworks how we handle linker relaxations:

 * DWARF is now properly supported

 * There is a ".option norelax" to disable relaxations, for when users
   write assembly that can't be relaxed (if it's to be later patched up,
   for example).

 * There is an additional _RELAX relocation that specifies when previous
   relocations can be relaxed.

We're in the process of documenting the RISC-V ELF ABI, which will
include documentation of our relocations

  https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md

but we expect that this relocation set will remain ABI compatible in the
future (ie, it's safe to release).

Thanks to Kuan-Lin Chen for figuring out how to correctly relax the
debug info!

include/
	* elf/riscv.h: Add R_RISCV_TPREL_I through R_RISCV_SET32.
bfd/
	* reloc.c (BFD_RELOC_RISCV_TPREL_I): New relocation.
	(BFD_RELOC_RISCV_TPREL_S): Likewise.
	(BFD_RELOC_RISCV_RELAX): Likewise.
	(BFD_RELOC_RISCV_CFA): Likewise.
	(BFD_RELOC_RISCV_SUB6): Likewise.
	(BFD_RELOC_RISCV_SET8): Likewise.
	(BFD_RELOC_RISCV_SET8): Likewise.
	(BFD_RELOC_RISCV_SET16): Likewise.
	(BFD_RELOC_RISCV_SET32): Likewise.
	* elfnn-riscv.c (perform_relocation): Handle the new
	relocations.
	(_bfd_riscv_relax_tls_le): Likewise.
	(_bfd_riscv_relax_align): Likewise.
	(_bfd_riscv_relax_section): Likewise.
	(howto_table): Likewise.
	(riscv_reloc_map): Likewise.
	(relax_func_t): New type.
	(_bfd_riscv_relax_call): Add reserve_size argument, which
	controls the maximal offset pessimism.  Correct type of max_alignment.
	(_bfd_riscv_relax_lui): Likewise.
	(_bfd_riscv_relax_tls_le): Likewise.
	(_bfd_riscv_relax_align): Likewise.
	(_bfd_riscv_relax_section): Compute the required reserve size
	when relocating and use it to when calling relax_func.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Likewise.
gas/
	* config/tc-riscv.c (riscv_set_options): Add relax.
	(riscv_opts): Likewise.
	(s_riscv_option): Add relax and norelax.
	(riscv_apply_const_reloc): New function.
	(append_insn): Move constant relocation handling to
	riscv_apply_const_reloc.
	(md_pcrel_from): Likewise.
	(parse_relocation): Skip BFD_RELOC_UNUSED.
	(md_pcrel_from): Handle BFD_RELOC_RISCV_SUB6,
	BFD_RELOC_RISCV_RELAX, BFD_RELOC_RISCV_CFA.
	(md_apply_fix): Likewise.
	(riscv_pre_output_hook): New function.
	* config/tc-riscv.h (md_pre_output_hook): Define.
	(riscv_pre_output_hook): Declare.
	(DWARF_CIE_DATA_ALIGNMENT): Always -4.
2016-12-20 12:26:33 +10:30
fincs
221855059a Implement and document --gc-keep-exported
include/
	* bfdlink.h (struct bfd_link_info): Add gc_keep_exported.
bfd/
	* elflink.c (bfd_elf_gc_mark_dynamic_ref_symbol): Add handling
	for info->gc_keep_exported.
	(bfd_elf_gc_sections): Likewise.
ld/
	* ld.texinfo: Document --gc-keep-exported.
	* ldlex.h (enum option_values): Add OPTION_GC_KEEP_EXPORTED.
	* lexsup.c (parse_args): Add handling for --gc-keep-exported.
2016-12-16 13:49:03 +10:30
Maciej W. Rozycki
5e7fc731f8 MIPS/opcodes: Also set disassembler's ASE flags from ELF structures
Respect any ASE flags recorded in ELF file structures for the purpose of
selecting instructions to be disassembled, preventing code from being
hex-dumped even though having been clearly indicated as valid at the
assembly time.  Use date from the MIPS ABI flags structure if present,
and otherwise there may be an MDMX ASE flag set in the ELF file header.
For backwards compatibility only set extra flags and do not clear any,
preserving all previously set by the architecture selected to be
disassembled for.

	include/
	* elf/mips.h (Elf_Internal_ABIFlags_v0): Also declare struct
	typedef as `elf_internal_abiflags_v0'.

	bfd/
	* bfd-in.h (elf_internal_abiflags_v0): New struct declaration.
	(bfd_mips_elf_get_abiflags): New prototype.
	* elfxx-mips.c (bfd_mips_elf_get_abiflags): New function.
	* bfd-in2.h: Regenerate.

	opcodes/
	* mips-dis.c (mips_convert_abiflags_ases): New function.
	(set_default_mips_dis_options): Also infer ASE flags from ELF
	file structures.

	binutils/
	* testsuite/binutils-all/mips/mips-ase-1.d: New test.
	* testsuite/binutils-all/mips/mips-ase-2.d: New test.
	* testsuite/binutils-all/mips/mips-ase-3.d: New test.
	* testsuite/binutils-all/mips/mips-ase-1.s: New test source.
	* testsuite/binutils-all/mips/mips-ase-2.s: New test source.
	* testsuite/binutils-all/mips/mips.exp: Run the new tests.
2016-12-14 22:12:21 +00:00
Renlin Li
a6a5175474 [Binutils][AARCH64]Remove Cn register for coprocessor CRn, CRm field
The internal CN register representation for coprocessor fields used in aarch64
sys, sysl instructions are removed in this patch.

After the change, those fields are represented as immediate. Related checks are
added as well.

opcodes/

	* aarch64-opc.c (aarch64_opnd_qualifiers): New CR value range
	qualifier.
	(operand_general_constraint_met_p): Remove case for CP_REG.
	(aarch64_print_operand): Print CRn, CRm operand using imm field.
	* aarch64-tbl.h (QL_SYS): Use CR qualifier.
	(QL_SYSL): Likewise.
	(aarch64_opcode_table): Change CRn, CRm operand class and type.
	* aarch64-opc-2.c : Regenerate.
	* aarch64-asm-2.c : Likewise.
	* aarch64-dis-2.c : Likewise.

include/

	* opcode/aarch64.h (aarch64_operand_class): Remove
	AARCH64_OPND_CLASS_CP_REG.
	(enum aarch64_opnd): Change AARCH64_OPND_Cn to AARCH64_OPND_CRn,
	AARCH64_OPND_Cm to AARCH64_OPND_CRm.
	(aarch64_opnd_qualifier): Define AARCH64_OPND_QLF_CR qualifier.

gas/

	* config/tc-aarch64.c (AARCH64_REG_TYPES): Remove CN register.
	(get_reg_expected_msg): Remove CN register case.
	(parse_operands): rewrite parser for CRn, CRm operand.
	(reg_names): Remove CN register.
	* testsuite/gas/aarch64/diagnostic.s: Add a new test case.
	* testsuite/gas/aarch64/diagnostic.l: Adjust error message.
2016-12-13 17:20:08 +00:00
Maciej W. Rozycki
64c1118340 MIPS16: Remove unused `>' operand code
This code has never been used throughout the repository history, and
likely not before either, as due to the assymetry of MIPS16 instruction
set encoding there are no 32-bit shift operations having their immediate
shift count placed in the position of the usual `rx' instruction field.

	gas/
	* config/tc-mips.c (mips16_macro_build) <'>'>: Remove case.

	include/
	* opcode/mips.h: Remove references to `>' operand code.

	opcodes/
	* mips16-opc.c (decode_mips16_operand) <'>'>: Remove cases.
2016-12-09 23:21:40 +00:00
Maciej W. Rozycki
4b0781150f MIPS/include: opcode/mips.h: Correct INSN_CHIP_MASK
Complement commit e407c74b5b ("Support for MIPS R5900 (Sony Playstation
2)"), <https://sourceware.org/ml/binutils/2012-12/msg00240.html>, and
commit 2c62985659 ("MIPS: Add Octeon 3 support") and update the chip
mask accordingly.

	include/
	* opcode/mips.h (INSN_CHIP_MASK): Update according to bit use.
2016-12-07 12:31:38 +00:00
Maciej W. Rozycki
b8760d2cb5 MIPS/include: opcode/mips.h: Add a comment for ASE_DSPR3
Complement commit 8f4f9071ad ("Add MIPS32 DSPr3 support.").

	include/
	* opcode/mips.h (ASE_DSPR3): Add a comment.
2016-12-07 12:26:11 +00:00
Szabolcs Nagy
a12fd8e1b1 [ARM] Add ARMv8.3 command line option and feature flag
ARMv8.3 is an architectural extension of ARMv8.  Add the
feature macro and -march=armv8.3-a gas command line option
for the ARM target.

https://community.arm.com/groups/processors/blog/2016/10/27/armv8-a-architecture-2016-additions

gas/
	* config/tc-arm.c (arm_archs): Add "armv8.3-a".
	* doc/c-arm.texi (-march): Add "armv8.3-a".

include/
	* opcode/arm.h (ARM_EXT2_V8_3A, ARM_AEXT2_V8_3A): New.
	(ARM_ARCH_V8_3A): New.
2016-12-05 14:07:25 +00:00
Claudiu Zissulescu
abe7c33b45 [ARC] Add checking for LP_COUNT reg usage, improve error reporting.
gas/
2016-11-29  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/tc-arc.c (find_opcode_match): New function argument
	errmsg.
	(assemble_tokens): Collect and report the eventual error message
	found during opcode matching process.
	* testsuite/gas/arc/lpcount-err.s: New file.
	* testsuite/gas/arc/add_s-err.s: Update error message.

opcode/
2016-11-29  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-opc.c (insert_ra_chk): New function.
	(insert_rb_chk): Likewise.
	(insert_rad): Update text error message.
	(insert_rcd): Likewise.
	(insert_rhv2): Likewise.
	(insert_r0): Likewise.
	(insert_r1): Likewise.
	(insert_r2): Likewise.
	(insert_r3): Likewise.
	(insert_sp): Likewise.
	(insert_gp): Likewise.
	(insert_pcl): Likewise.
	(insert_blink): Likewise.
	(insert_ilink1): Likewise.
	(insert_ilink2): Likewise.
	(insert_ras): Likewise.
	(insert_rbs): Likewise.
	(insert_rcs): Likewise.
	(insert_simm3s): Likewise.
	(insert_rrange): Likewise.
	(insert_fpel): Likewise.
	(insert_blinkel): Likewise.
	(insert_pcel): Likewise.
	(insert_nps_3bit_dst): Likewise.
	(insert_nps_3bit_dst_short): Likewise.
	(insert_nps_3bit_src2_short): Likewise.
	(insert_nps_bitop_size_2b): Likewise.
	(MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
	(RA_CHK): Define.
	(RB): Adjust.
	(RB_CHK): Define.
	(RC): Adjust.
	* arc-dis.c (print_insn_arc): Add LOAD and STORE class.
	* arc-tbl.h (div, divu): All instructions are DIVREM class.
	Change first insn argument to check for LP_COUNT usage.
	(rem): Likewise.
	(ld, ldd): All instructions are LOAD class.  Change first insn
	argument to check for LP_COUNT usage.
	(st, std): All instructions are STORE class.
	(mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
	Change first insn argument to check for LP_COUNT usage.
	(mov): All instructions are MOVE class.  Change first insn
	argument to check for LP_COUNT usage.

include/
2016-11-29  Claudiu Zissulescu  <claziss@synopsys.com>

	* opcode/arc.h (insn_class_t): Add DIVREM, LOAD, MOVE, MPY, STORE
	instruction classes.
2016-11-29 11:29:18 +01:00
Jose E. Marchesi
6884417a0f gas,opcodes: fix hardware capabilities bumping in the sparc assembler.
When the assembler finds an instruction which is part of a higher
opcode architecture it bumps the current opcode architecture.  For
example:

   $ echo "mwait" | as -bump
   {standard input}: Assembler messages:
   {standard input}:1: Warning: architecture bumped from "v6" to "v9m" on "mwait"

However, when two instructions pertaining to the same opcode
architecture but associated to different SPARC hardware capabilities
are found in the input stream, and no GAS architecture is specified in
the command line, the assembler bangs:

   $ echo "mwait; wr %g0,%g1,%mcdper" | as -bump
   {standard input}: Assembler messages:
   {standard input}:1: Warning: architecture bumped from "v6" to "v9m" on "mwait"
   {standard input}:1: Error: Hardware capability "sparc5" not enabled for "wr".

... and it should'nt, as WRMCDPER pertains to the same architecture
level than MWAIT.

This patch fixes this by extending the definition of sparc opcode
architectures to contain a set of hardware capabilities and making the
assembler to take these capabilities into account when updating the
set of allowed hwcaps when an architecture bump is triggered by some
instruction.

This way, hwcaps associated to architecture levels are maintained in
opcodes, while the assembler keeps the flexibiity of defining GAS
architectures including additional hwcaps (like -Asparcfmaf or the
v8plus* variants).

A test covering this failure case is included.

gas/ChangeLog:

2016-11-22  Jose E. Marchesi  <jose.marchesi@oracle.com>

       	* config/tc-sparc.c: Move HWS_* and HWS2_* definitions to
       	opcodes/sparc-opc.c.
       	(sparc_arch): Clarify the new role of the hwcap_allowed and
       	hwcap2_allowed fields.
       	(sparc_arch_table): Remove HWS_* and HWS2_* instances from
       	hwcap_allowed and hwcap2_allowed respectively.
       	(md_parse_option): Include the opcode arch hwcaps when processing
       	-A.
       	(sparc_ip): Use the current opcode arch hwcaps to update
       	hwcap_allowed, as well of the hwcaps of the instruction triggering
       	the bump.
       	* testsuite/gas/sparc/hwcaps-bump.s: New file.
       	* testsuite/gas/sparc/hwcaps-bump.l: Likewise.
       	* testsuite/gas/sparc/sparc.exp (gas_64_check): Run tests in
       	hwcaps-bump.

include/ChangeLog:

2016-11-22  Jose E. Marchesi  <jose.marchesi@oracle.com>

       	* opcode/sparc.h (sparc_opcode_arch): New fields hwcaps and
       	hwcaps2.

opcodes/ChangeLog:

2016-11-22  Jose E. Marchesi  <jose.marchesi@oracle.com>

       	* sparc-opc.c (HWS_V8): Definition moved from
       	gas/config/tc-sparc.c.
       	(HWS_V9): Likewise.
       	(HWS_VA): Likewise.
       	(HWS_VB): Likewise.
       	(HWS_VC): Likewise.
       	(HWS_VD): Likewise.
       	(HWS_VE): Likewise.
       	(HWS_VV): Likewise.
       	(HWS_VM): Likewise.
       	(HWS2_VM): Likewise.
       	(sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
       	existing entries.
2016-11-22 04:40:37 -08:00
Alan Modra
08dc996fed PR20744, Incorrect PowerPC VLE relocs
VLE 16A and 16D relocs were functionally swapped.

	PR 20744
include/
	* opcode/ppc.h: Define VLE insns using 16A and 16D relocs.
bfd/
	* elf32-ppc.h (struct ppc_elf_params): Add vle_reloc_fixup field.
	* elf32-ppc.c: Include opcode/ppc.h.
	(ppc_elf_howto_raw): Correct dst_mask for R_PPC_VLE_LO16A,
	R_PPC_VLE_LO16D, R_PPC_VLE_HI16A, R_PPC_VLE_HI16D, R_PPC_VLE_HA16A,
	R_PPC_VLE_HA16D, R_PPC_VLE_SDAREL_LO16A, R_PPC_VLE_SDAREL_LO16D,
	R_PPC_VLE_SDAREL_HI16A, R_PPC_VLE_SDAREL_HI16D,
	R_PPC_VLE_SDAREL_HA16A, and R_PPC_VLE_SDAREL_HA16D relocs.
	(ppc_elf_link_hash_table_create): Update default_params init.
	(ppc_elf_vle_split16): Correct shift and mask.  Add params.
	Report or fix insn/reloc mismatches.
	(ppc_elf_relocate_section): Pass input_section, offset and fixup
	to ppc_elf_vle_split16.
binutils/
	* NEWS: Mention PowerPC VLE relocation error.
gas/
	* config/tc-ppc.c: Delete VLE insn defines.
	(md_assemble): Swap use_a_reloc and use_d_reloc.
	* testsuite/gas/ppc/vle-reloc.d: Update.
ld/
	* emultempl/ppc32elf.em (params): Update initializer.  Handle
	--vle-reloc-fixup command line arg.
2016-11-22 20:19:29 +10:30
David Tolnay
535aade664 libiberty: Add Rust symbol demangling.
Adds Rust symbol demangler. Rust mangles symbols using GNU_V3 style,
adding a hash and various special character subtitutions. This adds
a new rust style to cplus_demangle and adds 3 helper functions
rust_demangle, rust_demangle_sym and rust_is_mangled.

rust-demangle.c was written by David. Mark did the code formatting to
GNU style and integration into the gcc/libiberty build system and
testsuite.

include/ChangeLog:

2016-11-03  David Tolnay <dtolnay@gmail.com>
           Mark Wielaard  <mark@klomp.org>

       * demangle.h (DMGL_RUST): New macro.
       (DMGL_STYLE_MASK): Add DMGL_RUST.
       (demangling_styles): Add dlang_rust.
       (RUST_DEMANGLING_STYLE_STRING): New macro.
       (RUST_DEMANGLING): New macro.
       (rust_demangle): New prototype.
       (rust_is_mangled): Likewise.
       (rust_demangle_sym): Likewise.

libiberty/ChangeLog:

2016-11-03  David Tolnay <dtolnay@gmail.com>
           Mark Wielaard  <mark@klomp.org>

       * Makefile.in (CFILES): Add rust-demangle.c.
       (REQUIRED_OFILES): Add rust-demangle.o.
       * cplus-dem.c (libiberty_demanglers): Add rust_demangling case.
       (cplus_demangle): Handle RUST_DEMANGLING.
       (rust_demangle): New function.
       * rust-demangle.c: New file.
       * testsuite/Makefile.in (really-check): Add check-rust-demangle.
       (check-rust-demangle): New rule.
       * testsuite/rust-demangle-expected: New file.
2016-11-18 11:06:18 +01:00
Jason Merrill
a4ddf8dc72 Implement P0012R1, Make exception specifications part of the type system.
libiberty/
	* cp-demangle.c (is_fnqual_component_type): New.
	(d_encoding, d_print_comp_inner, d_print_mod_list): Use it.
	(FNQUAL_COMPONENT_CASE): New.
	(d_make_comp, has_return_type, d_print_comp_inner)
	(d_print_function_type): Use it.
	(next_is_type_qual): New.
	(d_cv_qualifiers, d_print_mod): Handle noexcept and throw-spec.
include/
	* demangle.h (enum demangle_component_type): Add
	DEMANGLE_COMPONENT_NOEXCEPT, DEMANGLE_COMPONENT_THROW_SPEC.
2016-11-18 11:06:18 +01:00
Szabolcs Nagy
c2c4ff8d52 [AArch64] Add ARMv8.3 FCMLA and FCADD instructions
Add support for FCMLA and FCADD complex arithmetic SIMD instructions.
FCMLA has an indexed element variant where the index range has to be
treated specially because a complex number takes two elements and the
indexed vector size depends on the other operands.

These complex number SIMD instructions are part of ARMv8.3
https://community.arm.com/groups/processors/blog/2016/10/27/armv8-a-architecture-2016-additions

include/
2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_IMM_ROT1,
	AARCH64_OPND_IMM_ROT2, AARCH64_OPND_IMM_ROT3.
	(enum aarch64_op): Add OP_FCMLA_ELEM.

opcodes/
2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
	(aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
	(aarch64_opcode_table): Add fcmla and fcadd.
	(AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
	* aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
	* aarch64-asm.c (aarch64_ins_imm_rotate): Define.
	* aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
	* aarch64-dis.c (aarch64_ext_imm_rotate): Define.
	* aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
	* aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
	(operand_general_constraint_met_p): Rotate and index range check.
	(aarch64_print_operand): Handle rotate operand.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Likewise.
	* aarch64-opc-2.c: Likewise.

gas/
2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* config/tc-aarch64.c (parse_operands): Handle AARCH64_OPND_IMM_ROT*.
	* testsuite/gas/aarch64/advsimd-armv8_3.d: New.
	* testsuite/gas/aarch64/advsimd-armv8_3.s: New.
	* testsuite/gas/aarch64/illegal-fcmla.s: New.
	* testsuite/gas/aarch64/illegal-fcmla.l: New.
	* testsuite/gas/aarch64/illegal-fcmla.d: New.
2016-11-18 10:02:16 +00:00
Szabolcs Nagy
3f06e55061 [AArch64] Add ARMv8.3 combined pointer authentication load instructions
Add support for ARMv8.3 LDRAA and LDRAB combined pointer authentication and
load instructions.

These instructions authenticate the base register and load 8 byte from it plus
a scaled 10-bit offset with optional writeback to update the base register.

A new instruction class (ldst_imm10) and operand type (AARCH64_OPND_ADDR_SIMM10)
were introduced to handle the special addressing form.

include/
2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM10.
	(enum aarch64_insn_class): Add ldst_imm10.

opcodes/
2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* aarch64-tbl.h (QL_X1NIL): New.
	(arch64_opcode_table): Add ldraa, ldrab.
	(AARCH64_OPERANDS): Add "ADDR_SIMM10".
	* aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
	* aarch64-asm.c (aarch64_ins_addr_simm10): Define.
	* aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
	* aarch64-dis.c (aarch64_ext_addr_simm10): Define.
	* aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
	* aarch64-opc.c (fields): Add data for FLD_S_simm10.
	(operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
	(aarch64_print_operand): Likewise.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.

gas/
2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* config/tc-aarch64.c (parse_operands): Handle AARCH64_OPND_ADDR_SIMM10.
	(fix_insn): Likewise.
	(warn_unpredictable_ldst): Handle ldst_imm10.
	* testsuite/gas/aarch64/pac.s: Add ldraa and ldrab tests.
	* testsuite/gas/aarch64/pac.d: Likewise.
	* testsuite/gas/aarch64/illegal-ldraa.s: New.
	* testsuite/gas/aarch64/illegal-ldraa.l: New.
	* testsuite/gas/aarch64/illegal-ldraa.d: New.
2016-11-18 09:49:06 +00:00
Szabolcs Nagy
c84364ece4 [AArch64] Add ARMv8.3 PACGA instruction
Add support for the ARMv8.3 PACGA instruction.

include/
2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rm_SP.

opcodes/
2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* aarch64-tbl.h (arch64_opcode_table): Add pacga.
	(AARCH64_OPERANDS): Add Rm_SP.
	* aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.

gas/
2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* config/tc-aarch64.c (process_omitted_operand): Handle AARCH64_OPND_Rm_SP.
	(parse_operands): Likewise.
	* testsuite/gas/aarch64/pac.s: Add pacga.
	* testsuite/gas/aarch64/pac.d: Add pacga.
2016-11-11 10:39:46 +00:00
Szabolcs Nagy
1924ff7567 [AArch64] Add ARMv8.3 command line option and feature flag
ARMv8.3 can be selected with -march=armv8.3-a command line option.
An overview of the ARMv8.3 architecture extension is at
https://community.arm.com/groups/processors/blog/2016/10/27/armv8-a-architecture-2016-additions

gas/
2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* config/tc-aarch64.c (aarch64_archs): Add "armv8.3-a".
	* doc/c-aarch64.texi (-march): Likewise.

include/
2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* opcode/aarch64.h (AARCH64_FEATURE_V8_3): Define.
	(AARCH64_ARCH_V8_3): Define.
	(AARCH64_ARCH_V8_1, AARCH64_ARCH_V8_2): Simplify.
2016-11-11 10:20:30 +00:00
Thomas Preud'homme
d46a216553 Commit missing ChangeLog entry for Cortex-M33 support
2016-11-04  Thomas Preud'homme  <thomas.preudhomme@arm.com>

include/
	* opcode/arm.h (ARM_AEXT_V8M_MAIN_DSP): Define.
	(ARM_AEXT2_V8M_MAIN_DSP): Likewise.
	(ARM_ARCH_V8M_MAIN_DSP): Likewise.
2016-11-04 16:32:08 +00:00
Thomas Preud'homme
b19ea8d28b Add support for ARM Cortex-M33 processor
2016-11-04  Thomas Preud'homme  <thomas.preudhomme@arm.com>

gas/
	* config/tc-arm.c (cortex-m33): Declare new processor.
	* doc/c-arm.texi (-mcpu ARM command line option): Document new
	Cortex-M33 processor.
	* NEWS: Mention ARM Cortex-M33 support.
2016-11-04 16:24:59 +00:00
Graham Markall
5a736821ef arc: Implement NPS-400 dcmac instruction
gas/ChangeLog:

       * testsuite/gas/arc/nps-400-9.d: Added.
       * testsuite/gas/arc/nps-400-9.s: Added.

include/ChangeLog:

       * opcode/arc.h: Add PROTOCOL_DECODE to insn_class_t.

opcodes/ChangeLog:

       * arc-dis.c (arc_insn_length): Return length 8 for instructions with
       major opcode 0xa.
       * arc-nps-400-tbl.h: Add dcmac instruction.
       * arc-opc.c (arc_operands): Added operands for dcmac instruction.
       (insert_nps_rbdouble_64): Added.
       (extract_nps_rbdouble_64): Added.
       (insert_nps_proto_size): Added.
       (extract_nps_proto_size): Added.
2016-11-03 17:14:38 +00:00
Andrew Burgess
bdfe53e3cf arc: Change max instruction length to 64-bits
The current handling for arc instructions longer than 32-bits is all
handled as a special case in both the assembler and disassembler.

The problem with this approach is that it leads to code duplication,
selecting a long instruction is exactly the same process as selecting a
short instruction, except over more bits, in both cases we select based
on bit comparison, and initial operand insertion and extraction.

This commit unifies both the long and short instruction worlds,
converting the core opcodes library from being largely 32-bit focused,
to being largely 64-bit focused.

The changes are, on the whole, not too much.  There's obviously a lot of
type changes but otherwise the bulk of the code just works.  Most of the
actual functional changes are to code that previously handled the longer
48 or 64 bit instructions.  The insert/extract handlers for these have
now been brought into line with the short instruction insert/extract
handlers.

All of the special case handling code that was previously added has now
been removed again.  Overall, this commit reduces the amount of code in
the arc assembler and disassembler.

gas/ChangeLog:

	* config/tc-arc.c (struct arc_insn): Change type of insn field.
	(md_number_to_chars_midend): Support 6- and 8-byte values.
	(emit_insn0): Update debug output.
	(find_opcode_match): Likewise.
	(build_fake_opcode_hash_entry): Delete.
	(find_special_case_long_opcode): Delete.
	(find_special_case): Remove long format special case handling.
	(insert_operand): Change instruction type and update debug print
	format.
	(assemble_insn): Change instruction type, update debug print
	formats, and remove unneeded assert.

include/ChangeLog:

	* opcode/arc.h (struct arc_opcode): Change type of opcode and mask
	fields.
	(struct arc_long_opcode): Delete.
	(struct arc_operand): Change types for insert and extract
	handlers.

opcodes/ChangeLog:

	* arc-dis.c (struct arc_operand_iterator): Remove all fields
	relating to long instruction processing, add new limm field.
	(OPCODE): Rename to...
	(OPCODE_32BIT_INSN): ...this.
	(OPCODE_AC): Delete.
	(skip_this_opcode): Handle different instruction lengths, update
	macro name.
	(special_flag_p): Update parameter type.
	(find_format_from_table): Update for more instruction lengths.
	(find_format_long_instructions): Delete.
	(find_format): Update for more instruction lengths.
	(arc_insn_length): Likewise.
	(extract_operand_value): Update for more instruction lengths.
	(operand_iterator_next): Remove code relating to long
	instructions.
	(arc_opcode_to_insn_type): New function.
	(print_insn_arc):Update for more instructions lengths.
	* arc-ext.c (extInstruction_t): Change argument type.
	* arc-ext.h (extInstruction_t): Change argument type.
	* arc-fxi.h: Change type unsigned to unsigned long long
	extensively throughout.
	* arc-nps400-tbl.h: Add long instructions taken from
	arc_long_opcodes table in arc-opc.c.
	* arc-opc.c: Update parameter types on insert/extract handlers.
	(arc_long_opcodes): Delete.
	(arc_num_long_opcodes): Delete.
	(arc_opcode_len): Update for more instruction lengths.
2016-11-03 17:14:38 +00:00