PR 24717
* elf.c (is_debuginfo_file): New function.
(assign_file_positions_for_non_load_sections): Do not warn about
allocated sections outside of loadable segments if they are found
in a debuginfo file.
* elf-bfd.h (is_debuginfo_file): Prototype.
PR 24753
bfd * compress.c (bfd_get_full_section_contents): Do not complain
about linker created sections that are larger than the file size.
ld * emultempl/aarch64elf.em (_aarch64_add_stub_section): Include the
LINKER_CREATED section flag when creating the stub section.
As discussed in the PR, we do not support the case where CMSE stubs
are inserted too far from their destination. This would require an
intermediate long-branch stub, which is tricky in this context.
Instead of crashing, this patch emit an error message and exits.
2019-07-02 Christophe Lyon <christophe.lyon@linaro.org>
* bfd/elf32-arm.c (CMSE_STUB_NAME): New define.
(elf32_arm_get_stub_entry): Do not try to emit long-branch stubs
for CMSE stubs.
(arm_dedicated_stub_output_section_name): Use CMSE_STUB_NAME.
Change-Id: I6d4e1c0fdee6bb9f4b07e5e1b46700b5ba31c62e
Consider a file containing only Armv8-M secure entry functions.
This file is compiled and linked with "-march=armv8-m.main -mfloat-abi=hard
-mfpu=fpv5-sp-d16 -mcmse -static --specs=rdimon.specs
-Wl,--section-start,.gnu.sgstubs=0x190000 -ffunction-sections
-fdata-sections
-Wl,--gc-sections -g" options to generate an executable.
The executable generated does not contain any debug information of these
secure entry functions even though it contains secure entry functions in
the .text section. This patch fixes this problem.
PR 23839
bfd * elf32-arm.c (elf32_arm_update_relocs): Do not include the
section VMA in the offset used to update exidx relocs.
ld * testsuite/ld-arm/unwind-4.d: Adjust for corrected calculation of
exidx relocs.
PR 24708
* elf.c (_bfd_elf_slurp_version_tables): Check for an excessively
large version reference section.
* compress.c (bfd_get_full_section_contents): Check for an
uncompressed section whose size is larger than the file size.
This patch fixes failures with LTO on mingw32 targets. Since git
commit 7cf7fcc83c all possible targets (minus binary) are matched in
bfd_check_format_matches rather than lower priority targets being
excluded once a higher priority target matches. During linking that
results in the ld/plugin.c plugin_object_p function being called with
the input file xvec set to plugin_vec, which means
plugin_get_ir_dummy_bfd doesn't see the real format of the file
(pe-i386). It defaults to the output format instead, which happens to
be pei-i386, and this wrong choice persists for the dummy bfd.
pei-i386 isn't recognised as a valid linker input file.
So, omit recognizing a plugin object in bfd_check_format_matches when
some other object format matches, and make sure those other object
formats are checked first.
* format.c (bfd_check_format_matches): Don't match plugin target
if another target matches. Expand comment.
* targets.c (_bfd_target_vector): Move plugin_vec after all other
non-corefile targets, outside !SELECT_VECS.
* config.bfd: Don't handle targ=plugin here.
* configure.ac: Don't add plugin to enable_targets or handle in
target loop setting selvecs and other target vars.
* configure: Regenerate.
PR 24703
binutils* bucomm.c (bfd_nonfatal): If no bfd error code has been set then
indicate this in the output.
(bfd_nonfatal_message): Likewise.
bfd * mach-o-arm.c (bfd_mach_o_arm_canonicalize_one_reloc): Add error
messages for failures.
* mach-o.c (bfd_mach_o_canonicalize_relocs): Set an bfd error code
if returning an error value.
With my (oldish) gcc/glibc combination I'm seeing
.../bfd/elf-properties.c: In function elf_find_and_remove_property:
.../bfd/elf-properties.c:244: error: declaration of remove shadows a global declaration
/usr/include/stdio.h:157: error: shadowed declaration is here
2019-06-24 Ilia Diachkov <ilia.diachkov@optimitech.com>
bfd/
* elfnn-riscv.c (_bfd_riscv_relax_lui): Delete early exit when
SEC_MERGE or SEC_CODE flags are set.
(_bfd_riscv_relax_section): New local symtype. Set sym_sec and
symtype consistently. Don't include sec_addr (sym_sec) in symval.
Add check for SEC_INFO_TYPE_MERGE and call _bfd_merged_section_offset.
Add sec_addr (sym_sec) after handling merge sections.
commit d2ef37ebd9
Author: H.J. Lu <hjl.tools@gmail.com>
Date: Fri Dec 7 08:30:30 2018 -0800
elf: Report property change when merging properties
failed to remove the property after reporting it has been removed. This
patch corrects it.
bfd/
PR ld/24721
* elf-properties.c (elf_merge_gnu_property_list): Remove the
property after reporting property removal.
ld/
PR ld/24721
* testsuite/ld-x86-64/x86-64.exp: Run PR ld/24721 tests.
* testsuite/ld-x86-64/pr24721-x32.d: New file.
* testsuite/ld-x86-64/pr24721.d: Likewise.
* testsuite/ld-x86-64/pr24721.map: Likewise.
* testsuite/ld-x86-64/pr24721a.s: Likewise.
* testsuite/ld-x86-64/pr24721b.s: Likewise.
While the skiboot linker script bears some culpability in this PR,
it's also true that the GOT indirect to GOT relative optimisation for
16-bit offsets isn't safe. At least, it isn't safe to remove the GOT
entry based on distance between the GOT pointer and symbol calculated
from the preliminary layout. So this patch removes that optimisation,
and reduces the range allowed for 32-bit and 34-bit offsets.
PR 24704
bfd/
* elf64-ppc.c (R_PPC64_GOT16_DS): Don't set has_gotrel.
(ppc64_elf_edit_toc): Don't remove R_PPC64_GOT16_DS got entries.
Reduce range of offsets allowed for other GOT relocs.
ld/
* testsuite/ld-powerpc/elfv2exe.d: Update.
* testsuite/ld-powerpc/elfv2so.d: Update.
Depending on optimisation level and gcc version, git commit 890f750a3b
introduces a false positive warning that i_shdrp may be used
uninitialized.
PR 24689
* elfcode.h (elf_object_p): Warning fix.
The testcase in the PR had a e_shstrndx section of type SHT_GROUP.
hdr->contents were initialized by setup_group rather than being read
from the file, thus last byte was not zero and string dereference ran
off the end of the buffer.
PR 24689
* elfcode.h (elf_object_p): Check type of e_shstrndx section.
Calls from functions that don't have a valid toc pointer in r2 (these
calls are marked with _NOTOC relocs) to functions that require r2
valid must go via the callee global entry point. This patch corrects
the condition the linker was using to detect functions that require r2
to be valid. Values of both zero and one in st_other local entry bits
mean a function doesn't care about r2.
* elf64-ppc.c (ppc64_elf_inline_plt): Correct st_other test for
functions that require r2 valid to use local entry.
(ppc64_elf_size_stubs, ppc64_elf_relocate_section): Likewise.
The loc_hash_table should only contain local ifunc symbols. The current
code already aborts if there is anything else and for defined ifunc
symbols elfNN_aarch64_allocate_dynrelocs is a no-op.
bfd/ChangeLog:
* elfnn-aarch64.c (elfNN_aarch64_allocate_local_dynrelocs): Remove.
(elfNN_aarch64_size_dynamic_sections): Remove loc_hash_table traversal
with elfNN_aarch64_allocate_local_dynrelocs.
These ilp32 relocations were missing for some reason.
bfd/ChangeLog:
* elfnn-aarch64.c: Enable MOVW_PREL relocs for ELF32.
include/ChangeLog:
* elf/aarch64.h (R_AARCH64_P32_MOVW_PREL_G0): Define.
(R_AARCH64_P32_MOVW_PREL_G0_NC): Define.
(R_AARCH64_P32_MOVW_PREL_G1): Define.
ld/ChangeLog:
* testsuite/ld-aarch64/aarch64-elf.exp: Add emit-relocs-22 and -23.
* testsuite/ld-aarch64/emit-relocs-22.d: New test.
* testsuite/ld-aarch64/emit-relocs-22.s: New test.
* testsuite/ld-aarch64/emit-relocs-23.d: New test.
* testsuite/ld-aarch64/emit-relocs-23.s: New test.
"paddi rt,sym@pcrel" as an abbreviation for "paddi rt,0,sym@pcrel,1"
is invalid, so replace with "pla rt,sym@pcrel" which is a valid form
of "pla rt,sym@pcrel(0),1".
* elf64-ppc.c: Fix comments involving paddi.
PR 24643
* elf32-arm.c (arm_elf_find_function): Fail if the symol table is
absent, or the bfd is not in the ELF formart.
* elfnn-aarch64.c (aarch64_elf_find_function): Likewise.
PR 24650
* elf.c (elfcore_make_auxv_note_section): New function.
(elfcore_grok_note): Use it.
(elfcore_grok_freebsd_note): Likewise.
(elfcore_grok_openbsd_note): Likewise.
(elfcore_grok_netbsd_note): Likewise. Plus add support for
NT_NETBSDCORE_AUXV notes.
If the new GNU property section was being created by the linker
(this will happen only if none of the inputs have any GNU property
section but the command line to the linker forces a bti with
--force-bti), the alignment of the section and hence the program
header of PT_GNU_PROPERTY type was not being set correctly. This
patch fixes this issue.
bfd/ChangeLog:
2019-06-06 Sudakshina Das <sudi.das@arm.com>
* elfxx-aarch64.c (_bfd_aarch64_elf_link_setup_gnu_properties): Set
alignment of the new gnu property section.
ld/ChangeLog:
2019-06-06 Sudakshina Das <sudi.das@arm.com>
* testsuite/ld-aarch64/aarch64-elf.exp: Add new tests.
* testsuite/ld-aarch64/property-bti-pac4-a.d: New test.
* testsuite/ld-aarch64/property-bti-pac4-b.d: New test.
* testsuite/ld-aarch64/property-bti-pac4.s: New test.
Overflow checks were removed for all hi16 relocations except PC-relative
high relocations per PR ld/16720. Remove overflow checks from %pcrel_hi
relocations so that we can correctly handle negative offsets from PC.
bfd/
* elfxx-mips.c (mips_elf_calculate_relocation) <R_MIPS_PCHI16>:
Remove overflow check.
ld/
* testsuite/ld-mips-elf/undefweak-overflow.s: Remove test case
for pcrel_hi/pcrel_lo.
* testsuite/ld-mips-elf/undefweak-overflow.d: Update to match.
* testsuite/ld-mips-elf/reloc-pcrel-r6.s: New test source.
* testsuite/ld-mips-elf/reloc-pcrel-r6.d: New test linker script.
* testsuite/ld-mips-elf/reloc-pcrel-r6.ld: New test.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new test.
A plugin can change the element, so call the generic
bfd_link_add_symbols.
PR 24596
* cofflink.c (coff_link_check_archive_element): Don't assume
element is a coff object file after calling add_archive_element.
This patch cures a linker segfault, and "FAIL: Build pr22263-1".
PR 24596
* elf64-alpha.c (elf64_alpha_relocate_section): Don't attempt
to emit R_ALPHA_GOTTPREL in PIEs, for which no space is
allocated in alpha_dynamic_entries_for_reloc.
This doesn't fix the underlying bug, but an abort is better than a
segfault.
PR 24596
* elf32-m68k.c (elf_m68k_get_got_entry): Don't create a new
entry when MUST_FIND. Abort when MUST_FIND not found.
(elf_m68k_get_bfd2got_entry): Likewise.
(elf_m68k_relocate_section): Remove now useless assert.
One of the ld tests produces:
failed with: <Segmentation fault>, no expected output
FAIL: Discarded dynamic relocation section
This patch cures the segv. (The test still fails with ld producing
a really messed up output, DT_RELA at address 0!)
PR 24596
* elf64-hppa.c (elf64_hppa_finalize_dynreloc): Get the output bfd
from bfd_link_info, not an output section owner.
(elf64_hppa_finish_dynamic_symbol, elf64_hppa_finalize_opd): Likewise.
(elf_hppa_final_link_relocate): Likewise.
See also the FIXME. tic30-aout linker support is so bad (and has been
that way since the initial tic30-aout commit) that I'm obsoleting the
target. This patch fixes numerous linker testsuite segmentation faults.
PR 24596
* aout-tic30.c (MY_bfd_final_link): Don't segfault on missing
create_object_symbols_section, obj_textsec, obj_datasec or
obj_bsssec. Fix other errors in placement.
* config.bfd: Obsolete tic30-aout.
The XCOFF linker temporarily trims the output bfd section list,
without adjusting section_count to suit. This is a little rude, but
the dwarf line number code can easily cope with this situation. So
check for a NULL end of list as well as limiting the saved section
VMAs to the first section_count list entries.
Also fixes
-FAIL: Weak test 3 (main, static) (32-bit)
-FAIL: Weak test 3 (main, static) (64-bit)
PR 24596
* dwarf2.c (save_section_vma, section_vma_same): Check for NULL
end of section list as well as section_count.
* xcofflink.c (xcoff_link_add_symbols): Fix temporarily changed
section list before returning error.
After fixing the ld-elf/pr22836-1a segmentation fault we run into an
assertion failure due to the generic ELF target not removing empty
SHT_GROUP sections. Avoid that.
* elf.c (bfd_elf_set_group_contents): Exit on zero size section.
Even though the generic ELF target doesn't handle groups correctly,
this helps avoid a segfault in bfd_elf_set_group_contents seen on
d30v-elf, dlx-elf, pj-elf, and xgate-elf when linking the pr22836
testcase.
PR 24596
bfd/
* linker.c (_bfd_generic_link_output_symbols): Heed BSF_KEEP.
ld/
* emultempl/genelf.em (gld${EMULATION_NAME}_after_open): Set
BFS_KEEP on group signature symbol.
Propagate STO_AARCH64_VARIANT_PCS st_other attribute to the output and
add DT_AARCH64_VARIANT_PCS dynamic tag if necessary.
Mismatching attributes are not diagnosed.
bfd/ChangeLog:
* elfnn-aarch64.c (elfNN_aarch64_merge_symbol_attribute): New function.
(struct elf_aarch64_link_hash_table): Add variant_pcs member.
(elfNN_aarch64_allocate_dynrelocs): Update variant_pcs.
(elfNN_aarch64_size_dynamic_sections): Add DT_AARCH64_VARIANT_PCS.
(elf_backend_merge_symbol_attribute): Define.
ld/ChangeLog:
* testsuite/ld-aarch64/aarch64-elf.exp: Add new tests.
* testsuite/ld-aarch64/variant_pcs-1.s: New asm for tests.
* testsuite/ld-aarch64/variant_pcs-2.s: New asm for tests.
* testsuite/ld-aarch64/variant_pcs-now.d: New test.
* testsuite/ld-aarch64/variant_pcs-r.d: New test.
* testsuite/ld-aarch64/variant_pcs-shared.d: New test.
* testsuite/ld-aarch64/variant_pcs.ld: New linker script for tests.
bfd/
* elf64-ppc.c (ppc64_elf_check_relocs): Set has_gotrel for
R_PPC64_GOT_PCREL34.
(xlate_pcrel_opt): New function.
(ppc64_elf_edit_toc): Handle R_PPC64_GOT_PCREL34.
(ppc64_elf_relocate_section): Edit GOT indirect to GOT relative
for R_PPC64_GOT_PCREL34. Implement R_PPC64_PCREL_OPT optimisation.
ld/
* testsuite/ld-powerpc/pcrelopt.s,
* testsuite/ld-powerpc/pcrelopt.d,
* testsuite/ld-powerpc/pcrelopt.sec: New test.
* testsuite/ld-powerpc/powerpc.exp: Run it.
This patch avoids for bpf_elf64_le_vec to be referenced in targmatch.h
when building a BFD without BFD64, resulting in an undefined symbol.
This was a regression introduced along with the BPF target.
bfd/ChangeLog:
2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
* config.bfd (targ_cpu): Process bpf-*-none only if BFD64.
* configure.ac: Set target_size=64 for bpf_elf64_le_vec and
bpf_elf64_be_vec.
* configure: Regenerate.
The archive element cache needs tidying when closing an archive element.
This patch fixes these failures:
-FAIL: ar long file names (bfdtest1)
-FAIL: ar thin archive (bfdtest1)
-FAIL: ar thin archive with nested archive (bfdtest1)
* som.c (som_bfd_free_cached_info): Call
_bfd_generic_close_and_cleanup.
bfd/
* elfxx-mips.c (_bfd_mips_elf_check_relocs): Add NULL pointer
checks. Search the RELA table for n64 relocations.
ld/
* testsuite/ld-mips-elf/pic-reloc-5.d: New test.
* testsuite/ld-mips-elf/pic-reloc-6.d: New test.
* testsuite/ld-mips-elf/pic-reloc-7.d: New test.
* testsuite/ld-mips-elf/pic-reloc-5.s: New test source.
* testsuite/ld-mips-elf/pic-reloc-6.s: New test source.
* testsuite/ld-mips-elf/pic-reloc-7.s: New test source.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
Add a new option to get the linker to emit PLTs that use compact
branches instead of delay slot branches.
bfd/
* elfxx-mips.c (LA25_BC): New macro.
(mips_elf_link_hash_table)<compact_branches>: New field.
(STUB_JALRC): New macro.
(mipsr6_o32_exec_plt0_entry_compact): New array.
(mipsr6_n32_exec_plt0_entry_compact): Likewise.
(mipsr6_n64_exec_plt0_entry_compact): Likewise.
(mipsr6_exec_plt_entry_compact): Likewise.
(mips_elf_create_la25_stub): Use BC instead of J for stubs
when compact_branches is true.
(_bfd_mips_elf_finish_dynamic_symbol): Choose the compact
PLT for MIPSR6 with compact_branches. Do not reorder the
compact branches PLT. Switch the lazy stub for MIPSR6
with compact_branches to use JALRC.
(mips_finish_exec_plt): Choose the compact PLT0 for MIPSR6
when compact_branches is true.
(_bfd_mips_elf_compact_branches): New function.
* elfxx-mips.h (_bfd_mips_elf_compact_branches): New prototype.
ld/
* emultempl/mipself.em (compact_branches): New static variable.
(mips_create_output_section_statements): Call
_bfd_mips_elf_compact_branches.
(PARSE_AND_LIST_PROLOGUE): Add OPTION_COMPACT_BRANCHES and
OPTION_NO_COMPACT_BRANCHES.
(PARSE_AND_LIST_LONGOPTS): Add compact-branches,
no-compact-branches.
(PARSE_AND_LIST_OPTIONS): Add --compact-branches,
--no-compact-branches.
(PARSE_AND_LIST_ARGS_CASES): Handle the above.
* ld.texinfo: Document --compact-branches, --no-compact-branches.
* testsuite/ld-mips-elf/pic-and-nonpic-1-r6.dd: New test.
* testsuite/ld-mips-elf/pic-and-nonpic-1-r6.nd: New test.
* testsuite/ld-mips-elf/pic-and-nonpic-3a-r6.dd: New test.
* testsuite/ld-mips-elf/pic-and-nonpic-3a-r6.gd: New test.
* testsuite/ld-mips-elf/pic-and-nonpic-1a-r6.s: New test source.
* testsuite/ld-mips-elf/pic-and-nonpic-3a-r6.s: New test source.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
This patch fixes a hardcoded `l` specifier on a `bfd_signed_vma`.
Instead this now uses BFD_VMA_FMT which fixes the build on 32 bit
hosts.
Committed under the obvious rule.
bfd/ChangeLog:
PR ld/24373
* elfnn-aarch64.c (_bfd_aarch64_erratum_843419_branch_to_stub):
Fix print formatter.
The Cortex-A53 erratum currently has two ways it can resolve the erratum when
using the flag --fix-cortex-a53-843419:
1) If the address is within the range of an ADR instruction it rewrites the ADRP
into an ADR, and those doesn't need the use of a veneer.
2) If the address is not within range, it adds a branch to a veneer which will
execute the final bit of the erratum workaround and branch back to the call
site.
When we do this we always generate the veneers and we always align the size of
the text section to 4KB. This is because we only know which workaround we can
use after all linking has finished and all addresses are known. This means even
though the veneers are not used, we still generate the section and we still
change the size of the input section.
This is problematic for small memory devices as this would require the user to
take about a ~4KB hit in memory even though it's not even used.
Since there's no real way to restart the linking process from the final write
phase this patch solves the issue by allowing the user more control over which
erratum workaround gets used.
Concretely this changes the option --fix-cortex-a53-843419 to take optional
arguments --fix-cortex-a53-843419[=full|adr|adrp]
- full (default): Use both ADRP and ADR workaround. This is equivalent to not
specifying any options and is the default behavior before this
patch.
- adr: Only use the ADR workaround, this will not cause any increase in binary
size but linking will fail if the referenced address is out of range of
an ADR instruction.
- adrp: Use only the ADRP workaround, this will never rewrite your ADRP.
In the cases where the user knows how big their binaries are the `adr` option
would prevent the unneeded overhead.
bfd/ChangeLog:
PR ld/24373
* bfd-in.h (enum erratum_84319_opts): New
(bfd_elf64_aarch64_set_options, bfd_elf32_aarch64_set_options): Change
int to enum erratum_84319_opts.
* bfd-in2.h: Regenerate.
* elfnn-aarch64.c (struct elf_aarch64_link_hash_table): Change
fix_erratum_843419 to use new enum, remove fix_erratum_843419_adr.
(_bfd_aarch64_add_stub_entry_after): Conditionally create erratum stub.
(aarch64_size_one_stub): Conditionally size erratum 843419 stubs.
(_bfd_aarch64_resize_stubs): Amend comment.
(elfNN_aarch64_size_stubs): Don't generate stubs when no workaround
requested.
(bfd_elfNN_aarch64_set_options): Use new fix_erratum_843419 enum.
(_bfd_aarch64_erratum_843419_branch_to_stub): Implement selection of
erratum workaround.
(clear_erratum_843419_entry): Update erratum conditional.
ld/ChangeLog:
PR ld/24373
* emultempl/aarch64elf.em (PARSE_AND_LIST_LONGOPTS): Add optional args
to flags.
* NEWS: Add changes to flag.
(PARSE_AND_LIST_OPTIONS): Update help descriptions.
(PARSE_AND_LIST_ARGS_CASES): Add new options to parser.
* testsuite/ld-aarch64/aarch64-elf.exp: Add new run_dump_tests.
* testsuite/ld-aarch64/erratum843419-adr.d: New test.
* testsuite/ld-aarch64/erratum843419-adrp.d: New test.
* testsuite/ld-aarch64/erratum843419-far-adr.d: New test.
* testsuite/ld-aarch64/erratum843419-far-full.d: New test.
* testsuite/ld-aarch64/erratum843419-far.s: New test.
* testsuite/ld-aarch64/erratum843419-full.d: New test.
* testsuite/ld-aarch64/erratum843419-near.s: New test.
* testsuite/ld-aarch64/erratum843419-no-args.d: New test.
The range check done to transform an absolute call/jump to a pc-relative one is
off-by-one, and that causes this shortening optimization to be missed if the
branch target is right at the range boundary.
In the non-shrinkable case, the range is what is mentioned in the ISA - -4094
bytes in the backward direction, and 4096 bytes in the positive direction.
In the shrinkable case, the forward jump range increases by two bytes (deleted
because of the shortening from call/jmp to rcall/rjmp), and therefore, the
range is -4094 in the reverse, and 4098 in the positive direction.
Fix the ranges for !shrinkable and shrinkable cases, and add a test caes to
ensure jumps to max forward and backward ranges get relaxed to rjmp.
The current code to compute relative distance in the wrap around case does not
handle the edge case of the target (after adjusting for implicit PC increment)
being exactly half of the wrap around distance. This patch fixes that and adds a
testcase.
The range for a forward relative jump call is 4096 bytes ((2 * 2047) + (2 bytes
for the implicit PC increment)). If the target of the jump is at a distance of
4098 bytes, it is out of range for a forward jump - however, a backward jump can
still reach that address if pmem-wrap-around is 8192.
Assume address 0 has rjmp to address 4098. With a wrap around of 8192 and
*without* adjusting for the implicit PC increment of 2 bytes, rjmp .-4096 will
jump to address 4096 (wrap around at 8192 and decreasing addresses from then
on). Adjusting 2 bytes for the implicit PC increment, the actual target is 4098.
avr_relative_distance_considering_wrap_around though, does the wrap around only
if the passed in distance is less than half of the wrap around distance. In this
case, it is exactly equal to half (original distance 4098, adjusted distance of
4096 and wraparound of 8192), and the bypassed wrap around causes the reloc
overflow error.
Fix by wrapping around even if adjusted distance is equal to half of wrap around
distance.
bfd/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* elf32-arm.c (elf32_arm_merge_eabi_attributes): Add case for Tag_MVE_arch.
binutils/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* readelf.c (arm_attr_tag_MVE_arch): New array for Tag_MVE_arch values.
(arm_attr_public_tag arm_attr_public_tags): Add case for Tag_MVE_arch.
elfcpp/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* arm.h (Tag_MVE_arch): Define new enum value.
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (mve_ext, mve_fp_ext): New features.
(armv8_1m_main_ext_table): Add new extensions.
(aeabi_set_public_attributes): Translate new features to new build attributes.
(arm_convert_symbolic_attribute): Add Tag_MVE_arch.
* doc/c-arm.texi: Document new extensions and new build attribute.
include/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* elf/arm.h (Tag_MVE_arch): Define new enum value.
* opcode/arm.h (FPU_MVE, FPU_MVE_FP): New MACROs for new features.
Fixes a failure seen with MALLOC_PERTURB_=1.
* elf32-arm.c (elf32_arm_write_section): Don't leave
error case of STM32L4XX_ERRATUM_BRANCH_TO_VENEER with
unitialised section contents.
PR 19921
binutils* objcopy.c: Add new option --verilog-data-width. Use it to set
the value of VerilogDataWidth.
* doc/binutils.texi: Document the new option.
* testsuite/binutils-all/objcopy.exp: Run tests of new option.
* testsuite/binutils-all/verilog-1.hex: New file.
* testsuite/binutils-all/verilog-2.hex: New file.
* testsuite/binutils-all/verilog-4.hex: New file.
* testsuite/binutils-all/verilog-8.hex: New file.
* NEWS: Mention the new feature.
bfd * verilog.c: (VerilogDataWidth): New variable.
(verilog_write_record): Emit bytes in VerilogDataWidth bundles.
This fixes the recently added ld-elf/pr24511 test failure on pj-elf.
Incidentally, pj-elf has failed its gas "pj" test since 2005-12-22
(git commit 54758c3e39). I think that makes the target ripe for
obsolescence.
bfd/
* elf32-pj.c (pj_elf_reloc): Don't report undefined weak as an error.
ld/
* testsuite/ld-undefined/weak-undef.exp: Don't xfail pj.
GOT and PLT relocs shouldn't have their symbols replaced with a
section symbol plus added. Nor should the HIGHA TLS relocations,
which failed to be caught by the range test in ppc_fix_adjustable.
bfd/
* reloc.c (BFD_RELOC_PPC64_TPREL16_HIGH, BFD_RELOC_PPC64_TPREL16_HIGHA),
(BFD_RELOC_PPC64_DTPREL16_HIGH, BFD_RELOC_PPC64_DTPREL16_HIGHA):
Sort before BFD_RELOC_PPC64_DTPREL16_HIGHESTA entry.
gas/
* config/tc-ppc.c (ppc_fix_adjustable): Exclude all GOT and PLT
relocs, and VLE sdarel relocs.
* testsuite/gas/ppc/power4.d: Adjust.
This patch restricts the section names matched in coff_section_type,
a function that translates section names to symbol type, and arranges
to translate section flags to symbol type before looking at names.
The latter change resulted in various test failures due to improper
section flags being used in tests, and by the plugin support, so fix
that too.
The new test fails on many ELF targets that lack .init/fini_array
in their scripts. I've just xfailed those. pru-elf oddly defines
__init_array_begin rather than __init_array_start. I've left that
target as a FAIL, and pj-elf too which reports an error for undefined
weak symbols.
bfd/
PR 24511
* syms.c (coff_section_type): Only allow '.', '$' and numeric
following the standard section names.
(bfd_decode_symclass): Prioritize section flag tests in
decode_section_type before name tests in coff_section_type.
* plugin.c (bfd_plugin_canonicalize_symtab): Init fake_section
and fake_common_section using BFD_FAKE_SECTION. Use "fake" as
their names and choose standard .text section flags for
fake_section.
ld/
PR 24511
* testsuite/ld-elf/pr14156a.d: Allow for .init/.fini being a
data section on hppa64.
* testsuite/ld-elf/pr14156b.d: Likewise.
* testsuite/ld-scripts/pr18963.t: Map standard sections to set
output section flags.
* testsuite/ld-scripts/sane1.t: Likewise.
* testsuite/ld-elf/init-fini-arrays.s: Reference __init_array_start
and __fini_array_start. Define __start et al.
* testsuite/ld-elf/pr24511.d: New test.
When undefined non-weak references in IR objects are optimized out
by LTO, we can have weak dynamic referencs to symbols marked with
bfd_link_hash_undefined. We shouldn't complain such undefined weak
dynamic references.
bfd/
PR ld/24486
* elflink.c (elf_link_output_extsym): Don't complain undefined
weak dynamic reference.
ld/
PR ld/24486
* testsuite/ld-plugin/lto.exp: Run PR ld/24486 tests.
* testsuite/ld-plugin/pr24486a.c: New file.
* testsuite/ld-plugin/pr24486b.c: Likewise.
* testsuite/ld-plugin/pr24486c.c: Likewise.
This patch aims to improve the definitions of BTI and PAC based PLTs.
The following changes are made:
* PLT0 does not need PAC instructions since the PLTGOT[2] (and PLTGOT[1])
are readonly so they cannot be corrupted at runtime. Thus both PAC plt0
and BTI+PAC plt0 are removed and we can use basic plt0 and BTI plt0
instead, respectively.
* We can remove the extra padding nops when we add the new bti instructions.
BTI plt0 and BTI TLSDESC plt are updated.
* For better performance PLTn could be padded to 24bytes. Both BTI pltn and
PAC pltn are updated.
*** bfd/ChangeLog ***
2019-04-25 Sudakshina Das <sudi.das@arm.com>
* elfnn-aarch64.c (PLT_BTI_ENTRY_SIZE): Remove.
(PLT_BTI_TLSDESC_ENTRY_SIZE): Remove.
(PLT_PAC_ENTRY_SIZE, PLT_BTI_PAC_ENTRY_SIZE): Remove.
(PLT_BTI_SMALL_ENTRY_SIZE, PLT_PAC_SMALL_ENTRY_SIZE): Update.
(elfNN_aarch64_small_plt0_pac_entry): Remove.
(elfNN_aarch64_small_plt0_bti_pac_entry): Remove.
(elfNN_aarch64_small_plt0_bti_entry): Update.
(elfNN_aarch64_small_plt_bti_entry): Update.
(elfNN_aarch64_small_plt_pac_entry): Update.
(elfNN_aarch64_tlsdesc_small_plt_bti_entry): Update.
(setup_plt_values): Setup new entries.
(elfNN_aarch64_finish_dynamic_sections): Remove size change.
(elfNN_aarch64_plt_sym_val): Likewise.
*** ld/ChangeLog ***
2019-04-25 Sudakshina Das <sudi.das@arm.com>
* testsuite/ld-aarch64/bti-pac-plt-1.d: Update.
* testsuite/ld-aarch64/bti-pac-plt-2.d: Update.
* testsuite/ld-aarch64/bti-plt-1.d: Update.
* testsuite/ld-aarch64/bti-plt-3.d: Update.
* testsuite/ld-aarch64/bti-plt-5.d: Update.
* testsuite/ld-aarch64/pac-plt-1.d: Update.
* testsuite/ld-aarch64/pac-plt-2.d: Update.
This tidies the remaining --no-print-map-discarded fails. h8300-elf
warns on a section without flags, and s12z doesn't support
--gc-sections.
bfd/
* elf32-s12z.c (elf_backend_can_gc_sections): Don't define
ld/
* testsuite/ld-gc/skip-map-discarded.s: Add section attributes.
* testsuite/lib/ld-lib.exp (check_gc_sections_available): Add
s12z to list of targets not supporting --gc-sections.
GNU as' Arm backend assumes each mnemonic has a single entry in the instruction table but VLDR (system register) and VSTR (system register) are different instructions than VLDR and VSTR. It is thus necessary to add some form of demultiplexing in the parser. It starts by creating a new operand type OP_VLDR which indicate that the operand is either the existing OP_RVSD operand or a system register. The function parse_operands () then tries these two cases in order, calling the new parse_sys_vldr_vstr for the second case.
Since the encoding function is specified in the instruction table entry, it also need to have some sort of demultiplexing. This is done in do_vldr_vstr which either calls the existing do_neon_ldr_str () or calls the new do_t_vldr_vstr_sysreg ().
A new internal relocation is needed as well since the offset has a shorter range than in other Thumb coprocessor instructions. Disassembly also requires special care since VSTR (system register) reuse the STC encoding with the coprocessor number 15. Armv8.1-M Mainline ARM manual states that coprocessor 8, 14 and 15 are reserved for floating-point and MVE instructions a feature bit check is added if the coprocessor number is one of this value and we are trying to match a coprocessor instruction (eg. STC) to forbid the match.
ChangeLog entries are as follows:
*** bfd/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* reloc.c (BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM): New internal
relocation.
* bfd-in2.h: Regenerate.
* libbfd.h: Likewise.
*** gas/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (parse_sys_vldr_vstr): New function.
(OP_VLDR): New enum operand_parse_code enumerator.
(parse_operands): Add logic for OP_VLDR.
(do_t_vldr_vstr_sysreg): New function.
(do_vldr_vstr): Likewise.
(insns): Guard VLDR and VSTR by arm_ext_v4t for Thumb mode.
(md_apply_fix): Add bound check for VLDR and VSTR co-processor offset.
Add masking logic for BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM relocation.
* testsuite/gas/arm/archv8m_1m-cmse-main-bad.s: Add examples of bad
uses of VLDR and VSTR.
* testsuite/gas/arm/archv8m_1m-cmse-main-bad.l: Add error messages for
above bad uses.
* testsuite/gas/arm/archv8m_1m-cmse-main.s: Add examples of VLDR and
VSTR valid uses.
* testsuite/gas/arm/archv8m_1m-cmse-main.d: Add disassembly for the
above examples.
*** opcodes/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* arm-dis.c (coprocessor_opcodes): Document new %J and %K format
specifier. Add entries for VLDR and VSTR of system registers.
(print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
coprocessor instructions on Armv8.1-M Mainline targets. Add handling
of %J and %K format specifier.
s patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils.
This patch adds support to the Scalar low overhead loop instructions:
LE
WLS
DLS
We also add a new assembler resolvable relocation bfd_reloc_code_real enum for the 12-bit branch offset used in these instructions.
ChangeLog entries are as follows:
*** bfd/ChnageLog ***
2019-04-12 Sudakshina Das <sudi.das@arm.com>
* reloc.c (BFD_RELOC_ARM_THUMB_LOOP12): New.
* bfd-in2.h: Regenerated.
* libbfd.h: Regenerated.
*** gas/ChangeLog ***
2019-04-12 Sudakshina Das <sudi.das@arm.com>
Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (operand_parse_code): Add OP_LR and OP_oLR
for the LR operand and optional LR operand.
(parse_operands): Add switch cases for OP_LR and OP_oLR for
both type checking and value checking.
(encode_thumb32_addr_mode): New entries for DLS, WLS and LE.
(v8_1_loop_reloc): New helper function for handling labels
for the low overhead loop instructions.
(do_t_loloop): New function to encode DLS, WLS and LE.
(insns): New entries for WLS, DLS and LE.
(md_pcrel_from_section): New switch case
for BFD_RELOC_ARM_THUMB_LOOP12.
(md_appdy_fix): Likewise.
(tc_gen_reloc): Likewise.
* testsuite/gas/arm/armv8_1-m-tloop.s: New.
* testsuite/gas/arm/armv8_1-m-tloop.d: New.
* testsuite/gas/arm/armv8_1-m-tloop-bad.s: New.
* testsuite/gas/arm/armv8_1-m-tloop-bad.d: New.
* testsuite/gas/arm/armv8_1-m-tloop-bad.l: New.
*** opcodes/ChangeLog ***
2019-04-12 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (print_insn_thumb32): Updated to accept new %P
and %Q patterns.
s patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils.
This patch adds the BFCSEL instruction. It also adds a local relocation with a new bfd_reloc_code_real enum.
ChangeLog entries are as follows:
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* reloc.c (BFD_RELOC_THUMB_PCREL_BFCSEL): New relocation.
* bfd-in2.h: Regenerated.
* libbfd.h: Likewise.
*** gas/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (T16_32_TAB): New entriy for bfcsel.
(do_t_v8_1_branch): New switch case for bfcsel.
(toU): Define.
(insns): New instruction for bfcsel.
(md_pcrel_from_section): New switch case
for BFD_RELOC_THUMB_PCREL_BFCSEL.
(md_appdy_fix): Likewise
(tc_gen_reloc): Likewise.
* testsuite/gas/arm/armv8_1-m-bfcsel.d: New.
* testsuite/gas/arm/armv8_1-m-bfcsel.s: New.
*** ld/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* testsuite/ld-arm/bfcsel.s: New.
* testsuite/ld-arm/bfcsel.d: New.
* testsuite/ld-arm/arm-elf.exp: Add above test.
*** opcodes/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (thumb32_opcodes): New instruction bfcsel.
(print_insn_thumb32): Edit the switch case for %Z.
This patch is part of a series of patches to add support for Armv8.1-M Mainline
instructions to binutils.
This adds infrastructure for the BFCSEL instructions which is one of the first
instructions in Arm that have more than one relocations in them.
This adds a new relocation R_ARM_THM_BF12.
The inconsistency between external R_ARM_THM_BF12 and internal
BFD_RELOC_ARM_THUMB_BF13 is because internally we count the static bit-0 of the
immediate and we don't externally.
ChangeLog entries are as follows :
ChangeLog entries are as follows :
*** bfd/ChnageLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* reloc.c (BFD_RELOC_ARM_THUMB_BF13): New.
* bfd-in2.h: Regenerated.
* libbfd.h: Regenerated.
* elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF13.
(elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF13
and R_ARM_THM_BF12 together.
(elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF13.
*** elfcpp/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* arm.h (R_ARM_THM_BF12): New relocation code.
*** gas/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (md_pcrel_from_section): New switch case for
BFD_RELOC_ARM_THUMB_BF13.
(md_appdy_fix): Likewise.
(tc_gen_reloc): Likewise.
*** include/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF12.
*** opcodes/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils.
This adds infrastructure for the BFL instructions which is one of the first instructions in Arm that have more than one relocations in them.
This adds a new relocation R_ARM_THM_BF18.
The inconsistency between external R_ARM_THM_BF18 and internal
BFD_RELOC_ARM_THUMB_BF19 is because internally we count the static bit-0 of the immediate and we don't externally.
ChangeLog entries are as follows :
*** bfd/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* reloc.c (BFD_RELOC_ARM_THUMB_BF19): New
* libbfd.h: Regenerated.
* bfd-in2.h: Regenerated.
* bfd-elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF18.
(elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF19
and R_ARM_THM_BF18 together.
(elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF19.
*** elfcpp/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm.h (R_ARM_THM_BF18): New relocation code.
*** gas/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (md_pcrel_from_section): New switch case for
BFD_RELOC_ARM_THUMB_BF19.
(md_appdy_fix): Likewise.
(tc_gen_reloc): Likewise.
*** include/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF18.
*** opcodes/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils.
This adds infrastructure for the BF instructions which is one of the first instructions in Arm that have more than one relocations in them.
This is the third infrastructure patch that adds a new relocation R_ARM_THM_BF16.
The inconsistency between external R_ARM_THM_BF16 and internal
BFD_RELOC_ARM_THUMB_BF17 is because internally we count the static bit-0 of the immediate and we don't externally.
ChangeLog entries are as follows :
*** bfd/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* reloc.c (BFD_RELOC_ARM_THUMB_BF17): New enum.
* bfd-in2.h: Regenerated.
* libbfd.h: Regenerated.
* bfd-elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF16.
(elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF17
and R_ARM_THM_BF16 together.
(get_value_helper): New reloc helper.
(elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF16.
*** elfcpp/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm.h (R_ARM_THM_BF16): New relocation code.
*** gas/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (md_pcrel_from_section): New switch case for
BFD_RELOC_ARM_THUMB_BF17.
(md_appdy_fix): Likewise.
(tc_gen_reloc): Likewise.
*** include/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF16.
*** opcodes/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
This patch is part of a series of patches to add support for Armv8.1-M Mainline
instructions to binutils.
This adds infrastructure for the Branch Future instructions (BF, BFX, BFL, BFLX,
BFCSEL). These are the first instructions in ARM that have more than one
relocations in them.
This is the first infrastructure patch that adds a new bfd_reloc_code_real enum
for the fallback branch offset.
This is common for all such instructions and needs to be resolvable by the
assembler.
ChangeLog entries are as follows :
*** bfd/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* reloc.c (BFD_RELOC_THUMB_PCREL_BRANCH5): New enum.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
*** gas/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (md_pcrel_from_section): New switch case
for BFD_RELOC_THUMB_PCREL_BRANCH5.
(v8_1_branch_value_check): New function to check branch
offsets.
(md_appdy_fix): New switch case for
BFD_RELOC_THUMB_PCREL_BRANCH5.
(tc_gen_reloc): Likewise.
*** opcodes/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
The patch is straightforward, it does the following:
- support the new Tag_CPU_arch build attribute value, ie.:
+ declare the new value
+ update all the asserts forcing logic to be reviewed for new
architectures
+ create a corresponding bfd_mach_arm_8_1M_MAIN enumerator in bfd and
add mapping from Tag_CPU_arch to it
+ teach readelf about new Tag_CPU_arch value
- declare armv8.1-m.main as a supported architecture value
- define Armv8.1-M Mainline in terms of feature bits available
- tell objdump mapping from bfd_mach_arm_8_1M_MAIN enumerator to feature
bits available
- update architecture-specific logic in gas and bfd guarded by the
asserts mentioned above.
- tests for all the above
ChangeLog entries are as follows:
*** bfd/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* archures.c (bfd_mach_arm_8_1M_MAIN): Define.
* bfd-in2.h: Regenerate.
* cpu-arm.c (arch_info_struct): Add entry for Armv8.1-M Mainline.
* elf32-arm.c (using_thumb_only): Return true for Armv8.1-M Mainline
and update assert.
(using_thumb2): Likewise.
(using_thumb2_bl): Update assert.
(arch_has_arm_nop): Likewise.
(bfd_arm_get_mach_from_attributes): Add case for Armv8.1-M Mainline.
(tag_cpu_arch_combine): Add logic for Armv8.1-M Mainline merging.
*** binutils/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* readelf.c (arm_attr_tag_CPU_arch): Add entry for Armv8.1-M Mainline.
*** gas/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (cpu_arch_ver): Add entry for Armv8.1-M Mainline
Tag_CPU_arch build attribute value. Reindent.
(get_aeabi_cpu_arch_from_fset): Update assert.
(aeabi_set_public_attributes): Update assert for Tag_DIV_use logic.
* testsuite/gas/arm/attr-march-armv8_1-m.main.d: New test.
*** include/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* elf/arm.h (TAG_CPU_ARCH_V8_1M_MAIN): new macro.
(MAX_TAG_CPU_ARCH): Set value to above macro.
* opcode/arm.h (ARM_EXT2_V8_1M_MAIN): New macro.
(ARM_AEXT_V8_1M_MAIN): Likewise.
(ARM_AEXT2_V8_1M_MAIN): Likewise.
(ARM_ARCH_V8_1M_MAIN): Likewise.
*** ld/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* testsuite/ld-arm/attr-merge-13.attr: New test.
* testsuite/ld-arm/attr-merge-13a.s: New test.
* testsuite/ld-arm/attr-merge-13b.s: New test.
*** opcodes/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
When using DF_BIND_NOW on AArch64 we don't reserve the GOT slot for a TLSDESC,
but we still emitted DT_TLSDESC_GOT and DT_TLSDESC_PLT. This caused random
memory corruption as the "special" value of (bfd_vma)-1 would be set for
dt_tlsdesc_got.
Since we don't have a value of dt_tlsdesc_got I also don't emit DT_TLSDESC_PLT
now becuase it would point to an incomplete PLT. To be able to write the PLT
entry DT_TLSDESC_GOT is needed and since we don't have one we can't write the
PLT entry either.
It is my understanding that GLIBC doesn't need these two entries when not lazy
loading. Conversely AArch32 does not reserve neither the GOT not the PLT slot
when doing DF_BIND_NOW.
AArch32 does not need these checks because these values are initialized to 0
and so the if (...) checks don't pass, but on AArch64 these are initialized
to (bfd_vma)-1 and thus we need some extra checks.
bfd/ChangeLog:
PR ld/24302
* elfnn-aarch64.c (elfNN_aarch64_size_dynamic_sections): Don't emit
DT_TLSDESC_GOT and DT_TLSDESC_PLT when DF_BIND_NOW.
(elfNN_aarch64_finish_dynamic_sections): Don't write PLT if DF_BIND_NOW.
ld/ChangeLog:
PR ld/24302
* testsuite/ld-aarch64/aarch64-elf.exp: Add new test.
* testsuite/ld-aarch64/tls-relax-gdesc-le-now.d: New test.
x86_64-rdos is one of the few x86_64 targets that is 64-bit only and
the x86_64 configure entries don't depend on elf-vxworks.lo. This
results in undefined references from elfxx-x86.o.
* configure.ac (elfxx_x86): Define and use.
* configure: Regenerate.
This fixes a glib build failure reported in PR 24389. Using ld -b binary
creates an object file with no elf header flags set which has the wrong ABI
info for riscv64-linux. But the file also has no code sections, so I added
code borrowed from the arm port that only checks the ELF header ABI flags if
there is a code section.
bfd/
PR 24389
* elfnn-riscv.c (_bfd_riscv_elf_merge_private_bfd_data): Move read of
ELF header flags to after check for ELF object file. Loop through
sections looking for code sections, if none, then skip ABI checks.
shrink_dynamic_reloc_sections must remove PLT entry that was created for
an undefined weak symbol in the presence of --export-dynamic option when
relaxation coalesces literals pointing to that symbol. This fixes the
following assertion:
ld: BFD (GNU Binutils) 2.31.1 internal error, aborting at
elf32-xtensa.c:3292 in elf_xtensa_finish_dynamic_sections
2019-03-29 Max Filippov <jcmvbkbc@gmail.com>
bfd/
* elf32-xtensa.c (shrink_dynamic_reloc_sections): Add
info->export_dynamic to the conditional.
ld/
* testsuite/ld-xtensa/relax-undef-weak-pie-export-dynamic.d: New
test definition.
* testsuite/ld-xtensa/xtensa.exp
(relax-undef-weak-pie-export-dynamic): Add new test.
sym is only set for local symbols. h is only set for global symbols. Gas
won't let me create a global section symbol, but bfd appears to have some
support for that, and I can't rule out that other assemblers might do this.
So we need to support both, and verify sym and h are non-NULL before using.
bfd/
PR 24365
* elfnn-riscv.c (riscv_elf_relocate_section): For STT_SECTION check,
verify sym non-NULL before using. Add identical check using h.
The AArch64 linker option to turn on BTI (--force-bti) warns in case there are
input objects which have a missing GNU NOTE section for BTI. This patch is trying
to improve the warnings that come out.
In order to do so, I propose adding a new argument to elf_merge_gnu_properties
and the backend function merge_gnu_properties. This new argument makes sure
that we now pass both the objects along with the properties to which they
belong to. The x86 backend function has also been updated to match this
change.
*** bfd/ChangeLog ***
2019-03-21 Sudakshina Das <sudi.das@arm.com>
* elf-bfd.h (struct elf_backend_data): Add argument to
merge_gnu_properties.
* elf-properties.c (elf_merge_gnu_properties): Add argument to
itself and while calling bed->merge_gnu_properties.
(elf_merge_gnu_property_list): Update the calls for
elf_merge_gnu_properties.
* elfnn-aarch64.c (elfNN_aarch64_merge_gnu_properties): Update handling
of --force-bti warning and add argument.
* elfxx-aarch64.c (_bfd_aarch64_elf_link_setup_gnu_properties): Add
warning.
* elfxx-x86.c (_bfd_x86_elf_merge_gnu_properties): Add argument.
* elfxx-x86.h (_bfd_x86_elf_merge_gnu_properties): Likewise in
declaration.
*** ld/ChangeLog ***
2019-03-21 Sudakshina Das <sudi.das@arm.com>
* testsuite/ld-aarch64/aarch64-elf.exp: Add new test.
* testsuite/ld-aarch64/bti-plt-1.s: Add .ifdef for PAC note section.
* testsuite/ld-aarch64/bti-plt-6.d: Update warning.
* testsuite/ld-aarch64/bti-plt-7.d: Likewise.
* testsuite/ld-aarch64/bti-warn.d: New test.
This patch add support for elf_backend_fixup_gnu_properties for GNU
property support for AArch64. The new AArch64 specific definition
_bfd_aarch64_elf_link_fixup_gnu_properties goes through the property
list to find AArch64 type properties and removes the properties that
are marked as "property_remove".
*** bfd/ChangeLog ***
2019-03-20 Sudakshina Das <sudi.das@arm.com>
* elfxx-aarch64.c (_bfd_aarch64_elf_link_fixup_gnu_properties): Define.
* elfxx-aarch64.h (_bfd_aarch64_elf_link_fixup_gnu_properties): Declare.
(elf_backend_fixup_gnu_properties): Define for AArch64.
This one looks to be a bug going back to 2009, git commit e054468f6c
"STT_GNU_IFUNC support for PowerPC". That bug was carried over with
git commit 49c09209d0 "Rearrange PLT reloc output on powerpc".
If the refcount for an ifunc local sym plt entry was zero,
ppc_elf_size_dynamic_sections would correctly set plt.offset to -1 but
leave glink_offset uninitialized. That leads to occasional segfaults
(which can be made solid with MALLOC_PERTURB_=1 when using glibc).
So, guard the write_glink_stub call with plt.offset != -1. Also,
remove the totally ineffective attempt at writing multiple-use glink
stubs only once.
PR 24355
* elf32-ppc.c (ppc_finish_symbols): Don't call write_glink_stub
for local iplt syms with ent->plt.offset == -1. Remove ineffective
attempt at writing glink stubs only once.
Reverts commit 1ff31e135f, fixing the problem more generally. There
are likely other place that will segfault on a NULL section.
PR 24337
* elf.c (_bfd_elf_rela_local_sym): Revert last change.
(_bfd_elf_rel_local_sym): Likewise.
* elflink.c (elf_link_input_bfd): Use bfd_und_section for
section of symbols with unrecognized shndx.
For LTO, a symbol may defined in discarded section. We should mark it
as undefined so that LTO plugin will make IR definition available.
PR ld/24267
* coffgen.c (_bfd_coff_section_already_linked): Skip discarded
section.
* cofflink.c (coff_link_add_symbols): Check for symbols defined
in discarded section.
PR 24334
* dwarf2.c (struct dwarf2_debug): Add sec_vma_count field.
(save_section_vma): Initialise field to the number of entries in
the sec_vma table.
(section_vma_same): Check that the number of entries in the
sec_vma table matches the number of sections in the bfd.
PR 24332
* elflink.c (elf_link_add_object_symbols): Add new local variable
extversym_end. Initialise it to point to the end of the version
symbol table, if present. Check it when initialising and updating
the ever pointer.
This is part of the patch series to add support for BTI and
PAC in AArch64 linker.
1) This patch adds new definitions of PAC enabled PLTs
and both BTI and PAC enabled PLTs.
2) It also defines the new dynamic tag DT_AARCH64_PAC_PLT
for the PAC enabled PLTs.
3) This patch adds a new ld command line option: --pac-plt.
In the presence of this option, the linker uses the PAC
enabled PLTs and marks with DT_AARCH64_PAC_PLT.
4) In case both BTI and PAC are enabled the linker should
pick PLTs enabled with both and also use dynamic tags for both.
All these are made according to the new AArch64 ELF ABI
https://developer.arm.com/docs/ihi0056/latest/elf-for-the-arm-64-bit-architecture-aarch64-abi-2018q4
*** bfd/ChangeLog ***
2019-03-13 Sudakshina Das <sudi.das@arm.com>
* elfnn-aarch64.c (PLT_PAC_ENTRY_SIZE, PLT_PAC_SMALL_ENTRY_SIZE): New.
(PLT_BTI_PAC_ENTRY_SIZE, PLT_BTI_PAC_SMALL_ENTRY_SIZE): New.
(setup_plt_values): Account for PAC or PAC and BTI enabled PLTs.
(elfNN_aarch64_size_dynamic_sections): Add checks for PLT_BTI_PAC
and PLT_PAC_PLT.
(elfNN_aarch64_finish_dynamic_sections): Account for PLT_BTI_PAC.
(get_plt_type): Add case for DT_AARCH64_PAC_PLT.
(elfNN_aarch64_plt_sym_val): Add cases for PLT_BTI_PAC and PLT_PAC.
*** binutils/ChangeLog ***
2019-03-13 Sudakshina Das <sudi.das@arm.com>
* readelf.c (get_aarch64_dynamic_type): Add case for
DT_AARCH64_PAC_PLT.
(dynamic_section_aarch64_val): Likewise.
*** include/ChangeLog ***
2019-03-13 Sudakshina Das <sudi.das@arm.com>
* elf/aarch64.h (DT_AARCH64_PAC_PLT): New.
*** ld/ChangeLog ***
2019-03-13 Sudakshina Das <sudi.das@arm.com>
* NEWS: Document --pac-plt.
* emultempl/aarch64elf.em (OPTION_PAC_PLT): New.
(PARSE_AND_LIST_LONGOPTS, PARSE_AND_LIST_OPTIONS): Add pac-plt.
(PARSE_AND_LIST_ARGS_CASES): Handle OPTION_PAC_PLT.
* testsuite/ld-aarch64/aarch64-elf.exp: Add the following tests.
* testsuite/ld-aarch64/bti-pac-plt-1.d: New test.
* testsuite/ld-aarch64/bti-pac-plt-2.d: New test.
* testsuite/ld-aarch64/pac-plt-1.d: New test.
* testsuite/ld-aarch64/pac-plt-2.d: New test.
* testsuite/ld-aarch64/bti-plt-1.s: Add .ifndef directive.
This is part of the patch series to add support for BTI and
PAC in AArch64 linker.
1) This patch adds a new ld command line option: --force-bti.
In the presence of this option, the linker enables BTI with the
GNU_PROPERTY_AARCH64_FEATURE_1_BTI feature. This gives out warning
in case of missing gnu notes for BTI in inputs.
2) It also defines a new set of BTI enabled PLTs. These are used either
when all the inputs are marked with GNU_PROPERTY_AARCH64_FEATURE_1_BTI
or when the new --force-bti option is used. This required adding new
fields in elf_aarch64_link_hash_table so that we could make the PLT
related information more generic.
3) It also defines a dynamic tag DT_AARCH64_BTI_PLT. The linker uses
this whenever it picks BTI enabled PLTs.
All these are made according to the new AArch64 ELF ABI
https://developer.arm.com/docs/ihi0056/latest/elf-for-the-arm-64-bit-architecture-aarch64-abi-2018q4
*** bfd/ChangeLog ***
2019-03-13 Sudakshina Das <sudi.das@arm.com>
Szabolcs Nagy <szabolcs.nagy@arm.com>
* bfd-in.h (aarch64_plt_type, aarch64_enable_bti_type): New.
(aarch64_bti_pac_info): New.
(bfd_elf64_aarch64_set_options): Add aarch64_bti_pac_info argument.
(bfd_elf32_aarch64_set_options): Likewise.
* bfd-in2.h: Regenerate
* elfnn-aarch64.c (PLT_BTI_ENTRY_SIZE): New.
(PLT_BTI_SMALL_ENTRY_SIZE, PLT_BTI_TLSDESC_ENTRY_SIZE): New.
(elfNN_aarch64_small_plt0_bti_entry): New.
(elfNN_aarch64_small_plt_bti_entry): New.
(elfNN_aarch64_tlsdesc_small_plt_bti_entry): New.
(elf_aarch64_obj_tdata): Add no_bti_warn and plt_type fields.
(elf_aarch64_link_hash_table): Add plt0_entry, plt_entry and
tlsdesc_plt_entry_size fields.
(elfNN_aarch64_link_hash_table_create): Initialise the new fields.
(setup_plt_values): New helper function.
(bfd_elfNN_aarch64_set_options): Use new bp_info to set plt sizes and
bti enable type.
(elfNN_aarch64_allocate_dynrelocs): Use new size members instead of
fixed macros.
(elfNN_aarch64_size_dynamic_sections): Likewise and add checks.
(elfNN_aarch64_create_small_pltn_entry): Use new generic pointers
to plt stubs instead of fixed ones and update filling them according
to the need for bti.
(elfNN_aarch64_init_small_plt0_entry): Likewise.
(elfNN_aarch64_finish_dynamic_sections): Likewise.
(get_plt_type, elfNN_aarch64_get_synthetic_symtab): New.
(elfNN_aarch64_plt_sym_val): Update size accordingly.
(elfNN_aarch64_link_setup_gnu_properties): Set up plts if BTI GNU NOTE
is set.
(bfd_elfNN_get_synthetic_symtab): Define.
(elfNN_aarch64_merge_gnu_properties): Give out warning with --force-bti
and mising BTI NOTE SECTION.
*** binutils/ChangeLog ***
2019-03-13 Sudakshina Das <sudi.das@arm.com>
Szabolcs Nagy <szabolcs.nagy@arm.com>
* readelf.c (get_aarch64_dynamic_type): New.
(get_dynamic_type): Use above for EM_AARCH64.
(dynamic_section_aarch64_val): New.
(process_dynamic_section): Use above for EM_AARCH64.
*** include/ChangeLog ***
2019-03-13 Sudakshina Das <sudi.das@arm.com>
Szabolcs Nagy <szabolcs.nagy@arm.com>
* elf/aarch64.h (DT_AARCH64_BTI_PLT): New.
*** ld/ChangeLog ***
2019-03-13 Sudakshina Das <sudi.das@arm.com>
Szabolcs Nagy <szabolcs.nagy@arm.com>
* NEWS: Document --force-bti.
* emultempl/aarch64elf.em (plt_type, bti_type, OPTION_FORCE_BTI): New.
(PARSE_AND_LIST_SHORTOPTS, PARSE_AND_LIST_OPTIONS): Add force-bti.
(PARSE_AND_LIST_ARGS_CASES): Handle OPTION_FORCE_BTI.
* testsuite/ld-aarch64/aarch64-elf.exp: Add all the tests below.
* testsuite/ld-aarch64/bti-plt-1.d: New test.
* testsuite/ld-aarch64/bti-plt-1.s: New test.
* testsuite/ld-aarch64/bti-plt-2.s: New test.
* testsuite/ld-aarch64/bti-plt-2.d: New test.
* testsuite/ld-aarch64/bti-plt-3.d: New test.
* testsuite/ld-aarch64/bti-plt-4.d: New test.
* testsuite/ld-aarch64/bti-plt-5.d: New test.
* testsuite/ld-aarch64/bti-plt-6.d: New test.
* testsuite/ld-aarch64/bti-plt-7.d: New test.
* testsuite/ld-aarch64/bti-plt-so.s: New test.
* testsuite/ld-aarch64/bti-plt.ld: New test.
This is part of the patch series to add support for BTI and
PAC in AArch64 linker.
This patch implements the following:
1) This extends in the gnu property support in the linker for
AArch64 by defining backend hooks for elf_backend_setup_gnu_properties,
elf_backend_merge_gnu_properties and elf_backend_parse_gnu_properties.
2) It defines AArch64 specific GNU property
GNU_PROPERTY_AARCH64_FEATURE_1_AND and 2 bit for BTI and PAC in it.
3) It also adds support in readelf.c to read and print these new
GNU properties in AArch64.
All these are made according to the new AArch64 ELF ABI
https://developer.arm.com/docs/ihi0056/latest/elf-for-the-arm-64-bit-architecture-aarch64-abi-2018q4
*** bfd/ChangeLog ***
2019-03-13 Sudakshina Das <sudi.das@arm.com>
* elf-properties.c (_bfd_elf_link_setup_gnu_properties): Exclude
linker created inputs from merge.
* elfnn-aarch64.c (struct elf_aarch64_obj_tdata): Add field for
GNU_PROPERTY_AARCH64_FEATURE_1_AND properties.
(elfNN_aarch64_link_setup_gnu_properties): New.
(elfNN_aarch64_merge_gnu_properties): New.
(elf_backend_setup_gnu_properties): Define for AArch64.
(elf_backend_merge_gnu_properties): Likewise.
* elfxx-aarch64.c (_bfd_aarch64_elf_link_setup_gnu_properties): Define.
(_bfd_aarch64_elf_parse_gnu_properties): Define.
(_bfd_aarch64_elf_merge_gnu_properties): Define.
* elfxx-aarch64.h (_bfd_aarch64_elf_link_setup_gnu_properties): Declare.
(_bfd_aarch64_elf_parse_gnu_properties): Declare.
(_bfd_aarch64_elf_merge_gnu_properties): Declare.
(elf_backend_parse_gnu_properties): Define for AArch64.
*** binutils/ChangeLog ***
2019-03-13 Sudakshina Das <sudi.das@arm.com>
* readelf.c (decode_aarch64_feature_1_and): New.
(print_gnu_property_note): Add case for AArch64 gnu notes.
*** include/ChangeLog ***
2019-03-13 Sudakshina Das <sudi.das@arm.com>
* elf/common.h (GNU_PROPERTY_AARCH64_FEATURE_1_AND): New.
(GNU_PROPERTY_AARCH64_FEATURE_1_BTI): New.
(GNU_PROPERTY_AARCH64_FEATURE_1_PAC): New.
*** ld/ChangeLog ***
2019-03-13 Sudakshina Das <sudi.das@arm.com>
* NEWS: Document GNU_PROPERTY_AARCH64_FEATURE_1_BTI and
GNU_PROPERTY_AARCH64_FEATURE_1_PAC.
* testsuite/ld-aarch64/aarch64-elf.exp: Add run commands for new tests.
* testsuite/ld-aarch64/property-bti-pac1.d: New test.
* testsuite/ld-aarch64/property-bti-pac1.s: New test.
* testsuite/ld-aarch64/property-bti-pac2.d: New test.
* testsuite/ld-aarch64/property-bti-pac2.s: New test.
* testsuite/ld-aarch64/property-bti-pac3.d: New test.
There should be no AND properties if some input doesn't have them. We
should set IBT and SHSTK properties for -z ibt and -z shstk if needed.
bfd/
PR ld/24322
* elfxx-x86.c (_bfd_x86_elf_merge_gnu_properties): Properly
merge GNU_PROPERTY_X86_FEATURE_1_[IBT|SHSTK].
ld/
PR ld/24322
* testsuite/ld-i386/i386.exp: Run PR ld/24322 tests.
* testsuite/ld-x86-64/x86-64.exp: Likewise.
* testsuite/ld-i386/pr24322a.d: New file.
* testsuite/ld-i386/pr24322b.d: Likewise.
* testsuite/ld-x86-64/pr24322a-x32.d: Likewise.
* testsuite/ld-x86-64/pr24322a.d: Likewise.
* testsuite/ld-x86-64/pr24322b-x32.d: Likewise.
* testsuite/ld-x86-64/pr24322b.d: Likewise.
* testsuite/ld-x86-64/pr24322a.s: Likewise.
* testsuite/ld-x86-64/pr24322b.s: Likewise.
* testsuite/ld-x86-64/pr24322c.s: Likewise.
Compressed debug sections can have uncompressed sizes that exceed the
original file size, so we can't use bfd_get_file_size. objdump also
used bfd_get_file_size to limit reloc section size, but I believe the
underlying bug causing the PR22508 out of bounds buffer access was
that we had an integer overflow when calculating the reloc buffer
size. I've fixed that instead in most of the backends, som and
vms-alpha being the exceptions. SOM and vmd-alpha have rather more
serious bugs in their slurp_relocs routines that would need fixing
first if we want to fuss about making them safe against fuzzed object
files.
The patch also fixes a number of other potential overflows by using
the bfd_alloc2/malloc2/zalloc2 memory allocation functions.
bfd/
* coffcode.h (buy_and_read): Delete unnecessary forward decl. Add
nmemb parameter. Use bfd_alloc2.
(coff_slurp_line_table): Use bfd_alloc2. Update buy_and_read calls.
Delete assertion.
(coff_slurp_symbol_table): Use bfd_alloc2 and bfd_zalloc2.
(coff_slurp_reloc_table): Use bfd_alloc2. Update buy_and_read calls.
* coffgen.c (coff_get_reloc_upper_bound): Ensure size calculation
doesn't overflow.
* elf.c (bfd_section_from_shdr): Use bfd_zalloc2. Style fix.
(assign_section_numbers): Style fix.
(swap_out_syms): Use bfd_malloc2.
(_bfd_elf_get_reloc_upper_bound): Ensure size calculation doesn't
overflow.
(_bfd_elf_make_empty_symbol): Style fix.
(elfobj_grok_stapsdt_note_1): Formatting.
* elfcode.h (elf_object_p): Use bfd_alloc2.
(elf_write_relocs, elf_write_shdrs_and_ehdr): Likewise.
(elf_slurp_symbol_table): Use bfd_zalloc2.
(elf_slurp_reloc_table): Use bfd_alloc2.
(_bfd_elf_bfd_from_remote_memory): Use bfd_malloc2.
* elf64-sparc (elf64_sparc_get_reloc_upper_bound): Ensure
size calculation doesn't overflow.
(elf64_sparc_get_dynamic_reloc_upper_bound): Likewise.
* mach-o.c (bfd_mach_o_get_reloc_upper_bound): Likewise.
* pdp11.c (get_reloc_upper_bound): Copy aoutx.h version.
binutils/
* objdump.c (load_specific_debug_section): Don't compare section
size against file size.
(dump_relocs_in_section): Don't compare reloc size against file size.
Print "failed to read relocs" on bfd_get_reloc_upper_bound error.
Not padding string merge section output to its alignment can cause
failures of the S-record tests when input string merge sections are
padded, since the ELF linker output for the single string section
would shrink compared to the SREC linker output. That might result in
following sections having different addresses.
On the other hand, padding string merge section output when input
string merge sections are *not* padded can also cause failures, in
this case due to the ELF linker output for the string section being
larger (due to padding) than the SREC linker output.
It would be better to write a more robust test, but it is also nice
to leave input unchanged when no string merges occur.
PR 24311
* merge.c (merge_strings): Return secinfo. Don't pad section
to alignment here.
(_bfd_merge_sections): Pad section to alignment here, if input
sections contributing to merged output all pad to alignment.
Formatting.
* dwarf2.c (_bfd_dwarf2_find_symbol_bias): Check for a NULL symbol
table pointer.
* coffgen.c (coff_find_nearest_line_with_names): Do not call
_bfd_dwarf2_find_symbol_bias if there is no symbol table available.
https://bugzilla.redhat.com/show_bug.cgi?id=1685727
According to the specification for the CIE entries, when the CIE version is 1 then
the return address register field is always 1 byte. Readelf does this correctly in
read_cie in dwarf.c but ld does this incorrectly and always tries to read a
skip_leb128. If the value here has the top bit set then ld will incorrectly read
at least another byte, causing either an assert failure or an incorrect address to
be used in eh_frame.
I'm not sure how to generate a generic test for this as I'd need to write assembly,
and it's a bit hard to trigger. Essentially the relocated value needs to start with
something that & 0x70 != 0x10 while trying to write a personality.
bfd/ChangeLog:
* elf-eh-frame.c (_bfd_elf_write_section_eh_frame): Correct CIE parse.
The fix here is to use an unsigned comparison for
if (a->NumberOfRvaAndSizes > IMAGE_NUMBEROF_DIRECTORY_ENTRIES)
include/
PR 24272
* coff/internal.h (struct internal_extra_pe_aouthdr): Change type
of SizeOfCode, SizeOfInitializedData, and SizeOfUninitializedData
to bfd_vma. Change type of SectionAlignment, FileAlignment,
Reserved1, SizeOfImage, SizeOfHeaders, CheckSum, LoaderFlags,
and NumberOfRvaAndSizes to uint32_t.
bfd/
PR 24272
* peXXigen.c (_bfd_XXi_swap_aouthdr_in): Use unsigned index.
(_bfd_XX_print_private_bfd_data_common): Adjust for type changes.
Skip symbol defined by linker when checking copy reloc on protected
symbol.
bfd/
PR ld/24276
* elf64-x86-64.c (elf_x86_64_check_relocs): Skip symbol defined
by linker when checking copy reloc on protected symbol.
ld/
PR ld/24276
* testsuite/ld-i386/i386.exp: Run PR ld/24276 test.
* testsuite/ld-x86-64/x86-64.exp: Likewise.
* testsuite/ld-i386/pr24276.dso: New file.
* testsuite/ld-i386/pr24276.warn: Likewise.
* testsuite/ld-x86-64/pr24276.dso: Likewise.
* testsuite/ld-x86-64/pr24276.warn: Likewise.
Big section alignment requirements between source and destination of a
long call can result in making call range bigger than what's reachable
by the call opcode. Add biggest section alignment of sections between
the call site and call destination to the call distance when making
long call relaxation decision.
2019-02-20 Eric Tsai <erictsai@cadence.com>
bfd/
* elf32-xtensa.c (is_resolvable_asm_expansion): Scan output
sections between the call site and call destination and adjust
call distance by the largest alignment.
ld/
* testsuite/ld-xtensa/call_overflow.d: New test definition.
* testsuite/ld-xtensa/call_overflow1.s: New test source.
* testsuite/ld-xtensa/call_overflow2.s: New test source.
* testsuite/ld-xtensa/call_overflow3.s: New test source.
* testsuite/ld-xtensa/xtensa.exp: Add call_overflow test.
Used for the AArch64 pointer authentication code mask registers in Arm v8.3-a.
NT_ARM_PAC_MASK matches the value in Linux include/uapi/linux/elf.h
include/ChangeLog:
* elf/common.h (NT_ARM_PAC_MASK): Add define.
bfd/ChangeLog:
* elf-bfd.h (elfcore_write_aarch_pauth): Add declaration.
* elf.c (elfcore_grok_aarch_pauth): New function.
(elfcore_grok_note): Check for NT_ARM_PAC_MASK.
(elfcore_write_aarch_pauth): New function.
(elfcore_write_register_note): Check for AArch64 pauth section.
git a31b8bd9a0 introduced a warning (depending on your system
headers).
PR 24225
* elf32-nios2.c (nios2_elf32_relocate_section): Check asprintf
return value.
PR 24236
* archive64.c (_bfd_archive_64_bit_slurp_armap): Move code adding
sentinel NUL to string buffer nearer to loop where it is used.
Don't go past sentinel when scanning strings, and don't write
NUL again.
* archive.c (do_slurp_coff_armap): Simplify string handling to
archive64.c style.
Recent gcc commit b4371b277f1e ("[ARC] Enable init_array support")
inhibits DT_"INIT,FINI} in favor of DT_{INIT,FINI}ARRAY.
Even prior to that, it seems ARC port is the only one with this
special DT_INIT/FINI handling in linker emulation. Removing it
doesn't seem to change any uClibc/glibc testsuite results,
so this can RIP anyways.
bfd/
2019-02-01 Vineet Gupta <vgupta@synopsys.com>
* elf32-arc.c: Delete init_str, fini_str
ld/
2019-02-01 Vineet Gupta <vgupta@synopsys.com>
* emultempl/arclinux.em : Delete special INIT/FINI handling.
This was always supposed to be an error. Code emitted by gcc for
inline PLT calls assumes PLT is an array of addresses.
* elf32-ppc.c (ppc_elf_relocate_section): Add %X to "unsupported
for bss-plt" warning to make it an error.
This fixes the last ld failures on SPARC64/Linux:
FAIL: Run pr18841 with libpr18841b.so
FAIL: Run pr18841 with libpr18841c.so
FAIL: Run pr18841 with libpr18841bn.so (-z now)
FAIL: Run pr18841 with libpr18841cn.so (-z now)
by mimicing what has been done on x86-64 and Aarch64 to fix the PR.
bfd/
PR ld/18841
* elf32-sparc.c (elf32_sparc_reloc_type_class): Return
reloc_class_ifunc for ifunc symbols.
* elf64-sparc.c (elf64_sparc_reloc_type_class): Likewise.
bfd * config.bfd: Move the powerpc-lynxos and powerpc-windiss targets
into the definitely obsolete list.
binutils * README-how-to-make-a-release: Add a note about updating the
obsolete targets in the bfd/config.bfd file.
commit bd7ab16b45
Author: H.J. Lu <hjl.tools@gmail.com>
Date: Tue Feb 13 07:34:22 2018 -0800
x86-64: Generate branch with PLT32 relocation
removed check R_X86_64_PC32 relocation against protected symbols in
shared objects. Since elf_x86_64_check_relocs is called after we
have seen all input files, we can check for PC-relative relocations in
elf_x86_64_check_relocs. We should not allow PC-relative relocations
against protected symbols since address of protected function and
location of protected data may not be in the shared object.
bfd/
PR ld/24151
* elf64-x86-64.c (elf_x86_64_need_pic): Check
SYMBOL_DEFINED_NON_SHARED_P instead of def_regular.
(elf_x86_64_relocate_section): Move PIC check for PC-relative
relocations to ...
(elf_x86_64_check_relocs): Here.
(elf_x86_64_finish_dynamic_symbol): Use SYMBOL_DEFINED_NON_SHARED_P
to check if a symbol is defined in a non-shared object.
* elfxx-x86.h (SYMBOL_DEFINED_NON_SHARED_P): New.
ld/
PR ld/24151
* testsuite/ld-x86-64/pr24151a-x32.d: New file.
* testsuite/ld-x86-64/pr24151a.d: Likewise.
* testsuite/ld-x86-64/pr24151a.s: Likewise.
* testsuite/ld-x86-64/x86-64.exp: Run pr24151a and pr24151a-x32.
Fedora Rawhide has just switched to GCC9, and now GDB doesn't compile
because of a BFD warning:
BUILDSTDERR: ../../bfd/elf32-arm.c: In function 'elf32_arm_final_link_relocate':
BUILDSTDERR: ../../bfd/elf32-arm.c:10907:10: error: absolute value function 'labs' given an argument of type 'bfd_signed_vma' {aka 'long long int'} but has parameter of type 'long int' which may cause truncation of value [-Werror=absolute-value]
BUILDSTDERR: 10907 | value = labs (relocation);
BUILDSTDERR: | ^~~~
You can take a look at the full build log here:
https://kojipkgs.fedoraproject.org//work/tasks/4828/32174828/build.log
The fix is (apparently) simple: instead of using 'labs', we should use
'llabs', since we're passing a 'bfd_signed_vma' to it, which is at
least a 'long long int', as far as I have checked. This is what this
patch does.
bfd/ChangeLog:
2019-01-25 Sergio Durigan Junior <sergiodj@redhat.com>
* elf32-arm.c (elf32_arm_final_link_relocate): Use 'llabs' instead
of 'labs' (and fix GCC warning).