I get the following error with gcc 6.3.0:
/home/simark/src/binutils-gdb/gdb/dwarf2read.c: In function 'void read_func_scope(die_info*, dwarf2_cu*)':
/home/simark/src/binutils-gdb/gdb/dwarf2read.c:13838:12: error: types may not be defined in a for-range-declaration [-Werror]
for (struct symbol *sym : template_args)
^~~~~~
Removing the struct keyword fixes it.
gdb/ChangeLog:
* dwarf2read.c (read_func_scope): Remove struct keyword in
range-based for.
This adds --enable-ubsan to gdb's configure. By default it is enabled
in development mode, and disabled otherwise. This passes both
-fsanitize=undefined and -fno-sanitize-recover=undefined to
compilations, so that undefined behavior violations will be sure to
cause test failures.
gdb/ChangeLog
2018-10-03 Tom Tromey <tom@tromey.com>
* README: Mention --enable-ubsan.
* NEWS: Mention --enable-ubsan.
* acinclude.m4: Include sanitize.m4.
* configure: Rebuild.
* configure.ac: Call AM_GDB_UBSAN.
* sanitize.m4: New file.
gdb/doc/ChangeLog
2018-10-03 Tom Tromey <tom@tromey.com>
* gdb.texinfo (Configure Options): Document --enable-ubsan.
-fsanitize=undefined pointed out undefined behavior in
dump_raw_expression like:
runtime error: load of value 2887952, which is not a valid value for type 'exp_opcode'
dump_raw_expression will try to print the opcode for each element of
the expression, even when it is not valid. To allow this, but have it
avoid undefined behavior, this patch sets the underlying type of enum
exp_opcode, and arranges for op_name to handle invalid opcodes more
nicely.
Before this patch, debug-expr.exp shows:
Dump of expression @ 0x60f000007750, before conversion to prefix form:
Language c, 8 elements, 16 bytes each.
Index Opcode Hex Value String Value
0 OP_TYPE 89 Y...............
<unknown 3851920> 107820862850704 ..:..b..........
2 OP_TYPE 89 Y...............
3 OP_VAR_VALUE 40 (...............
4 <unknown 2807568> 107820861806352 ..*..b..........
5 <unknown 2806368> 107820861805152 `.*..b..........
6 OP_VAR_VALUE 40 (...............
7 UNOP_MEMVAL_TYPE 57 9...............
Afterward, the output is:
Dump of expression @ 0x4820f90, before conversion to prefix form:
Language c, 8 elements, 16 bytes each.
Index Opcode Hex Value String Value
0 OP_TYPE 89 Y...............
1 unknown opcode: 176 75444400 .0..............
2 OP_TYPE 89 Y...............
3 OP_VAR_VALUE 40 (...............
4 OP_BOOL 74616912 P.r.............
5 unknown opcode: 128 74615680 ..r.............
6 OP_VAR_VALUE 40 (...............
7 UNOP_MEMVAL_TYPE 57 9...............
gdb/ChangeLog
2018-10-03 Tom Tromey <tom@tromey.com>
* expression.h (enum exp_opcode): Use uint8_t as base type.
* expprint.c (op_name): Handle invalid opcodes.
-fsanitize=undefined pointed out this error:
runtime error: load of value 2887952, which is not a valid value for type 'exp_opcode'
This happens in gdb.ada/complete.exp when processing "complete p
my_glob". This does not parse, so the Ada parser throws an exception;
but then the code in parse_exp_in_context_1 accepts the expression
anyway. However, as no elements have been written to the expression,
undefined behavior results.
The fix is to notice this case in parse_exp_in_context_1. This patch
also adds an assertion to prefixify_expression to enforce this
pre-existing constraint.
gdb/ChangeLog
2018-10-03 Tom Tromey <tom@tromey.com>
* parse.c (prefixify_expression): Add assert.
(parse_exp_in_context_1): Throw exception if the expression is
empty.
-fsanitize=undefined pointed out that read_signed_leb128 had an
undefined left-shift when processing the final byte of a 64-bit leb:
runtime error: left shift of 127 by 63 places cannot be represented in type 'long int'
and an undefined negation:
runtime error: negation of -9223372036854775808 cannot be represented in type 'long int'; cast to an unsigned type to negate this value to itself
Both of these problems are readily avoided by havinng
read_signed_leb128 work in an unsigned type, and then casting to the
signed type at the return.
gdb/ChangeLog
2018-10-03 Tom Tromey <tom@tromey.com>
* dwarf2read.c (read_signed_leb128): Work in ULONGEST.
-fsanitize=undefined pointed out that c-exp.y relied on undefined
behavior here:
if (c != 'l' && c != 'u')
n *= base;
...when a large hex constant "just fit" into a LONGEST, causing the
high bit to be set.
This fixes the problem by having the function work in an unsigned
type.
gdb/ChangeLog
2018-10-03 Tom Tromey <tom@tromey.com>
* c-exp.y (parse_number): Work in unsigned. Remove casts.
-fsanitize=undefined pointed out an undefined shift of a negative
value in read_subrange_type. The fix is to do the work in an unsigned
type, where this is defined.
gdb/ChangeLog
2018-10-03 Tom Tromey <tom@tromey.com>
* dwarf2read.c (read_subrange_type): Make "negative_mask"
unsigned.
-fsanitize=undefined showed that extract_integer could left-shift a
negative value, which is undefined. This patch fixes the problem by
doing all the work in an unsigned type. This relies on
implementation-defined behavior, but I tend to think we are on safe
ground there. (Also, if need be, violations of this could probably be
detected, either by configure or by a static_assert.)
gdb/ChangeLog
2018-10-03 Tom Tromey <tom@tromey.com>
* findvar.c (extract_integer): Do work in an unsigned type.
-fsanitize=undefined complains about using operator~ on various enum
types that are used with DEF_ENUM_FLAGS_TYPE. This patch fixes these
problems by explicitly setting the base type for these enums to
unsigned. It also adds a static assert to enum_flags to ensure that
future enums used this way have an unsigned underlying type.
gdb/ChangeLog
2018-10-03 Tom Tromey <tom@tromey.com>
* common/enum-flags.h (enum_flags::operator~): Add static assert.
* symfile-add-flags.h (enum symfile_add_flag): Use unsigned as
base type.
* objfile-flags.h (enum objfile_flag): Use unsigned as base type.
* gdbtypes.h (enum type_instance_flag_value): Use unsigned as base
type.
* c-lang.h (enum c_string_type_values): Use unsigned as base
type.
* btrace.h (enum btrace_thread_flag): Use unsigned as base type.
This changes dwarf2_frame_state_reg_info::reg to be a std::vector.
This avoids passing NULL to memcpy in the copy constructor when the
original object does not have any registers.
gdb/ChangeLog
2018-10-03 Tom Tromey <tom@tromey.com>
* dwarf2-frame.h (dwarf2_frame_state_reg_info)
<~dwarf2_frame_state_reg_info>: Update.
<dwarf2_frame_state_reg_info>: Update.
<alloc_regs>: Add assertion. Update.
<reg>: Now a std::vector.
<num_regs>: Remove.
<swap>: Update.
* dwarf2-frame.c (dwarf2_restore_rule, execute_cfa_program)
(execute_cfa_program_test, dwarf2_frame_cache): Update.
-fsanitize=undefined pointed out a spot that passes NULL to memcpy,
which is undefined behavior according to the C standard.
gdb/ChangeLog
2018-10-03 Tom Tromey <tom@tromey.com>
* namespace.c (add_using_directive): Don't pass NULL to memcpy.
Add testcases to verify that all SHT_NOTE sections with the same section
alignment are placed in a single PT_NOTE segment.
PR ld/23658
* testsuite/ld-elf/pr23658-1.d: New file.
* testsuite/ld-elf/pr23658-1a.s: Likewise.
* testsuite/ld-elf/pr23658-1b.s: Likewise.
* testsuite/ld-elf/pr23658-1c.s: Likewise.
* testsuite/ld-elf/pr23658-1d.s: Likewise.
* testsuite/ld-elf/pr23658-2.rd: Likewise.
* testsuite/ld-elf/pr23658-3.d: Likewise.
* testsuite/ld-elf/pr23658-3.s: Likewise.
* testsuite/ld-elf/pr23658-3.t: Likewise.
* testsuite/ld-elf/shared.exp: Run PR ld/23658 tests.
To support putting all adjacent SHT_NOTE sections with the same section
alignment into a single PT_NOTE segment, lang_insert_orphan must group
and sort output note sections by section alignments in both output
section list as well as output section statement list.
PR ld/23658
* ldlang.c (lang_insert_orphan): Group and sort output note
sections by section alignments.
Alignments of SHT_NOTE sections can be 8 bytes for 64-bit ELF files. We
should put all adjacent SHT_NOTE sections with the same section alignment
into a single PT_NOTE segment even when the section alignment != 4 bytes.
Also check SHT_NOTE section type instead of section name.
PR ld/23658
* elf.c (get_program_header_size): Put all adjacent SHT_NOTE
sections with the same section alignment into a single PT_NOTE
segment. Check SHT_NOTE section type instead of section name.
(_bfd_elf_map_sections_to_segments): Likewise.
This patch adds the tests and expected output for each of the conditions where
the MOVPRFX constraint should apply.
The specific test cases are all documented to indicate what the expected
behavior should be.
gas/
* testsuite/gas/aarch64/sve-movprfx_1.d: New test.
* testsuite/gas/aarch64/sve-movprfx_1.s: New test.
* testsuite/gas/aarch64/sve-movprfx_10.d: New test.
* testsuite/gas/aarch64/sve-movprfx_10.l: New test.
* testsuite/gas/aarch64/sve-movprfx_10.s: New test.
* testsuite/gas/aarch64/sve-movprfx_11.d: New test.
* testsuite/gas/aarch64/sve-movprfx_11.s: New test.
* testsuite/gas/aarch64/sve-movprfx_12.d: New test.
* testsuite/gas/aarch64/sve-movprfx_12.s: New test.
* testsuite/gas/aarch64/sve-movprfx_13.d: New test.
* testsuite/gas/aarch64/sve-movprfx_13.l: New test.
* testsuite/gas/aarch64/sve-movprfx_13.s: New test.
* testsuite/gas/aarch64/sve-movprfx_14.d: New test.
* testsuite/gas/aarch64/sve-movprfx_14.l: New test.
* testsuite/gas/aarch64/sve-movprfx_14.s: New test.
* testsuite/gas/aarch64/sve-movprfx_15.d: New test.
* testsuite/gas/aarch64/sve-movprfx_15.l: New test.
* testsuite/gas/aarch64/sve-movprfx_15.s: New test.
* testsuite/gas/aarch64/sve-movprfx_16.d: New test.
* testsuite/gas/aarch64/sve-movprfx_16.s: New test.
* testsuite/gas/aarch64/sve-movprfx_17.d: New test.
* testsuite/gas/aarch64/sve-movprfx_17.l: New test.
* testsuite/gas/aarch64/sve-movprfx_17.s: New test.
* testsuite/gas/aarch64/sve-movprfx_18.d: New test.
* testsuite/gas/aarch64/sve-movprfx_18.l: New test.
* testsuite/gas/aarch64/sve-movprfx_18.s: New test.
* testsuite/gas/aarch64/sve-movprfx_19.d: New test.
* testsuite/gas/aarch64/sve-movprfx_19.s: New test.
* testsuite/gas/aarch64/sve-movprfx_2.d: New test.
* testsuite/gas/aarch64/sve-movprfx_2.l: New test.
* testsuite/gas/aarch64/sve-movprfx_2.s: New test.
* testsuite/gas/aarch64/sve-movprfx_20.d: New test.
* testsuite/gas/aarch64/sve-movprfx_20.l: New test.
* testsuite/gas/aarch64/sve-movprfx_20.s: New test.
* testsuite/gas/aarch64/sve-movprfx_21.d: New test.
* testsuite/gas/aarch64/sve-movprfx_21.s: New test.
* testsuite/gas/aarch64/sve-movprfx_22.d: New test.
* testsuite/gas/aarch64/sve-movprfx_22.l: New test.
* testsuite/gas/aarch64/sve-movprfx_22.s: New test.
* testsuite/gas/aarch64/sve-movprfx_23.d: New test.
* testsuite/gas/aarch64/sve-movprfx_23.l: New test.
* testsuite/gas/aarch64/sve-movprfx_23.s: New test.
* testsuite/gas/aarch64/sve-movprfx_24.d: New test.
* testsuite/gas/aarch64/sve-movprfx_24.l: New test.
* testsuite/gas/aarch64/sve-movprfx_24.s: New test.
* testsuite/gas/aarch64/sve-movprfx_25.d: New test.
* testsuite/gas/aarch64/sve-movprfx_25.l: New test.
* testsuite/gas/aarch64/sve-movprfx_25.s: New test.
* testsuite/gas/aarch64/sve-movprfx_26.d: New test.
* testsuite/gas/aarch64/sve-movprfx_26.l: New test.
* testsuite/gas/aarch64/sve-movprfx_26.s: New test.
* testsuite/gas/aarch64/sve-movprfx_3.d: New test.
* testsuite/gas/aarch64/sve-movprfx_3.l: New test.
* testsuite/gas/aarch64/sve-movprfx_3.s: New test.
* testsuite/gas/aarch64/sve-movprfx_4.d: New test.
* testsuite/gas/aarch64/sve-movprfx_4.l: New test.
* testsuite/gas/aarch64/sve-movprfx_4.s: New test.
* testsuite/gas/aarch64/sve-movprfx_5.d: New test.
* testsuite/gas/aarch64/sve-movprfx_5.s: New test.
* testsuite/gas/aarch64/sve-movprfx_6.d: New test.
* testsuite/gas/aarch64/sve-movprfx_6.l: New test.
* testsuite/gas/aarch64/sve-movprfx_6.s: New test.
* testsuite/gas/aarch64/sve-movprfx_7.d: New test.
* testsuite/gas/aarch64/sve-movprfx_7.l: New test.
* testsuite/gas/aarch64/sve-movprfx_7.s: New test.
* testsuite/gas/aarch64/sve-movprfx_8.d: New test.
* testsuite/gas/aarch64/sve-movprfx_8.l: New test.
* testsuite/gas/aarch64/sve-movprfx_8.s: New test.
* testsuite/gas/aarch64/sve-movprfx_9.d: New test.
* testsuite/gas/aarch64/sve-movprfx_9.l: New test.
* testsuite/gas/aarch64/sve-movprfx_9.s: New test.
This patch wires in the new constraint verifiers into the assembler and
disassembler. Because of this the MOVPRFX tests have to be split out from the
generic SVE tests into their own tests so warnings can be ignored.
These tests are only intended to test the encoding correctness and not the
constraints.
gas/
* testsuite/gas/aarch64/sve-movprfx.d: New test.
* testsuite/gas/aarch64/sve-movprfx.s: New test.
* testsuite/gas/aarch64/sve.d: Refactor.
* testsuite/gas/aarch64/sve.s: Refactor.
* testsuite/gas/aarch64/sysreg-diagnostic.d: Update.
opcodes/
* aarch64-asm.c (aarch64_opcode_encode): Apply constraint verifier.
* aarch64-dis.c (print_operands): Refactor to take notes.
(print_verifier_notes): New.
(print_aarch64_insn): Apply constraint verifier.
(print_insn_aarch64_word): Update call to print_aarch64_insn.
* aarch64-opc.c (aarch64_print_operand): Remove attribute, update notes format.
Any open sequence at the end of a section or assembly is considered an error.
This patch adds a check at the end to ensure that all sequences have been closed
and if not reports a warning.
During disassembly it's not possible to detect this condition in the back-end so
the warning is only emitted from the assembler for now.
gas/
* config/tc-aarch64.c (force_automatic_sequence_close,
aarch64_frob_section): New.
* config/tc-aarch64.h (tc_frob_section, aarch64_frob_section): New.
This patch adds the verification rules for move prefix constraints.
The Arm SVE instruction MOVPRFX introduces[1] constraints on the instruction at
PC+4. Particularly the following constraints are handled by this patch
* MOVPRFX must be followed by an instruction.
* MOVPRFX can only be followed by non-layout altering directives.
* MOVPRFX destination register MUST be used as the destination register in the
instruction at PC+4, and is not allowed to be used in any other position other than
destructive input. This includes registers that architecturally overlap. e.g. x1
should be treated as z1.
* MOVPRFX must be followed by a restricted set of SVE instructions.
* The size of the destination register of MOVPRFX must be equal to that of
the operation at PC+4.
* The predicate register and operation of MOVPRFX must match that of the instruction
at PC+4
* The predicated instruction at PC+4 must use the merging predicate.
* Architectural aliases and pseudo-instructions need to be supported as well.
* MOVPRFX cannot be the last instruction in a sequence
Any failure to adhere to any of these constrains will emit an assembly warning
and a disassembly note.
[1] https://developer.arm.com/docs/ddi0584/latest/arm-architecture-reference-manual-supplement-the-scalable-vector-extension-sve-for-armv8-a
include/
* opcode/aarch64.h (aarch64_inst): Remove.
(enum err_type): Add ERR_VFI.
(aarch64_is_destructive_by_operands): New.
(init_insn_sequence): New.
(aarch64_decode_insn): Remove param name.
opcodes/
* aarch64-opc.c (init_insn_block): New.
(verify_constraints, aarch64_is_destructive_by_operands): New.
* aarch64-opc.h (verify_constraints): New.
gas/
* config/tc-aarch64.c (output_operand_error_report): Order warnings.
The current verifiers only take an instruction description and encoded value as
arguments. This was enough when the verifiers only needed to do simple checking
but it's insufficient for the purposes of validating instruction sequences.
This patch adds the required arguments and also a flag to allow a verifier to
distinguish between whether it's being run during encoding or decoding. It also
allows for errors and warnings to be returned by a verifier instead of a simple
pass/fail.
include/
* opcode/aarch64.h (struct aarch64_opcode): Expand verifiers to take
more arguments.
opcodes/
* aarch64-dis.c (aarch64_opcode_decode): Update verifier call.
* aarch64-opc.c (verify_ldpsw): Update arguments.
Previously the ERR_ values were defined as different constants, to make this a
bit more type safe and so they can be more easily re-used I'm changing them into
an actual enum and updating any usages.
include/
* opcode/aarch64.h (enum err_type): New.
(aarch64_decode_insn): Use it.
opcodes/
* aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove.
(aarch64_decode_insn, print_insn_aarch64_word): Use err_type.
This patch introduces aarch64_instr_sequence which is a structure similar to IT
blocks on Arm in order to track instructions that introduce a constraint or
dependency on instruction 1..N positions away from the instruction that opened
the block.
The struct is also wired through to the locations that require it.
gas/
* config/tc-aarch64.c (now_instr_sequence):
(*insn_sequence, now_instr_sequence): New.
(output_operand_error_record, do_encode): Add insn_sequence.
(md_assemble): Update insn_sequence.
(try_to_encode_as_unscaled_ldst, fix_mov_imm_insn, fix_insn):
Pass insn_sequence.
* config/tc-aarch64.h (struct aarch64_segment_info_type):
Add insn_sequence.
include/
* opcode/aarch64.h (struct aarch64_instr_sequence): New.
(aarch64_opcode_encode): Use it.
opcodes/
* aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
* aarch64-dis.c (insn_sequence): New.
This patch series is to allow certain instructions such as the SVE MOVPRFX
instruction to apply a constraint/dependency on the instruction at PC+4.
This patch starts this off by marking which instructions impose the constraint
and which instructions must adhere to the constraint. This is done in a
generic way by extending the verifiers.
* The constraint F_SCAN indicates that an instruction opens a sequence and imposes
a constraint on an instructions following it. The length of the sequence depends
on the instruction itself and it handled in the verifier code.
* The C_SCAN_MOVPRFX flag is used to indicate which constrain the instruction is
checked against. An instruction with both F_SCAN and C_SCAN_MOVPRFX starts a
block for the C_SCAN_MOVPRFX instruction, and one with only C_SCAN_MOVPRFX must
adhere to a previous block constraint is applicable.
The SVE instructions in this list have been marked according to the SVE
specification[1].
[1] https://developer.arm.com/docs/ddi0584/latest/arm-architecture-reference-manual-supplement-the-scalable-vector-extension-sve-for-armv8-a
include/
* opcode/aarch64.h (struct aarch64_opcode): Add constraints,
extend flags field size.
(F_SCAN, C_SCAN_MOVPRFX, C_MAX_ELEM): New.
opcodes/
* aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
_LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
_SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
constraints.
(_SVE_INSNC): New.
(struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
constraints.
(movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
F_SCAN flags.
(msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
I tried a build on macOS today and it failed due to a mismatch between
the printf format and the type in aarch64-linux-tdep.c. This patch
fixes the problem by using pulongest and %s rather than %ld.
gdb/ChangeLog
2018-10-02 Tom Tromey <tom@tromey.com>
* aarch64-linux-tdep.c (aarch64_linux_sigframe_init): Use pulongest.
The RISC-V memory model has been ratified, and it includes an additional
fence: "fence.tso". This pseudo instruction extends one of the
previously reserved full fence patterns to be less restrictive, and
therefor will execute correctly on all existing microarchitectures.
Thus there is no reason to allow this instruction to be disabled (or
unconverted to a full fence), so it's just unconditionally allowed.
I've added a test case for GAS to check that "fence.tso" correctly
assembles on rv32i-based targets. I checked to see that "fence.tso"
appears in "gas.log", but that's the only testing I've done.
gas/ChangeLog
2018-10-02 Palmer Dabbelt <palmer@sifive.com>
* testsuite/gas/riscv/fence-tso.d: New file.
* testsuite/gas/riscv/fence-tso.s: Likewise.
include/ChangeLog
2018-10-02 Palmer Dabbelt <palmer@sifive.com>
* opcode/riscv-opc.h (MATCH_FENCE_TSO): New define.
(MASK_FENCE_TSO): Likewise.
opcodes/ChangeLog
2018-10-02 Palmer Dabbelt <palmer@sifive.com>
* riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
Extend the "target remote" and "target extended-remote" commands
such that if the filename provided is a Unix local domain (AF_UNIX)
socket, then it'll be treated as such, instead of trying to open
it as if it were a character device.
gdb/ChangeLog:
* NEWS: Mention changed commands.
* ser-uds.c: New file.
* configure.ac (SER_HARDWIRE): Add ser-uds.o.
* configure: Regenerate.
* Makefile.in: Add new file.
* serial.c (serial_open): Check if filename is a socket
and lookup the appropriate interface accordingly.
gdb/doc/ChangeLog:
* gdb.texinfo (Remote Connection Commands): Describe
the changes to target remote and target extended-remote
relating to Unix domain sockets.
As reported by Jan here:
https://sourceware.org/ml/gdb-patches/2018-09/msg00831.html
the check that sets the number of available registers is backwards.
gdb/testsuite/ChangeLog:
* gdb.arch/i386-avx512.exp: Fix setting of nr_regs based on
is_amd64_regs_target.
Add Aarch64 test to check register values of a previous frame
can be shown correctly across a signal.
gdb/testsuite/ChangeLog:
* gdb.arch/aarch64-sighandler-regs.c: New test.
* gdb.arch/aarch64-sighandler-regs.exp: New file.
* lib/gdb.exp (skip_aarch64_sve_tests): New proc.
Both the VFP and SVE registers may be contained within the reserved space of
the sigcontext and can be found by seraching for MAGIC values. Detect these
and add the registers (including pseudos) to the trad frame cache.
gdb/
* aarch64-linux-tdep.c (AARCH64_SIGCONTEXT_RESERVED_OFFSET): Add
define.
(AARCH64_EXTRA_MAGIC): Likewise.
(AARCH64_FPSIMD_MAGIC): Likewise.
(AARCH64_SVE_MAGIC): Likewise.
(AARCH64_EXTRA_DATAP_OFFSET): Likewise.
(AARCH64_FPSIMD_FPSR_OFFSET): Likewise.
(AARCH64_FPSIMD_FPCR_OFFSET): Likewise.
(AARCH64_FPSIMD_V0_OFFSET): Likewise.
(AARCH64_FPSIMD_VREG_SIZE): Likewise.
(AARCH64_SVE_CONTEXT_VL_OFFSET): Likewise.
(AARCH64_SVE_CONTEXT_REGS_OFFSET): Likewise.
(AARCH64_SVE_CONTEXT_P_REGS_OFFSET): Likewise.
(AARCH64_SVE_CONTEXT_FFR_OFFSET): Likewise.
(AARCH64_SVE_CONTEXT_SIZE): Likewise.
(read_aarch64_ctx): Add function.
(aarch64_linux_sigframe_init): Detect FP registers.
Inserted offset in final section in the GOT entry of type DTSOFF soon to be
relocated by the dynamic loader.
bfd/
2018-09-06 Cupertino Miranda <cmiranda@synopsys.com>
* arc-got.h (relocate_fix_got_relocs_for_got_info): Changed. Take TLS
section alignment in consideration for this relocation.
* elf32-arc.c (FINAL_SECTSTART): Added this formula macro.
(ARC_TLS_DTPOFF) Updated reloc to use new created macro instead.
A change upstream reveiled this issue, triggering an assert when linking glibc.
bfd/
2018-03-01 Cupertino Miranda <cmiranda@synopsys.com>
* elf32-arc.c (elf_arc_check_relocs): Changed.
Problem identified in the context of glibc with latest upstream binutils.
Dynamic symbol space was being reserved but, no actual information for the
symbol was being set. Data for the symbol was kept initialized with -1.
No easy test case was possible to be created.
bfd/
2018-03-01 Cupertino Miranda <cmiranda@synopsys.com>
* elf32-arc.c (elf_arc_check_relocs): Changed.
Change location where GOT information is collected for ARC target, avoiding
posible use conflicts of the previous .got field in the symbols hash_entry.
bfd/
2018-03-01 Cupertino Miranda <cmiranda@synopsys.com>
* arc-got.h (get_got_entry_list_for_symbol): Changed.
* ef32-arc.c (struct elf_arc_link_hash_entry): Moved and changed.
(elf_arc_link_hash_newfunc): Changed.
(arc_elf_link_hash_table_create): Removed old initializations.
(elf_arc_relocate_section, elf_arc_finish_dynamic_symbol): Changed.
This commit removes a workaround for a bug in glibc 2.1.3, which
was released 2000-02-24 and superseded 2000-11-09.
gdb/ChangeLog:
* gdb_proc_service.h (gdb_prfpregset_t): Remove typedef.
* proc-service.c (ps_lgetfpregs, ps_lsetfpregs): Use
prfpregset_t instead of gdb_prfpregset_t.
* configure.ac (PRFPREGSET_T_BROKEN): Remove check.
* configure, config.in: Rebuild.
This commit moves now-identical code from gdb/gdb_proc_service.h
and gdb/gdbserver/gdb_proc_service.h into the new shared file
gdb/common/gdb_proc_service.h.
gdb/ChangeLog:
* common/gdb_proc_service.h: New file, factored out from...
* gdb_proc_service.h: Moved common code to the above file.
* Makefile.in (HFILES_NO_SRCDIR): Add the above new file.
gdb/gdbserver/ChangeLog:
* gdb_proc_service.h: Moved common code to
common/gdb_proc_service.h.
This commit updates GDB's gdb_proc_service.h to use elf_{g,fp}regset_t
instead of gdb_{g,fp}regset_t if pr{g,fp}regset_t are undefined.
The types have been equivalent on GNU/Linux since at least 2005.
gdb/ChangeLog:
* gdb_proc_service.h: Use elf_gregset_t if prgregset_t is
undefined. Use elf_fpregset_t if prfpregset_t is undefined.
This commit adds a workaround from gdbserver's gdb_proc_service.h
to GDB's. It doesn't seem to have been needed on any glibc as far
back as 2001, but it's possibly required for other C libraries so
I've retained it.
gdb/ChangeLog:
* configure.ac: Check if sys/procfs.h defines elf_fpregset_t.
(AC_CHECK_HEADERS): Check for linux/elf.h.
* configure, config.in: Rebuild.
* gdb_proc_service.h: Include linux/elf.h if sys/procfs.h
doesn't define elf_fpregset_t.
GDB Administrator
Simon Marchi
Tom Tromey
H.J. Lu
Philippe Waroquiers
Tamar Christina
Sandra Loosemore
Millan Wolff
Nick Clifton
John Darrington
Palmer Dabbelt
Cupertino Miranda
Simon Marchi
Alan Hayward
Gary Benson