sim/aarch64/
* simulator.c (vec_load): Add M argument. Rewrite to iterate over
registers based on structure size.
(LD4, LD3, LD2, LD1_2, LD1_3, LD1_4): Pass new arg to vec_load.
(LD1_1): Replace with call to vec_load.
(vec_store): Add new M argument. Rewrite to iterate over registers
based on structure size.
(ST4, ST3, ST2, ST1_2, ST1_3, ST1_4): Pass new arg to vec_store.
(ST1_1): Replace with call to vec_store.
sim/testsuite/sim/aarch64/
* fcvtz.s, fstur.s, ldn_single.s, ldnr.s, mla.s, mls.s, uzp.s: Align
data.
* sumulh.s: Delete unnecessary data alignment.
* stn_single.s: Align data. Fix unaligned ldr insns. Adjust cmp
arguments to match change.
* ldn_multiple.s, stn_multiple.s: New.
sim/aarch64/
* simulator.c (set_flags_for_add32): Cast result to uint32_t in carry
flag check.
sim/testsuite/sim/aarch64/
* adds.s: Add checks for values -2 and 1, where C is not set.
sim/aarch64/
* simulator.c (mul64hi): Shift carry left by 32.
(smulh): Change signum to negate. If negate, invert result, and add
carry bit if low part of multiply result is zero.
sim/testsuite/sim/aarch64/
* sumov.s: Correct compare test values.
* sumulh.s: New.
sim/aarch64/
* simulator.c (do_vec_ADDV): Mov val declaration inside each case,
with type set to input type size.
(do_vec_xtl): Change bias from 3 to 4 for byte case.
sim/testsuite/sim/aarch64/
* bit.s: Change cmp immediates to account for addv bug fix.
* cmtst.s, ldn_single.s, stn_single.s: Likewise.
* xtl.s: New.
sim/aarch64/
* simulator.c (do_vec_bit): Change loop limits from 16 and 8 to 4 and
2. Move test_false if inside loop. Fix logic for computing result
stored to vd.
sim/testsuite/sim/aarch64
* bit.s: New.
sim/aarch64/
* simulator.c: (LDn_STn_SINGLE_LANE_AND_SIZE): New.
(do_vec_LDn_single, do_vec_STn_single): New.
(do_vec_LDnR): Add and set new nregs var. Replace switch on nregs with
loop over nregs using new var n. Add n times size to address in loop.
Add n to vd in loop.
(do_vec_load_store): Add comment for instruction bit 24. New var
single to hold instruction bit 24. Add new code to use single. Move
ldnr support inside single if statements. Fix ldnr register counts
inside post if statement. Change HALT_NYI calls to HALT_UNALLOC.
sim/testsuite/sim/aarch64/
* ldn_single.s: New.
* ldnr.s: New.
* stn_single.s: New.
sim/aarch64/
* simulator.c (do_vec_ADDV): Call aarch64_set_vec_u64 instead of
aarch64_set_reg_u64. In case 2, call HALT_UNALLOC if not full. In
case 3, call HALT_UNALLOC unconditionally.
(do_vec_XTN): Delete shifts. In case 2, change index from i + 4 to
i + 2. Delete if on bias, change index to i + bias * X.
sim/testsuite/sim/aarch64/
* addv.s: New.
* xtn.s: New.
sim/aarch64/
* cpustate.c: Include math.h.
(aarch64_set_FP_float): Use signbit to check for signed zero.
(aarch64_set_FP_double): Likewise.
* simulator.c (do_vec_MOV_immediate, case 0x8): Add missing break.
(do_vec_mul): In all DO_VEC_WIDENING_MUL calls, make second and fourth
args same size as third arg.
(fmaxnm): Use isnan instead of fpclassify.
(fminnm, dmaxnm, dminnm): Likewise.
(do_vec_MLS): Reverse order of subtraction operands.
(dexSimpleFPCondSelect): Call aarch64_get_FP_double or
aarch64_get_FP_float to get source register contents.
(UINT_MIN, ULONG_MIN, FLOAT_UINT_MAX, FLOAT_UINT_MIN,
DOUBLE_UINT_MAX, DOUBLE_UINT_MIN, FLOAT_ULONG_MAX, FLOAT_ULONG_MIN,
DOUBLE_ULONG_MAX, DOUBLE_ULONG_MIN): New.
(do_fcvtzu): Use ULONG instead of LONG, and UINT instead of INT in
raise_exception calls.
sim/testsuite/sim/aarch64/
* fcsel.s: New.
* fcvtz.s: New.
* fminnm.s: New.
* mls.s: New.
* mul.s: New.
This applies the second part of GDB's End of Year Procedure, which
updates the copyright year range in all of GDB's files.
gdb/ChangeLog:
Update copyright year range in all GDB files.
sim/aarch64
* simulator.c (NEG, POS): Move before set_flags_for_add64.
(set_flags_for_add64): Replace with a modified copy of
set_flags_for_sub64.
sim/testsuite/sim/aarch64
* testutils.inc (pass): Move .Lpass to start.
(fail): Move .Lfail to start. Return 1 instead of 0.
(start): Moved .Lpass and .Lfail to here.
* adds.s: New.
* fstur.s: New.
* tbnz.s: New.
The common sim tracing code already handles loading and tracking of
symbols from the target program so that it can show symbol info in
trace/disassembly calls. Once we touch up the trace code and add a
few API callbacks, ports don't need to do loading and searching of
symbol tables themselves anymore.
* simulator.c (aarch64_step): Revert pervious delta.
(aarch64_run): Call sim_events_tick after each
instruction is simulated, and if necessary call
sim_events_process.
* simulator.h: Revert previous delta.
* interp.c (sim_create_inferior): Allow for being called with a
NULL abfd parameter. If a bfd is provided, initialise the sim
with that start address.
* simulator.c (HALT_NYI): Just print out the numeric value of the
instruction when not tracing.
(aarch64_step): Change from static to global.
* simulator.h: Add a prototype for aarch64_step().
* cpustate.h: Include config.h.
(union GRegisterValue): Add WORDS_BIGENDIAN check. For big endian code
use anonymous structs to align members.
* simulator.c (aarch64_step): Use sim_core_read_buffer and
endian_le2h_4 to read instruction from pc.
PR 19872
bfd * dwarf2.c (parse_comp_unit): Skip warning about unrecognised
version number if the version is zero.
bin * dwarf.c (display_debug_aranges): Skip warning about unrecognised
version number if the version is zero.
* cpustate.c (aarch64_set_reg_s32): New function.
(aarch64_set_reg_u32): New function.
(aarch64_get_FP_half): Place half precision value into the correct
slot of the union.
(aarch64_set_FP_half): Likewise.
* cpustate.h: Add prototypes for aarch64_set_reg_s32 and
aarch64_set_reg_u32.
* memory.c (FETCH_FUNC): Cast the read value to the access type
before converting it to the return type. Rename to FETCH_FUNC64.
(FETCH_FUNC32): New macro. Duplicates FETCH_FUNC64 but for 32-bit
accesses. Use for 32-bit memory access functions.
* simulator.c (ldrsb_wb): Use sign extension not zero extension.
(ldrb_scale_ext, ldrsh32_abs, ldrsh32_wb): Likewise.
(ldrsh32_scale_ext, ldrsh_abs, ldrsh64_wb): Likewise.
(ldrsh_scale_ext, ldrsw_abs): Likewise.
(ldrh32_abs): Store 32 bit value not 64-bits.
(ldrh32_wb, ldrh32_scale_ext): Likewise.
(do_vec_MOV_immediate): Fix computation of val.
(do_vec_MVNI): Likewise.
(DO_VEC_WIDENING_MUL): New macro.
(do_vec_mull): Use new macro.
(do_vec_mul): Use new macro.
(do_vec_MLA): Read values before writing.
(do_vec_xtl): Likewise.
(do_vec_SSHL): Select correct shift value.
(do_vec_USHL): Likewise.
(do_scalar_UCVTF): New function.
(do_scalar_vec): Call new function.
(store_pair_u64): Treat reads of SP as reads of XZR.
* cpustate.c: Remove space after asterisk in function parameters.
* decode.h (greg): Delete unused function.
(vreg, shift, extension, scaling, writeback, condcode): Likewise.
* simulator.c: Use INSTR macro in more places.
(HALT_NYI): Use sim_io_eprintf in place of fprintf.
Remove extraneous whitespace.
* cpustate.c (aarch64_get_FP_half): New function. Read a vector
register as a half precision floating point number.
(aarch64_set_FP_half): New function. Similar, but for setting
a half precision register.
(aarch64_get_thread_id): New function. Returns the value of the
CPU's TPIDR register.
(aarch64_get_FPCR): New function. Returns the value of the CPU's
floating point control register.
(aarch64_set_FPCR): New function. Set the value of the CPU's FPCR
register.
* cpustate.h: Add prototypes for new functions.
* sim-main.h (struct _sim_cpu): Add FPCR and tpidr fields.
* memory.c: Use unaligned core access functions for all memory
reads and writes.
* simulator.c (HALT_NYI): Generate an error message if tracing
will not tell the user why the simulator is halting.
(HALT_UNREACHABLE): Delete. Delete (unneeded) uses of the macro.
(INSTR): New time-saver macro.
(fldrb_abs): New function. Loads an 8-bit value using a scaled
offset.
(fldrh_abs): New function. Likewise for 16-bit values.
(do_vec_SSHL): Allow for negative shift values.
(do_vec_USHL): Likewise.
(do_vec_SHL): Correct computation of shift amount.
(do_vec_SSHR_USHR): Correct decision of signed vs unsigned
shifts and computation of shift value.
(clz): New function. Counts leading zero bits.
(do_vec_CLZ): New function. Implements CLZ (vector).
(do_vec_MOV_element): Call do_vec_CLZ.
(dexSimpleFPCondCompare): Implement.
(do_FCVT_half_to_single): New function. Implements one of the
FCVT operations.
(do_FCVT_half_to_double): New function. Likewise.
(do_FCVT_single_to_half): New function. Likewise.
(do_FCVT_double_to_half): New function. Likewise.
(dexSimpleFPDataProc1Source): Call new FCVT functions.
(do_scalar_SHL): Handle negative shifts.
(do_scalar_shift): Handle SSHR.
(do_scalar_USHL): New function.
(do_double_add): Simplify to just performing a double precision
add operation. Move remaining code into...
(do_scalar_vec): ... New function.
(dexLoadUnsignedImmediate): Call new fldrb_abs and fldrh_abs
functions.
(system_get): Add support for TPIDR, CTR, FPCR, FPSR and CPSR
registers.
(system_set): New function.
(do_MSR_immediate): New function. Stub for now.
(do_MSR_reg): New function. Likewise. Partially implements MSR
instruction.
(do_SYS): New function. Stub for now,
(dexSystem): Call new functions.
* simulator.c (set_flags_for_sub32): Correct type of signbit.
(CondCompare): Swap interpretation of bit 30.
(DO_ADDP): Delete macro.
(do_vec_ADDP): Copy source registers before starting to update
destination register.
(do_vec_FADDP): Likewise.
(do_vec_load_store): Fix computation of sizeof_operation.
(rbit64): Fix type of constant.
(aarch64_step): When displaying insn value, display all 32 bits.
* aarch64/simulator.c (system_get): New function. Provides read
access to the dczid system register.
(do_mrs): New function - implements the MRS instruction.
(dexSystem): Call do_mrs for the MRS instruction. Halt on
unimplemented system instructions.
Jim Wilson
Joel Brobecker
Mike Frysinger
Nick Clifton
Tristan Gingold