Commit Graph

874 Commits

Author SHA1 Message Date
Jim Wilson 0fd3a4776c Kaveh Ghazi's printf format attribute checking patch.
bfd:
	* elf32-xtensa.c (vsprint_msg): Add format attribute.  Fix
	format bugs.
	* vms.h (_bfd_vms_debug): Add format attribute.
	(_bfd_vms_debug, _bfd_hexdump): Fix typos.

binutils:
	* bucomm.h (report): Add format attribute.
	* dlltool.c (inform): Likewise.
	* dllwrap.c (display, inform, warn): Likewise.
	* objdump.c (objdump_sprintf): Likewise.
	* readelf.c (error, warn): Likewise.  Fix format bugs.

gas:
	* config/tc-tic30.c (debug): Add format attribute.  Fix format
	bugs.

include:
	* dis-asm.h (fprintf_ftype): Add format attribute.

opcodes:
	* arc-dis.c, arm-dis.c, cris-dis.c, crx-dis.c, d10v-dis.c,
	d30v-dis.c, fr30-dis.c, h8300-dis.c, h8500-dis.c, i860-dis.c,
	ia64-dis.c, ip2k-dis.c, m10200-dis.c, m10300-dis.c,
	m88k-dis.c, mcore-dis.c, mips-dis.c, ms1-dis.c, or32-dis.c,
	ppc-dis.c, sh64-dis.c, sparc-dis.c, tic4x-dis.c, tic80-dis.c,
	v850-dis.c: Fix format bugs.
	* ia64-gen.c (fail, warn): Add format attribute.
	* or32-opc.c (debug): Likewise.
2005-07-07 19:27:52 +00:00
Nick Clifton 22f8fcbd5c arm-dis.c (opcode32 arm_opcodes): Fix ARM VFP fadds instruction disassembly
pattern.
vfp1xD.d: Adjust expected fadds disassemblies now that the dissassembler has
  been fixed.
2005-07-07 11:37:10 +00:00
Alan Modra d125c27b97 * Makefile.am (stamp-m32r): Fix path to cpu files.
(stamp-m32r, stamp-iq2000): Likewise.
	* Makefile.in: Regenerate.
	* m32r-asm.c: Regenerate.
	* po/POTFILES.in: Remove arm-opc.h.  Add ms1-asm.c, ms1-desc.c,
	ms1-desc.h, ms1-dis.c, ms1-ibld.c, ms1-opc.c, ms1-opc.h.
2005-07-06 08:19:39 +00:00
Nick Clifton 3ec2b351bd Fix compile time warnings from a GCC 4.0 compiler 2005-07-05 15:07:46 +00:00
Jan Beulich 3012383869 gas/
2005-07-05  Jan Beulich  <jbeulich@novell.com>

	* config/tc-i386.h (CpuSVME): New.
	(CpuUnknownFlags): Include CpuSVME.
	* config/tc-i386.c (cpu_arch): Add .pacifica and .svme. Add opteron
	as alias of sledgehammer.
	(md_assemble): Include invlpga in the check for insns with two source
	operands.
	(process_operands): Include SVME insns in the check for ignored
	segment overrides. Adjust diagnostic.
	(i386_index_check): Special-case SVME insns with memory operands.

gas/testsuite/
2005-07-05  Jan Beulich  <jbeulich@novell.com>

	* gas/i386/svme.d: New.
	* gas/i386/svme.s: New.
	* gas/i386/svme64.d: New.
	* gas/i386/i386.exp: Run new tests.

include/opcode/
2005-07-05  Jan Beulich  <jbeulich@novell.com>

	* i386.h (i386_optab): Add new insns.

opcodes/
2005-07-05  Jan Beulich  <jbeulich@novell.com>

	* i386-dis.c (SVME_Fixup): New.
	(grps): Use it for the lidt entry.
	(PNI_Fixup): Call OP_M rather than OP_E.
	(INVLPG_Fixup): Likewise.
2005-07-05 07:16:54 +00:00
H.J. Lu b0eec63e04 2005-07-04 H.J. Lu <hongjiu.lu@intel.com>
* tic30-dis.c (cnvt_tmsfloat_ieee): Use HUGE_VALF if defined.
2005-07-04 17:51:36 +00:00
Nick Clifton 47b0e7ad8c Update function declarations to ISO C90 formatting 2005-07-01 11:16:33 +00:00
Ben Elliston cc16ba8c4f * m68k-dis.c: Use ISC C90.
* m68k-opc.c: Formatting fixes.
2005-06-23 11:18:26 +00:00
David Ung 4b185e973e * mips16-opc.c (mips16_opcodes): Add the following MIPS16e
instructions to the table; seb/seh/sew/zeb/zeh/zew.
2005-06-16 17:01:12 +00:00
Dave Brolley ac18822241 2005-06-15 Dave Brolley <brolley@redhat.com>
Contribute Morpho ms1 on behalf of Red Hat
        * ms1-asm.c, ms1-desc.c, ms1-dis.c, ms1-ibld.c, ms1-opc.c,
        ms1-opc.h: New files, Morpho ms1 target.

        2004-05-14  Stan Cox  <scox@redhat.com>

        * disassemble.c (ARCH_ms1): Define.
        (disassembler): Handle bfd_arch_ms1

        2004-05-13  Michael Snyder  <msnyder@redhat.com>

        * Makefile.am, Makefile.in: Add ms1 target.
        * configure.in: Ditto.
2005-06-15 16:23:54 +00:00
Zack Weinberg 6b5d3a4d35 opcodes:
* arm-opc.h: Delete; fold contents into ...
	* arm-dis.c: ... here.  Move includes of internal COFF headers
	next to includes of internal ELF headers.
	(streq, WORD_ADDRESS, BDISP, BDISP23): Delete, unused.
	(struct arm_opcode): Rename struct opcode32.  Make 'assembler' const.
	(struct thumb_opcode): Rename struct opcode16.  Make 'assembler' const.
	(arm_conditional, arm_fp_const, arm_shift, arm_regname, regnames)
	(iwmmxt_wwnames, iwmmxt_wwssnames):
	Make const.
	(regnames): Remove iWMMXt coprocessor register sets.
	(iwmmxt_regnames, iwmmxt_cregnames): New statics.
	(get_arm_regnames): Adjust fourth argument to match above changes.
	(set_iwmmxt_regnames): Delete.
	(print_insn_arm): Constify 'c'.  Use ISO syntax for function
	pointer calls.  Expand sole use of BDISP.  Use iwmmxt_regnames
	and iwmmxt_cregnames, not set_iwmmxt_regnames.
	(print_insn_thumb16, print_insn_thumb32): Constify 'c'.  Use
	ISO syntax for function pointer calls.
include:
	* dis-asm.h (get_arm_regnames): Update prototype.
2005-06-08 17:27:41 +00:00
Zack Weinberg 4a5329c63a * arm-dis.c: Split up the comments describing the format codes, so
that the ARM and 16-bit Thumb opcode tables each have comments
	preceding them that describe all the codes, and only the codes,
	valid in those tables.  (32-bit Thumb table is already like this.)
	Reorder the lists in all three comments to match the order in
	which the codes are implemented.
	Remove all forward declarations of static functions.  Convert all
	function definitions to ISO C format.
	(print_insn_arm, print_insn_thumb16, print_insn_thumb32):
	Return nothing.
	(print_insn_thumb16): Remove unused case 'I'.
	(print_insn): Update for changed calling convention of subroutines.
2005-06-07 22:16:52 +00:00
Jan Beulich 3d456fa193 gas/testsuite/
2005-05-25  Jan Beulich  <jbeulich@novell.com>

	* gas/i386/intelok.d: Account for 32-bit displacements being shown
	in hex.

opcodes/
2005-05-25  Jan Beulich  <jbeulich@novell.com>

	* i386-dis.c (OP_E): In Intel mode, display 32-bit displacements in
	hex (but retain it being displayed as signed). Remove redundant
	checks. Add handling of displacements for 16-bit addressing in Intel
	mode.
2005-05-25 06:50:23 +00:00
Jan Beulich 2888cb7a54 opcodes/
2005-05-25  Jan Beulich  <jbeulich@novell.com>

	* i386-dis.c (prefix_name): Remove pointless mode_64bit check.
	(OP_E): Remove redundant REX_EXTZ handling. Remove pointless
	masking of 'rm' in 16-bit memory address handling.
2005-05-25 06:47:58 +00:00
Alan Modra 1ed8e1e4fb * ppc-dis.c (powerpc_dialect): Handle "-Mpower5".
(print_ppc_disassembler_options): Document it.
	* ppc-opc.c (SCV_LEV): Define.
	(LEV): Allow optional operand.
	(POWER5): Define.
	(powerpc_opcodes): Extend "sc".  Adjust "svc" and "svcl".  Add
	"hrfid", "popcntb", "fsqrtes", "fsqrtes.", "fre" and "fre.".
2005-05-19 07:00:40 +00:00
Kelley Cook 49cc2e69fc 2005-05-19 Kelley Cook <kcook@gcc.gnu.org>
* Makefile.in:  Regenerate.
2005-05-19 03:18:04 +00:00
Zack Weinberg c19d120533 include/elf:
* arm.h: Import complete list of official relocation names
	and numbers from AAELF.  Define FAKE_RELOCs for old names.
	Remove a few old names no longer used anywhere.

bfd:
	* elf32-arm.c: Wherever possible, use official reloc names
	from AAELF.
	(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
	(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
	(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
	(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
	(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
	(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
	elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
	Add many new relocations from AAELF.
	(elf32_arm_howto_from_type): Update to match.
	(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
	R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
	R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
	(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
	(elf32_arm_final_link_relocate): Add support for
	R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6.  Remove
	case entries redundant with default.

	* reloc.c: Reorganize ARM relocations.  Add Thumb
	assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
	BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
	Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
	BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
	Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
	* bfd-in2.h, libbfd.h: Regenerate.

opcodes:
	* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
	instructions.  Adjust disassembly of some opcodes to match
	unified syntax.
	(thumb32_opcodes): New table.
	(print_insn_thumb): Rename print_insn_thumb16; don't handle
	two-halfword branches here.
	(print_insn_thumb32): New function.
	(print_insn): Choose among print_insn_arm, print_insn_thumb16,
	and print_insn_thumb32.  Be consistent about order of
	halfwords when printing 32-bit instructions.

gas:
	* hash.c (hash_lookup): Add len parameter.  All callers changed.
	(hash_find_n): New interface.
	* hash.h: Prototype hash_find_n.
	* sb.c: Include as.h.
	(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
	(sb_scrub_and_add_sb): New interface.
	* sb.h: Prototype sb_scrub_and_add_sb.
	* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.

	* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
	reference to BFD_RELOC_ARM_GOT12 which is never generated.
	* config/tc-arm.c: Rewrite, adding Thumb-2 support.

gas/testsuite:
	* gas/arm/arm.exp: Convert all existing "gas_test" tests to
	"run_dump_test" tests.  Run more tests unconditionally.  Run new tests.
	* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
	* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
	* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
	Adjust to work as a dump test.
	* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
	* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
	* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
	New files.

	* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
	diagnostics that don't happen in the first pass anymore.

	* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
	* gas/arm/vfp-bad.l:
	Update expected diagnostics.
	* gas/arm/pic.d: Update expected reloc name.
	* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
	* gas/arm/r15-bad.s: Avoid two-argument mul.
	* gas/arm/req.s: Adjust comments.
	* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
	use of PC.

	* gas/arm/macro-1.d, gas/arm/macro1.s
	* gas/arm/t16-bad.l, gas/arm/t16-bad.s
	* gas/arm/tcompat.d, gas/arm/tcompat.s
	* gas/arm/tcompat2.d, gas/arm/tcompat2.s
	* gas/arm/thumb32.d, gas/arm/thumb32.s
	New test pair.

ld/testsuite:
	* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-18 05:40:12 +00:00
H.J. Lu 003519a7c2 gas/testsuite/
2005-05-07  H.J. Lu  <hongjiu.lu@intel.com>

	PR 843
	* gas/i386/i386.exp: Add x86-64-branch.

	* gas/i386/x86-64-branch.d: New.
	* gas/i386/x86-64-branch.s: New.

opcodes/

2005-05-07  H.J. Lu  <hongjiu.lu@intel.com>

	PR 843
	* i386-dis.c (branch_v_mode): New.
	(indirEv): Use branch_v_mode instead of v_mode.
	(OP_E): Handle branch_v_mode.
2005-05-07 13:30:02 +00:00
H.J. Lu 920a34a7b2 2005-05-07 H.J. Lu <hongjiu.lu@intel.com>
* d10v-dis.c (dis_2_short): Support 64bit host.
2005-05-07 13:26:28 +00:00
Nick Clifton 5de773c13e Update Dutch translation 2005-05-07 07:52:54 +00:00
Nick Clifton f432110413 Update the address and phone number of the FSF 2005-05-07 07:34:31 +00:00
Jim Wilson 10b076a2ee Fix ia64-hpux build failure.
* ia64-opc.c: Include sysdep.h before libiberty.h.
2005-05-05 21:45:58 +00:00
Nick Clifton 022716b6cc * configure.in (ALL_LINGUAS): Add vi.
* configure: Regenerate.
* po/vi.po: New.
2005-05-05 09:17:37 +00:00
Jerome Guitton db5152b48d * configure.in: Fix the check for basename declaration.
* configure: Regenerate.
2005-04-26 10:24:45 +00:00
Alan Modra eed0d89a39 * ppc-opc.c (RTO): Define.
(powerpc_opcodes <tlbsx, tlbsx., tlbre>): Combine PPC403 and BOOKE
	entries to suit PPC440.
2005-04-19 04:50:37 +00:00
Mark Kettenis 791fe84908 gas/ChangeLog:
* config/tc-i386.c (md_begin): Allow hyphens in mnemonics.
include/opcode/ChangeLog:
* i386.h: Insert hyphens into selected VIA PadLock extensions.
Add xcrypt-ctr.  Provide aliases without hyphens.
opcodes/ChangeLog:
* i386-dis.c: Insert hyphens into selected VIA PadLock extensions.
Add xcrypt-ctr.
2005-04-18 20:59:20 +00:00
Nick Clifton ffe58f7c73 * po/fi.po: New translation: Finnish.
* configure.in (ALL_LINGUAS): Add fi.
* configure: Regenerate.
2005-04-14 09:48:24 +00:00
Alan Modra 9e9b66a956 bfd/
* Makefile.am (NO_WERROR): Define.
	* warning.m4: New file
	* acinclude.m4: Include warning.m4.
	* configure.in: Invoke AM_BINUTILS_WARNINGS.
	* Makefile.in: Regenerate.
	* configure: Regenerate.
bfd/doc/
	* Makefile.in: Regenerate.
binutils/
	* Makefile.am (NO_WERROR): Define.  Use instead of -Wno-error.
	* configure.in: Include ../bfd/warning.m4 contents.
	* Makefile.in: Regenerate.
	* configure: Regenerate.
	* doc/Makefile.in: Regenerate.
gas/
	* Makefile.am (NO_WERROR): Define.  Use instead of -Wno-error.
	* acinclude.m4: Include ../bfd/warning.m4.
	* configure.in: Invoke AM_BINUTILS_WARNINGS.
	* Makefile.in: Regenerate.
	* configure: Regenerate.
	* doc/Makefile.in: Regenerate.
gprof/
	* Makefile.am (NO_WERROR): Define.
	* acinclude.m4: Include ../bfd/warning.m4.
	* configure.in: Invoke AM_BINUTILS_WARNINGS.
	* Makefile.in: Regenerate.
	* aclocal.m4: Regenerate.
	* configure: Regenerate.
ld/
	* Makefile.am (NO_WERROR): Define.  Use instead of -Wno-error.
	* configure.in: Include ../bfd/warning.m4 contents.
	* Makefile.in: Regenerate.
	* configure: Regenerate.
opcodes/
	* Makefile.am (NO_WERROR): Define.
	* configure.in: Invoke AM_BINUTILS_WARNINGS.
	* Makefile.in: Regenerate.
	* aclocal.m4: Regenerate.
	* configure: Regenerate.
2005-04-14 05:26:44 +00:00
Nick Clifton 9494d73902 Initialise value to zero to avoid a compile time warning. 2005-04-04 10:09:52 +00:00
Jan Beulich 6128c599ed opcodes/
2005-04-01  Jan Beulich  <jbeulich@novell.com>

	* i386-dis.c (PNI_Fixup): Neither mwait nor monitor have any
	visible operands in Intel mode. The first operand of monitor is
	%rax in 64-bit mode.
2005-04-01 16:06:40 +00:00
Jan Beulich 373ff435a8 include/opcode/
2005-04-01  Jan Beulich  <jbeulich@novell.com>

	* i386.h (i386_optab): Add rdtscp.

opcodes/
2005-04-01  Jan Beulich  <jbeulich@novell.com>

	* i386-dis.c (INVLPG_Fixup): Decode rdtscp; change code to allow for
	easier future additions.
2005-04-01 16:03:40 +00:00
Jerome Guitton 4bd6089634 * configure.in: Check for basename.
* configure: Regenerate.
        * config.in: Ditto.
2005-03-31 16:52:54 +00:00
H.J. Lu 4cc91dba12 gas/testsuite/
2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/i386.exp: Run segment and inval-seg for i386. Run
	x86-64-segment and x86-64-inval-seg for x86-64.

	* gas/i386/intel.d: Expect movw for moving between memory and
	segment register.
	* gas/i386/naked.d: Likewise.
	* gas/i386/opcode.d: Likewise.
	* gas/i386/x86-64-opcode.d: Likewise.

	* gas/i386/opcode.s: Use movw for moving between memory and
	segment register.
	* gas/i386/x86-64-opcode.s: Likewise.

	* : Likewise.

	* gas/i386/inval-seg.l: New.
	* gas/i386/inval-seg.s: New.
	* gas/i386/segment.l: New.
	* gas/i386/segment.s: New.
	* gas/i386/x86-64-inval-seg.l: New.
	* gas/i386/x86-64-inval-seg.s: New.
	* gas/i386/x86-64-segment.l: New.
	* gas/i386/x86-64-segment.s: New.

include/opcode/

2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>

	* i386.h (i386_optab): Don't allow the `l' suffix for moving
	moving between memory and segment register. Allow movq for
	moving between general-purpose register and segment register.

opcodes/

2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (SEG_Fixup): New.
	(Sv): New.
	(dis386): Use "Sv" for 0x8c and 0x8e.
2005-03-29 19:30:47 +00:00
Nick Clifton ec72cfe589 Add VAX specific disassembler option -Mentry: to specify a function entry
address, and add code to test this new option.
2005-03-29 16:13:48 +00:00
H.J. Lu 85064c7906 2005-03-23 H.J. Lu <hongjiu.lu@intel.com>
* cris-dis.c (print_with_operands): Use ~31L for long instead
	of ~31.
2005-03-23 19:21:16 +00:00
H.J. Lu de7141c7b1 2005-03-20 H.J. Lu <hongjiu.lu@intel.com>
* mmix-opc.c (O): Revert the last change.
	(Z): Likewise.
2005-03-20 17:12:16 +00:00
H.J. Lu e493ab45b1 2005-03-19 H.J. Lu <hongjiu.lu@intel.com>
* mmix-opc.c (O): Use 24UL instead of 24 for unsigned long.
	(Z): Likewise.
2005-03-19 18:29:14 +00:00
Hans-Peter Nilsson d8d7c45959 * mmix-opc.c (O, Z): Force expression as unsigned long. 2005-03-19 04:23:24 +00:00
Nick Clifton ebdb038304 Change wording of error message to "percent-operand" from "%operand" as the
latter confuses xgettext into thinking that it is a C printf formating directive,
which	prevents proper translation.
2005-03-18 16:12:38 +00:00
Nick Clifton 569acd2ce2 Rename switch to enable/disable -Werror to --enable-werror/--disable-werror
for compatibility with gcc.
2005-03-16 17:18:17 +00:00
Nick Clifton 1ad12f975f Enable -Werror by default 2005-03-16 16:17:14 +00:00
Alan Modra 4eb30afc41 * ppc-dis.c (powerpc_dialect): Don't set PPC_OPCODE_ALTIVEC when
BOOKE.
2005-03-16 02:38:39 +00:00
Alan Modra 729ae8d20e Commit new Spanish translation. 2005-03-15 05:25:37 +00:00
Alan Modra ea8409f729 Commit new French translation. 2005-03-14 23:39:09 +00:00
Nick Clifton 4f495e616d Use ".word 0x0012 # Entry mask: r1 r2 >" instead of just "Entry mask: < r1 ... >" 2005-03-14 09:35:26 +00:00
Zack Weinberg 885fc2570f gas:
* config/tc-arm.c (tinsns): Add ARMv6K instructions sev, wfe,
	wfi, yield.
opcodes:
	* arm-dis.c (thumb_opcodes): Add ARMv6K instructions nop, sev,
	wfe, wfi, yield.
gas/testsuite:
	* gas/arm/thumbv6k.d, gas/arm/thumbv6k.s: New dump test.
	* gas/arm/arm.exp: Run it.
2005-03-12 18:25:47 +00:00
Zack Weinberg b9fd58c7eb Revert accidental commit of V6K ops 2005-03-12 18:17:42 +00:00
Zack Weinberg 0a003adc41 include:
* opcode/arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
	Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
	and ARM_ARCH_V6ZKT2.
opcodes:
	* arm-dis.c (arm_opcodes): Document %E and %V.
	Add entries for v6T2 ARM instructions:
	bfc bfi mls strht ldrht ldrsht ldrsbt movw movt rbit ubfx sbfx.
	(print_insn_arm): Add support for %E and %V.
2005-03-12 18:14:05 +00:00
Alan Modra da99ee721e opcodes/
* ppc-opc.c (insert_sprg, extract_sprg): New Functions.
	(powerpc_operands <SPRG>): Call the above.  Bit field is 5 bits.
	(SPRG_MASK): Delete.
	(XSPRG_MASK): Mask off extra bits now part of sprg field.
        (powerpc_opcodes): Asjust mfsprg and mtsprg to suit new mask.  Move
	mfsprg4..7 after msprg and consolidate.

gas/testsuite
	* gas/ppc/booke.s: Add new m[t,f]sprg testcases.
	* gas/ppc/booke.d: Likewise.
2005-03-10 12:52:30 +00:00
Alan Modra 220abb21d1 * vax-dis.c (entry_mask_bit): New array.
(print_insn_vax): Decode function entry mask.
2005-03-09 13:08:26 +00:00