PR target/20068
* config/tc-arm.c (add_to_lit_pool): Ensure that the padding added
to the pool uses O_constant.
* testsuite/gas/arm/pr20068.s: New test.
* testsuite/gas/arm/pr20068.d: Test driver.
2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
bfd/
* elf32-arm.c (elf32_arm_size_stubs): Use new macros
ARM_GET_SYM_BRANCH_TYPE and ARM_SET_SYM_BRANCH_TYPE to respectively get
and set branch type of a symbol.
(bfd_elf32_arm_process_before_allocation): Likewise.
(elf32_arm_relocate_section): Likewise and fix identation along the
way.
(allocate_dynrelocs_for_symbol): Likewise.
(elf32_arm_finish_dynamic_symbol): Likewise.
(elf32_arm_swap_symbol_in): Likewise.
(elf32_arm_swap_symbol_out): Likewise.
gas/
* config/tc-arm.c (arm_adjust_symtab): Use ARM_SET_SYM_BRANCH_TYPE to
set branch type of a symbol.
gdb/
* arm-tdep.c (arm_elf_make_msymbol_special): Use
ARM_GET_SYM_BRANCH_TYPE to get branch type of a symbol.
include/
* arm.h (enum arm_st_branch_type): Add new ST_BRANCH_ENUM_SIZE
enumerator.
(NUM_ENUM_ARM_ST_BRANCH_TYPE_BITS): New macro.
(ENUM_ARM_ST_BRANCH_TYPE_BITMASK): Likewise.
(ARM_SYM_BRANCH_TYPE): Replace by ...
(ARM_GET_SYM_BRANCH_TYPE): This and ...
(ARM_SET_SYM_BRANCH_TYPE): This in two versions depending on whether
BFD_ASSERT is defined or not.
ld/
* emultempl/armelf.em (gld${EMULATION_NAME}_finish): Use
ARM_GET_SYM_BRANCH_TYPE to get branch type of a symbol.
opcodes/
* arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
branch type of a symbol.
(print_insn): Likewise.
2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
gas/
* config/tc-arm.c (struct arm_option_extension_value_table): Make
allowed_archs an array with 2 entries.
(ARM_EXT_OPT): Adapt to only fill the first entry of allowed_archs.
(ARM_EXT_OPT2): New macro filling the two entries of allowed_archs.
(arm_extensions): Use separate entries in allowed_archs when several
archs are allowed to use an extension and change ARCH_ANY in
ARM_ARCH_NONE in allowed_archs.
(arm_parse_extension): Check that, for each allowed_archs entry, all
bits are set in the current architecture, ignoring ARM_ANY entries.
(s_arm_arch_extension): Likewise.
include/
* arm.h (ARM_FSET_CPU_SUBSET): Define macro.
2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
gas/
* config/tc-arm.c (arm_ext_m): Add feature bit ARM_EXT2_V8M_MAIN.
(arm_ext_v8m_main): New feature set for bit ARM_EXT2_V8M_MAIN.
(arm_ext_v8m_m_only): New feature set for instructions in ARMv8-M not
shared with a non M profile architecture.
(do_rn): New function.
(known_t32_only_insn): Check opcode against arm_ext_v8m_m_only rather
than arm_ext_v8m.
(v7m_psrs): Add ARMv8-M security extensions new special registers.
(insns): Add ARMv8-M Security Extensions instructions.
(aeabi_set_public_attributes): Use arm_ext_v8m_m_only instead of
arm_ext_v8m_m to decide the profile and the Thumb ISA.
* testsuite/gas/arm/archv8m-cmse.s: New file.
* testsuite/gas/arm/archv8m-cmse-main.s: Likewise..
* testsuite/gas/arm/archv8m-cmse-msr.s: Likewise.
* testsuite/gas/arm/any-cmse.d: Likewise.
* testsuite/gas/arm/any-cmse-main.d: Likewise.
* testsuite/gas/arm/archv8m-cmse-base.d: Likewise.
* testsuite/gas/arm/archv8m-cmse-msr-base.d: Likewise.
* testsuite/gas/arm/archv8m-cmse-main-1.d: Likewise.
* testsuite/gas/arm/archv8m-cmse-main-2.d: Likewise.
* testsuite/gas/arm/archv8m-cmse-msr-main.d: Likewise.
include/
* opcode/arm.h (ARM_EXT2_V8M_MAIN): new feature bit.
(ARM_AEXT2_V8M_MAIN): New architecture extension feature set.
(ARM_ARCH_V8M_MAIN): Use ARM_AEXT2_V8M_MAIN instead of ARM_AEXT2_V8M
for the high core bits.
opcodes/
* arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
Mainline Security Extensions instructions.
(thumb_opcodes): Add entries for narrow ARMv8-M Security
Extensions instructions.
(thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
instructions.
(psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
special registers.
opcodes/ChangeLog:
2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
gas/ChangeLog:
2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
* testsuite/gas/sparc/sparc5vis4.s: Fix mnemonic of faligndatai.
* testsuite/gas/sparc/sparc5vis4.d: Likewise.
Correct a regression introduced with commit 919731affbef ("Add MIPS
.module directive") causing code like:
.set mips3
dli $2, 0x9000000080000000
to fail assembly with the following error message produced:
Error: number (0x9000000080000000) larger than 32 bits
if built with `mips3' selected as the global ISA (e.g. `-march=mips3').
This is because a `.set' directive doing an ISA override does not lift
the ABI restriction on register sizes if the ISA remains unchanged.
Previously the directive always set register sizes from the ISA chosen,
which is what some code expects. Restore the old semantics then.
gas/
* config/tc-mips.c (code_option_type): New enum.
(parse_code_option): Return status indicating option type.
(s_mipsset): Update `parse_code_option' call site accordingly.
Always set register sizes from the ISA with ISA overrides.
(s_module): Update `parse_code_option' call site.
* testsuite/gas/mips/isa-override-1.d: New test.
* testsuite/gas/mips/micromips@isa-override-1.d: New test.
* testsuite/gas/mips/mips1@isa-override-1.d: New test.
* testsuite/gas/mips/mips2@isa-override-1.d: New test.
* testsuite/gas/mips/mips32@isa-override-1.d: New test.
* testsuite/gas/mips/mips32r2@isa-override-1.d: New test.
* testsuite/gas/mips/mips32r3@isa-override-1.d: New test.
* testsuite/gas/mips/mips32r5@isa-override-1.d: New test.
* testsuite/gas/mips/mips32r6@isa-override-1.d: New test.
* testsuite/gas/mips/mips64r2@isa-override-1.d: New test.
* testsuite/gas/mips/mips64r3@isa-override-1.d: New test.
* testsuite/gas/mips/mips64r5@isa-override-1.d: New test.
* testsuite/gas/mips/mips64r6@isa-override-1.d: New test.
* testsuite/gas/mips/r3000@isa-override-1.d: New test.
* testsuite/gas/mips/r3900@isa-override-1.d: New test.
* testsuite/gas/mips/r5900@isa-override-1.d: New test.
* testsuite/gas/mips/octeon@isa-override-1.d: New test.
* testsuite/gas/mips/octeon3@isa-override-1.d: New test.
* testsuite/gas/mips/isa-override-2.l: New list test.
* testsuite/gas/mips/mips1@isa-override-2.l: New list test.
* testsuite/gas/mips/mips2@isa-override-2.l: New list test.
* testsuite/gas/mips/mips32@isa-override-2.l: New list test.
* testsuite/gas/mips/mips32r2@isa-override-2.l: New list test.
* testsuite/gas/mips/mips32r3@isa-override-2.l: New list test.
* testsuite/gas/mips/mips32r5@isa-override-2.l: New list test.
* testsuite/gas/mips/mips32r6@isa-override-2.l: New list test.
* testsuite/gas/mips/r3000@isa-override-2.l: New list test.
* testsuite/gas/mips/r3900@isa-override-2.l: New list test.
* testsuite/gas/mips/octeon3@isa-override-2.l: New list test.
* testsuite/gas/mips/octeon3@isa-override-1.l: New stderr
output.
* testsuite/gas/mips/isa-override-1.s: New test source.
* testsuite/gas/mips/r5900@isa-override-1.s: New test source.
* testsuite/gas/mips/isa-override-2.s: New test source.
* testsuite/gas/mips/mips1@isa-override-2.s: New test source.
* testsuite/gas/mips/mips2@isa-override-2.s: New test source.
* testsuite/gas/mips/mips32@isa-override-2.s: New test source.
* testsuite/gas/mips/mips32r2@isa-override-2.s: New test source.
* testsuite/gas/mips/mips32r3@isa-override-2.s: New test source.
* testsuite/gas/mips/mips32r5@isa-override-2.s: New test source.
* testsuite/gas/mips/mips32r6@isa-override-2.s: New test source.
* testsuite/gas/mips/r3000@isa-override-2.s: New test source.
* testsuite/gas/mips/r3900@isa-override-2.s: New test source.
* testsuite/gas/mips/octeon3@isa-override-2.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
Add nps400 to the list of acceptable values for the -mcpu command line
switch, and to the .cpu directive.
I've added an extra cross reference from -mcpu to .cpu to improve
navigation of the documentation.
gas/ChangeLog:
* doc/c-arc.texi (ARC Options): Add nps400 to list of valus for
-mcpu. Add cross reference to .cpu directive from -mcpu option.
(ARC Directives): Add NPS400 to .cpu directive list.
The RAS extension was introduced as part of the ARMv8.2 architecture
where it is a required feature. It is also available as an optional
feature for ARMv8 and ARMv8.1. In binutils, the RAS extension is
currently enabled by default for -march=armv8.2-a but is not available
for -march=armv8 or -march=armv8.1-a.
This patch adds the feature extension '+ras' to enable the RAS extension
for ARMv8 and ARMv8.1, it is disabled by default.
gas/
2016-04-20 Matthew Wahab <matthew.wahab@arm.com>
* config/tc-aarch64.c (aarch64_features): Add "ras".
* doc/c-aarch64.texi (AArch64 Extensions): Add "ras".
* testsuite/gas/aarch64/armv8-ras-1.d: New.
* testsuite/gas/aarch64/armv8-ras-1.s: New.
* testsuite/gas/aarch64/illegal-ras-1.d: New.
* testsuite/gas/aarch64/illegal-ras-1.s: New.
Change-Id: I824fb9bc8cf846bcc03aa17a726efb1350d78b9d
This reverts commit 9a452709fe126ea6da23a53426362e4435d2dc06.
This change was committed as obvious, but it has been rightly been
pointed out to me that this change is not obvious, and as such I am
reverting it.
gas/ChangeLog:
Revert prevous change.
* config/tc-arc.c (arc_option): Make .cpu directive
case-sensitive again.
Presumably this was supposed to be regname[sizeof (regname) - 1] but was typoed
to regname[sizeof (rename) - 1]. However that should be unnecessary because
sprintf should null terminate. As is this assignment is invalid ISO C because
rename refers to the function rename (), and sizeof on functions is undefined.
In GNU C C the size of functions is 1 so the expression is the same as
regname[0]. The following call to sprintf () clearly will over right that, so
the statement either has no effect or is invalid. Given that it seems safe to
just remove it. While we are there correct the size of regname, and switch
from snprintf to sprintf since we know the exact length of the result.
gas/ChangeLog:
2016-04-15 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-mips.c (md_begin): Remove useless assignment.
They are only used in one file, so we might as well restrict there scope to
that file, and theoretically this might slightly improve compilers ability to
optimize usage of these variables.
gas/ChangeLog:
2016-04-14 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-nios2.c (nios2_as_options): Make file static.
* config/tc-ppc.c (toc_reloc_ypes): Likewise.
* config/tc-sparc.c (native_op_table): Likewise.
Add support for arc/nps400 cmem instructions, these load and store
instructions are hard-wired to access "0x57f00000 + 16-bit-offset".
Supporting this relocation required some additions to the arc relocation
handling in the bfd library, as well as the standard changes required to
add a new relocation type.
There's a test of the new instructions in the assembler, and a test of
the relocation in the linker.
bfd/ChangeLog:
* reloc.c: Add BFD_RELOC_ARC_NPS_CMEM16 entry.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
* elf32-arc.c: Add 'opcode/arc.h' include.
(struct arc_relocation_data): Add symbol_name.
(arc_special_overflow_checks): New function.
(arc_do_relocation): Use arc_special_overflow_checks, reindent as
required, add an extra comment.
(elf_arc_relocate_section): Setup symbol_name in reloc_data.
gas/ChangeLog:
* testsuite/gas/arc/nps400-3.d: New file.
* testsuite/gas/arc/nps400-3.s: New file.
include/ChangeLog:
* elf/arc-reloc.def: Add ARC_NPS_CMEM16 reloc.
* opcode/arc.h (NPS_CMEM_HIGH_VALUE): Define.
ld/ChangeLog:
* testsuite/ld-arc/arc.exp: New file.
* testsuite/ld-arc/nps-1.s: New file.
* testsuite/ld-arc/nps-1a.d: New file.
* testsuite/ld-arc/nps-1b.d: New file.
* testsuite/ld-arc/nps-1b.err: New file.
opcodes/ChangeLog:
* arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
instructions.
* arc-opc.c (insert_nps_cmem_uimm16): New function.
(extract_nps_cmem_uimm16): New function.
(arc_operands): Add NPS_XLDST_UIMM16 operand.
We were running a slightly different set of assembler tests on big and
little endian arc targets. This commit unifies the set of tests run.
gas/ChangeLog:
* testsuite/gas/arc/add_s-err.s: Update target pattern.
* testsuite/gas/arc/warn.s: Likewise.
* testsuite/gas/elf/elf.exp: Run test for arc.
PR target/19938
bfd * elf-bbfd.h (struct elf_backend_data): New field:
elf_strtab_flags.
New field: elf_backend_set_special_section_info_and_link
* elfxx-target.h (elf_backend_strtab_flags): Define if not already
defined.
(elf_backend_set_special_section_info_and_link): Define if not
already defined.
(elfNN_bed): Use elf_backend_set_special_section_info_and_link and
elf_backend_strtab_flags macros to initialise fields in structure.
* elf.c (_bfd_elf_make_section_from_shdr): Check for SHF_STRINGS
being set even if SHF_MERGE is not set.
(elf_fake_sections): Likewise.
(section_match): New function. Matches two ELF sections based
upon fixed characteristics.
(find_link): New function. Locates a section in a BFD that
matches a section in a different BFD.
(_bfd_elf_copy_private_bfd_data): Copy the sh_info and sh_link
fields of reserved sections.
(bfd_elf_compute_section_file_positions): Set the flags for the
.shstrtab section based upon the elf_strtab_flags field in the
elf_backend_data structure.
(swap_out_syms): Likewise for the .strtab section.
* elflink.c (bfd_elf_final_link): Set the flags for the
.strtab section based upon the elf_strtab_flags field in the
elf_backend_data structure.
* elf32-i386.c (elf32_i386_set_special_info_link): New function.
(elf_backend_strtab_flags): Set to SHF_STRINGS for Solaris
targets.
(elf_backend_set_special_section_info_and_link): Define for
Solaris targets.
* elf32-sparc.c: Likewise.
* elf64-x86-64.c: Likewise.
binutils* testsuite/binutils-all/i386/compressed-1b.d: Allow for the
string sections possibly having the SHF_STRINGS flag bit set.
* testsuite/binutils-all/i386/compressed-1c.d: Likewise.
* testsuite/binutils-all/readelf.s: Likewise.
* testsuite/binutils-all/readelf.s-64: Likewise.
* testsuite/binutils-all/x86-64/compressed-1b.d: Likewise.
* testsuite/binutils-all/x86-64/compressed-1c.d: Likewise.
gas * testsuite/gas/i386/ilp32/x86-64-unwind.d: Allow for the string
sections possibly having the SHF_STRINGS flag bit set.
* testsuite/gas/i386/x86-64-unwind.d: Likewise.
gas/
2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
* config/tc-arc.c (mach_type_specified_p): Change type to
bfd_boolean.
(arc_option): Set private flags when parsing cpu pseudo-op.
(md_parse_option): Set mach_type_specified_p to TRUE.
PR target/19937
opcode * v850-opc.c (v850_opcodes): Correct masks for long versions of
the LD.B and LD.BU instructions.
gas * testsuite/gas/v850/pr19937.s: New test.
* testsuite/gas/v850/pr19937.d: New test control file.
* testsuite/gas/v850/basic.exp: Run the new test.
Weak symbols can be preempted at link time so always choose the longer
sequence in branch relaxation, according to the relaxation level chosen,
so that any symbol finally used as the branch target is reachable.
2016-04-13 Maciej W. Rozycki <macro@imgtec.com>
Andrew Bennett <andrew.bennett@imgtec.com>
gas/
* config/tc-mips.c (relaxed_branch_length): Use the long
sequence where the target is a weak symbol.
(relaxed_micromips_32bit_branch_length): Likewise.
(relaxed_micromips_16bit_branch_length): Likewise.
* testsuite/gas/mips/branch-weak-1.d: New test.
* testsuite/gas/mips/branch-weak-2.d: New test.
* testsuite/gas/mips/branch-weak-3.d: New test.
* testsuite/gas/mips/branch-weak-4.d: New test.
* testsuite/gas/mips/branch-weak-5.d: New test.
* testsuite/gas/mips/branch-weak.l: New stderr output.
* testsuite/gas/mips/branch-weak.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
Where branch relaxation is enabled emit the long sequence for branches
whose distance cannot be determined, i.e. to symbols that are undefined
or in a different segment. These symbols are only resolved at link time
and therefore the longer sequence ensures the branch target is in range,
which cannot be guaranteed with a direct branch.
This is the opposite to the current implementation, originally proposed
here: <https://sourceware.org/ml/binutils/2002-09/msg00218.html>. The
proposal was then extensively discussed before the final version was
posted here: <https://sourceware.org/ml/binutils/2002-10/msg00191.html>
and eventually committed:
commit 4a6a3df43dbb37853a7b88b10ae97d9ec5daf987
Author: Alexandre Oliva <aoliva@redhat.com>
Date: Sat Oct 12 05:23:33 2002 +0000
The case considered here was not commented in the review however and the
original version remains. With branch relaxation enabled it makes more
sense to do it consistently, so that all code impure with respect to
branch distances can be linked. Direct branches are still produced for
the cases concerned where branch relaxation is disabled, which is the
default.
gas/
* config/tc-mips.c (relaxed_branch_length): Use the long
sequence where the distance cannot be determined.
(relaxed_micromips_32bit_branch_length): Likewise.
* testsuite/gas/mips/branch-extern-1.d: New test.
* testsuite/gas/mips/branch-extern-2.d: New test.
* testsuite/gas/mips/branch-extern-3.d: New test.
* testsuite/gas/mips/branch-extern-4.d: New test.
* testsuite/gas/mips/branch-extern.l: New stderr output.
* testsuite/gas/mips/branch-extern.s: New test source.
* testsuite/gas/mips/branch-section-1.d: New test.
* testsuite/gas/mips/branch-section-2.d: New test.
* testsuite/gas/mips/branch-section-3.d: New test.
* testsuite/gas/mips/branch-section-4.d: New test.
* testsuite/gas/mips/branch-section.l: New stderr output.
* testsuite/gas/mips/branch-section.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
gas/
* config/tc-mips.c (s_option): Sanitize `.option picX'
pseudo-op.
* testsuite/gas/mips/option-pic-1.d: New test.
* testsuite/gas/mips/option-pic-2.l: New list test.
* testsuite/gas/mips/option-pic-1.s: New test source.
* testsuite/gas/mips/option-pic-2.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
gas/
* config/tc-mips.c (s_option): Reject `.option picX' if VxWorks
PIC.
* testsuite/gas/mips/option-pic-vxworks-1.l: New list test.
* testsuite/gas/mips/option-pic-vxworks-2.l: New list test.
* testsuite/gas/mips/option-pic-vxworks-1.s: New test source.
* testsuite/gas/mips/option-pic-vxworks-2.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
