Correct a regression from commit 8614eeee67 ("Traditional MIPS
patches"), <https://sourceware.org/ml/binutils/2000-07/msg00018.html>,
which caused symbols in linkonce or what is these days known as comdat
sections to be treated as external for the purpose of PIC relocation
generation even if their binding remains STB_LOCAL. This in turn
disabled GOT16/LO16 relocation pairing with references to such symbols,
as no complementing LO16 relocation is expected for external GOT16
references in the o32 ABI, which ultimately leads to link errors, e.g.:
ld: comdat-reloc.o: Can't find matching LO16 reloc against `foo' for R_MIPS_GOT16 at 0x24 in section `.text.bar[bar]'
as with the LD test case included with this change.
Revert the special case for symbols in comdat sections then, making code
actually match `adjust_reloc_syms' as indicated in its explanatory
comment, and adjust calling code accordingly. Also bring back the
corresponding description of what now is `s_is_linkonce', lost with
commit 5f0fe04bc5 ("Improved MIPS16/MIPS32 code intermixing for
gas."), <https://www.sourceware.org/ml/binutils/2006-07/msg00039.html>.
gas/
PR gas/20649
* config/tc-mips.c (pic_need_relax): Don't check for linkonce
symbols, remove the `segtype' parameter.
(mips_frob_file, md_estimate_size_before_relax): Adjust
accordingly.
(s_is_linkonce): Add an explanatory comment.
* testsuite/gas/mips/comdat-reloc.d: New test.
* testsuite/gas/mips/comdat-reloc.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new test.
ld/
PR gas/20649
* testsuite/ld-mips-elf/mips-elf.exp: Add PIC comdat GOT16/LO16
relocation pairing link test.
Bit 24 of the indexed element vcmla decode mask was incorrectly
left unset. This could cause incorrect disassembly of some
currently undefined instructions as vcmla.
Rotatation immediates were not printed correctly in the disassembly
(could print 170 and 280 instead of 180 and 270).
opcodes/
* arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
gas/
* testsuite/gas/arm/armv8_3-a-simd.s: Add vcmla tests.
* testsuite/gas/arm/armv8_3-a-simd.d: Update.
PR 21059
binutils* arlex.l: Support processing with flex 2.6.3.
* deflex.l: Likewise.
gas * config/bfin-lex.l: Support processing with flex 2.6.3.
* itbl-lex.l: Likewise.
* read.c (temp_ilp): New function. Installs a temporary input
line pointer.
(restore_ilp): New function. Restores the original input line
pointer.
* read.h (temp_ilp): Prototype.
(restore_ilp): Prototype.
* stabs.c (dot_func_p): Use bfd_boolean type.
(generate_asm_file): Use temp_ilp and restore_ilp.
(stabs_generate_asm_lineno): Likewise.
(stabs_generate_asm_endfunc): Likewise.
bfd * config.bfd: Add entries for i686-redox and x86_64-redox.
gas * configure.tgt: Add entry for i386-redox.
ld * configure.tgt: Add entries for x86-redox and x86_64-redox.
gas/
* read.c (emit_leb128_expr): Extended unsigned big number for
sleb128.
* testsuite/gas/all/gas.exp (test_cond): Add sleb128-8 test.
* testsuite/gas/all/sleb128.d: New test.
* testsuite/gas/all/sleb128.s: New test source.
Previously, some pseudoinstructions like "call" only accepted
symbolic addresses and rejected constant addresses with an
esoteric internal error. This patch enables them by deferring
application of constant relocations to md_apply_fix, rather than
eagerly applying them during instruction assembly.
gas/ChangeLog
2017-01-09 Andrew Waterman <andrew@sifive.com>
* config/tc-riscv.c (append_insn): Don't eagerly apply relocations
against constants.
(md_apply_fix): Mark relocations against constants as "done."
TLS relocs against constants previously segfaulted, and illegal
symbol subtractions were silently ignored.
The previous behavior was to segfault.
gas/ChangeLog
2017-01-09 Andrew Waterman <andrew@sifive.com>
* config/tc-riscv.c (md_apply_fix): Report TLS relocations against
constants. Report disallowed symbol subtractions.
This was added so compressed loads could have smaller offsets for
accessing the data section, but the result was that writable sections
ended up in INITIAL_READONLY_SECTIONS. This is a bad idea. The fix is
to just remove this micro-optimization.
Thanks to Alan Morda for finding the problem!
ld/ChangeLog
2017-01-09 Palmer Dabbelt <palmer@dabbelt.com>
Kito Cheng <kito.cheng@gmail.com>
* emulparams/elf32lriscv-defs.sh (INITIAL_READONLY_SECTIONS):
Removed.
(SDATA_START_SYMBOLS): Likewise.
The weaker release consistency support of ARMv8.3-A is allowed as an optional
extension for ARMv8.2-A, so separate command line option and feature flag is
added: -march=armv8.2-a+rcpc turns LDAPR, LDAPRB, LDAPRH instructions on.
opcodes/
* aarch64-tbl.h (RCPC, RCPC_INSN): Define.
(aarch64_opcode_table): Use RCPC_INSN.
include/
* opcode/aarch64.h (AARCH64_FEATURE_RCPC): Define.
(AARCH64_ARCH_V8_3): Update.
gas/
* config/tc-aarch64.c (aarch64_features): Add rcpc.
* doc/c-aarch64.texi (AArch64 Extensions): Document rcpc.
* testsuite/gas/aarch64/ldst-exclusive-armv8_3.d: Rename to ...
* testsuite/gas/aarch64/ldst-rcpc.d: This.
* testsuite/gas/aarch64/ldst-exclusive-armv8_3.s: Rename to ...
* testsuite/gas/aarch64/ldst-rcpc.s: This.
* testsuite/gas/aarch64/ldst-rcpc-armv8_2.d: New test.
gas * config/tc-riscv.c (riscv_set_arch): Whitelist the "q" ISA
extension.
(riscv_after_parse_args): Set FLOAT_ABI_QUAD when the Q ISA is
enabled and no other ABI is specified.
include * opcode/riscv-opc.h: Add support for the "q" ISA extension.
opcodes * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
extension.
* riscv-opcodes/all-opcodes: Likewise.
The PRU GAS port I originally submitted does not build on 32bit hosts.
This patch fixes it by aligning md_number_to_chars's definition with
the global declaration in tc.h.
Here is the original bug report I got:
https://github.com/rcn-ee/repos/pull/23#issuecomment-269915175
* config/tc-pru.c (md_number_to_chars): Fix parameter to be
valueT, as declared in tc.h.
(md_apply_fix): Fix to work on 32-bit hosts.
Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
Add ASMACRO instruction support as per the MIPS16e ASE architecture
specifications [1][2], completing MIPS16e instruction set support.
[1] "MIPS32 Architecture for Programmers, Volume IV-a: The MIPS16e
Application-Specific Extension to the MIPS32 Architecture", MIPS
Technologies, Inc., Document Number: MD00076, Revision 2.63, July
16, 2013, Section 4.1 "MIPS16e Instruction Descriptions", p. 65
[2] "MIPS64 Architecture for Programmers, Volume IV-a: The MIPS16e
Application-Specific Extension to the MIPS64 Architecture", MIPS
Technologies, Inc., Document Number: MD00077, Revision 2.60, June
25, 2008, Section 1.1 "MIPS16e Instruction Descriptions", p. 66
include/
* opcode/mips.h: Document `0', `1', `2', `3', `4' and `s'
operand codes.
opcodes/
* mips16-opc.c (decode_mips16_operand): Add `0', `1', `2', `3',
`4' and `s' operand codes.
(mips16_opcodes): Add "asmacro" entry.
binutils/
* testsuite/binutils-all/mips/mips16-extend-insn.d: Update for
ASMACRO support.
gas/
* testsuite/gas/mips/mips16-asmacro.d: New test.
* testsuite/gas/mips/mips16-32@mips16-asmacro.d: New test.
* testsuite/gas/mips/mips16-64@mips16-asmacro.d: New test.
* testsuite/gas/mips/mips16-asmacro.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
Simplify extended operand handling and only specially process immediates
which require bit shuffling, using the generic operand insertion and
extraction handlers for the '<' (5-bit shift amount) operand code in
particular. Require the least significant bit of all extended operand
forms to be (artificially) set to 0 for their special processing to
trigger.
gas/
* config/tc-mips.c (mips16_immed): Limit `mips16_immed_extend'
use to operands whose LSB position is zero.
opcodes/
* mips-dis.c (print_mips16_insn_arg): Simplify processing of
extended operands.
* mips16-opc.c (decode_mips16_operand): Switch the extended
form of the `<' operand type to LSB position 22.
Bail out right away when an unextended instruction encoding is required
either with the use of a `.t' suffix or by means of `.set noautoextend',
however an operand supplied requires the extended instruction form to be
used.
This is to avoid messing up with the internal state of the assembler,
even though no actual failures are known to happen as a result. Add
test cases for the situation concerned.
gas/
* config/tc-mips.c (match_mips16_insn): Don't update
`forced_insn_length' or the instruction opcode if an operand
requires an extended instruction form, but an unextended one
has been requested.
* testsuite/gas/mips/mips16-relax-unextended-1.d: New test.
* testsuite/gas/mips/mips16-relax-unextended-2.d: New test.
* testsuite/gas/mips/mips16-relax-unextended-1.l: New stderr
output.
* testsuite/gas/mips/mips16-relax-unextended-2.l: New stderr
output.
* testsuite/gas/mips/mips16-relax-unextended-1.s: New test
source.
* testsuite/gas/mips/mips16-relax-unextended-2.s: New test
source.
* testsuite/gas/mips/mips.exp: Run the new tests.
Replace `0' and `4' operand codes with `.' and `F' respectively to free
up the `0'-`4' consecutive range. No functional change.
gas/
* config/tc-mips.c (mips16_macro_build): Replace `0' and `4'
operand codes with `.' and `F' respectively.
(mips16_macro): Likewise.
include/
* opcode/mips.h: Replace `0' and `4' operand codes with `.' and
`F' respectively.
opcodes/
* mips16-opc.c (decode_mips16_operand): Replace `0' and `4'
operand codes with `.' and `F' respectively.
(mips16_opcodes): Likewise.
Identify non-extensible instructions in the MIPS16 opcode table and
disallow their use with the `.e' instruction size suffix in assembly and
do not interpret any EXTEND prefix present as a part of the instruction
in disassembly.
According to all versions of the MIPS16 ASE specifications the following
instructions encodings are not extensible [1][2][3][4][5][6]: I8/MOV32R,
I8/MOVR32, all RRR minor opcodes, all RR minor opcodes except from DSRA
and DSRL, and EXTEND itself, and as from revision 2.50 of the MIPS16e
ASE specifications it has been further clarified what was previously
implied, that non-extesiable instructions when preceded with an EXTEND
prefix must cause a Reserved Instruction exception [3][5].
Therefore in the presence of an EXTEND prefix none of these instructions
are supposed to be handled as extended instructions and supporting these
forms in disassembly causes confusion, and in the case of the RRR major
opcode it also clashes with the ASMACRO encoding.
References:
[1] "Product Description, MIPS16 Application-Specific Extension",
Version 1.3, MIPS Technologies, Inc., 970130, Table 3. "MIPS16
Instruction Set Summary", p. 5
[2] same, Table 5 "RR Minor Opcodes (RR-type instructions)", p.10
[3] "MIPS32 Architecture for Programmers, Volume IV-a: The MIPS16e
Application-Specific Extension to the MIPS32 Architecture", MIPS
Technologies, Inc., Document Number: MD00076, Revision 2.63, July
16, 2013, Section 3.9 "MIPS16e Instruction Summaries", pp. 37-39
[4] same, Section 3.15 "Instruction Bit Encoding", pp. 46-49
[5] "MIPS64 Architecture for Programmers, Volume IV-a: The MIPS16e
Application-Specific Extension to the MIPS64 Architecture", MIPS
Technologies, Inc., Document Number: MD00077, Revision 2.60, June
25, 2008, Section 1.9 "MIPS16e Instruction Summaries", pp. 38-41
[6] same, Section 1.15 "Instruction Bit Encoding", pp. 48-51
include/
* opcode/mips.h (INSN2_SHORT_ONLY): New macro.
gas/
* config/tc-mips.c (is_size_valid_16): Disallow a `.e' suffix
instruction size override for INSN2_SHORT_ONLY opcode table
entries.
* testsuite/gas/mips/mips16-extend-swap.d: Adjust output.
* testsuite/gas/mips/mips16-macro-e.l: Adjust error messages.
* testsuite/gas/mips/mips16-32@mips16-macro-e.l: Adjust error
messages.
* testsuite/gas/mips/mips16e-32@mips16-macro-e.l: Adjust error
messages.
* testsuite/gas/mips/mips16-insn-e.d: New test.
* testsuite/gas/mips/mips16-insn-t.d: New test.
* testsuite/gas/mips/mips16-32@mips16-insn-e.d: New test.
* testsuite/gas/mips/mips16-64@mips16-insn-e.d: New test.
* testsuite/gas/mips/mips16e-32@mips16-insn-e.d: New test.
* testsuite/gas/mips/mips16-32@mips16-insn-t.d: New test.
* testsuite/gas/mips/mips16-64@mips16-insn-t.d: New test.
* testsuite/gas/mips/mips16e-32@mips16-insn-t.d: New test.
* testsuite/gas/mips/mips16-insn-e.l: New stderr output.
* testsuite/gas/mips/mips16-insn-t.l: New stderr output.
* testsuite/gas/mips/mips16-32@mips16-insn-e.l: New stderr
output.
* testsuite/gas/mips/mips16-64@mips16-insn-e.l: New stderr
output.
* testsuite/gas/mips/mips16e-32@mips16-insn-e.l: New stderr
output.
* testsuite/gas/mips/mips16-32@mips16-insn-t.l: New stderr
output.
* testsuite/gas/mips/mips16-64@mips16-insn-t.l: New stderr
output.
* testsuite/gas/mips/mips16e-32@mips16-insn-t.l: New stderr
output.
* testsuite/gas/mips/mips16-insn-e.s: New test source.
* testsuite/gas/mips/mips16-insn-t.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
opcodes/
* mips-dis.c (print_insn_mips16): Disallow EXTEND prefix
matching for INSN2_SHORT_ONLY opcode table entries.
* mips16-opc.c (SH): New macro.
(mips16_opcodes): Set SH in `pinfo2' for non-extensible
instruction entries: "nop", "addu", "and", "break", "cmp",
"daddu", "ddiv", "ddivu", "div", "divu", "dmult", "dmultu",
"drem", "dremu", "dsllv", "dsll", "dsrav", "dsra", "dsrlv",
"dsrl", "dsubu", "exit", "entry", "jalr", "jal", "jr", "j",
"jalrc", "jrc", "mfhi", "mflo", "move", "mult", "multu", "neg",
"not", "or", "rem", "remu", "sllv", "sll", "slt", "sltu",
"srav", "sra", "srlv", "srl", "subu", "xor", "sdbbp", "seb",
"seh", "sew", "zeb", "zeh", "zew" and "extend".
binutils/
* testsuite/binutils-all/mips/mips16-extend-insn.d: New test.
* testsuite/binutils-all/mips/mips16-extend-insn.s: New test
source.
* testsuite/binutils-all/mips/mips.exp: Run the new tests.
Remove special casing for the `6' operand code used for the embedded
trap code of the BREAK and the SDBBP instructions to support supposedly
extended forms of these instructions.
According to all versions of the MIPS16 ASE specifications these
instructions are not extensible [1][2][3][4][5][7][8][10][11], and as
from revision 2.50 of the MIPS16e ASE specifications it has been further
clarified what was previously implied, that non-extesiable instructions
when preceded with an EXTEND prefix must cause a Reserved Instruction
exception [5][6][9][10].
Therefore supposedly extended BREAK and SDBBP instructions do not serve
their purpose anymore as they do not cause a Bp and a Debug exception
respectively and supporting these forms in disassembly only causes
confusion.
References:
[1] "Product Description, MIPS16 Application-Specific Extension",
Version 1.3, MIPS Technologies, Inc., 970130, Table 3. "MIPS16
Instruction Set Summary", p. 5
[2] same, Table 5 "RR Minor Opcodes (RR-type instructions)", p.10
[3] same, Table 18. "Extendable MIPS16 Instructions", p. 24
[4] "MIPS32 Architecture for Programmers, Volume IV-a: The MIPS16e
Application-Specific Extension to the MIPS32 Architecture", MIPS
Technologies, Inc., Document Number: MD00076, Revision 2.63, July
16, 2013, Table 3.8 "MIPS16e Special Instructions", p. 38
[5] same, Section 3.11 "MIPS16e Extensible Instructions, p. 41
[6] same, Table 3.15 "MIPS16e Extensible Instructions", p. 41
[7] same, Table 3.24 "MIPS16e RR Encoding of the Funct Field", p. 49
[8] "MIPS64 Architecture for Programmers, Volume IV-a: The MIPS16e
Application-Specific Extension to the MIPS64 Architecture", MIPS
Technologies, Inc., Document Number: MD00077, Revision 2.60, June
25, 2008, Table 1.8 "MIPS16e Special Instructions", p. 39
[9] same, Section 1.11 "MIPS16e Extensible Instructions", p. 42
[10] same, Table 1.15 "MIPS16e Extensible Instructions", pp. 42-43
[11] same, Table 1.24 "MIPS16e RR Encoding of the Funct Field", p. 50
gas/
* config/tc-mips.c (match_mips16_insn): Remove the `6' operand
code special case and its associated comment.
opcodes/
* mips16-opc.c (decode_mips16_operand) <'6'>: Remove extended
encoding support.
Correct the handling of `.e' and `.t' instruction size suffixes with
instruction mnemonics which are not followed by any text on the same
line, such as arguments or white space, e.g.:
$ cat test.s
.set mips16
foo:
entry.t # comment
entry.t
exit.t # comment
exit.t
nop.t # comment
nop.t
$ as -32 -o test.o test.s
test.s: Assembler messages:
test.s:4: Error: unrecognized opcode `entry.t'
test.s:6: Error: unrecognized opcode `exit.t'
test.s:8: Error: unrecognized opcode `nop.t'
$
gas/
* config/tc-mips.c (mips16_ip): Handle `.e' and `.t' instruction
suffixes followed by a null character rather than a space too.
* testsuite/gas/mips/mips16-insn-length-noargs.d: New test.
* testsuite/gas/mips/mips16-insn-length-noargs.s: New test
source.
* testsuite/gas/mips/mips.exp: Run the new test.
Do not allow any explicitly coded EXTEND instruction to be automatically
scheduled into a jump delay slot, as an EXTEND prefix is coupled with
the next regular MIPS16 instruction and therefore swapping it with a
jump would change program's semantics; EXTEND is not architecturally
allowed to be present in a jump delay slot anyway.
opcodes/
* mips16-opc.c (mips16_opcodes): Set NODS in `pinfo' for
"extend".
gas/
* testsuite/gas/mips/mips16-extend-swap.d: New test.
* testsuite/gas/mips/mips16-extend-swap.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new test.
This patch syncs the generated data structure in tc-msp430.c with the
latest version of devices.csv released by TI.
My understanding is that the devices being removed were "invalid spins",
so can't be being used by anyone, and never will be. Current web
searches related to these devices return no relevant results.
Built and tested (no regressions) as follows:
Configured with: --target=msp430-elf --disable-gdb
Test variations:
msp430-sim/-mcpu=msp430
msp430-sim/-mcpu=msp430x
msp430-sim/-mcpu=msp430x/-mlarge/-mdata-region=either/-mcode-region=either
msp430-sim/-mhwmult=none
msp430-sim/-mhwmult=f5series
gas/
* config/tc-msp430.c (msp430_mcu_data): Sync with data from TI's
devices.csv file as of September 2016.
Previously, the alignment directives were not correctly supported
in the text section when current alignment was only 1 byte (i.e.,
when the address was odd). Since there are no 1-byte instructions
in RISC-V, this patch resolves the bug by writing a zero byte to
obtain 2-byte alignment, at which point a 2-byte NOP can be used
to obtain 4-byte alignment.
Resolves https://github.com/riscv/riscv-gnu-toolchain/issues/205
* config/tc-riscv.c (riscv_make_nops): Emit 2-byte NOPs.
(riscv_frag_align_code): Correct frag_align_code arg.
gas/
* doc/c-lm32.texi: Fix chars with high bit set.
* testsuite/gas/bfin/vector2.s: Likewise.
gold/
* arm.cc: Fix comment chars with high bit set.
include/
* coff/pe.h: Fix comment chars with high bit set.
* opcode/xgate.h: Likewise.
ld/
* testsuite/ld-scripts/sysroot-prefix.exp: Fix chars with high bit set.
Limit MIPS16 instruction disassembly according to the ISA level and ASE
set selected, as with the regular MIPS and microMIPS instruction sets.
Retain the property of `objdump -m mips:16' disassembling all MIPS16
instructions however, regardless of any ISA level recorded in the binary
examined.
To validate the disassembler use the GAS test suite for its convenience
of running tests across multiple ISAs, even though placing the tests in
the binutils test suite would be more appropriate. Adjust the single
binutils test which depends on 64-bit instruction disassembly to have
the ISA level required actually recorded in the binary examined.
opcodes/
* mips-dis.c (mips_arch_choices): Use ISA_MIPS64 rather than
ISA_MIPS3 as the `isa' selection in the `bfd_mach_mips16' entry.
(print_insn_mips16): Check opcode entries for validity against
the ISA level and ASE set selected.
binutils/
* testsuite/binutils-all/mips/mips16-undecoded.s: Use `.module'
rather than `.set' to set the ISA level.
gas/
* testsuite/gas/mips/mips16-sub.d: New test.
* testsuite/gas/mips/mips16-32@mips16-sub.d: New test.
* testsuite/gas/mips/mips16e-32@mips16-sub.d: New test.
* testsuite/gas/mips/mips16e-sub.d: New test.
* testsuite/gas/mips/mips16-32@mips16e-sub.d: New test.
* testsuite/gas/mips/mips16-64@mips16e-sub.d: New test.
* testsuite/gas/mips/mips16e-64-sub.d: New test.
* testsuite/gas/mips/mips16-32@mips16e-64-sub.d: New test.
* testsuite/gas/mips/mips16-64@mips16e-64-sub.d: New test.
* testsuite/gas/mips/mips16e-32@mips16e-64-sub.d: New test.
* testsuite/gas/mips/mips16-sub.s: New test source.
* testsuite/gas/mips/mips16e-sub.s: New test source.
* testsuite/gas/mips/mips16e-64-sub.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
Add a RESTORE instruction smoke test to the `mips16e' GAS test.
gas/
* testsuite/gas/mips/mips16e.s: Add a RESTORE instruction.
* testsuite/gas/mips/mips16e.d: Adjust accordingly.
Run the `mips16', `mips16-64', `mips16e-64', `mips16-macro',
`mips16-macro-e' and `mips16-macro-t' GAS tests over multiple MIPS16
ISAs.
gas/
* testsuite/gas/mips/mips16.d: Adjust test for multiple MIPS16
ISA testing.
* testsuite/gas/mips/mips16-64.d: Adjust test for multiple
MIPS16 ISA testing.
* testsuite/gas/mips/mips16e-64.d: Adjust test for multiple
MIPS16 ISA testing.
* testsuite/gas/mips/mips16-macro.d: Adjust test for multiple
MIPS16 ISA testing.
* testsuite/gas/mips/mips16e-64.s: Ensure MIPS16 ISA annotation.
* testsuite/gas/mips/mips16e-64.l: Rename to...
* testsuite/gas/mips/mips16e-32@mips16e-64.l: ... this.
* testsuite/gas/mips/mips16-64@mips16.d: New test.
* testsuite/gas/mips/mips16-64@mips16-64.d: New test.
* testsuite/gas/mips/mips16e-32@mips16e-64.d: New test.
* testsuite/gas/mips/mips16-32@mips16-macro.d: New test.
* testsuite/gas/mips/mips16-64@mips16-macro.d: New test.
* testsuite/gas/mips/mips16e-32@mips16-macro.d: New test.
* testsuite/gas/mips/mips16-32@mips16-macro-e.d: New test.
* testsuite/gas/mips/mips16e-32@mips16-macro-e.d: New test.
* testsuite/gas/mips/mips16-32@mips16-macro-t.d: New test.
* testsuite/gas/mips/mips16e-32@mips16-macro-t.d: New test.
* testsuite/gas/mips/mips16e-32@mips16e-64.l: New stderr output.
* testsuite/gas/mips/mips16-32@mips16-macro.l: New stderr
output.
* testsuite/gas/mips/mips16e-32@mips16-macro.l: New stderr
output.
* testsuite/gas/mips/mips16-32@mips16-macro-e.l: New stderr
output.
* testsuite/gas/mips/mips16e-32@mips16-macro-e.l: New stderr
output.
* testsuite/gas/mips/mips16-32@mips16-macro-t.l: New stderr
output.
* testsuite/gas/mips/mips16e-32@mips16-macro-t.l: New stderr
output.
* testsuite/gas/mips/mips.exp: Run `mips16', `mips16-64',
`mips16-macro', `mips16-macro-t', `mips16-macro-e' and
`mips16e-64' testing across multiple MIPS16 ISAs. Fold
`mips16-macro' and `mips16e-64' list test invocations into
corresponding dump tests.
Implement individual MIPS16 ISA GAS testing for the 32-bit and 64-bit
variants of the base MIPS16 and the MIPS16e ISA each.
gas/
* testsuite/gas/mips/mips.exp (run_dump_test_arch): Add
`mips16e' and `mips16' prefixes.
(run_list_test_arch): Likewise.
Rename `mips16' architecture to `mips16-32'. Add `mips16-64',
`mips16e-32' and `mips16e-64' architectures. Update `rol64',
`mips16e', `elf${el}-rel2' and `elf-rel4' test invocations
accordingly.
* testsuite/gas/mips/mips16e@branch-swap-3.d: New test.
* testsuite/gas/mips/mips16e@branch-swap-4.d: New test.
* testsuite/gas/mips/mips16e@loc-swap-dis.d: New test.
* testsuite/gas/mips/mips16e@loc-swap.d: New test.
Pad alignment with zeros rather than NOP instructions, for sensible
multi-ISA MIPS16 testing.
gas/
* testsuite/gas/mips/loc-swap.s: Use zeros rather than NOPs for
trailing alignment padding.
* testsuite/gas/mips/loc-swap.d: Adjust accordingly.
* testsuite/gas/mips/micromips@loc-swap.d: Likewise.
* testsuite/gas/mips/mips16@loc-swap-dis.d: Likewise.
Switch to 32-bit MIPS16 opcode table entry interpretation, similar to
how the microMIPS opcode table is handled, for both the `match' and
`mask' fields, removing special casing for JAL and JALX instructions and
their `a' and `i' operand codes throughout, while retaining automatic
processing of extendable opcodes in assembly and disassembly.
In assembly disallow size enforcement suffixes as appropriate: `.t' for
both 32-bit instructions and macros and `.e' for macros only, making
macro handling consistent with the microMIPS instruction set.
In disassembly fully decode EXTEND prefixes prepended to unsupported
instruction encodings (according to the ISA selection) rather than
dumping them as hexadecimal data along with the following instruction,
removing all special casing for the EXTEND prefix and making its
handling rely on its opcode table entry, except where it is considered a
part of an extendable instruction.
include/
* opcode/mips.h (mips_opcode_32bit_p): New inline function.
gas/
* config/tc-mips.c (micromips_insn_length): Use
`mips_opcode_32bit_p'.
(is_size_valid): Adjust description.
(is_size_valid_16): New function.
(validate_mips_insn): Use `mips_opcode_32bit_p' in MIPS16
operand decoding.
(validate_mips16_insn): Remove `a' and `i' operand code special
casing, use `mips_opcode_32bit_p' to determine instruction
width.
(append_insn): Adjust forced MIPS16 instruction size
determination.
(match_mips16_insn): Likewise. Don't shift the instruction's
opcode with the `a' and `i' operand codes. Use
`mips_opcode_32bit_p' in operand decoding.
(match_mips16_insns): Check for forced instruction size's
validity.
(mips16_ip): Don't force instruction size in the `noautoextend'
mode.
* testsuite/gas/mips/mips16-jal-e.d: New test.
* testsuite/gas/mips/mips16-jal-t.d: New test.
* testsuite/gas/mips/mips16-macro-e.d: New test.
* testsuite/gas/mips/mips16-macro-t.d: New test.
* testsuite/gas/mips/mips16-jal-t.l: New stderr output.
* testsuite/gas/mips/mips16-macro-e.l: New stderr output.
* testsuite/gas/mips/mips16-macro-t.l: New stderr output.
* testsuite/gas/mips/mips16-jal-e.s: New test source.
* testsuite/gas/mips/mips16-jal-t.s: New test source.
* testsuite/gas/mips/mips16-macro-e.s: New test source.
* testsuite/gas/mips/mips16-macro-t.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
opcodes/
* mips-dis.c (print_mips16_insn_arg): Always handle `extend' and
`insn' together, with `extend' as the high-order 16 bits.
(match_kind): New enum.
(print_insn_mips16): Rework for 32-bit instruction matching.
Do not dump EXTEND prefixes here.
* mips16-opc.c (mips16_opcodes): Move "extend" entry to the end.
Recode `match' and `mask' fields as 32-bit in absolute "jal" and
"jalx" entries.
binutils/
* testsuite/binutils-all/mips/mips16-extend-noinsn.d: Adjust
test for separate EXTEND prefix disassembly.
Limit the DDIV, DDIVU, DREM, DREMU and DSUBU macros to the MIPS III
rather than MIPS I ISA. These macros expand to machine code sequences
including 64-bit instructions which require a 64-bit ISA. Entries for
those instructions are already correctly marked, however the marking is
ignored if entries are used in the process of macro expansion rather
than directly, making it possible to indirectly produce 64-bit machine
code even when output requested has been limited to a 32-bit ISA.
opcodes/
* mips16-opc.c (mips16_opcodes): Set membership to I3 rather
than I1 for the "ddiv", "ddivu", "drem", "dremu" and "dsubu"
INSN_MACRO entries.
gas/
* testsuite/gas/mips/mips16-macro.l: New list test.
* testsuite/gas/mips/mips.exp: Run the new test.
Limit the `SD ra, offset(sp)' instruction (I64/SDRASP major/minor
opcode) to the MIPS III rather than MIPS I ISA. This is a 64-bit
instruction requiring a 64-bit ISA. This bug has been there since
forever.
opcodes/
* mips16-opc.c (mips16_opcodes): Set membership to I3 rather
than I1 for the SP-relative "sd"/$ra entry (SDRASP minor
opcode).
gas/
* testsuite/gas/mips/mips16-sdrasp.d: New test.
* testsuite/gas/mips/mips16-sdrasp.l: New stderr output.
* testsuite/gas/mips/mips16-sdrasp.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new test.
Nick Clifton
Maciej W. Rozycki
Szabolcs Nagy
Bernhard Rosenkranzer
Nathan Sidwell
Igor Tsimbalist
Jeremy Soller
Tristan Gingold
Andrew Waterman
Palmer Dabbelt
Norm Jacobs
Kito Cheng
Dimitar Dimitrov
Alan Modra
Joe Seymour
Tim Newsome