Now that the Blackfin libgloss code extracts the 2nd result and the
error code from the R1/R2 registers, have the sim fill them up.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The LSHIFT/ASHIFT insns that work with accumulators lacked AV/AVS
handling in the ASTAT register, so add it to match the hardware.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
If we're shifting accumulators, we don't want to touch the V bit in
ASTAT, so add size checks to the ashiftrt/lshiftrt helpers.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The logical shift insn does not sign extend before shifting, so
we shouldn't either.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This too should have been squashed into an earlier change. It covers
a few more cases in the V/VS saturation patch when working with TFU
and FU modes of dsp insns.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
When the shift magnitude exceeds 32 bits, the values rotate around (since
the hardware is actually a barrel shifter). So handle this edge case,
update the corresponding AV bit in ASTAT which was missing previously,
and tweak the AZ setting based on how the hardware behaves.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The shift magnitude is a 5-bit signed value. When it is between 0 and
15, then we do the requested shift, but when it is outside of that, we
have to do the opposite.
That means we flip between lshift and ashiftrt to match the hardware.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This reverts the previous commit and does it right. This change got
lost in the shuffle of patches I have pending.
Basically the logic is to change the 32bit saturation (and then masked
to 16bits) to a proper 16bit saturation.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Some saturation cases with dsp mac insns were not setting the V flag.
So implement that part and split up the logic between the dual macs.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Our handling of the M_IU/M_TFU modes are missing signed saturation when
the MM flag is set, so add it to match the hardware behavior.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
After testing the hardware with all the different dsp flags, the MM flag
triggers sign extension in all modes. So drop the limited use of it, and
the local custom helper that was also extending unsigned values. We also
can see that the flag checks in the mult/mac insns have the same behavior
with sign extending, so add a helper func to keep the logic the same in
both places.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
When using the IH modifier, we need to first saturate the value before
rounding it, and then further saturate it a bit more. This makes the
sim match the hardware behavior with these insns.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
When the accumulator saturates, it needs to be greater than, but not
equal to, the largest unsigned value as this is what the hardware does.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The BF537 family glues a bunch of peripherals into single interrupt lines
that run into the SIC. To model this same behavior in the sim, we need to
use the glue-or device, and in order to use that, we need to tweak things
a bit in the mach code to allow declaring of these new devices.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The machs.c file is the best place for holding cpu-specific details, so
restructure the way the SIC manages its ports to do just that. Now the
SIC's have a standard set of input pins and the different line routing
from peripherals is kept in the device tree only. This better models
the hardware where the SIC doesn't care about the exact peripheral that
is sending it stuff, just which input pin it gets it on.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Now that the common code supports the syscall trace level, change the
Blackfin code from using the event level to the syscall level.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Pull the model data (register addresses/sizes) out of the different model
files and into the machs.h header. The models themselves don't care about
where they're mapped, only the mach code does. This allows us to keep the
model headers from being included in the mach code which can cause issues
with model-specific names colliding. Such as when a newer device model is
created, but with incompatible register names/layouts.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The UART has a LOOP_ENA bit in its MCR register where writes to the THR
go to the RBR. Implement support for this mode.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
A few bits in the newer UART LSR register are not sticky, so make sure
we clear them when returning updated status rather than leaving them
always set.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Make all of the pins bidirectional, and support sending signals when
software drives the pins as outputs.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
When the mask a/b MMRs are written, the output signal might change levels
(as pins are [un]masked), so make sure we update the output level.
Further, make sure we handle edge ints correctly by first sending a high
signal followed by a low signal.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
A bunch of 32bit insns were not using the store buffer, so when they were
used in parallel insns, they would incorrectly clobber a register early.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
When most video related insns are used in parallel with Ireg loads, the
DISALGNEXCPT insn behavior is implicitly in effect.
Reported-by: Anton Shokurov <shokurov.anton.v@yandex.ru>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The SIC latches ints from peripherals to the CEC, but the peripherals
need to be able to tell the SIC when to stop. So use the incoming level
to figure out when to set the int bits and when to clear it.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This doesn't currently generate any interrupts (as there doesn't appear
to be any documentation to *when* it would even do so), but since the
HRM does say an interrupt line exists between the OTP and the SIC, add
one for completeness sake. This will make a follow up patch easier.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The current implementation attempts to handle the 16bit sign extension
itself. Unfortunately, it gets it right in some cases. So rather than
fix that logic, just drop it in favor of using 16bit signed casts. Now
gcc will take care of getting the logic right.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The current handling of the subtraction insn with the RND12 modifier
works when saturation isn't involved. So add handling for this edge
case to match the hardware.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The 16bit add/sub insns missed setting the VS bit in ASTAT whenever the
V bit was also set.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Makes it a lot easier to find out what's going on with interrupt lines
if the ports have tracing output.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
We need the DIR bit cleared, not set, in order for the pin to be treated
as an input.
When looking up the data value, we need to shift the "level" value over by
"my_port" rather than "bit" as the latter has already been shifted over.
We also should normalize the "level" coming in from the outside worlds to
the set of {0,1} since those are the only values that matter to GPIOs.
We need the BOTH bit set, not cleared, in order for the pin to trigger
on both edges.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The clear/set/toggle MMRs aren't backed by "real" data; they implicitly
perform bit operations on the associated data register. So when we go
to process writes to them, we need to adjust the pointer accordingly so
that the actual backing data is modified.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
When I originally wrote the w1c helper funcs, I used it in a few places.
Then I forgot how it worked and when I later documented it, I described
the 3rd arg in the exact opposite way it is actually used. This error
propagated to a bunch of devices registers that were not explicitly
tested (a bunch of the devices are stubs which merely exist to say "no
device is connected" to make device drivers happy).
So once the documentation is unscrewed, fix all of the broken call sites.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
We'll need these bits in an upcoming patch, so map out the whole
LSR MMR now.
Fix up indentation style while we're here.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The Blackfin PRM says that the top 8 bits of the accumulator must be
cleared when using the VIT_MAX insn, so the sim has followed this spec.
Matching the hardware behavior though when the high bits are not cleared
is easy to do and doesn't break existing behavior, so go for it.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The Blackfin PRM does not cover this case, but the hardware is clear: even
if the search criteria is not met (and thus a new 16bit value is loaded up
into the accumulator), the accumulator undergoes 16bit sign extension. So
simply reload the low signed 16bits in that case.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The Acc=-Acc insn can overflow or carry with edge values, so make sure
we update the ASTAT bits accordingly to match the hardware. Also fix
a thinko where we always updated AC0 even when working with A1 regs.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
When encoding the SIC/pin info into unique input port ids, I used bases
of 100 when I meant to use 0x100. Rather than simply fix the decoding
math in the different functions, create a few helper macros to simplify
the SIC/pin encoding and decoding steps. This makes the resulting tables
nice & clear.
And now that pins are clear, the 533 and 537 port_event handlers may
easily be merged into one.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The hardware allows the byteop[123]p insns to use the same src reg pair,
so remove the combination check in the sim.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The bus addresses have to be valid numbers, so 'g' and 'h' won't work.
Oddly, the common code silently ignored this which is why I didn't notice
in the first place.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Mike Frysinger