Commit Graph

3665 Commits

Author SHA1 Message Date
Bob Wilson a02728c81d * config/tc-xtensa.c (init_op_placement_info_table): Check for formats
of the same length but different numbers of slots.
2006-04-03 19:11:05 +00:00
Andreas Schwab 9dfde49d60 * configure.in: Fix help string for --enable-targets option.
* configure: Regenerate.
2006-03-30 13:35:17 +00:00
Nathan Sidwell 6d89cc8f6b * gas/config/tc-m68k.c (find_cf_chip): Merge into ...
(m68k_ip): ... here.  Use for all chips.  Protect against buffer
	overrun and avoid excessive copying.
2006-03-28 07:21:49 +00:00
Nathan Sidwell 2da12c6027 gas:
* config/tc-m68k.c (m68000_control_regs, m68010_control_regs,
	m68020_control_regs, m68040_control_regs, m68060_control_regs,
	mcf_control_regs, mcf5208_control_regs, mcf5213_control_regs,
	mcf5329_control_regs, mcf5249_control_regs, mcf528x_control_regs,
	mcfv4e_control_regs, m68010_control_regs): Rename and reorder to ...
	(m68000_ctrl, m68010_ctrl, m68020_ctrl, m68040_ctrl, m68060_ctrl,
	mcf_ctrl, mcf5208_ctrl, mcf5213_ctrl, mcf5235_ctrl, mcf5249_ctrl,
	mcf5216_ctrl, mcf5250_ctrl, mcf5271_ctrl, mcf5272_ctrl,
	mcf5282_ctrl, mcfv4e_ctrl): ... these.
	(mcf5275_ctrl, mcf5329_ctrl, mcf5373_ctrl): New.
	(struct m68k_cpu): Change chip field to control_regs.
	(current_chip): Remove.
	(control_regs): New.
	(m68k_archs, m68k_extensions): Adjust.
	(m68k_cpus): Reorder to be in cpu number order.  Adjust.
	(CPU_ALLOW_MC, CPU_ALLOW_NEGATION): Remove.
	(find_cf_chip): Reimplement for new organization of cpu table.
	(select_control_regs): Remove.
	(mri_chip): Adjust.
	(struct save_opts): Save control regs, not chip.
	(s_save, s_restore): Adjust.
	(m68k_lookup_cpu): Give deprecated warning when necessary.
	(m68k_init_arch): Adjust.
	(md_show_usage): Adjust for new cpu table organization.

	include/opcodes:
	* m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
	cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
	cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
	cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
	cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
2006-03-28 07:19:16 +00:00
Bernd Schmidt 1ac4baeded * config/bfin-defs.h (Expr_Node_Type enum): Add Expr_Node_GOT_Reloc.
* config/bfin-lex.l: Recognize GOT17M4 and FUNCDESC_GOT17M4.
	* config/bfin-parse.y: Include "libbfd.h", "elf/common.h" and
	"elf/bfin.h".
	(GOT17M4, FUNCDESC_GOT17M4): New tokens of type <value>.
	(any_gotrel): New rule.
	(got): Use it, and create Expr_Node_GOT_Reloc nodes.
	* config/tc-bfin.c: Include "libbfd.h", "elf/common.h" and
	"elf/bfin.h".
	(DEFAULT_FLAGS, bfin_flags, bfin_pic_flag): New.
	(bfin_pic_ptr): New function.
	(md_pseudo_table): Add it for ".picptr".
	(OPTION_FDPIC): New macro.
	(md_longopts): Add -mfdpic.
	(md_parse_option): Handle it.
	(md_begin): Set BFD flags.
	(md_apply_fix3, bfin_fix_adjustable): Handle new relocs.
	(bfin_gen_ldstidxi): Adjust to match the trees that the parser gives
	us for GOT relocs.
	* Makefile.am (bfin-parse.o): Update dependencies.
	(DEPTC_bfin_elf): Likewise.
	* Makefile.in: Regenerate.
2006-03-26 01:12:07 +00:00
Richard Sandiford a9d3488055 bfd/
* cpu-m68k.c (bfd_m68k_compatible): Treat ISA A+ and ISA B code as
	incompatible.  Likewise MAC and EMAC code.
	* elf32-m68k.c (elf32_m68k_merge_private_bfd_data): Use
	bfd_get_compatible to set the new bfd architecture.  Rely on it
	to detect incompatibilities.

gas/
	* config/tc-m68k.c (m68k_cpus): Change cpu_cf5208 entries to use
	mcfemac instead of mcfmac.

ld/testsuite/
	* ld-m68k/merge-error-1a.s, ld-m68k/merge-error-1b.s,
	* ld-m68k/merge-error-1a.d, ld-m68k/merge-error-1b.d,
	* ld-m68k/merge-error-1c.d, ld-m68k/merge-error-1d.d,
	* ld-m68k/merge-error-1e.d, ld-m68k/merge-ok-1a.d,
	* ld-m68k/merge-ok-1b.d: New tests.
	* ld-m68k/m68k.exp: Run them.
2006-03-25 10:24:27 +00:00
H.J. Lu 9e61c69e1e 2006-03-23 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/rep.s: Pad with .p2align.
	* gas/i386/rep.d: Adjust.
2006-03-24 05:07:53 +00:00
Andreas Jaeger 7b81dfbbf9 Patch by matz@suse.de:
bfd/ChangeLog:
	* reloc.c: Add BFD_RELOC_X86_64_GOT64, BFD_RELOC_X86_64_GOTPCREL64,
	BFD_RELOC_X86_64_GOTPC64, BFD_RELOC_X86_64_GOTPLT64,
	BFD_RELOC_X86_64_PLTOFF64.
	* bfd-in2.h: Regenerated.
	* libbfd.h: Regenerated.
	* elf64-x86-64.c (x86_64_elf_howto_table): Correct comment.
	Add howtos for above relocs.
	(x86_64_reloc_map): Add mappings for new relocs.
	(elf64_x86_64_check_relocs): R_X86_64_GOT64, R_X86_64_GOTPCREL64,
	R_X86_64_GOTPLT64 need a got entry.  R_X86_64_GOTPLT64 also a PLT
	entry.  R_X86_64_GOTPC64 needs a .got section.  R_X86_64_PLTOFF64
	needs a PLT entry.
	(elf64_x86_64_gc_sweep_hook): Reflect changes from
	elf64_x86_64_check_relocs for the new relocs.
	(elf64_x86_64_relocate_section): Handle new relocs.

gas/ChangeLog:
	* config/tc-i386.c (type_names): Correct placement of 'static'.
	(reloc): Map some more relocs to their 64 bit counterpart when
	size is 8.
	(output_insn): Work around breakage if DEBUG386 is defined.
	(output_disp): A BFD_RELOC_64 with GOT_symbol as operand also
	needs to be mapped to BFD_RELOC_X86_64_GOTPC64 or
	BFD_RELOC_X86_64_GOTPC32.  Also x86-64 handles pcrel addressing
	different from i386.
	(output_imm): Ditto.
	(lex_got): Recognize @PLTOFF and @GOTPLT.  Make @GOT accept also
	Imm64.
	(md_convert_frag): Jumps can now be larger than 2GB away, error
	out in that case.
	(tc_gen_reloc): New relocs are passed through.  BFD_RELOC_64
	and BFD_RELOC_64_PCREL are mapped to BFD_RELOC_X86_64_GOTPC64.

gas/testsuite/ChangeLog:
	* gas/i386/reloc64.s: Accept 64-bit forms.
	* gas/i386/reloc64.d: Adjust.
	* gas/i386/reloc64.l: Adjust.

include/ChangeLog:
	* elf/x86-64.h: Add the new relocations with their official
	numbers.
2006-03-23 08:23:09 +00:00
Richard Sandiford 0a44bf6950 Richard Sandiford <richard@codesourcery.com>
Daniel Jacobowitz  <dan@codesourcery.com>
	Phil Edwards  <phil@codesourcery.com>
	Zack Weinberg  <zack@codesourcery.com>
	Mark Mitchell  <mark@codesourcery.com>
	Nathan Sidwell  <nathan@codesourcery.com>

bfd/
	* bfd-in2.h: Regenerate.
	* config.bfd (mips*-*-vxworks*, mips*el-*-vxworks*): New stanzas.
	* configure.in (bfd_elf32_bigmips_vxworks_vec): New stanza.
	(bfd_elf32_littlemips_vxworks_vec): Likewise.
	(bfd_elf32_bigmips_vec): Add elf-vxworks.lo.
	(bfd_elf32_littlemips_vec): Likewise.
	(bfd_elf32_nbigmips_vec): Likewise.
	(bfd_elf32_nlittlemips_vec): Likewise.
	(bfd_elf32_ntradbigmips_vec): Likewise.
	(bfd_elf32_ntradlittlemips_vec): Likewise.
	(bfd_elf32_tradbigmips_vec): Likewise.
	(bfd_elf32_tradlittlemips_vec): Likewise.
	(bfd_elf64_bigmips_vec): Likewise.
	(bfd_elf64_littlemips_vec): Likewise.
	(bfd_elf64_tradbigmips_vec): Likewise.
	(bfd_elf64_tradlittlemips_vec): Likewise.
	* elf32-mips.c: Include elf-vxworks.h.
	(mips_info_to_howto_rel): Use elf_backend_mips_rtype_to_howto
	instead of calling mips_elf32_rtype_to_howto directly.
	(mips_vxworks_copy_howto_rela): New reloc howto.
	(mips_vxworks_jump_slot_howto_rela): Likewise.
	(mips_vxworks_bfd_reloc_type_lookup): New function.
	(mips_vxworks_rtype_to_howto): Likewise.
	(mips_vxworks_final_write_processing): Likewise.
	(TARGET_LITTLE_SYM, TARGET_LITTLE_NAME): Override for VxWorks.
	(TARGET_BIG_SYM, TARGET_BIG_NAME, elf_bed, ELF_MAXPAGESIZE): Likewise.
	(elf_backend_want_got_plt): Likewise.
	(elf_backend_want_plt_sym): Likewise.
	(elf_backend_got_symbol_offset): Likewise.
	(elf_backend_want_dynbss): Likewise.
	(elf_backend_may_use_rel_p): Likewise.
	(elf_backend_may_use_rela_p): Likewise.
	(elf_backend_default_use_rela_p): Likewise.
	(elf_backend_got_header_size: Likewise.
	(elf_backend_plt_readonly): Likewise.
	(bfd_elf32_bfd_reloc_type_lookup): Likewise.
	(elf_backend_mips_rtype_to_howto): Likewise.
	(elf_backend_adjust_dynamic_symbol): Likewise.
	(elf_backend_finish_dynamic_symbol): Likewise.
	(bfd_elf32_bfd_link_hash_table_create): Likewise.
	(elf_backend_add_symbol_hook): Likewise.
	(elf_backend_link_output_symbol_hook): Likewise.
	(elf_backend_emit_relocs): Likewise.
	(elf_backend_final_write_processing: Likewise.
	(elf_backend_additional_program_headers): Likewise.
	(elf_backend_modify_segment_map): Likewise.
	(elf_backend_symbol_processing): Likewise.
	* elfxx-mips.c: Include elf-vxworks.h.
	(mips_elf_link_hash_entry): Add is_relocation_target and
	is_branch_target fields.
	(mips_elf_link_hash_table): Add is_vxworks, srelbss, sdynbss, srelplt,
	srelplt2, sgotplt, splt, plt_header_size and plt_entry_size fields.
	(MIPS_ELF_RELA_SIZE, MIPS_ELF_REL_DYN_NAME): New macros.
	(MIPS_RESERVED_GOTNO): Take a mips_elf_link_hash_table argument.
	Return 3 for VxWorks.
	(ELF_MIPS_GP_OFFSET): Change the argument from a bfd to a
	mips_elf_link_hash_table.  Return 0 for VxWorks.
	(MIPS_ELF_GOT_MAX_SIZE): Change the argument from a bfd to a
	mips_elf_link_hash_table.  Update the call to ELF_MIPS_GP_OFFSET.
	(mips_vxworks_exec_plt0_entry): New variable.
	(mips_vxworks_exec_plt_entry): Likewise.
	(mips_vxworks_shared_plt0_entry): Likewise.
	(mips_vxworks_shared_plt_entry): Likewise.
	(mips_elf_link_hash_newfunc): Initialize the new hash_entry fields.
	(mips_elf_rel_dyn_section): Change the bfd argument to a
	mips_elf_link_hash_table.  Use MIPS_ELF_REL_DYN_NAME to get
	the name of the section.
	(mips_elf_initialize_tls_slots): Update the call to
	mips_elf_rel_dyn_section.
	(mips_elf_gotplt_index): New function.
	(mips_elf_local_got_index): Add an input_section argument.
	Update the call to mips_elf_create_local_got_entry.
	(mips_elf_got_page): Likewise.
	(mips_elf_got16_entry): Likewise.
	(mips_elf_create_local_got_entry): Add bfd_link_info and input_section
	arguments.  Create dynamic relocations for each entry on VxWorks.
	(mips_elf_merge_gots): Update the use of MIPS_ELF_GOT_MAX_SIZE.
	(mips_elf_multi_got): Update the uses of MIPS_ELF_GOT_MAX_SIZE
	and MIPS_RESERVED_GOTNO.
	(mips_elf_create_got_section): Update the uses of
	MIPS_ELF_GOT_MAX_SIZE.  Create .got.plt on VxWorks.
	(is_gott_symbol): New function.
	(mips_elf_calculate_relocation): Use a dynobj local variable.
	Update the calls to mips_elf_local_got_index, mips_elf_got16_entry and
	mips_elf_got_page_entry.  Set G to the .got.plt entry when calculating
	VxWorks R_MIPS_CALL* relocations.  Calculate and use G for all GOT
	relocations on VxWorks.  Add dynamic relocations for references
	to the VxWorks __GOTT_BASE__ and __GOTT_INDEX__ symbols.  Don't
	create dynamic relocations for R_MIPS_32, R_MIPS_REL32 or R_MIPS_64
	in VxWorks executables.
	(mips_elf_allocate_dynamic_relocations): Add a bfd_link_info argument.
	Use MIPS_ELF_RELA_SIZE to calculate the size of a VxWorks entry.
	Don't allocate a null entry on VxWorks.
	(mips_elf_create_dynamic_relocation): Update the call to
	mips_elf_rel_dyn_section.  Use absolute rather than relative
	relocations for VxWorks, and make them RELA rather than REL.
	(_bfd_mips_elf_create_dynamic_sections): Don't make .dynamic
	read-only on VxWorks.  Update the call to mips_elf_rel_dyn_section.
	Create the .plt, .rela.plt, .dynbss and .rela.bss sections on
	VxWorks.  Likewise create the _PROCEDURE_LINKAGE_TABLE symbol.
	Call elf_vxworks_create_dynamic_sections for VxWorks and
	initialize the plt_header_size and plt_entry_size fields.
	(_bfd_mips_elf_check_relocs): Don't allow GOT relocations to be
	used in VxWorks executables.  Don't allocate dynamic relocations
	for R_MIPS_32, R_MIPS_REL32 or R_MIPS_64 in VxWorks executables.
	Set is_relocation_target for each symbol referenced by a relocation.
	Allocate .rela.dyn entries for relocations against the special
	VxWorks __GOTT_BASE__ and __GOTT_INDEX__ symbols.  Create GOT
	entries for all VxWorks R_MIPS_GOT16 relocations.  Don't allocate
	a global GOT entry for symbols mentioned in VxWorks R_MIPS_CALL*,
	R_MIPS_32, R_MIPS_REL32 or R_MIPS_64 relocations.  Update the calls
	to mips_elf_rel_dyn_section and mips_elf_allocate_dynamic_relocations.
	Set is_branch_target for symbols mentioned in R_MIPS_PC16 or R_MIPS_26
	relocations.  Don't set no_fn_stub on VxWorks.
	(_bfd_mips_elf_adjust_dynamic_symbol): Update the call to
	mips_elf_allocate_dynamic_relocations.
	(_bfd_mips_vxworks_adjust_dynamic_symbol): New function.
	(_bfd_mips_elf_always_size_sections): Do not allocate GOT page
	entries for VxWorks, and do not create multiple GOTs.
	(_bfd_mips_elf_size_dynamic_sections): Use MIPS_ELF_REL_DYN_NAME.
	Handle .got specially for VxWorks.  Update the uses of
	MIPS_RESERVED_GOTNO and mips_elf_allocate_dynamic_relocations.
	Check for sgotplt and splt.  Allocate the .rel(a).dyn contents last,
	once its final size is known.  Set DF_TEXTREL for VxWorks.  Add
	DT_RELA, DT_RELASZ, DT_RELAENT, DT_PLTREL, DT_PLTRELSZ and DT_JMPREL
	tags on VxWorks.  Do not add the MIPS-specific tags for VxWorks.
	(_bfd_mips_vxworks_finish_dynamic_symbol): New function.
	(mips_vxworks_finish_exec_plt): Likewise.
	(mips_vxworks_finish_shared_plt): Likewise.
	(_bfd_mips_elf_finish_dynamic_sections): Remove an unncessary call
	to mips_elf_rel_dyn_section.  Use a VxWorks-specific value of
	DT_PLTGOT.  Handle DT_RELA, DT_RELASZ, DT_RELAENT, DT_PLTREL,
	DT_PLTRELSZ and DT_JMPREL.  Update the uses of MIPS_RESERVED_GOTNO
	and mips_elf_rel_dyn_section.  Use a different GOT header for
	VxWorks.  Don't sort .rela.dyn on VxWorks.  Finish the PLT on VxWorks.
	(_bfd_mips_elf_link_hash_table_create): Initialize the new
	mips_elf_link_hash_table fields.
	(_bfd_mips_vxworks_link_hash_table_create): New function.
	(_bfd_mips_elf_final_link): Set the GP value to _GLOBAL_OFFSET_TABLE_
	on VxWorks.  Update the call to ELF_MIPS_GP_OFFSET.
	* elfxx-mips.h (_bfd_mips_vxworks_adjust_dynamic_symbol): Declare.
	(_bfd_mips_vxworks_finish_dynamic_symbol): Likewise.
	(_bfd_mips_vxworks_link_hash_table_create): Likewise.
	* libbfd.h: Regenerate.
	* Makefile.am (elfxx-mips.lo): Depend on elf-vxworks.h.
	(elf32-mips.lo): Likewise.
	* Makefile.in: Regenerate.
	* reloc.c (BFD_RELOC_MIPS_COPY, BFD_RELOC_MIPS_JUMP_SLOT): Declare.
	* targets.c (bfd_elf32_bigmips_vxworks_vec): Declare.
	(bfd_elf32_littlemips_vxworks_vec): Likewise.
	(_bfd_target_vector): Add entries for them.

gas/
	* config/tc-mips.c (mips_target_format): Handle vxworks targets.
	(md_begin): Complain about -G being used for PIC.  Don't change
	the text, data and bss alignments on VxWorks.
	(reloc_needs_lo_p): Don't return true for R_MIPS_GOT16 when
	generating VxWorks PIC.
	(load_address): Extend SVR4_PIC handling to VXWORKS_PIC.
	(macro): Likewise, but do not treat la $25 specially for
	VxWorks PIC, and do not handle jal.
	(OPTION_MVXWORKS_PIC): New macro.
	(md_longopts): Add -mvxworks-pic.
	(md_parse_option): Don't complain about using PIC and -G together here.
	Handle OPTION_MVXWORKS_PIC.
	(md_estimate_size_before_relax): Always use the first relaxation
	sequence on VxWorks.
	* config/tc-mips.h (VXWORKS_PIC): New.

gas/testsuite/
	* gas/mips/vxworks1.s, gas/mips/vxworks1.d,
	* gas/mips/vxworks1-xgot.d: New tests.
	* gas/mips/mips.exp: Run them.  Do not run other tests on VxWorks.

include/elf/
	* mips.h (R_MIPS_COPY, R_MIPS_JUMP_SLOT): New relocs.

ld/
	* configure.tgt (mips*el-*-vxworks*, mips*-*-vxworks*): Use
	separate VxWorks emulations.
	* emulparams/elf32ebmipvxworks.sh: New file.
	* emulparams/elf32elmipvxworks.sh: New file.
	* Makefile.am (ALL_EMULATIONS): Add eelf32ebmipvxworks.o and
	eelf32elmipvxworks.o.
	(eelf32ebmipvxworks.c, eelf32elmipvxworks.c): New rules.
	* Makefile.in: Regenerate.

ld/testsuite/
	* ld-mips/vxworks1.dd, ld-mips/vxworks1.ld, ld-mips/vxworks1-lib.dd,
	* ld-mips/vxworks1-lib.nd, ld-mips/vxworks1-lib.rd,
	* ld-mips/vxworks1-lib.s, ld-mips/vxworks1.rd, ld-mips/vxworks1.s,
	* ld-mips/vxworks1-static.d, ld-mips/vxworks2.s, ld-mips/vxworks2.sd,
	* ld-mips/vxworks2-static.sd: New tests.
	* ld-mips/mips-elf.exp: Run them.
2006-03-22 09:28:15 +00:00
Paul Brook 080eb7fec2 2006-03-21 Paul Brook <paul@codesourcery.com>
* config/tc-arm.c (md_apply_fix): Fix typo in offset mask.
2006-03-21 22:52:06 +00:00
Bob Wilson 03aaa5932e * config/tc-xtensa.c (enforce_three_byte_loop_align): New flag.
(xtensa_setup_hw_workarounds): Set this new flag for older hardware.
	(get_loop_align_size): New.
	(xtensa_end): Skip xtensa_mark_narrow_branches when not aligning.
	(xtensa_mark_zcl_first_insns): Prevent widening of first loop frag.
	(get_text_align_power): Rewrite to handle inputs in the range 2-8.
	(get_noop_aligned_address): Use get_loop_align_size.
	(get_aligned_diff): Likewise.
2006-03-21 20:34:38 +00:00
Paul Brook 3e94bf1a01 2006-03-21 Paul Brook <paul@codesourcery.com>
gas/
	* config/tc-arm.c (insns): Correct opcodes for ldrbt and strbt.
gas/testsuite/
	* gas/arm/thumb32.d: Correct expected output.
2006-03-21 14:35:27 +00:00
Paul Brook dfa9f0d57b 2006-03-20 Paul Brook <paul@codesourcery.com>
gas/
	* config/tc-arm.c (BAD_BRANCH, BAD_NOT_IT): Define.
	(do_t_branch): Encode branches inside IT blocks as unconditional.
	(do_t_cps): New function.
	(do_t_blx, do_t_bkpt, do_t_branch23, do_t_bx, do_t_bxj, do_t_cpsi,
	do_t_czb, do_t_it, do_t_setend, do_t_tb): Add IT constaints.
	(opcode_lookup): Allow conditional suffixes on all instructions in
	Thumb mode.
	(md_assemble): Advance condexec state before checking for errors.
	(insns): Use do_t_cps.
gas/testsuite/
	* gas/arm/thumb2_bcond.d: New test.
	* gas/arm/thumb2_bcond.s: New test.
	* gas/arm/thumb2_it_bad.d: New test.
	* gas/arm/thumb2_it_bad.l: New test.
	* gas/arm/thumb2_it_bad.s: New test.
2006-03-20 15:38:02 +00:00
Paul Brook 6e1cb1a6e6 2006-03-20 Paul Brook <paul@codesourcery.com>
* config/tc-arm.c (output_relax_insn): Call dwarf2_emit_insn before
	outputting the insn.
2006-03-20 15:14:49 +00:00
Jan-Benedict Glaw 0a966e2d8f * config/tc-vax.c: Update copyright year.
* config/tc-vax.h: Likewise.
2006-03-18 11:23:38 +00:00
Jan-Benedict Glaw a49fcc17bf * config/tc-vax.c (md_chars_to_number): Used only locally, so
make it static.
	* config/tc-vax.h (md_chars_to_number): Remove obsolete declaration.
2006-03-18 11:06:47 +00:00
Paul Brook f5208ef27a 2006-03-17 Paul Brook <paul@codesourcery.com>
gas/
	* config/tc-arm.c (insns): Add ldm and stm.
gas/testsuite/
	* gas/arm/thumb32.d: Add ldm and stm tests.
	* gas/arm/thumb32.s: Ditto.
2006-03-17 14:03:36 +00:00
Ben Elliston cb4c78d64a PR gas/2446
* doc/as.texinfo (Ident): Document this directive more thoroughly.
2006-03-17 00:45:13 +00:00
Bernd Schmidt 2db51539bb * gas/bfin/shift2.s: Add new tests.
* gas/bfin/shift.d: Match changed disassembler behaviour.
	* gas/bfin/parallel2.d: Likewise.
	* gas/bfin/shift2.d: Likewise; also match new tests.
2006-03-16 19:09:25 +00:00
Paul Brook c16d2bf065 2006-03-16 Paul Brook <paul@codesourcery.com>
gas/
	* config/tc-arm.c (insns): Add "svc".
gas/testsuite/
	* gas/arm/svc.d: New test.
	* gas/arm/svc.s: New test.
	* gas/arm/inst.d: Accept svc mnemonic.
	* gas/arm/thumb.d: Ditto.
	* gas/arm/wince_inst.d: Ditto.
opcodes/
	* arm-dis.c (arm_opcodes): Rename swi to svc.
	(thumb_opcodes): Ditto.
2006-03-16 15:08:48 +00:00
Bob Wilson 80ca4e2ca2 * config/tc-xtensa.c (xg_translate_sysreg_op): Remove has_underbar
flag and avoid double underscore prefixes.
2006-03-13 21:46:53 +00:00
Paul Brook 3a4a14e9ea 2006-03-10 Paul Brook <paul@codesourcery.com>
bfd/
	* elf32-arm.c (INTERWORK_FLAG): Handle EABIv5.
	(elf32_arm_print_private_bfd_data): Ditto.
binutils/
	* readelf.c (decode_ARM_machine_flags):  Handle EABIv5.
gas/
	* config/tc-arm.c (md_begin): Handle EABIv5.
	(arm_eabis): Add EF_ARM_EABI_VER5.
	* doc/c-arm.texi: Document -meabi=5.
include/elf/
	* arm.h (EF_ARM_EABI_VER5): Define.
2006-03-10 17:20:30 +00:00
Ben Elliston 518051dc53 * app.c (do_scrub_chars): Simplify string handling. 2006-03-10 10:57:18 +00:00
Paul Brook 384060486d 2006-03-09 Paul Brook <paul@codesourcery.com>
bfd/
	* cpu-arm.c (bfd_is_arm_mapping_symbol_name): Recognise additional
	mapping symbols.
gas/testsuite/
	* gas/arm/nomapping.d: New test.
	* gas/arm/nomapping.s: New test.
2006-03-09 23:05:59 +00:00
H.J. Lu 35c52694b9 gas/testsuite/
2006-03-07  H.J. Lu  <hongjiu.lu@intel.com>

	PR binutils/2428
	* gas/i386/i386.exp: Add rep, rep-suffix, x86-64-rep and
	x86-64-rep-suffix.

	* gas/i386/naked.d: Replace repz with rep.
	* gas/i386/x86_64.d: Likewise.

	* gas/i386/rep-suffix.d: New file.
	* gas/i386/rep-suffix.s: Likewise.
	* gas/i386/rep.d: Likewise.
	* gas/i386/rep.s: Likewise.
	* gas/i386/x86-64-rep-suffix.d: Likewise.
	* gas/i386/x86-64-rep-suffix.s: Likewise.
	* gas/i386/x86-64-rep.d: Likewise.
	* gas/i386/x86-64-rep.s: Likewise.

opcodes/

2006-03-07  H.J. Lu  <hongjiu.lu@intel.com>

	PR binutils/2428
	* i386-dis.c (REP_Fixup): New function.
	(AL): Remove duplicate.
	(Xbr): New.
	(Xvr): Likewise.
	(Ybr): Likewise.
	(Yvr): Likewise.
	(indirDXr): Likewise.
	(ALr): Likewise.
	(eAXr): Likewise.
	(dis386): Updated entries of ins, outs, movs, lods and stos.
2006-03-07 20:18:06 +00:00
Richard Sandiford 00a976722a bfd/
* configure.in (bfd_elf32_bigarm_vec): Include elf-vxworks.lo.
	(bfd_elf32_bigarm_symbian_vec): Likewise.
	(bfd_elf32_bigarm_vxworks_vec): Likewise.
	(bfd_elf32_littlearm_vec): Likewise.
	(bfd_elf32_littlearm_symbian_vec): Likewise.
	(bfd_elf32_littlearm_vxworks_vec): Likewise.
	* configure: Regenerate.
	* elf32-arm.c: Include libiberty.h and elf-vxworks.h.
	(RELOC_SECTION, RELOC_SIZE, SWAP_RELOC_IN, SWAP_RELOC_OUT): New macros.
	(elf32_arm_vxworks_bed): Add forward declaration.
	(elf32_arm_howto_table_1): Fix the masks for R_ASM_ABS12.
	(elf32_arm_vxworks_exec_plt0_entry): New table.
	(elf32_arm_vxworks_exec_plt_entry): Likewise.
	(elf32_arm_vxworks_shared_plt_entry): Likewise.
	(elf32_arm_link_hash_table): Add vxworks_p and srelplt2 fields.
	(reloc_section_p): New function.
	(create_got_section): Use RELOC_SECTION.
	(elf32_arm_create_dynamic_sections): Likewise.  Call
	elf_vxworks_create_dynamic_sections for VxWorks targets.
	Choose between the two possible values of plt_header_size
	and plt_entry_size.
	(elf32_arm_link_hash_table_create): Initialize vxworks_p and srelplt2.
	(elf32_arm_abs12_reloc): New function.
	(elf32_arm_final_link_relocate): Call it.  Allow the creation of
	dynamic R_ARM_ABS12 relocs on VxWorks.  Use reloc_section_p,
	RELOC_SIZE, SWAP_RELOC_OUT and RELOC_SECTION.  Initialize the
	r_addend fields of relocs.  On rela targets, skip any code that
	adjusts in-place addends.  When using _bfd_link_final_relocate
	to perform a final relocation, pass rel->r_addend as the addend
	argument.
	(elf32_arm_merge_private_bfd_data): If one of the bfds is a VxWorks
	object, ignore flags that are not standard on VxWorks.
	(elf32_arm_check_relocs): Allow the creation of dynamic R_ARM_ABS12
	relocs on VxWorks.  Use reloc_section_p.
	(elf32_arm_adjust_dynamic_symbol): Use RELOC_SECTION and RELOC_SIZE.
	(allocate_dynrelocs): Use RELOC_SIZE.  Account for the size of
	.rela.plt.unloaded relocs on VxWorks targets.
	(elf32_arm_size_dynamic_sections): Use RELOC_SIZE.  Check for
	.rela.plt.unloaded as well as .rel(a).plt.  Add DT_RELA* tags
	instead of DT_REL* tags on RELA targets.
	(elf32_arm_finish_dynamic_symbol): Use RELOC_SECTION, RELOC_SIZE
	and SWAP_RELOC_OUT.  Initialize r_addend fields.  Handle VxWorks
	PLT entries.  Do not make _GLOBAL_OFFSET_TABLE_ absolute on VxWorks.
	(elf32_arm_finish_dynamic_sections): Use RELOC_SECTION, RELOC_SIZE
	and SWAP_RELOC_OUT.  Initialize r_addend fields.  Handle DT_RELASZ
	like DT_RELSZ.  Handle the VxWorks form of initial PLT entry.
	Correct the .rela.plt.unreloaded symbol indexes.
	(elf32_arm_output_symbol_hook): Call the VxWorks version of this
	hook on VxWorks targets.
	(elf32_arm_vxworks_link_hash_table_create): Set vxworks_p to true.
	Minor formatting tweak.
	(elf32_arm_vxworks_final_write_processing): New function.
	(elf_backend_add_symbol_hook): Override for VxWorks and reset
	for Symbian.
	(elf_backend_final_write_processing): Likewise.
	(elf_backend_emit_relocs): Likewise.
	(elf_backend_want_plt_sym): Likewise.
	(ELF_MAXPAGESIZE): Likewise.
	(elf_backend_may_use_rel_p): Minor formatting tweak.
	(elf_backend_may_use_rela_p): Likewise.
	(elf_backend_default_use_rela_p): Likewise.
	(elf_backend_rela_normal): Likewise.
	* Makefile.in (elf32-arm.lo): Depend on elf-vxworks.h.

gas/
	* config/tc-arm.c (md_apply_fix): Install a value of zero into a
	BFD_RELOC_ARM_OFFSET_IMM field if we're going to generate a RELA
	R_ARM_ABS12 reloc.
	(tc_gen_reloc): Keep the original fx_offset for RELA pc-relative
	relocs, but adjust by md_pcrel_from_section.  Create R_ARM_ABS12
	relocations for BFD_RELOC_ARM_OFFSET_IMM on RELA targets.

gas/testsuite/
	* gas/arm/abs12.s, gas/arm/abs12.d: New test.
	* gas/arm/pic.d: Skip for *-*-vxworks*...
	* gas/arm/pic_vxworks.d: ...use this version instead.
	* gas/arm/unwind_vxworks.d: Fix expected output.

ld/
	* emulparams/armelf_vxworks.sh: Include vxworks.sh.
	(MAXPAGESIZE): Define.
	* emulparams/vxworks.sh: Undefine.
	* Makefile.am (earmelf_vxworks.c): Depend on vxworks.sh and vxworks.em.
	* Makefile.in: Regenerate.

ld/testsuite/
	* ld-arm/vxworks1.dd, ld-arm/vxworks1.ld, ld-arm/vxworks1-lib.dd,
	* ld-arm/vxworks1-lib.nd, ld-arm/vxworks1-lib.rd,
	* ld-arm/vxworks1-lib.s, ld-arm/vxworks1.rd, ld-arm/vxworks1.s,
	* ld-arm/vxworks1-static.d, ld-arm/vxworks2.s, ld-arm/vxworks2.sd,
	* ld-arm/vxworks2-static.sd: New tests.
	* ld-arm/arm-elf.exp: Run them.
2006-03-07 08:39:21 +00:00
Bob Wilson b29757dc18 * config/tc-xtensa.c (xtensa_post_relax_hook): Generate literal tables
even when using the text-section-literals option.
2006-03-06 18:02:06 +00:00
Nathan Sidwell 0b2e31dc3b bfd:
* archures.c (bfd_mach_mcf_isa_a_nodiv, bfd_mach_mcf_isa_b_nousp):
	New.  Adjust other variants.
	(bfd_default_scan): Update.
	* bfd-in2.h: Rebuilt.
	* cpu-m68k.c: Adjust.
	(bfd_m68k_compatible): New. Use it for architectures.
	* elf32-m68k.c (elf32_m68k_object_p): Adjust.
	(elf32_m68k_merge_private_bfd_data): Adjust.  Correct isa-a/b
	mismatch.
	(elf32_m68k_print_private_bfd_data): Adjust.
	* ieee.c (ieee_write_processor): Adjust.

	binutils:
	* readelf.c (get_machine_flags): Adjust.

	gas:
	* config/tc-m68k.c (m68k_extensions): Allow 'float' on both m68k
	and cf.
	(m68k_ip): <case 'J'> Check we have some control regs.
	(md_parse_option): Allow raw arch switch.
	(m68k_init_arch): Better detection of arch/cpu mismatch.  Detect
	whether 68881 or cfloat was meant by -mfloat.
	(md_show_usage): Adjust extension display.
	(m68k_elf_final_processing): Adjust.

	gas/testsuite:
	* gas/m68k/arch-cpu-1.s: Tweak.
	* gas/m68k/arch-cpu-1.d: Tweak.

	include/elf:
	* m68k.h (EF_M68K_ISA_MASK, EF_M68K_ISA_A,
	EF_M68K_ISA_A_PLUS, EF_M68K_ISA_B, EF_M68K_ISA_C): Adjust.
	(EF_M68K_ISA_A_NODIV, EF_M68K_ISA_B_NOUSP): New.
	(EF_M68K_HW_DIV, EF_M68K_USP): Remove.
	(EF_M68K_MAC, EF_M68K_EMAC, EF_M68K_FLOAT): Adjust.
	(EF_M68K_EMAC_B): New.

	ld/testsuite:
	* ld-m68k: New tests.
2006-03-06 13:42:05 +00:00
Nick Clifton df406460e9 Add linker relaxation support for the AVR 2006-03-03 15:25:31 +00:00
Jim Wilson 53022e4a53 Fix problem with double-stop-bit after itc.i instruction.
* config/tc-ia64.c (emit_one_bundle): For IA64_OPCODE_LAST, if we
change the template, then clear md.slot[curr].end_of_insn_group.
2006-03-03 01:10:42 +00:00
Jan Beulich 9f6f925e1e gas/
2006-02-28  Jan Beulich  <jbeulich@novell.com>

	* macro.c (get_any_string): Don't insert quotes for <>-quoted input.

gas/testsuite/
2006-02-28  Jan Beulich  <jbeulich@novell.com>

	* gas/all/altmacro.s: Adjust.
	* gas/all/altmac2.s: Adjust.
2006-02-28 07:57:09 +00:00
Jan Beulich 0e31b3e1a3 gas/
2006-02-28  Jan Beulich  <jbeulich@novell.com>

	PR/1070
	* macro.c (getstring): Don't treat parentheses special anymore.
	(get_any_string): Don't consider '(' and ')' as quoting anymore.
	Special-case '(', ')', '[', and ']' when dealing with non-quoting
	characters.

gas/testsuite/
2006-02-28  Jan Beulich  <jbeulich@novell.com>

	* gas/macros/paren[sd]: New.
	* gas/macros/macros.exp: Run new test.
2006-02-28 07:55:36 +00:00
Alan Modra 10cd14b412 * dwarf2dbg.c (get_filenum): Don't inadvertently decrease files_in_use. 2006-02-28 00:38:19 +00:00
Jakub Jelinek 8502d88294 Fix up ChangeLog entry. 2006-02-27 23:21:41 +00:00
Jakub Jelinek 63752a757f bfd/
* elf-eh-frame.c (_bfd_elf_discard_section_eh_frame): Handle S flag.
	(_bfd_elf_write_section_eh_frame): Likewise.
gas/
	* dw2gencfi.c (struct fde_entry, struct cie_entry): Add signal_frame
	field.
	(CFI_signal_frame): Define.
	(cfi_pseudo_table): Add .cfi_signal_frame.
	(dot_cfi): Handle CFI_signal_frame.
	(output_cie): Handle cie->signal_frame.
	(select_cie_for_fde): Don't share CIE if signal_frame flag is
	different.  Copy signal_frame from FDE to newly created CIE.
	* doc/as.texinfo: Document .cfi_signal_frame.
2006-02-27 23:07:06 +00:00
Carlos O'Donell f7d9e5c379 bfd/doc/
2006-10-14  Carlos O'Donell  <carlos@codesourcery.com>

       * Makefile.am: Add html target.
       * Makefile.in: Regenerate.

bfd/
2006-10-14  Carlos O'Donell  <carlos@codesourcery.com>

       * po/Make-in: Add html target.

binutils/
2006-10-14  Carlos O'Donell  <carlos@codesourcery.com>

       * po/Make-in: Add html target.

gas/
2006-10-14  Carlos O'Donell  <carlos@codesourcery.com>

       * doc/Makefile.am: Add html target.
       * doc/Makefile.in: Regenerate.
       * po/Make-in: Add html target.

gprof/
2006-10-14  Carlos O'Donell  <carlos@codesourcery.com>

       * po/Make-in: Add html target.

ld/
2006-10-14  Carlos O'Donell  <carlos@codesourcery.com>

       * Makefile.am: Add html target.
       * Makefile.in: Regenerate.
       * po/Make-in: Add html target.

opcodes/
2006-10-14  Carlos O'Donell  <carlos@codesourcery.com>

       * po/Make-in: Add html target.

etc/
2006-10-14  Carlos O'Donell  <carlos@codesourcery.com>

       * Makefile.in: TEXI2HTML uses makeinfo. Define
       HTMLFILES. Add html targets.
       * configure.texi: Use ifnottex. Add alternative
       image format specifier as jpg.
       * standards.texi: Use ifnottex.

intl/
2006-10-14  Carlos O'Donell  <carlos@codesourcery.com>

       * intl/Makefile.in: Add html target.
2006-02-27 16:26:26 +00:00
H.J. Lu 331d2d0d9c gas/
2006-02-27  H.J. Lu <hongjiu.lu@intel.com>

	* gas/config/tc-i386.c (output_insn): Support Intel Merom New
	Instructions.

	* gas/config/tc-i386.h (CpuMNI): New.
	(CpuUnknownFlags): Add CpuMNI.

gas/testsuite/

2006-02-27  H.J. Lu <hongjiu.lu@intel.com>

	* gas/i386/i386.exp: Add merom and x86-64-merom.

	* gas/i386/merom.d: New file.
	* gas/i386/merom.s: Likewise.
	* gas/i386/x86-64-merom.d: Likewise.
	* gas/i386/x86-64-merom.s: Likewise.

include/opcode/

2006-02-27  H.J. Lu <hongjiu.lu@intel.com>

	* i386.h (i386_optab): Support Intel Merom New Instructions.

opcodes/

2006-02-27  H.J. Lu <hongjiu.lu@intel.com>

	* i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by
	Intel Merom New Instructions.
	(THREE_BYTE_0): Likewise.
	(THREE_BYTE_1): Likewise.
	(three_byte_table): Likewise.
	(dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use
	THREE_BYTE_1 for entry 0x3a.
	(twobyte_has_modrm): Updated.
	(twobyte_uses_SSE_prefix): Likewise.
	(print_insn): Handle 3-byte opcodes used by Intel Merom New
	Instructions.
2006-02-27 15:35:37 +00:00
Nathan Sidwell 04ede391a6 missing from 2006-02-07 Nathan Sidwell <nathan@codesourcery.com> commit 2006-02-26 10:00:30 +00:00
David S. Miller 83d634e3da 2006-02-24 David S. Miller <davem@sunset.davemloft.net>
* gas/sparc/rdhpr.s: New test.
	* gas/sparc/rdhpr.d: New test.
	* gas/sparc/wrhpr.s: New test.
	* gas/sparc/wrhpr.d: New test.
	* gas/sparc/window.s: New test.
	* gas/sparc/window.d: New test.
	* gas/sparc/rdpr.s: Add case for reading %gl register.
	* gas/sparc/rdpr.d: Likewise.
	* gas/sparc/wrpr.s: Add case for writing %gl register.
	* gas/sparc/wrpr.d: Likewise.
	* gas/sparc/sparc.exp: Update for new tests.
2006-02-25 01:36:12 +00:00
David S. Miller 10156f834a 2006-02-24 David S. Miller <davem@sunset.davemloft.net>
* config/tc-sparc.c (priv_reg_table): Add entry for "gl".
	(hpriv_reg_table): New table for hyperprivileged registers.
	(sparc_ip): New cases '$' and '%' for wrhpr/rdhpr hyperprivileged
	register encoding.
2006-02-25 01:34:09 +00:00
DJ Delorie 6772dd07c4 [include/elf]
* m32c.h: Add relax relocs.

[cpu]
	* m32c.cpu (RL_TYPE): New attribute, with macros.
	(Lab-8-24): Add RELAX.
	(unary-insn-defn-g, binary-arith-imm-dst-defn,
	binary-arith-imm4-dst-defn): Add 1ADDR attribute.
	(binary-arith-src-dst-defn): Add 2ADDR attribute.
	(jcnd16-5, jcnd16, jcnd32, jmp16.s, jmp16.b, jmp16.w, jmp16.a,
	jmp32.s, jmp32.b, jmp32.w, jmp32.a, jsr16.w, jsr16.a): Add JUMP
	attribute.
	(jsri16, jsri32): Add 1ADDR attribute.
	(jsr32.w, jsr32.a): Add JUMP attribute.

[opcodes]
	* m32c-desc.c: Regenerate with linker relaxation attributes.
	* m32c-desc.h: Likewise.
	* m32c-dis.c: Likewise.
	* m32c-opc.c: Likewise.

[gas]
	* config/tc-m32c.h (md_apply_fix): Define to m32c_apply_fix.
	(tc_gen_reloc): Don't define.
	* config/tc-m32c.c (rl_for, relaxable): New convenience macros.
	(OPTION_LINKRELAX): New.
	(md_longopts): Add it.
	(m32c_relax): New.
	(md_parse_options): Set it.
	(md_assemble): Emit relaxation relocs as needed.
	(md_convert_frag): Emit relaxation relocs as needed.
	(md_cgen_lookup_reloc): Add LAB_8_8 and LAB_8_16.
	(m32c_apply_fix): New.
	(tc_gen_reloc): New.
	(m32c_force_relocation): Force out jump relocs when relaxing.
	(m32c_fix_adjustable): Return false if relaxing.

[bfd]
	* elf32-m32c.c (m32c_elf_howto_table): Add relaxation relocs.
	(m32c_elf_relocate_section): Don't relocate them.
	(compare_reloc): New.
	(relax_reloc): Remove.
	(m32c_offset_for_reloc): New.
	(m16c_addr_encodings): New.
	(m16c_jmpaddr_encodings): New.
	(m32c_addr_encodings): New.
	(m32c_elf_relax_section): Relax jumps and address displacements.
	(m32c_elf_relax_delete_bytes): Adjust for internal syms.  Fix up
	short jumps.

	* reloc.c: Add m32c relax relocs.
	* libbfd.h: Regenerate.
2006-02-24 22:10:36 +00:00
Paul Brook ebdca51ad9 Check in correct version of previous patch. 2006-02-24 17:09:33 +00:00
Paul Brook 62b3e31101 2006-02-24 Paul Brook <paul@codesourcery.com>
gas/
	* config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
	arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
	(struct asm_barrier_opt): Define.
	(arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
	(parse_psr): Accept V7M psr names.
	(parse_barrier): New function.
	(enum operand_parse_code): Add OP_oBARRIER.
	(parse_operands): Implement OP_oBARRIER.
	(do_barrier): New function.
	(do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
	(do_t_cpsi): Add V7M restrictions.
	(do_t_mrs, do_t_msr): Validate V7M variants.
	(md_assemble): Check for NULL variants.
	(v7m_psrs, barrier_opt_names): New tables.
	(insns): Add V7 instructions.  Mark V6 instructions absent from V7M.
	(md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
	(arm_cpu_option_table): Add Cortex-M3, R4 and A8.
	(arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
	(struct cpu_arch_ver_table): Define.
	(cpu_arch_ver): New.
	(aeabi_set_public_attributes): Use cpu_arch_ver.  Set
	Tag_CPU_arch_profile.
	* doc/c-arm.texi: Document new cpu and arch options.
gas/testsuite/
	* gas/arm/thumb32.d: Fix expected msr and mrs output.
	* gas/arm/arch7.d: New test.
	* gas/arm/arch7.s: New test.
	* gas/arm/arch7m-bad.l: New test.
	* gas/arm/arch7m-bad.d: New test.
	* gas/arm/arch7m-bad.s: New test.
include/opcode/
	* arm.h: Add V7 feature bits.
opcodes/
	* arm-dis.c (arm_opcodes): Add V7 instructions.
	(thumb32_opcodes): Ditto.  Handle V7M MSR/MRS variants.
	(print_arm_address): New function.
	(print_insn_arm): Use it.  Add 'P' and 'U' cases.
	(psr_name): New function.
	(print_insn_thumb32): Add 'U', 'C' and 'D' cases.
2006-02-24 15:36:36 +00:00
H.J. Lu 59cf82fe74 bfd/
2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>

	* cpu-ia64-opc.c (ins_immu5b): New.
	(ext_immu5b): Likewise.
	(elf64_ia64_operands): Add IMMU5b.

gas/

2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-ia64.c (operand_match): Handle IA64_OPND_IMMU5b.

gas/testsuite/

2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/ia64/opc-i.s: Add tests for tf.
	* gas/ia64/pseudo.s: Likewise.
	* gas/ia64/opc-i.d: Updated.
	* gas/ia64/pseudo.d: Likewise.

include/opcode/

2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>

	* ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.

opcodes/

2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>

	* ia64-opc-i.c (bXc): New.
	(mXc): Likewise.
	(OpX2TaTbYaXcC): Likewise.
	(TF). Likewise.
	(TFCM). Likewise.
	(ia64_opcodes_i): Add instructions for tf.

	* ia64-opc.h (IMMU5b): New.

	* ia64-asmtab.c: Regenerated.
2006-02-23 21:36:18 +00:00
H.J. Lu 19a7219fd1 Update copyright years. 2006-02-23 14:49:32 +00:00
H.J. Lu 7f3dfb9cf7 gas/
2006-02-22  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-ia64.c (specify_resource): Add the rule 17 from
	SDM 2.2.

gas/testsuite/

2006-02-22  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/ia64/dv-raw-err.s: Add check for vmsw.0.
	* gas/ia64/dv-raw-err.l: Updated.

	* gas/ia64/opc-b.s: Add vmsw.0 and vmsw.1.
	* gas/ia64/opc-b.d: Updated.

opcodes/

2006-02-22  H.J. Lu  <hongjiu.lu@intel.com>

	* ia64-gen.c (lookup_regindex): Handle ".vm".
	(print_dependency_table): Handle '\"'.

	* ia64-ic.tbl: Updated from SDM 2.2.
	* ia64-raw.tbl: Likewise.
	* ia64-waw.tbl: Likewise.
	* ia64-asmtab.c: Regenerated.

	* ia64-opc-b.c (ia64_opcodes_b): Add vmsw.0 and vmsw.1.
2006-02-23 00:17:24 +00:00
Paul Brook f40d164325 2005-02-22 Paul Brook <paul@codesourcery.com>
gas/
	* config/tc-arm.c (do_pld): Remove incorrect write to
	inst.instruction.
	(encode_thumb32_addr_mode): Use correct operand.
gas/testsuite/
	* gas/arm/thumb32.d: Fix expected pld opcode.
2006-02-22 15:03:30 +00:00
Paul Brook 216d22bc1d 2006-02-21 Paul Brook <paul@codesourcery.com>
* config/tc-arm.c (md_apply_fix): Fix off-by-one errors.
2006-02-21 15:13:54 +00:00
Nick Clifton d70c5fc7c5 Add support for the Infineon XC16X. 2006-02-17 14:36:28 +00:00
Nick Hudson aaa2ab3d61 bfd:
* config.bfd (mips*el-*-netbsd*, mips*-*-netbsd*): Use
	traditional MIPS ELF targets.

	gas:
	* configure.tgt: set emulation for mips-*-netbsd*

	ld:
	* configure.tgt (mips*el-*-netbsd*, mips*-*-netbsd*):
	Use the traditional target.
2006-02-16 08:05:02 +00:00