Commit Graph

1990 Commits

Author SHA1 Message Date
Claudiu Zissulescu 72f3b6aae7 [ARC] Allow non-instruction relocations within .text sections
bfd/
2016-03-08  Cupertino Miranda  <Cupertino.Miranda@synopsys.com>
	    Andrew Burgess  <andrew.burgess@embecosm.com>

	* elf32-arc.c (arc_bfd_get_32): Becomes an alias for bfd_get_32.
	(arc_bfd_put_32): Becomes an alias for bfd_put_32.
	(arc_elf_howto_init): Added assert to validate relocations.
	(get_middle_endian_relocation): Delete.
	(middle_endian_convert): New function.
	(ME): Redefine, now does nothing.
	(IS_ME): New define.
	(arc_do_relocation): Extend the attached 'ARC_RELOC_HOWTO'
	definition to call middle_endian_convert.  Add a new local
	variable and make use of this throughout. Added call to
	arc_bfd_get_8 and arc_bfd_put_8 for 8 bit relocations.

gas/
2016-03-08  Andrew Burgess  <andrew.burgess@embecosm.com>

	* testsuite/gas/arc/inline-data-1.d: New file.
	* testsuite/gas/arc/inline-data-1.s: New file.

include/
2016-03-08  Cupertino Miranda  <Cupertino.Miranda@synopsys.com>
	    Andrew Burgess  <andrew.burgess@embecosm.com>

	* elf/arc-reloc.def: Add a call to ME within the formula for each
	relocation that requires middle-endian correction.
2016-03-08 14:19:52 +01:00
Trevor Saunders f86f586366 Add const qualifiers at various places.
opcodes	* mcore-opc.h: Add const qualifiers.
	* microblaze-opc.h (struct op_code_struct): Likewise.
	* sh-opc.h: Likewise.
	* tic4x-dis.c (tic4x_print_indirect): Likewise.
	(tic4x_print_op): Likewise.

include	* opcode/dlx.h (struct dlx_opcode): Add const qualifiers.
	* opcode/h8300.h (struct h8_opcode): Likewise.
	* opcode/hppa.h (struct pa_opcode): Likewise.
	* opcode/msp430.h: Likewise.
	* opcode/spu.h (struct spu_opcode): Likewise.
	* opcode/tic30.h (struct _register): Likewise.
	* opcode/tic4x.h (struct tic4x_register): Likewise.
	(struct tic4x_cond): Likewise.
	(struct tic4x_indirect): Likewise.
	(struct tic4x_inst): Likewise.
	* opcode/visium.h (struct reg_entry): Likewise.

gas	* config/tc-arc.c: Add const qualifiers.
	* config/tc-h8300.c (md_begin): Likewise.
	* config/tc-ia64.c (print_prmask): Likewise.
	* config/tc-msp430.c (msp430_operands): Likewise.
	* config/tc-nds32.c (struct suffix_name): Likewise.
	(struct nds32_parse_option_table): Likewise.
	(struct nds32_set_option_table): Likewise.
	(do_pseudo_pushpopm): Likewise.
	(do_pseudo_pushpop_stack): Likewise.
	(nds32_relax_relocs): Likewise.
	(nds32_flag): Likewise.
	(struct nds32_hint_map): Likewise.
	(nds32_find_reloc_table): Likewise.
	(nds32_match_hint_insn): Likewise.
	* config/tc-s390.c: Likewise.
	* config/tc-sh.c (get_specific): Likewise.
	* config/tc-tic30.c: Likewise.
	* config/tc-tic4x.c (tic4x_inst_add): Likewise.
	(tic4x_indirect_parse): Likewise.
	* config/tc-vax.c (vax_cons): Likewise.
	* config/tc-z80.c (struct reg_entry): Likewise.
	* config/tc-epiphany.c (md_assemble): Adjust.
	(epiphany_assemble): New function.
	(epiphany_elf_section_rtn): Call do_align directly.
	(epiphany_elf_section_text): Likewise.
	* config/tc-ip2k.c (ip2k_elf_section_rtn): Likewise.
	(ip2k_elf_section_text): Likewise.
	* read.c (do_align): Make it not static.
	* read.h (do_align): New prototype.
2016-03-07 15:16:28 +00:00
Cary Coutant 9b738e36e6 Fix datestamps on ChangeLog entries to read 2015 instead of 2016. 2016-03-04 14:19:12 -08:00
H.J. Lu 3f1f41f55f Add missing ChangeLog entries for commit 82838
Fix gold/testsuite/plugin_layout_with_alignment.sh permission.
2016-03-04 08:28:12 -08:00
Matthew Wahab 643afb90da [ARM] Add feature check for ARMv8.1 AdvSIMD instructions.
gas/
2016-03-04  Matthew Wahab  <matthew.wahab@arm.com>

	* config/gas/tc-arm.c (fpu_neon_ext_v8_1): Restrict to the ARMv8.1 RDMA
	feature.
	(record_feature_use): New.
	(mark_feature_used): Use record_feature_use.
	(do_neon_qrdmlah): New.
	(insns): Use do_neon_qrdmlah for vqrdmlah and vqrdmlsh and
	variants.
	(arm_extensions): Put into alphabetical order.  Re-indent "simd"
	and "rdma" entries.  Fix the incorrect merge value for "+rdma".
	* testsuite/gas/arm/armv8-a+rdma-warning.d: New.
	* testsuite/gas/arm/armv8-a+rdma.d: Add assembler command line options.
	Make source file explicit.
	* testsuite/gas/arm/armv8-a+rdma.l: New.
	* testsuite/gas/arm/armv8-a+rdma.s: Remove .arch and .arch_extension
	directives.  Fix white-space.
	* testsuite/gas/arm/armv8_1-a+simd.d: New.

include/opcode
2016-03-04  Matthew Wahab  <matthew.wahab@arm.com>

	* arm.h (ARM_ARCH_V8_1A): Add FPU_NEON_EXT_RDMA.
	(ARM_CPU_HAS_FEATURE): Add comment.

Change-Id: Ie19250e8fa50aed44e44ab40ff30b04b38bc1a3d
2016-03-04 11:32:04 +00:00
Cary Coutant 82838bd626 Add new plugin hooks to support querying section alignment and size.
include/
2016-03-03  Than McIntosh <thanm@google.com>

	* plugin-api.h: Add new hooks to the plugin transfer vector to
	to support querying section alignment and section size.
	(ld_plugin_get_input_section_alignment): New hook.
	(ld_plugin_get_input_section_size): New hook.
	(ld_plugin_tag): Add LDPT_GET_INPUT_SECTION_ALIGNMENT
	and LDPT_GET_INPUT_SECTION_SIZE.
	(ld_plugin_tv): Add tv_get_input_section_alignment and
	tv_get_input_section_size.

gold/
2016-03-03  Than McIntosh  <thanm@google.com>

	* plugin.cc (Plugin::load): Include hooks for get_input_section_size
	and get_input_section_alignment in transfer vector.
	(get_input_section_alignment): New function.
	(get_input_section_size): New function.
	* testsuite/Makefile.am: Add plugin_layout_with_alignment.sh test.
	* testsuite/Makefile.in: [Regenerate.]
	* testsuite/plugin_section_alignment.cc: New test file.
	* testsuite/plugin_layout_with_alignment.cc: New test file.
	* testsuite/plugin_layout_with_alignment.sh: New test file.
2016-03-03 12:09:06 -08:00
Evgenii Stepanov 95ecdfbfcb get_symbols() plugin API tweak to support --start-lib/--end-lib.
Let the plugin know that a file is not being included in the link by
returning LDPS_NO_SYMS from get_symbols().

include/
	* plugin-api.h (enum ld_plugin_tag): Add LDPT_GET_SYMBOLS_V3.

gold/
	* plugin.h (Pluginobj::get_symbol_resolution_info): Add version
	parameter.
	* plugin.cc (get_symbols_v3): New function.
	(Plugin::load): Add LDPT_GET_SYMBOLS_V3.
	(Pluginobj::get_symbol_resolution_info): Return LDPS_NO_SYMS when using
	new version.
2016-03-03 11:42:13 -08:00
H.J. Lu 11e5f1ec54 Add ChangeLog entries for PR ld/19645 2016-02-26 06:44:03 -08:00
H.J. Lu b8871f357f Properly implement STT_COMMON
The BFD configure option, --enable-elf-stt-common, can't be to used to
verify STT_COMMON implementation with the normal binutils build.  Instead,
this patch removes it from BFD.  It adds --elf-stt-common=[no|yes] to ELF
assembler/objcopy and adds -z common/-z nocommon to ld.

A configure option, --enable-elf-stt-common, is added to gas to specify
whether ELF assembler should generate common symbols with the STT_COMMON
type by default.

Since BSF_KEEP_G is never used, it is renamed to BSF_ELF_COMMON for ELF
common symbols.

bfd/

	PR ld/19645
	* bfd.c (bfd): Change flags to 20 bits.
	(BFD_CONVERT_ELF_COMMON): New.
	(BFD_USE_ELF_STT_COMMON): Likewise.
	(BFD_FLAGS_SAVED): Add BFD_CONVERT_ELF_COMMON and
	BFD_USE_ELF_STT_COMMON.
	(BFD_FLAGS_FOR_BFD_USE_MASK): Likewise.
	* configure.ac: Remove --enable-elf-stt-common.
	* elf.c (swap_out_syms): Choose STT_COMMON or STT_OBJECT for
	common symbol depending on BFD_CONVERT_ELF_COMMON and
	BFD_USE_ELF_STT_COMMON.
	* elfcode.h (elf_slurp_symbol_table): Set BSF_ELF_COMMON for
	STT_COMMON.
	* elflink.c (bfd_elf_link_mark_dynamic_symbol): Also check
	STT_COMMON.
	(elf_link_convert_common_type): New function.
	(elf_link_output_extsym): Choose STT_COMMON or STT_OBJECT for
	common symbol depending on BFD_CONVERT_ELF_COMMON and
	BFD_USE_ELF_STT_COMMON.  Set sym.st_info after sym.st_shndx.
	* elfxx-target.h (TARGET_BIG_SYM): Add BFD_CONVERT_ELF_COMMON
	and BFD_USE_ELF_STT_COMMON to object_flags.
	(TARGET_LITTLE_SYM): Likewise.
	* syms.c (BSF_KEEP_G): Renamed to ...
	(BSF_ELF_COMMON): This.
	* bfd-in2.h: Regenerated.
	* config.in: Likewise.
	* configure: Likewise.

binutils/

	PR ld/19645
	* NEWS: Mention --elf-stt-common= for objcopy.
	* doc/binutils.texi: Document --elf-stt-common= for objcopy.
	* objcopy.c (do_elf_stt_common): New.
	(command_line_switch): Add OPTION_ELF_STT_COMMON.
	(copy_options): Add --elf-stt-common=.
	(copy_usage): Add --elf-stt-common=.
	(copy_object): Also check do_elf_stt_common for ELF targets.
	(copy_file): Handle do_elf_stt_common.
	(copy_main): Handle OPTION_ELF_STT_COMMON.
	* readelf.c (apply_relocations): Support STT_COMMON.
	* testsuite/binutils-all/common-1.s: New file.
	* testsuite/binutils-all/common-1a.d: Likewise.
	* testsuite/binutils-all/common-1b.d: Likewise.
	* testsuite/binutils-all/common-1c.d: Likewise.
	* testsuite/binutils-all/common-1d.d: Likewise.
	* testsuite/binutils-all/common-1e.d: Likewise.
	* testsuite/binutils-all/common-1f.d: Likewise.
	* testsuite/binutils-all/common-2.s: Likewise.
	* testsuite/binutils-all/common-2a.d: Likewise.
	* testsuite/binutils-all/common-2b.d: Likewise.
	* testsuite/binutils-all/common-2c.d: Likewise.
	* testsuite/binutils-all/common-2d.d: Likewise.
	* testsuite/binutils-all/common-2e.d: Likewise.
	* testsuite/binutils-all/common-2f.d: Likewise.
	* testsuite/binutils-all/objcopy.exp
	(objcopy_test_elf_common_symbols): New proc.
	Run objcopy_test_elf_common_symbols for ELF targets

gas/

	PR ld/19645
	* NEWS: Mention --enable-elf-stt-common and --elf-stt-common=
	for ELF assemblers.
	* as.c (flag_use_elf_stt_common): New.
	(show_usage): Add --elf-stt-common=.
	(option_values): Add OPTION_ELF_STT_COMMON.
	(std_longopts): Add --elf-stt-common=.
	(parse_args): Handle --elf-stt-common=.
	* as.h (flag_use_elf_stt_common): New.
	* config.in: Regenerated.
	* configure: Likewise.
	* configure.ac: Add --enable-elf-stt-common and define
	DEFAULT_GENERATE_ELF_STT_COMMON.
	* gas/write.c (write_object_file): Set BFD_CONVERT_ELF_COMMON
	and BFD_USE_ELF_STT_COMMON if flag_use_elf_stt_common is set.
	* doc/as.texinfo: Document --elf-stt-common=.
	* testsuite/gas/elf/common3.s: New file.
	* testsuite/gas/elf/common3a.d: Likewise.
	* testsuite/gas/elf/common3b.d: Likewise.
	* testsuite/gas/elf/common4.s: Likewise.
	* testsuite/gas/elf/common4a.d: Likewise.
	* testsuite/gas/elf/common4b.d: Likewise.
	* testsuite/gas/i386/dw2-compress-3b.d: Likewise.
	* testsuite/gas/i386/dw2-compressed-3b.d: Likewise.
	* testsuite/gas/elf/elf.exp: Run common3a, common3b, common4a
	and common4b.
	* testsuite/gas/i386/dw2-compress-3.d: Renamed to ...
	* testsuite/gas/i386/dw2-compress-3a.d: This.  Pass
	--elf-stt-common=no to as.
	* testsuite/gas/i386/dw2-compressed-3.d: Renamed to ...
	* testsuite/gas/i386/dw2-compressed-3a.d: This.  Pass
	--elf-stt-common=no to as.
	* testsuite/gas/i386/i386.exp: Run dw2-compress-3a,
	dw2-compress-3b, dw2-compressed-3a and dw2-compressed-3b instead
	of dw2-compress-3 and dw2-compressed-3.

include/

	PR ld/19645
	* bfdlink.h (bfd_link_elf_stt_common): New enum.
	(bfd_link_info): Add elf_stt_common.

ld/

	PR ld/19645
	* NEWS: Mention -z common/-z nocommon for ELF targets.
	* emultempl/elf32.em (gld${EMULATION_NAME}_handle_option): Handle
	-z common and -z nocommon.
	* ld.texinfo: Document -z common/-z nocommon.
	* lexsup.c (elf_shlib_list_options): Add -z common/-z nocommon.
	* testsuite/ld-elf/tls_common.exp: Test --elf-stt-common=no and
	--elf-stt-common=yes with assembler.
	* testsuite/ld-elfcomm/common-1.s: New file.
	* testsuite/ld-elfcomm/common-1a.d: Likewise.
	* testsuite/ld-elfcomm/common-1b.d: Likewise.
	* testsuite/ld-elfcomm/common-1c.d: Likewise.
	* testsuite/ld-elfcomm/common-1d.d: Likewise.
	* testsuite/ld-elfcomm/common-1e.d: Likewise.
	* testsuite/ld-elfcomm/common-1f.d: Likewise.
	* testsuite/ld-elfcomm/common-2.s: Likewise.
	* testsuite/ld-elfcomm/common-2a.d: Likewise.
	* testsuite/ld-elfcomm/common-2b.d: Likewise.
	* testsuite/ld-elfcomm/common-2c.d: Likewise.
	* testsuite/ld-elfcomm/common-2d.d: Likewise.
	* testsuite/ld-elfcomm/common-2e.d: Likewise.
	* testsuite/ld-elfcomm/common-2f.d: Likewise.
	* testsuite/ld-elfcomm/common-3a.rd: Likewise.
	* testsuite/ld-elfcomm/common-3b.rd: Likewise.
	* testsuite/ld-i386/pr19645.d: Likewise.
	* testsuite/ld-i386/pr19645.s: Likewise.
	* testsuite/ld-x86-64/largecomm-1.s: Likewise.
	* testsuite/ld-x86-64/largecomm-1a.d: Likewise.
	* testsuite/ld-x86-64/largecomm-1b.d: Likewise.
	* testsuite/ld-x86-64/largecomm-1c.d: Likewise.
	* testsuite/ld-x86-64/largecomm-1d.d: Likewise.
	* testsuite/ld-x86-64/largecomm-1e.d: Likewise.
	* testsuite/ld-x86-64/largecomm-1f.d: Likewise.
	* testsuite/ld-x86-64/pr19645.d: Likewise.
	* testsuite/ld-x86-64/pr19645.s: Likewise.
	* testsuite/ld-elfcomm/elfcomm.exp: Test --elf-stt-common=yes
	with assembler.
	(assembler_generates_commons): Removed.
	Run -z common/-z nocommon tests.  Run *.d tests.
	* testsuite/ld-i386/i386.exp: Run pr19645.
	* testsuite/ld-x86-64/x86-64.exp: Likewise.
	* testsuite/ld-x86-64/dwarfreloc.exp: Test --elf-stt-common with
	assembler.  Test STT_COMMON with readelf.
2016-02-26 05:01:34 -08:00
H.J. Lu aec6b87e0b [x86] Resolve non-PIC undefweak symbols in executable
For i386 and x86-64, non-PIC references to undefined weak symbols are
resolved without dynamic relocation when creating executable.  Resolved
undefined weak symbols are removed from the dynamic symbol table in
executable.  One exception is on i386, we need resolved undefined weak
symbols in the dynamic symbol table in PIE if input relocatable files
contain branchs without PLT so that we can branch to 0 with dynamic
relocation in text section.

This makes behaviors of dynamic executable and position independent
executable predictable with mixed PIC and non-PIC references to undefined
weak symbols.  If all references to undefined weak symbols are PIC,
dynamic relocations against undefined weak symbols will be generated
in executable unless -z nodynamic-undefined-weak is passed to linker.

bfd/

	PR ld/19636
	PR ld/19704
	PR ld/19719
	* elf32-i386.c (UNDEFINED_WEAK_RESOLVED_TO_ZERO): New.
	(elf_i386_link_hash_entry): Add has_got_reloc and
	has_non_got_reloc.
	(elf_i386_link_hash_table): Add interp.
	(elf_i386_link_hash_newfunc): Initialize has_got_reloc and
	has_non_got_reloc.
	(elf_i386_copy_indirect_symbol): Copy has_got_reloc and
	has_non_got_reloc.
	(elf_i386_check_relocs): Set has_got_reloc and has_non_got_reloc.
	(elf_i386_fixup_symbol): New function.
	(elf_i386_pie_finish_undefweak_symbol): Likewise.
	(elf_i386_allocate_dynrelocs): Don't allocate space for dynamic
	relocations and discard relocations against resolved undefined
	weak symbols in executable.  Don't make resolved undefined weak
	symbols in executable dynamic.  Keep dynamic non-GOT/non-PLT
	relocation against undefined weak symbols in PIE.
	(elf_i386_size_dynamic_sections): Set interp to .interp section.
	(elf_i386_relocate_section): Don't generate dynamic relocations
	against resolved undefined weak symbols in PIE, except for
	R_386_PC32.
	(elf_i386_finish_dynamic_symbol): Keep PLT/GOT entries without
	dynamic PLT/GOT relocations for resolved undefined weak symbols.
	Don't generate dynamic relocation against resolved undefined weak
	symbol in executable.
	(elf_i386_finish_dynamic_sections): Call
	elf_i386_pie_finish_undefweak_symbol on all symbols in PIE.
	(elf_backend_fixup_symbol): New.
	* elf64-x86-64.c (UNDEFINED_WEAK_RESOLVED_TO_ZERO): New.
	(elf_x86_64_link_hash_entry): Add has_got_reloc and
	has_non_got_reloc.
	(elf_x86_64_link_hash_table): Add interp.
	(elf_x86_64_link_hash_newfunc): Initialize has_got_reloc and
	has_non_got_reloc.
	(elf_x86_64_copy_indirect_symbol): Copy has_got_reloc and
	has_non_got_reloc.
	(elf_x86_64_check_relocs): Set has_got_reloc and
	has_non_got_reloc.
	(elf_x86_64_fixup_symbol): New function.
	(elf_x86_64_pie_finish_undefweak_symbol): Likewise.
	(elf_x86_64_allocate_dynrelocs): Don't allocate space for dynamic
	relocations and discard relocations against resolved undefined
	weak symbols in executable.  Don't make resolved undefined weak
	symbols in executable dynamic.
	(elf_x86_64_size_dynamic_sections): Set interp to .interp section.
	(elf_x86_64_relocate_section): Check relocation overflow for
	dynamic relocations against unresolved weak undefined symbols.
	Don't generate dynamic relocations against resolved weak
	undefined symbols in PIE.
	(elf_x86_64_finish_dynamic_symbol): Keep PLT/GOT entries without
	dynamic PLT/GOT relocations for resolved undefined weak symbols.
	Don't generate dynamic relocation against resolved undefined weak
	symbol in executable.
	(elf_x86_64_finish_dynamic_sections): Call
	elf_x86_64_pie_finish_undefweak_symbol on all symbols in PIE.
	(elf_backend_fixup_symbol): New.

include/

	PR ld/19636
	PR ld/19704
	PR ld/19719
	* bfdlink.h (bfd_link_info): Add dynamic_undefined_weak.

ld/

	PR ld/19636
	PR ld/19704
	PR ld/19719
	* Makefile.am (ELF_X86_DEPS): Add dynamic_undefined_weak.sh.
	* Makefile.in: Regenerated.
	* NEWS: Mention -z nodynamic-undefined-weak.
	* ld.texinfo: Document -z nodynamic-undefined-weak.
	* ldmain.c (main): Initialize dynamic_undefined_weak to -1.
	* emulparams/dynamic_undefined_weak.sh: New file.
	* emulparams/elf32_x86_64.sh: Source dynamic_undefined_weak.sh.
	* emulparams/elf_i386.sh: Likewise.
	* emulparams/elf_i386_be.sh: Likewise.
	* emulparams/elf_i386_chaos.sh: Likewise.
	* emulparams/elf_i386_ldso.sh: Likewise.
	* emulparams/elf_i386_vxworks.sh: Likewise.
	* emulparams/elf_iamcu.sh: Likewise.
	* emulparams/elf_k1om.sh: Likewise.
	* emulparams/elf_l1om.sh: Likewise.
	* emulparams/elf_x86_64.sh: Likewise.
	* emulparams/extern_protected_data.sh (PARSE_AND_LIST_OPTIONS):
	Append.
	(PARSE_AND_LIST_ARGS_CASE_Z): Likewise.
	* testsuite/ld-elf/pr19719a.c: New file.
	* testsuite/ld-elf/pr19719b.c: Likewise.
	* testsuite/ld-elf/pr19719c.c: Likewise.
	* testsuite/ld-elf/pr19719d.c: Likewise.
	* testsuite/ld-i386/pr19636-1.s: Likewise.
	* testsuite/ld-i386/pr19636-1a.d: Likewise.
	* testsuite/ld-i386/pr19636-1b.d: Likewise.
	* testsuite/ld-i386/pr19636-1c.d: Likewise.
	* testsuite/ld-i386/pr19636-1d-nacl.d: Likewise.
	* testsuite/ld-i386/pr19636-1d.d: Likewise.
	* testsuite/ld-i386/pr19636-1e.d: Likewise.
	* testsuite/ld-i386/pr19636-1f.d: Likewise.
	* testsuite/ld-i386/pr19636-1g.d: Likewise.
	* testsuite/ld-i386/pr19636-1h.d: Likewise.
	* testsuite/ld-i386/pr19636-1i.d: Likewise.
	* testsuite/ld-i386/pr19636-2.s: Likewise.
	* testsuite/ld-i386/pr19636-2a.d: Likewise.
	* testsuite/ld-i386/pr19636-2b.d: Likewise.
	* testsuite/ld-i386/pr19636-2c-nacl.d: Likewise.
	* testsuite/ld-i386/pr19636-2c.d: Likewise.
	* testsuite/ld-i386/pr19636-2d-nacl.d: Likewise.
	* testsuite/ld-i386/pr19636-2d.d: Likewise.
	* testsuite/ld-i386/pr19636-2e-nacl.d: Likewise.
	* testsuite/ld-i386/pr19636-2e.d: Likewise.
	* testsuite/ld-i386/pr19636-3.s: Likewise.
	* testsuite/ld-i386/pr19636-3a.d: Likewise.
	* testsuite/ld-i386/pr19636-3b.d: Likewise.
	* testsuite/ld-i386/pr19636-3c.d: Likewise.
	* testsuite/ld-i386/pr19636-3d.d: Likewise.
	* testsuite/ld-i386/pr19636-3e.d: Likewise.
	* testsuite/ld-i386/pr19636-3f.d: Likewise.
	* testsuite/ld-i386/pr19636-3g.d: Likewise.
	* testsuite/ld-i386/pr19636-4.s: Likewise.
	* testsuite/ld-i386/pr19636-4a.d: Likewise.
	* testsuite/ld-i386/pr19636-4b.d: Likewise.
	* testsuite/ld-i386/pr19636-4c.d: Likewise.
	* testsuite/ld-i386/pr19636-4d.d: Likewise.
	* testsuite/ld-i386/pr19704.out: Likewise.
	* testsuite/ld-i386/pr19704a.c: Likewise.
	* testsuite/ld-i386/pr19704b.c: Likewise.
	* testsuite/ld-x86-64/pr19636-1.s: Likewise.
	* testsuite/ld-x86-64/pr19636-1a.d: Likewise.
	* testsuite/ld-x86-64/pr19636-1b.d: Likewise.
	* testsuite/ld-x86-64/pr19636-1c.d: Likewise.
	* testsuite/ld-x86-64/pr19636-1d.d: Likewise.
	* testsuite/ld-x86-64/pr19636-1e.d: Likewise.
	* testsuite/ld-x86-64/pr19636-1f.d: Likewise.
	* testsuite/ld-x86-64/pr19636-1g.d: Likewise.
	* testsuite/ld-x86-64/pr19636-2.s: Likewise.
	* testsuite/ld-x86-64/pr19636-2a.d: Likewise.
	* testsuite/ld-x86-64/pr19636-2b.d: Likewise.
	* testsuite/ld-x86-64/pr19636-2c.d: Likewise.
	* testsuite/ld-x86-64/pr19636-2d-nacl.d: Likewise.
	* testsuite/ld-x86-64/pr19636-2d.d: Likewise.
	* testsuite/ld-x86-64/pr19636-2e.d: Likewise.
	* testsuite/ld-x86-64/pr19636-2f.d: Likewise.
	* testsuite/ld-x86-64/pr19636-2g.d: Likewise.
	* testsuite/ld-x86-64/pr19636-2h.d: Likewise.
	* testsuite/ld-x86-64/pr19636-2i.d: Likewise.
	* testsuite/ld-x86-64/pr19636-3.s: Likewise.
	* testsuite/ld-x86-64/pr19636-3a.d: Likewise.
	* testsuite/ld-x86-64/pr19636-3b.d: Likewise.
	* testsuite/ld-x86-64/pr19636-3c.d: Likewise.
	* testsuite/ld-x86-64/pr19636-3d.d: Likewise.
	* testsuite/ld-x86-64/pr19704.out: Likewise.
	* testsuite/ld-x86-64/pr19704a.c: Likewise.
	* testsuite/ld-x86-64/pr19704b.c: Likewise.
	* testsuite/ld-elf/shared.exp (mix_pic_and_non_pic): New.
	Run mix_pic_and_non_pic.
	* testsuite/ld-i386/i386.exp (undefined_weak): New.
	Run undefined_weak and PR ld/19636 tests.
	* testsuite/ld-x86-64/x86-64.exp: Likewise.
	* testsuite/ld-x86-64/pr13082-3b.d: Updated.
	* testsuite/ld-x86-64/pr13082-4b.d: Likewise.
2016-02-26 04:55:57 -08:00
Jiong Wang b8ec4e871e [ARM] Add FP16 feature extension for ARMv8.2 architecture
include/
  * opcode/arm.h (ARM_EXT2_FP16_INSN): New.

gas/
  * config/tc-arm.c (arm_ext_fp16): New.
  (arm_extensions): New entry for "fp16".
2016-02-19 14:27:23 +00:00
Claudiu Zissulescu 4670103e86 Add support for ARC instruction relaxation in the assembler.
gas/
2016-01-26  Claudiu Zissulescu  <claziss@synopsys.com>
	    Janek van Oirschot <jvanoirs@synopsys.com>

        * config/tc-arc.h (TC_FRAG_TYPE, TC_PCREL_ADJUST, MAX_INSN_ARGS)
        (MAX_INSN_FLGS, MAX_FLAG_NAME_LENGHT, TC_GENERIC_RELAX_TABLE):
        Define.
        (arc_flags, arc_relax_type): New structure.
        * config/tc-arc.c (FRAG_MAX_GROWTH, RELAX_TABLE_ENTRY)
	(RELAX_TABLE_ENTRY_MAX): New define.
        (relaxation_state, md_relax_table, arc_relaxable_insns)
	(arc_num_relaxable_ins): New variable.
	(rlx_operand_type, arc_rlx_types): New enums.
	(arc_relaxable_ins): New structure.
        (OPTION_RELAX): New option.
        (arc_insn): New relax member.
        (arc_flags): Remove.
        (relax_insn_p): New function.
        (apply_fixups): Likewise.
        (relaxable_operand): Likewise.
        (may_relax_expr): Likewise.
        (relaxable_flag): Likewise.
        (arc_pcrel_adjust): Likewise.
        (md_estimate_size_before_relax): Implement.
        (md_convert_frag): Likewise.
        (md_parse_option): Handle new mrelax option.
        (md_show_usage): Likewise.
        (assemble_insn): Set relax member.
        (emit_insn0): New function.
        (emit_insn1): Likewise.
        (emit_insn): Handle relaxation case.
	* NEWS: Mention the new relaxation option.
	* doc/c-arc.texi (ARC Options): Document new mrelax option.

gas/testsuite
2016-01-26  Claudiu Zissulescu  <claziss@synopsys.com>

        * gas/arc/relax-avoid1.d: New file.
        * gas/arc/relax-avoid1.s: Likewise.
        * gas/arc/relax-avoid2.d: Likewise.
        * gas/arc/relax-avoid2.s: Likewise.
        * gas/arc/relax-avoid3.d: Likewise.
        * gas/arc/relax-avoid3.s: Likewise.
	* gas/arc/relax-b.d: Likewise.
        * gas/arc/relax-b.s: Likewise.

include/opcode/
2016-01-26  Claudiu Zissulescu  <claziss@synopsys.com>
	    Janek van Oirschot  <jvanoirs@synopsys.com>

        * arc.h (arc_opcode arc_relax_opcodes, arc_num_relax_opcodes):
        Declare.

opcodes/
2016-01-26  Claudiu Zissulescu  <claziss@synopsys.com>
	    Janek van Oirschot  <jvanoirs@synopsys.com>

        * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
        variable.
2016-02-10 12:09:01 +00:00
Nick Clifton 609332f15c Fix compile time warnings building the binutils with a gcc6 compiler.
include	* opcode/metag.h (metag_scondtab): Mark as possibly unused.
	* opcode/nds32.h (nds32_r45map): Likewise.
	(nds32_r54map): Likewise.
	* opcode/visium.h (gen_reg_table): Likewise.
	(fp_reg_table, cc_table, opcode_table): Likewise.

bfd	* oasys.c (oasys_archive_p): Fix indentation.
	* elf32-nds32.c (nds32_elf_relax_section): Use an unsigned
	constant for left shifting.
2016-02-09 16:34:24 +00:00
Alan Modra 24f5f69a8a Fix macro redefinition error on Solaris
PR 16583
	* elf/common.h (AT_SUN_HWCAP): Undef before defining.
2016-02-09 13:11:16 +10:30
Nick Clifton c1d9289fef Fix the encoding of the MSP430's RRUX instruction.
PR target/19561
opcdoe	* msp430-dis.c (print_insn_msp430): Add a special case for
	decoding an RRC instruction with the ZC bit set in the extension
	word.

include	* opcode/msp430.h (IGNORE_CARRY_BIT): New define.
	(RRUX): Synthesise using case 2 rather than 7.

gas	* config/tc-msp430.c (msp430_operands): Remove case 7.  Use case 2
	to handle encoding of RRUX instruction.
	* testsuite/gas/msp430/msp430x.s: Add more tests of the extended
	shift instructions.
	* testsuite/gas/msp430/msp430x.d: Update expected disassembly.
2016-02-04 09:55:10 +00:00
John Baldwin f4ddf30f11 Add support to readelf for reading FreeBSD ELF core notes.
binutils/ChangeLog:

	* readelf.c (get_freebsd_elfcore_note_type): New
	(process_note): Add support for FreeBSD core notes.

include/ChangeLog:

	* elf/common.h (NT_FREEBSD_THRMISC): Define.
	(NT_FREEBSD_PROCSTAT_PROC): Define.
	(NT_FREEBSD_PROCSTAT_FILES): Define.
	(NT_FREEBSD_PROCSTAT_VMMAP): Define.
	(NT_FREEBSD_PROCSTAT_GROUPS): Define.
	(NT_FREEBSD_PROCSTAT_UMASK): Define.
	(NT_FREEBSD_PROCSTAT_RLIMIT): Define.
	(NT_FREEBSD_PROCSTAT_OSREL): Define.
	(NT_FREEBSD_PROCSTAT_PSSTRINGS): Define.
	(NT_FREEBSD_PROCSTAT_AUXV): Define.
2016-01-19 08:15:08 -08:00
Miranda Cupertino 34e967a5f3 Add PIC and TLS support to the ARC target.
bfd/ChangeLog:
	* arc-plt.def: New file.
	* arc-plt.h: Likewise.
	* elf32-arc.c (elf_arc_abs_plt0_entry, elf_arc_abs_pltn_entry,
		       elf_arcV2_abs_plt0_entry, elf_arcV2_abs_pltn_entry,
		       elf_arc_pic_plt0_entry, elf_arc_pic_pltn_entry,
		       elf_arcV2_pic_plt0_entry, elf_arcV2_pic_pltn_entry): Remove.
	(name_for_global_symbol): Added.
	(ADD_RELA): Helper to create dynamic relocs.
	(new_got_entry_to_list): Create a new got entry in linked list.
	(symbol_has_entry_of_type): Search for specific type of entry in
	list.
	(is_reloc_for_GOT): return FALSE for any TLS related relocs.
	(is_reloc_for_TLS, arc_elf_set_private_flags)
	(arc_elf_print_private_bfd_data, arc_elf_copy_private_bfd_data)
	(arc_elf_merge_private_bfd_data): New functions.
	(debug_arc_reloc): Cleaned debug info printing.
	(PDATA reloc): Changed not to perform address alignment.
	(reverse_me): Added. Fix for ARC_32 relocs.
	(arc_do_relocation): Return bfd_reloc_of when no relocation should
	occur.
	(arc_get_local_got_ents): Renamed from arc_get_local_got_offsets.
	Changed function to access an array of list of GOT entries instead
	of just an array of offsets.
	(elf_arc_relocate_section): Added support for PIC and TLS related relocations.
	(elf_arc_check_relocs): Likewise.
	(elf_arc_adjust_dynamic_symbol, elf_arc_finish_dynamic_symbol,
	(elf_arc_finish_dynamic_sections): Likewise
	(arc_create_dynamic_sections): Modified conditions to create
	dynamic sections.
	(ADD_SYMBOL_REF_SEC_AND_RELOC): New macro.
	(plt_do_relocs_for_symbol, relocate_plt_for_symbol)
	(relocate_plt_for_entry): Changed to support new way to define PLT
	related code.
	(add_symbol_to_plt): Likewise.
	(arc_elf_link_hash_table_create): New function.

include/ChangeLog:
	* elf/arc-reloc.def (ARC_32, ARC_GOTPC, ARC_TLS_GD_GOT)
	(ARC_TLS_IE_GOT, ARC_TLS_DTPOFF, ARC_TLS_DTPOFF_S9, ARC_TLS_LE_S9)
	(ARC_TLS_LE_32): Fixed formula.
	(ARC_TLS_GD_LD): Use new special function.
	* opcode/arc-func.h: Changed all the replacement
	functions to clear the patching bits before doing an or it with the value
	argument.
2016-01-19 15:25:58 +00:00
Nick Clifton 9ae678af99 Use a 32-bit value to hold the section number in the internal COFF symbol structure.
PR ld/19440
inc	* coff/internal.h (internal_syment): Use int to hold section
	number.
	(N_UNDEF): Cast to int not short.
	(N_ABS): Likewise.
	(N_DEBUG): Likewise.
	(N_TV): Likewise.
	(P_TV): Likewise.

bfd	PR ld/19440
	* coff-rs6000.c (_bfd_xcoff_swap_sym_in): Sign extend external
	section number into internal section number.
	* coff64-rs6000.c (_bfd_xcoff64_swap_sym_in): Likewise.
	* coffswap.h (coff_swap_sym_in): Likewise.
	* peXXigen.c (_bfd_XXi_swap_sym_in): Likewise.
	* coffcode.h (_coff_bigobj_swap_sym_in): Make sure that internal
	section number field is big enough to hold the external value.
2016-01-18 15:58:47 +00:00
Nick Clifton 4849dfd8f4 Import changes made to files shared with the FSF GCC project.
Import the following changes from the GCC mainline:

	2015-11-13  Tsvetkova Alexandra  <aleksandra.tsvetkova@intel.com>

	* configure.ac: Enable libmpx by default.
	* configure: Regenerated.

	2015-11-19  Martin Liska  <mliska@suse.cz>

	* .gitignore: Add .clang-format to ignored files.
	* Makefile.tpl: Add clang-format.
	* Makefile.in: Regenerate.

	2015-12-01  Andreas Tobler  <andreast@gcc.gnu.org>

	PR libffi/65726
	* Makefile.def (lang_env_dependencies): Make libffi depend
	on cxx.
	* Makefile.in: Regenerate.

	2015-12-02  Ian Lance Taylor  <iant@google.com>

	PR go/66147
	* Makefile.tpl (HOST_EXPORTS): Add XGCC_FLAGS_FOR_TARGET.
	* Makefile.in: Regenerate.

	2015-12-17  Nathan Sidwell  <nathan@acm.org>

	* config/isl.m4 (ISL_CHECK_VERSION): Add gmp libs.
	* configure: Regenerate.

	2015-12-17  Sebastian Pop  <s.pop@samsung.com>

	* Makefile.in: Replace ISL with isl.
	* Makefile.tpl: Same.
	* config/isl.m4: Same.
	* configure.ac: Same.
	* contrib/download_prerequisites: Same.
	* configure: Regenerate.

	2016-01-01  Ben Elliston  <bje@gnu.org>

	* config.guess: Import version 2016-01-01.
	* config.sub: Likewise.

include	2016-01-07  Mike Frysinger  <vapier@gentoo.org>

	* longlong.h: Change !__SHMEDIA__ to
	(!defined (__SHMEDIA__) || !__SHMEDIA__).
	Change __SHMEDIA__ to defined (__SHMEDIA__) && __SHMEDIA__.
2016-01-11 11:06:56 +00:00
Mike Frysinger 2e3d4f4d5d sim: sim_{create_inferior,open,parse_args}: constify argv/env slightly
2016-01-03  Mike Frysinger  <vapier@gentoo.org>

	* sim-options.c (sim_parse_args): Mark argv array const.
	* sim-options.h (sim_parse_args): Likewise.
2016-01-06 21:48:59 -05:00
Maciej W. Rozycki b31e480331 MIPS/include: opcode/mips.h: Add a summary of MIPS16 operand codes
include/
	* opcode/mips.h: Add a summary of MIPS16 operand codes.
2016-01-06 18:37:58 +00:00
Mike Frysinger b36c1ccb1f libiberty: {count,dup,write}argv: constify argv input slightly
Would be more useful if we could use "const char * const *", but there's
a long standing bug where gcc warns about incompatible pointers when you
try to pass in "char **".  We can at least constify the array itself as
gcc will not warn in that case.
2016-01-05 15:25:13 -05:00
Alan Modra 6f2750feaf Copyright update for binutils 2016-01-01 23:00:01 +10:30
Alan Modra 3499769a6a New 2016 binutils ChangeLog files
Note that this does not create bfd/doc/ChangeLog, */testsuite/ChangeLog
and include/*/ChangeLog files.
2016-01-01 22:59:42 +10:30
Alan Modra 4120fa118f binutils ChangeLog rotation 2016-01-01 22:59:17 +10:30
Joel Brobecker 618f726fcb GDB copyright headers update after running GDB's copyright.py script.
gdb/ChangeLog:

        Update year range in copyright notice of all files.
2016-01-01 08:43:22 +04:00
Alan Modra 331e61312e Fix assorted ChangeLog errors 2015-12-30 11:44:35 +10:30
Thomas Preud'homme ff8646eef8 Add assembler support for ARMv8-M Baseline
2015-12-24  Thomas Preud'homme  <thomas.preudhomme@arm.com>

bfd/
    (tag_cpu_arch_combine): Adjust comment in v4t_plus_v6_m with regards
    to merging with ARMv8-M Baseline.

binutils/
    * readelf.c (arm_attr_tag_CPU_arch): Add ARMv8-M Baseline Tag_CPU_arch
    value.

gas/
    * config/tc-arm.c (arm_ext_v6t2_v8m): New feature for instructions
    shared between ARMv6T2 and ARMv8-M.
    (move_or_literal_pool): Check mov.w/mvn and movw availability against
    arm_ext_v6t2 and arm_ext_v6t2_v8m respectively instead of checking
    arm_arch_t2.
    (do_t_branch): Error out for wide conditional branch instructions if
    targetting ARMv8-M Baseline.
    (non_v6t2_wide_only_insn): Add the logic for new wide-only instructions
    in ARMv8-M Baseline.
    (wide_insn_ok): New function.
    (md_assemble): Use wide_insn_ok instead of non_v6t2_wide_only_insn and
    adapt error message for unsupported wide instruction to ARMv8-M
    Baseline.
    (insns): Reorganize instructions shared by ARMv8-M Baseline and
    ARMv6t2 architecture.
    (arm_cpus): Set feature bit ARM_EXT2_V6T2_V8M for marvell-pj4 and
    marvell-whitney cores.
    (arm_archs): Define armv8-m.base architecture.
    (cpu_arch_ver): Define ARM_ARCH_V8M_BASE architecture version.
    (aeabi_set_public_attributes): Add logic to set Tag_CPU_arch to 17 for
    ARMv8-M Mainline.  Set Tag_DIV_use for ARMv8-M Baseline as well.

gas/testsuite/
    * gas/arm/archv8m-base.d: New file.
    * gas/arm/attr-march-armv8m.base.d: Likewise.
    * gas/arm/armv8m.base-idiv.d: Likewise.
    * gas/arm/any-armv8m.d: Adapt to deal with ARMv8-M Baseline.

include/elf/
    * arm.h (TAG_CPU_ARCH_V8M_BASE): Declare.

include/opcode/
    * arm.h (ARM_EXT2_V6T2_V8M): New extension bit.
    (ARM_AEXT2_V8A): New architecture extension bitfield.
    (ARM_AEXT2_V8_1A): Use ARM_AEXT2_V8A instead of ARM_EXT2_ATOMICS.
    (ARM_AEXT_V8M_BASE): New architecture extension bitfield.
    (ARM_AEXT2_V8M): Add extension bit ARM_EXT2_V6T2_V8M.
    (ARM_ARCH_V6T2): Use ARM_EXT2_V6T2_V8M for the second extension
    bitfield.
    (ARM_ARCH_V6KT2): Likewise.
    (ARM_ARCH_V6ZT2): Likewise.
    (ARM_ARCH_V6KZT2): Likewise.
    (ARM_ARCH_V7): Likewise.
    (ARM_ARCH_V7A): Likewise.
    (ARM_ARCH_V7VE): Likewise.
    (ARM_ARCH_V7R): Likewise.
    (ARM_ARCH_V7M): Likewise.
    (ARM_ARCH_V7EM): Likewise.
    (ARM_ARCH_V8A): Likewise.
    (ARM_ARCH_V8M_BASE): New architecture bitfield.
    (ARM_ARCH_THUMB2): Include instructions shared by ARMv6t2 and ARMv8-M.
    (ARM_ARCH_V7A_SEC): Use ARM_EXT2_V6T2_V8M for the second extension
    bitfield and reindent.
    (ARM_ARCH_V7A_MP_SEC): Likewise.
    (ARM_ARCH_V7R_IDIV): Likewise.
    (ARM_ARCH_V8A_FP): Use ARM_AEXT2_V8A instead of ARM_EXT2_ATOMICS.
    (ARM_ARCH_V8A_SIMD): Likewise.
    (ARM_ARCH_V8A_CRYPTOV1): Likewise.

opcodes/
    * arm-dis.c (arm_opcodes): Guard movw, movt cbz, cbnz, clrex, ldrex,
    ldrexb, ldrexh, strex, strexb, strexh shared by ARMv6T2 and ARMv8-M by
    ARM_EXT2_V6T2_V8M instead of ARM_EXT_V6T2.
2015-12-24 17:27:21 +08:00
Thomas Preud'homme 4ed7ed8db2 Add assembler support for ARMv8-M Mainline
2015-12-24  Thomas Preud'homme  <thomas.preudhomme@arm.com>

bfd/
    (tag_cpu_arch_combine): Adjust v4t_plus_v6_m and comb array to account
    for new TAG_CPU_ARCH_V4T_PLUS_V6_M value.  Deal with NULL values in
    comb array.

binutils/
    * readelf.c (arm_attr_tag_CPU_arch): Add ARMv8-M Mainline Tag_CPU_arch
    value.
    (arm_attr_tag_THUMB_ISA_use): Add ARMv8-M Mainline Tag_THUMB_ISA_use
    value.

gas/
    * config/tc-arm.c (arm_ext_m): Include ARMv8-M.
    (arm_ext_v8m): New feature for ARMv8-M.
    (arm_ext_atomics): New feature for ARMv8 atomics.
    (do_tt): New encoding function for TT* instructions.
    (insns): Add new entries for ARMv8-M specific instructions and
    reorganize the ones shared by ARMv8-M Mainline and ARMv8-A.
    (arm_archs): Define armv8-m.main architecture.
    (cpu_arch_ver): Define ARM_ARCH_V8M_MAIN architecture version and
    clarify the ordering rule.
    (aeabi_set_public_attributes): Use TAG_CPU_ARCH_* macro to refer to
    Tag_CPU_arch values for ARMv7e-M detection.  Add logic to keep setting
    Tag_CPU_arch to ARMv8-A for -march=all.  Also set Tag_CPU_arch_profile
    to 'A' if extension bit for atomic instructions is set, unless it is
    ARMv8-M.  Set Tag_THUMB_ISA_use to 3 for ARMv8-M.  Set Tag_DIV_use to 0
    for ARMv8-M Mainline.

gas/testsuite/
    * gas/arm/archv8m.s: New file.
    * gas/arm/archv8m-main.d: Likewise.
    * gas/arm/attr-march-armv8m.main.d: Likewise.
    * gas/arm/any-armv8m.s: Likewise.
    * gas/arm/any-armv8m.d: Likewise.

include/elf/
    * arm.h (TAG_CPU_ARCH_V8M_MAIN): Declare.
    (MAX_TAG_CPU_ARCH): Define to TAG_CPU_ARCH_V8M_MAIN.
    (TAG_CPU_ARCH_V4T_PLUS_V6_M): Define to unused value 15.

include/opcode/
    * arm.h (ARM_EXT2_ATOMICS): New extension bit.
    (ARM_EXT2_V8M): Likewise.
    (ARM_EXT_V8): Adjust comment with regards to atomics and remove
    mention of legacy use for that bit.
    (ARM_AEXT2_V8_1A): New architecture extension bitfield.
    (ARM_AEXT2_V8_2A): Likewise.
    (ARM_AEXT_V8M_MAIN): Likewise.
    (ARM_AEXT2_V8M): Likewise.
    (ARM_ARCH_V8A): Use ARM_EXT2_ATOMICS for features in second bitfield.
    (ARM_ARCH_V8_1A): Likewise with ARM_AEXT2_V8_1A.
    (ARM_ARCH_V8_2A): Likewise with ARM_AEXT2_V8_2A.
    (ARM_ARCH_V8M_MAIN): New architecture feature bitfield.
    (ARM_ARCH_V8A_FP): Use ARM_EXT2_ATOMICS for features in second bitfield
    and reindent.
    (ARM_ARCH_V8A_SIMD): Likewise.
    (ARM_ARCH_V8A_CRYPTOV1): Likewise.
    (ARM_ARCH_V8_1A_FP): Use ARM_AEXT2_V8_1A to set second bitfield of
    feature bits.
    (ARM_ARCH_V8_1A_SIMD): Likewise.
    (ARM_ARCH_V8_1A_CRYPTOV1): Likewise.

opcodes/
    * arm-dis.c (arm_opcodes): Guard lda, ldab, ldaex, ldaexb, ldaexh, stl,
    stlb, stlh, stlex, stlexb and stlexh by ARM_EXT2_ATOMICS instead of
    ARM_EXT_V8.
    (thumb32_opcodes): Add entries for wide ARMv8-M instructions.
2015-12-24 17:26:54 +08:00
Thomas Preud'homme fc289b0a83 Consolidate Thumb-1/Thumb-2 ISA detection
2015-12-24  Thomas Preud'homme  <thomas.preudhomme@arm.com>

gas/
    * config/tc-arm.c (move_or_literal_pool): Check mov.w, mvm and movw
    availability against arm_ext_v6t2 instead of checking arm_arch_t2,
    fixing comments along the way.
    (handle_it_state): Check arm_ext_v6t2 instead of arm_arch_t2 to
    generate IT instruction.
    (t1_isa_t32_only_insn): New function.
    (md_assemble): Use above new function to check for invalid wide
    instruction for CPU Thumb ISA and to determine what Thumb extension
    bit is necessary for that instruction.
    (md_apply_fix): Use arm_ext_v6t2 instead of arm_arch_t2 to decide if
    branch is out of range.

include/opcode/
    * arm.h (ARM_ARCH_THUMB2): Add comment explaining its meaning and
    remove extension bit not including any Thumb-2 instruction.
2015-12-24 17:03:50 +08:00
Mickael Guene ac4c9b0459 Add support for ARM's NOREAD section flag.
include/elf
     * arm.h: Add arm SHF_ARM_NOREAD section flag.

bfd  * bfd-in2.h: Regenerate.
     * section.c: Add SEC_ELF_NOREAD.
     * elf32-arm.c (elf32_arm_post_process_headers): Only set
     PF_X attribute if a segment only contains section with
     SHF_ARM_NOREAD flag.
     (elf32_arm_fake_sections): Add SEC_ELF_NOREAD conversion.
     (elf32_arm_section_flags): New function to convert SHF_ARM_NOREAD
     to bfd flag.
     (elf32_arm_lookup_section_flags): New function to allow
     INPUT_SECTION_FLAGS directive with SHF_ARM_NOREAD flag.
     (elf32_arm_special_sections): Add special sections array
     to catch section prefix by '.text.noread' pattern.

ld/testsuite
     * ld-arm/arm-elf.exp: New tests.
     * ld-arm/thumb1-input-section-flag-match.d: New
     * ld-arm/thumb1-input-section-flag-match.s: New
     * ld-arm/thumb1-noread-not-present-mixing-two-section.d: New
     * ld-arm/thumb1-noread-not-present-mixing-two-section.s: New
     * ld-arm/thumb1-noread-present-one-section.d: New
     * ld-arm/thumb1-noread-present-one-section.s: New
     * ld-arm/thumb1-noread-present-two-section.d: New
     * ld-arm/thumb1-noread-present-two-section.s: New

binutils
	* readelf.c (get_elf_section_flags): Add support for ARM specific
	section flags.
2015-12-22 14:12:35 +00:00
Ramana Radhakrishnan 10c9892b66 [Patch ARM] Fix build attributes for armv8-a in case of assembler files that contain no directives.
There is currently a problem in the way in which we produce
build attributes for simple assembler files that have armv8-a
instructions.

In these case we need to generate TAG_ISA_THUMB_Use to be Thumb-2
and set the architecture profile to be 'A' rather than not
setting architecture profile to be 'A' and setting TAG_ISA_THUMB_Use
to be Thumb-1.

This is a pre-requisite for any v8-m patches that have been posted.
arm-none-eabi gas testsuite run. no regressions.

2015-12-17  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

	* gas/config/tc-arm.c (aeabi_set_public_attributes): Adjust
	TAG_ARCH_profile for armv8-a.
	* gas/testsuite/gas/arm/armv8a-automatic-hlt.d: New test.
	* gas/testsuite/gas/arm/armv8a-automatic-hlt.s: New test.
	* gas/testsuite/gas/arm/armv8a-automatic-lda.d: New test.
	* gas/testsuite/gas/arm/armv8a-automatic-lda.s: New test.
2015-12-17 11:34:39 +00:00
Christophe Lyon 0bef041426 Add forgotten ChangeLog updates for 72d98d16ed09584660d0cbb759d90f8dfeef2343:
2015-12-16  Mickael Guene <mickael.guene@st.com>

	bfd/
	* bfd-in2.h: Regenerate.
	* reloc.c: Add new relocations.
	* libbfd.h (bfd_reloc_code_real_names): Add new relocations
	display names.
	* elf32-arm.c (elf32_arm_howto_table_1): Add HOWTO for new
	relocations.
	(elf32_arm_reloc_map): Add bfd/arm mapping for new relocations.
	(elf32_arm_final_link_relocate): Implement new relocations
	resolution.

	gas/
	* doc/c-arm.texi: Add documentation about new directives
	* config/tc-arm.c (group_reloc_table): Add mapping between gas
	syntax and new relocations.
	(do_t_add_sub): Keep new relocations for add operand.
	(do_t_mov_cmp): Keep new relocations for mov operand.
	(insns): Use 'shifter operand with possible group relocation'
	operand parse code for movs operand.
	(md_apply_fix): Implement mov and add encoding when new
	relocations on them.
	(tc_gen_reloc): Add new relocations.
	(arm_fix_adjustable): Since offset has a limited range ([0:255])
	we disable adjust_reloc_syms() for new relocations.

	gas/testsuite/
	* gas/arm/adds-thumb1-reloc-local.d: New
	* gas/arm/adds-thumb1-reloc-local.s: New
	* gas/arm/movs-thumb1-reloc-local.d: New
	* gas/arm/movs-thumb1-reloc-local.s: New

	include/
	* elf/arm.h: Add new arm relocations.

	ld/testsuite/
	* ld-arm/arm-elf.exp (armelftests_common): Add new relocations
	tests.
	* ld-arm/thumb1-adds.d: New
	* ld-arm/thumb1-adds.s: New
	* ld-arm/thumb1-movs.d: New
	* ld-arm/thumb1-movs.s: New
2015-12-17 11:14:37 +01:00
Mickael Guene 72d98d16ed [ARM] Add support for thumb1 pcrop relocations.
To support thumb1 execute-only code we need to support four new
relocations (R_ARM_THM_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G1_NC,
R_ARM_THM_ALU_ABS_G2_NC and  R_ARM_THM_ALU_ABS_G3_NC).
These relocations allow the static linker to finalize construction
of symbol address.
Typical sequence of code to get address of the symbol foo is then
the following :
	movs	r3, #:upper8_15:#foo
	lsls	r3, #8
	adds	r3, #:upper0_7:#foo
	lsls	r3, #8
	adds	r3, #:lower8_15:#foo
	lsls	r3, #8
	adds	r3, #:lower0_7:#foo
This will give following sequence of text and relocations after
assembly :
   4:	2300      	movs	r3, #0
			4: R_ARM_THM_ALU_ABS_G3_NC	foo
   6:	021b      	lsls	r3, r3, #8
   8:	3300      	adds	r3, #0
			8: R_ARM_THM_ALU_ABS_G2_NC	foo
   a:	021b      	lsls	r3, r3, #8
   c:	3300      	adds	r3, #0
			c: R_ARM_THM_ALU_ABS_G1_NC	foo
   e:	021b      	lsls	r3, r3, #8
  10:	3300      	adds	r3, #0
			10: R_ARM_THM_ALU_ABS_G0_NC	foo
2015-12-16 10:19:51 +01:00
Matthew Wahab 29b1539538 [ARM] Enable CRC by default for ARMv8.1 and later.
ARMv8.1 includes CRC as a required extension but the +crc feature isn't
enabled by -march=armv8.1-a as it should be. This patch fixes that.

opcode/include
2015-12-15  Matthew Wahab  <matthew.wahab@arm.com>

	* arm.h (ARM_ARCH_V8_1A): Add the CRC_EXT_ARMV8 co-processor
	feature macro.
	(ARM_ARCH_V8_2A): Likewise.

Change-Id: Id1fe0e6fa51dede19d61e1fd08e68628ea1b1e9e
2015-12-15 16:38:58 +00:00
Yoshinori Sato a117b0a51c Add support for RX V2 Instruction Set
binutils
	* readelf.c(get_machine_flags): Add v2 flag.

gas
	* config/rx-defs.h(rx_cpu_type): Add RXV2 type.
	* config/tc-rx.c(cpu_type_list): New type lookup table.
	(md_parse_option): Use lookup table for choose cpu.
	(md_show_usage): Add rxv2 for mcpu option.
	* doc/c-rx.texi: Likewise.
	* config/rx-parse.y: Add v2 instructions and ACC register.
	(rx_check_v2): check v2 type.

include/elf
	* rx.h(E_FLAG_RX_V2): New RXv2 type.

include/opcode
	* rx.h: Add new instructions.

opcoes
	* rx-deocde.opc(rx_decode_opcode): Add new instructions pattern.
	* rx-dis.c(register_name): Add new register.

gas/testsuite
	* gas/rx/emaca.d: New.
	* gas/rx/emaca.sm: New.
	* gas/rx/emsba.d: New.
	* gas/rx/emsba.sm: New.
	* gas/rx/emula.d: New.
	* gas/rx/emula.sm: New.
	* gas/rx/fadd.d: Add new pattern.
	* gas/rx/fadd.sm: Add new pattern.
	* gas/rx/fmul.d: Add new pattern.
	* gas/rx/fmul.sm: Add new pattern.
	* gas/rx/fsqrt.d: New.
	* gas/rx/fsqrt.sm: New.
	* gas/rx/fsub.d: Add new pattern.
 	* gas/rx/fsub.sm: Add new pattern.
	* gas/rx/ftou.d: New.
	* gas/rx/ftou.sm: New.
	* gas/rx/maclh.d: New.
	* gas/rx/maclh.sm: New.
	* gas/rx/maclo.d: Add new pattern.
	* gas/rx/maclo.sm: Add new pattern.
	* gas/rx/macros.inc: Add new register.
	* gas/rx/movco.d: New.
	* gas/rx/movco.sm: New.
	* gas/rx/movli.d: New.
	* gas/rx/movli.sm: New.
	* gas/rx/msbhi.d: New.
	* gas/rx/msbhi.sm: New.
	* gas/rx/msblh.d: New.
	* gas/rx/msblh.sm: New.
	* gas/rx/msblo.d: New.
	* gas/rx/msblo.sm: New.
	* gas/rx/mullh.d: New.
	* gas/rx/mullh.sm: New.
	* gas/rx/mvfacgu.d: New.
	* gas/rx/mvfacgu.sm: New.
	* gas/rx/mvfachi.d: Add new pattern.
	* gas/rx/mvfachi.sm: Add new pattern.
	* gas/rx/mvfaclo.d: Add new pattern.
	* gas/rx/mvfaclo.sm: Add new pattern.
	* gas/rx/mvfacmi.d: Add new pattern.
	* gas/rx/mvfacmi.sm: Add new pattern.
	* gas/rx/mvfc.d: Add new pattern.
	* gas/rx/mvtacgu.d: New.
	* gas/rx/mvtacgu.sm: New.
	* gas/rx/mvtc.d: Add new pattern.
	* gas/rx/popc.d: Add new pattern.
	* gas/rx/pushc.d: Add new pattern.
	* gas/rx/racl.d: New.
	* gas/rx/racl.sm: New.
	* gas/rx/racw.d: Add new pattern.
	* gas/rx/racw.sm: Add new pattern.
	* gas/rx/rdacl.d: New.
	* gas/rx/rdacl.sm: New.
	* gas/rx/rdacw.d: New.
	* gas/rx/rdacw.sm: New.
	* gas/rx/rx.exp: Add option.
	* gas/rx/stnz.d: Add new pattern.
	* gas/rx/stnz.sm: Add new pattern.
	* gas/rx/stz.d: Add new pattern.
	* gas/rx/stz.sm: Add new pattern.
	* gas/rx/utof.d: New.
	* gas/rx/utof.sm: New.
2015-12-15 09:26:56 +00:00
Matthew Wahab 3067d3b96c [AArch64][PATCH 11/14] Add support for the 2H vector type.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. The FP16 additions to the
scalar pairwise group introduce a new vector type, 2H. This patch adds
support for this vector type to binutils.

The patch adds a new operand qualifier to the enum
aarch64.h:aarch64_opnd_qualifier. This interferes with the calculation
used by aarch64-dis.c:get_vreg_qualifier_from_value, called when
decoding an instruction. Since the new vector type is only used in FP16
scalar pairwise instructions which do not require the function, this
patch adjusts the function to ignore the new qualifier.

gas/
2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>

	* config/tc-aarch64.c (parse_neon_type_for_operand): Adjust to
	take into account new vector type 2H.
	(vectype_to_qualifier): Likewise.

include/opcode/
2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64.h (enum aarch64_opnd_qualifier): Add
	AARCH64_OPND_QLF_V_2H.

opcodes/
2015-12-14  Matthew Wahab  <matthew.wahab@arm.coM>

	* aarch64-dis.c (get_vreg_qualifier_from_value): Update comment
	and adjust calculation to ignore qualifier for type 2H.
	* aarch64-opc.c (aarch64_opnd_qualifier): Add "2H".

Change-Id: Idf9a3694732962c80fde04f08c7304de9164f126
2015-12-14 17:27:52 +00:00
Matthew Wahab 1e6f4800fc [AArch64][Patch 5/5] Add instruction PSB CSYNC
The Statistical Profile Extension adds the instruction PSB CSYNC as an
alias for the HINT #17 instruction. This patch adds the instruction to
binutils as a HINT alias that takes an operand.

A new operand type, AARCH64_OPND_BARRIER_PSB, is added to represent the
operand to PSB. A parser for the operand type is added to the assembler
and a printer to the disassembler. The operand name "csync" is added to
the list of HINT options with HINT number #17. Encoding and decoding of
the operand is handled by the ins_hint/ext_hint functions added in the
preceding patches.

gas/
2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>

	* config/tc-aarch64.c (aarch64_hint_opt_hsh): New.
	(parse_barrier_psb): New.
	(parse_operands): Add case for AARCH64_OPND_BARRIER_PSB.
	(md_begin): Set up aarch64_hint_opt_hsh.

gas/testsuite/
2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>

	* gas/aarch64/system-2.d: Enable the statistical profiling
	extension.  Update the expected output.
	* gas/aarch64/system-2.s: Add tests for PSB CSYNC.
	* gas/aarch64/system.d: Update the expected output.

include/opcode/
2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64.h (aarch64_opnd): Add AARCH64_OPND_BARRIER_PSB.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-opc.c (aarch64_hint_options): Add "csync".
	(aarch64_print_operands): Handle AARCH64_OPND_BARRIER_PSB.
	* aarch64-tbl.h (aarch64_feature_stat_profile): New.
	(STAT_PROFILE): New.
	(aarch64_opcode_table): Add "psb".
	(AARCH64_OPERANDS): Add "BARRIER_PSB".

Change-Id: I5ffb672d26a8b15b48785478d359350a9b70ca09
2015-12-11 10:22:40 +00:00
Matthew Wahab 9ed608f98b [AArch64][Patch 4/5] Support HINT aliases taking operands.
The Statistical Profile Extension adds the instruction PSB CSYNC as an
alias for the HINT #17 instruction. This patch adds support for aliases
of HINT which take an operand, adding a table to store operand names and
their matching hint number as well as encoding and decoding functions
for such operands. Parsing and printing the operands are deferred to any
support added for aliases with such operands.

include/opcode/
2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64.h (aarch64_hint_options): Declare.
	(aarch64_opnd_info): Add field hint_option.

opcodes/
2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-asm.c (aarch64_ins_hint): New.
	* aarch64-asm.h (aarch64_ins_hint): Declare.
	* aarch64-dis.c (aarch64_ext_hint): New.
	* aarch64-dis.h (aarch64_ext_hint): Declare.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-opc.c (aarch64_hint_options): New.
	* aarch64-tbl.h (AARCH64_OPERANDS): Fix typos.

Change-Id: I2205038fc1c47d3025d1f0bc2fbf405b5575b287
2015-12-11 10:12:34 +00:00
Matthew Wahab 73af8ed6b1 [AArch64][Patch 1/5] Support the ARMv8.2 Statistical Profiling Extension.
The Statistical Profile extension included in the ARMv8.2 architecture
adds a number of system registers and a new instruction. This patch set
adds support for the extension to binutils, enabled when
-march=armv8.2-a+profile is given.

The patches in this series:
- Add the new command line option and feature flags.
- Add the new system registers.
- Adjust the maximum number of aliases permitted for an instruction.
- Add support for HINT aliases which take operands.
- Add the new instruction, an alias of the HINT instruction.

This patch adds the option "profile" to the permitted architecture
extensions, disabling it by default.

gas/
2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>

	* config/tc-aarch64.c (aarch64_features): Add "profile".
	* doc/c-aarch64.texi (AArch64 Extensions): Add "profile".

include/opcode/
2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64.h (AARCH64_FEATURE_PROFILE): New.

Change-Id: If9bb4a9b69a264180f96f8ffaf10b15ced273699
2015-12-11 09:30:26 +00:00
Matthew Wahab d6bf7ce6c2 [AArch64][PATCH 2/2] Support ARMv8.2 DC CVAP instruction.
ARMv8.2 adds the new system instruction DC CVAP. This patch adds support
for the instruction to binutils, enabled when -march=armv8.2-a is
selected.

gas/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* config/tc-aarch64.c (parse_sys_ins_reg): Add check of
	architectural support for system register.

gas/testsuite/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* gas/aarch64/sysreg-2.d: Add tests for dc instruction.
	* gas/aarch64/sysreg-2.s: Add uses of dc instruction.

include/opcode/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64.h (aarch64_sys_ins_reg_supported_p): Declare.

opcodes/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap".
	(aarch64_sys_ins_reg_supported_p): New.

Change-Id: I3158b97d9bbee9644c2d0e2986db807412ef1053
2015-12-10 16:40:45 +00:00
Matthew Wahab ea2deeec92 [AArch64][PATCH 1/2] Add support for ARMv8.2 DC CVAP instruction.
ARMv8.2 adds the new system instruction DC CVAP. This patch series adds
support for this instruction to binutils, enabled when -march=armv8.2-a
is selected.

The AArch64 binutils record of some system registers uses a boolean
value to hold the single flag currently supported for them. To allow
these registers to be limited to specific architectures, the first patch
in this series replaces the boolean flag with a bitset and feature test.

include/opcode/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64.h (aarch64_sys_ins_reg): Replace has_xt with flags.
	(aarch64_sys_ins_reg_has_xt): Declare.

opcodes/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt
	with aarch64_sys_ins_reg_has_xt.
	(aarch64_ext_sysins_op): Likewise.
	* aarch64-opc.c (operand_general_constraint_met_p): Likewise.
	(F_HASXT): New.
	(aarch64_sys_regs_ic): Update for changes to aarch64_sys_ins_reg.
	(aarch64_sys_regs_dc): Likewise.
	(aarch64_sys_regs_at): Likewise.
	(aarch64_sys_regs_tlbi): Likewise.
	(aarch64_sys_ins_reg_has_xt): New.

Change-Id: I363637a6c3f54d7ffff953b3a0734e8139cae819
2015-12-10 16:40:44 +00:00
Matthew Wahab c8a6db6fa0 [AArch64][PATCH 1/2] Add support for RAS instruction ESB.
The ARMv8.2 RAS extension adds a new barrier instruction ESB as an alias
and the preferred form of HINT 16.

This patch adds an architectural feature flag for the RAS extension and
includes it in the features selected enabled by -march=armv8.2-a. It
also adds the ESB instruction, making it available whenever the RAS
feature is enabled.

Because ESB is the preferred form and because the target architecture
isn't available to the disassembler, HINT 16 will be disassembled as ESB
even when the target has no support for the RAS extension.

gas/testsuite/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* gas/aarch64/system-2.d: New.
	* gas/aarch64/system-2.s: New.
	* gas/aarch64/system.d: Adjust expected output for HINT 16.

include/opcode/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64.h (AARCH64_FEATURE_RAS): New.
	(AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_RAS.

opcodes/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-tbl.h (aarch64_feature_ras): New.
	(RAS): New.
	(aarch64_opcode_table): Add "esb".

Change-Id: Id4713917da15cca3b977284f43febd1c9b3d9faf
2015-12-10 14:10:15 +00:00
Matthew Wahab af117b3cf1 [AArch64] Fix ARMv8.1 and ARMv8.2 feature settings.
ARMv8.1 includes CRC as a required extension but this isn't reflected in
the features enabled by -march=armv8.1-a. The FP16 feature modifier also
clashes with AARCH64_FEATURE_V8_1 and the list of features for ARMv8.2
is missing ARMv8.1 features.

This patch enables +crc for -march values of armv8.1-a and later. It
also fixes the values for AARCH64_FEATURE_F16 and makes
AARCH64_ARCH_V8_2 and superset of AARCH64_ARCH_V8_2.

gas/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* doc/c-aarch64.texi (AArch64 Extensions): Update entry for crc.

include/opcode
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64.h (AARCH64_FEATURE_F16): Fix clash with
	AARCH64_FEATURE_V8_1.
	(AARCH64_ARCH_V8_1): Add AARCH64_FEATURE_CRC.
	(AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_CRC and
	AARCH64_FEATURE_V8_1.

Change-Id: I8af5369f6df2430b28f6cec92870d2a4d14a7431
2015-12-10 14:10:06 +00:00
Alan Modra 006589cfa1 R_PPC64_ENTRY
Add a new relocation that marks large-model entry code, for edit back
to medium-model.

include/elf/
	* ppc64.h (R_PPC64_ENTRY): Define.
bfd/
	* reloc.c (BFD_RELOC_PPC64_ENTRY): New.
	* elf64-ppc.c (reloc_howto_type ppc64_elf_howto_raw): Add
	entry for R_PPC64_ENTRY.
	(LD_R2_0R12, ADD_R2_R2_R12, LIS_R2, ADDIS_R2_R12): Define.
	(ppc64_elf_reloc_type_lookup): Handle R_PPC64_ENTRY.
	(ppc64_elf_relocate_section): Edit code at R_PPC64_ENTTY.  Use
	new insn defines.
	* libbfd.h: Regenerate.
	* bfd-in2.h: Regenerate.
2015-12-07 13:14:53 +10:30
Claudiu Zissulescu 24b368f853 Fix failures in the GAS testsuite for the ARC architecture.
gas	* config/tc-arc.c (arc_option): Sets all internal gas options when
	parsing .cpu directive.
	(declare_register_set): Declare all 64 registers.
	(md_section_align): Refactor.
	(md_pcrel_from_section): Remove assert.
	(pseudo_operand_match): Fix pseudo operand match.
	(find_reloc): Use flags filed, extend matching.
	* config/tc-arc.h (TC_VALIDATE_FIX): Don't fixup any PLT
	relocation.

testsuite	* gas/arc/bic.d: Update test.
	* gas/arc/add_s-err.s: New file.
	* gas/arc/cpu-warn1.s: Likewise.
	* gas/arc/pcl-relocs.d: Likewise.
	* gas/arc/pcl-relocs.s: Likewise.
	* gas/arc/pcrel-relocs.d: Likewise.
	* gas/arc/pcrel-relocs.s: Likewise.
	* gas/arc/pic-relocs.d: Likewise.
	* gas/arc/pic-relocs.s: Likewise.
	* gas/arc/plt-relocs.d: Likewise.
	* gas/arc/plt-relocs.s: Likewise.
	* gas/arc/pseudos.d: Likewise.
	* gas/arc/pseudos.s: Likewise.
	* gas/arc/sda-relocs.d: Likewise.
	* gas/arc/sda-relocs.s: Likewise.
	* gas/arc/sda-relocs2.d: Likewise.
	* gas/arc/sda-relocs2.s: Likewise.
	* gas/arc/tls-relocs.d: Likewise.
	* gas/arc/tls-relocs.s: Likewise.

opcode	* arc.h (arc_reloc_equiv_tab): Replace flagcode with flags[32].

opcodes	* arc-dis.c (special_flag_p): Match full mnemonic.
	* arc-opc.c (print_insn_arc): Check section size to read
	appropriate number of bytes. Fix printing.
	* arc-tbl.h: Fix instruction table. Allow clri/seti instruction without
	arguments.
2015-12-04 10:49:57 +00:00
Tristan Gingold b4687fcc2b Darwin: add new mach-o header flags.
binutils/
	* od-macho.c (bfd_mach_o_header_flags_name): Add name
	for flags until BFD_MACH_O_MH_APP_EXTENSION_SAFE.

include/mach-o/
	* loader.h (bfd_mach_o_header_flags): Add
	BFD_MACH_O_MH_APP_EXTENSION_SAFE.
2015-12-03 12:00:50 +01:00
Alan Modra bbb1afc89b Invoke aout N_* macros with pointer to struct internal_exec
No functional changes here.

BTW, some of these headers don't seem to be used anywhere:
include/aout/dynix3.h, include/aout/encap.h, include/aout/hp.h,
gas/config/aout_gnu.h

bfd/
	* aout-adobe.c: Invoke aout N_* macros with pointer to
	struct internal_exec.
	* aout-arm.c: Likewise.
	* aout-cris.c: Likewise.
	* aout-target.h: Likewise.
	* aout-tic30.c: Likewise.
	* aoutf1.h: Likewise.
	* aoutx.h: Likewise.
	* bout.c: Likewise.
	* freebsd.h: Likewise.
	* gen-aout.c: Likewise.
	* hp300hpux.c: Likewise.
	* i386aout.c: Likewise.
	* i386linux.c: Likewise.
	* i386lynx.c: Likewise.
	* i386mach3.c: Likewise.
	* i386os9k.c: Likewise.
	* libaout.h: Likewise.
	* m68klinux.c: Likewise.
	* m88kmach3.c: Likewise.
	* mipsbsd.c: Likewise.
	* netbsd.h: Likewise.
	* pc532-mach.c: Likewise.
	* pdp11.c: Likewise.
	* riscix.c: Likewise.
	* sparclinux.c: Likewise.
	* sparclynx.c: Likewise.
gas/
	* config/aout_gnu.h: Invoke aout N_* macros with pointer to
	struct internal_exec.
include/
	* bout.h: Invoke aout N_* macros with pointer to
	struct internal_exec.
	* os9k.h: Likewise.
include/aout/
	* adobe.h: Invoke aout N_* macros with pointer to
	struct internal_exec.
	* aout64.h: Likewise.
	* dynix3.h: Likewise.
	* encap.h: Likewise.
	* hp.h: Likewise.
	* hp300hpux.h: Likewise.
	* sun4.h: Likewise.
2015-12-01 13:40:05 +10:30
Rainer Orth 87746c154a Port libvtv to Solaris
libstdc++-v3:
	* acinclude.m4 (GLIBCXX_ENABLE_VTABLE_VERIFY) <solaris2*>: Use
	-Wl,-R in VTV_CXXLINKFLAGS.
	* configure: Regenerate.

	* testsuite/18_support/bad_exception/23591_thread-1.c: Use
	-fvtable-verify=none on Solaris 12+.

	libgcc:
	* Makefile.in (VTV_CFLAGS): New variable.
	(vtv_start$(objext), vtv_end$(objext), vtv_end$(objext))
	(vtv_start_preinit$(objext), vtv_end_preinit$(objext)): Use it.
	* config.host (*-*-solaris2*): Add t-crtstuff-pic to tmake_file.
	Add vtv_start.o, vtv_end.o, vtv_start_preinit.o, vtv_end_preinit.o
	to extra_parts if $enable_vtable_verify = yes.

	libvtv:
	* configure.tgt (*-*-solaris2.[1-9]*): Declare supported.
	* configure.ac: Call AC_USE_SYSTEM_EXTENSIONS.
	<*-*-solaris2*>: Check for init priority support.
	Check for getexecname, __fortify_fail, _obstack_begin.
	(VTV_NO_OBSTACK): New conditional.
	* configure: Regenerate.
	* Makefile.am [VTV_NO_OBSTACK] (obstack.c): Use new condition.
	Create empty config.h
	* Makefile.in: Regenerate.

	* vtv_rts.cc [HAVE_GETEXECNAME] (program_invocation_name): New
	variable.
	(read_section_offset_and_length) [HAVE_GETEXECNAME]: Set it.
	(dl_iterate_phdr_callback) [HAVE_GETEXECNAME]: Set it.

	(__fortify_fail): Wrap in HAVE___FORTIFY_FAIL
	[!HAVE___FORTIFY_FAIL]: Provide non-Cygwin implementation.

	(read_section_offset_and_length): Assert sh_size >= VTV_PAGE_SIZE.
	(iterate_modules): Fix typo.
	Use VTV_PAGE_SIZE.
	(dl_iterate_phdr_callback): Fix typo.
	Use VTV_PAGE_SIZE.
	(__VLTChangePermission): Fix typos.

	include:
	* vtv-change-permission.h (VTV_PAGE_SIZE) [__sun__ && __svr4__ &&
	__sparc__]: Define.

	gcc:
	* config/sol2.h (SUPPORTS_INIT_PRIORITY): Move up.
	(STARTFILE_VTV_SPEC, ENDFILE_VTV_SPEC): Define.
	(STARTFILE_SPEC): Use %(startfile_vtv).
	(ENDFILE_SPEC): Use %(endfile_vtv).
	(SUBTARGET_EXTRA_SPECS): Handle STARTFILE_VTV_SPEC,
	ENDFILE_VTV_SPEC.

	* gcc.c (LINK_COMMAND_SPEC): Move VTABLE_VERIFICATION_SPEC after %{L*}.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@230865 138bc75d-0d04-0410-961f-82ee72b054a4
2015-11-28 16:39:32 +00:00
Rich Felker f4936735c5 SH FDPIC backend support
gcc/ChangeLog
	* config.gcc: Handle --enable-fdpic.
	* config/sh/constraints.md (Ccl): New constraint.
	* config/sh/linux.h (SUBTARGET_LINK_EMUL_SUFFIX): Handle -mfdpic.
	* config/sh/sh-c.c (sh_cpu_cpp_builtins): Add __FDPIC__ and
	__SH_FDPIC__.
	* config/sh/sh-mem.cc (expand_block_move): Support FDPIC for calls
	to library functions.
	* config/sh/sh-protos.h (function_symbol_result): New struct.
	(function_symbol): Return function_symbol_result.
	(sh_get_fdpic_reg_initial_val, sh_load_function_descriptor): New
	declarations.
	* config/sh/sh.c (TARGET_ASM_INTEGER, sh_assemble_integer):
	Implement target hook.
 	(TARGET_CANNOT_FORCE_CONST_MEM, sh_cannot_force_const_mem_p):
	Likewise.
	(sh_option_override): Force -fPIC if FDPIC is in effect.
 	(sh_asm_output_addr_const_extra): Add UNSPEC_GOTFUNCDESC and
	UNSPEC_GOTOFFFUNCDESC cases.
	(prepare_move_operands): Use FDPIC initial GOT register for
	TLS-related GOT access; inhibit cross-section address offset
	constants for FDPIC.
	(sh_assemble_integer): New function.
	(sh_cannot_copy_insn_p): Inhibit copying insns that are FDPIC
	PC-relative call sites.
	(expand_ashiftrt): Adapt invocation of function_symbol.
	(sh_expand_prologue): Inhibit PC-relative GOT address load for
	FDPIC.
	(nonpic_symbol_mentioned_p): Add cases for UNSPEC_GOTFUNCDESC and
	UNSPEC_GOTOFFFUNCDESC.
	(legitimize_pic_address): Resolve function symbols to function
	descriptors for FDPIC.  Do not use GOT-relative addressing for
	local data that may be read-only on FDPIC.
	(sh_emit_storesi, sh_emit_storehi): New functions.
	(sh_trampoline_init): Generate FDPIC trampolines.
	(sh_function_ok_for_sibcall): Add TARGET_FDPIC check.
	(sh_expand_sym_label2reg): Don't assume sibcalls are local.
	(sh_output_mi_thunk): Generate FDPIC call.
	(function_symbol): Return function_symbol_result.  For
	SFUNC_STATIC on FDPIC, generate call site labels to use
	PC-relative addressing rather than GOT-relative addressing.
	(sh_conditional_register_usage): Make PIC register fixed and call used
	when FDPIC is in effect.
	(sh_legitimate_constant_p): Impose FDPIC
	constant constraints.
	(sh_cannot_force_const_mem_p, sh_load_function_descriptor)
	(sh_get_fdpic_reg_initial_val): New functions.
	* config/sh/sh.h (SUBTARGET_ASM_SPEC, SUBTARGET_LINK_EMUL_SUFFIX):
	Handle -mfdpic.
	(FDPIC_SELF_SPECS, SUBTARGET_DRIVER_SELF_SPECS)
	(PIC_OFFSET_TABLE_REG_CALL_CLOBBERED)
	(SH_OFFSETS_MUST_BE_WITHIN_SECTIONS_P): New macros.
	(DRIVER_SELF_SPECS): Add SUBTARGET_DRIVER_SELF_SPECS and
	FDPIC_SELF_SPECS.
	(TRAMPOLINE_SIZE): Select trampoline size for FDPIC.
	(ASM_PREFERRED_EH_DATA_FORMAT): Add EH format constraints for
	FDPIC.
	(ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX): Handle FDPIC case.
	* config/sh/sh.md (UNSPEC_GOTFUNCDESC, UNSPEC_GOTOFFFUNCDESC): New
	constants.
	(calli_fdpic, call_valuei_fdpic, sibcalli_fdpic)
	(sibcalli_pcrel_fdpic, sibcall_pcrel_fdpic, sibcall_valuei_fdpic)
	(sibcall_valuei_pcrel_fdpic, sibcall_value_pcrel_fdpic)
	(sym2GOTFUNCDESC, symGOTFUNCDESC2reg, sym2GOTOFFFUNCDESC)
	(symGOTOFFFUNCDESC2reg): New patterns.
	(udivsi3_i1, udivsi3_i4, udivsi3_i4_single, udivsi3,
	*divsi_inv_call_combine, divsi3_i4, divsi3_i4_single, divsi3)
	(ashlsi3, ashlsi3_d_call, ashrsi3_n, lshrsi3, lshrsi3_d_call)
	(calli, call_valuei, call, call_value, sibcalli, sibcalli_pcrel)
	(sibcall_pcrel, sibcall, sibcall_valuei, sibcall_valuei_pcrel)
	(sibcall_value_pcrel, sibcall_value, GOTaddr2picreg, symGOT_load)
	(symGOTOFF2reg, block_move_real, block_lump_real)
	(block_move_real_i4, block_lump_real_i4): Add support for FDPIC
	calls.
	(mulsi3, ic_invalidate_line, initialize_trampoline, call_pop,
	call_value_pop): Adjust for new function_symbol signature.
	* config/sh/sh.opt (-mfdpic): New option.
	* doc/install.texi (Options specification): Document
	--enable-fdpic.
	* doc/invoke.texi (SH Options): Document -mfdpic.

include/ChangeLog:
	* longlong.h (udiv_qrnnd): Add FDPIC compatible version for SH.

libitm/ChangeLog:
	* config/sh/sjlj.S (_ITM_beginTransaction): Bypass PLT calling
	GTM_begin_transaction for compatibility with FDPIC.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@229438 138bc75d-0d04-0410-961f-82ee72b054a4
2015-11-28 16:39:31 +00:00