Commit Graph

71 Commits

Author SHA1 Message Date
Chris Demetriou 1e799e28c1 2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
        * mips.igen (mips32, mips64): New models, add to all instructions
        and functions as appropriate.
        (loadstore_ea, check_u64): New variant for model mips64.
        (check_fmt_p): New variant for models mipsV and mips64, remove
        mipsV model marking fro other variant.
        (SLL) Rename to...
        (SLLa) this.
        (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
        for mips32 and mips64.
        (DCLO, DCLZ): New instructions for mips64.
2002-03-12 22:53:01 +00:00
Stan Shebs 7a292a7adf import gdb-19990422 snapshot 1999-04-26 18:34:20 +00:00
Stan Shebs c906108c21 Initial creation of sourceware repository 1999-04-16 01:35:26 +00:00
Stan Shebs 071ea11e85 Initial creation of sourceware repository 1999-04-16 01:34:07 +00:00
Gavin Romig-Koch d0d495f601 improve sanitation 1999-02-04 21:23:37 +00:00
Stan Shebs bd164e2835 Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
* configure.in, configure (mips64vr5*-*-*): Added missing ;; in
 	case statement.
(actually a sanitize-cygnus mistake, but Rainer doesn't know that)
1998-12-30 21:16:13 +00:00
Frank Ch. Eigler 14bbac6609 * eCos->devo merge; tx3904 sanitize tags removed
1998-12-29  Frank Ch. Eigler  <fche@cygnus.com>
	* interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
	(load_word): Call SIM_CORE_SIGNAL hook on error.
	(signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
	starting.  For exception dispatching, pass PC instead of NULL_CIA.
	(decode_coproc): Use COP0_BADVADDR to store faulting address.
	* sim-main.h (COP0_BADVADDR): Define.
	(SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
	(SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
	(_sim_cpu): Add exc_* fields to store register value snapshots.
	* mips.igen (*): Replace memory-related SignalException* calls
	with references to SIM_CORE_SIGNAL hook.
	* dv-tx3904irc.c (tx3904irc_port_event): printf format warning
	fix.
	* sim-main.c (*): Minor warning cleanups.
1998-12-30 12:21:43 +00:00
Gavin Romig-Koch f87366ec28 New 'hack' generator 1998-12-16 05:07:34 +00:00
Gavin Romig-Koch bff2d36890 5xxx and el 1998-12-14 15:14:24 +00:00
Gavin Romig-Koch f14397f057 for bfd:
* archures.c,bfd-in2.h (bfd_mach_mips4121): New.
	* cpu-mips.c: Added vr4121.
	* elf32-mips.c (elf_mips_mach): Same.
	(_bfd_mips_elf_final_write_processing): Same.

for gas:
	* config/tc-mips.c (mips_4121): New.
	(md_begin,mips_ip,md_longopts,md_parse_option): Add vr4121.

for gcc:
	* config/mips/mips.c (override_options): Add vr4121.
	* config/mips/t-vr4xxx (MULTILIB_MATCHES): Same.

for include/elf:
	* mips.h (E_MIPS_MACH_4121): New.

for include/opcode:
	* mips.h (INSN_4121): New.

for opcodes:
	* mips-dis.c (set_mips_isa_type): Add bfd_mach_mips4121.
	(_print_insn_mips): Same.
	* mips-opc.c: Add vr4121.

for sim/mips:
	* configure.in,mips.igen,vr.igen: Add vr4121.
	* configure: Rebuilt.
1998-12-13 16:14:24 +00:00
Gavin Romig-Koch 82aeada70c * configure.in (mips64vr4xxx): Enable TARGET_ENABLE_FR.
Set mips_fpu, and mips_fpu_bitsize.
	Set sim_gen, and sim_igen_machine.
	* configure: Rebuild.
	* mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
	* sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1998-12-12 22:43:54 +00:00
Andrew Cagney baa1a48801 Explicitly tag vr41/mips16 instructions.
Update configure.in/configure.
1998-11-25 06:50:48 +00:00
Andrew Cagney 554eb429e4 gencode.c: Kill, Kill, Kill....
Remove last remenats of old gencode simulator.
1998-11-23 11:37:56 +00:00
Andrew Cagney 57791952b6 Configure mips64vr4100-elf nee mips64vr41* as a 64 bit mips16 igen simulator.
Fix problems: All vr.igen instructions are 64 bit.
1998-11-23 07:16:03 +00:00
Andrew Cagney ee562da4c4 Reconize target mips-tx19-elf 1998-11-23 06:06:12 +00:00
Andrew Cagney a83d7d870f Switch mips-lsi-elf mips16 simulator to igen (from gencode). 1998-11-23 05:50:21 +00:00
Andrew Cagney d1cbd70abb Add configury for mips-lsi-elf target (32 bit MIPS16).
Fix numerous problems with PENDING_* code.
In old gencode simulator, don't double tick each cycle.
Add BREAK instruction to MIPS16 gencode simulator.
1998-11-12 06:42:34 +00:00
Frank Ch. Eigler fda83b6795 * MONSTER sky -> devo merge
* ChangeLog / ChangeLog.sky entries were merged with original time stamps;
  a few were moved between the files
1998-10-27 12:48:08 +00:00
Frank Ch. Eigler 36e838d13b * eCos tx3904sio sim - devo part 2/2
Tue Aug 25 12:49:46 1998  Frank Ch. Eigler  <fche@cygnus.com>
	* dv-tx3904sio.c: New file: tx3904 serial I/O module.
	* configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
	Reorganize target-specific sim-hardware checks.
	* configure: rebuilt.
	* interp.c (sim_open): For tx39 target boards, set
	OPERATING_ENVIRONMENT, add tx3904sio devices.
	* tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
	ROM executables.  Install dv-sockser into sim-modules list.
	* dv-tx3904irc.c: Compiler warning clean-up.
	* dv-tx3904tmr.c: Compiler warning clean-up.  Remove particularly
	frequent hw-trace messages.
1998-08-25 14:16:58 +00:00
Ken Raeburn 3d759c53c9 sanitize-vr5400 -> sanitize-cygnus, for 98r2 1998-08-12 10:50:35 +00:00
Jillian Ye f915cc9125 configure.in: Add -lXext to mips_extra_libs 1998-06-23 17:59:31 +00:00
Gavin Romig-Koch 55ad270f9a * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
parts.
	* configure: Update.
1998-06-09 15:42:04 +00:00
Frank Ch. Eigler da040f2a6c * Early check-in of tx3904 timer sim implementation for ECC.
It is not yet properly tested.
Thu Jun  4 15:37:33 1998  Frank Ch. Eigler  <fche@cygnus.com>
	* dv-tx3904tmr.c: New file - implements tx3904 timer.
	* dv-tx3904{irc,cpu}.c: Mild reformatting.
	* configure.in: Include tx3904tmr in hw_device list.
	* configure: Rebuilt.
	* interp.c (sim_open): Instantiate three timer instances.
	Fix address typo of tx3904irc instance.
1998-06-04 12:43:45 +00:00
Andrew Cagney df26156d68 Match mips*tx39 not mipst*tx39. 1998-05-29 01:42:20 +00:00
Andrew Cagney f872d0d643 Only enable H/W on some mips targets.
Move common hw-obj to Make-common
Pacify GCC
1998-05-22 05:23:04 +00:00
Frank Ch. Eigler 3fa454e95f * Monster patch - may destablize MIPS sims for a little while.
* Followup patch for SCEI PR 15853
* First check-in of TX3904 interrupt controller devices for ECC. [sanitized]
* First implementation of MIPS hardware interrupt emulation.
Mon May 18 18:22:42 1998  Frank Ch. Eigler  <fche@cygnus.com>
	* configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
 	modules.  Recognize TX39 target with "mips*tx39" pattern.
	* configure: Rebuilt.
	* sim-main.h (*): Added many macros defining bits in
 	TX39 control registers.
	(SignalInterrupt): Send actual PC instead of NULL.
	(SignalNMIReset): New exception type.
	* interp.c (board): New variable for future use to identify
	a particular board being simulated.
	(mips_option_handler,mips_options): Added "--board" option.
	(interrupt_event): Send actual PC.
	(sim_open): Make memory layout conditional on board setting.
	(signal_exception): Initial implementation of hardware interrupt
 	handling.  Accept another break instruction variant for simulator
 	exit.
	(decode_coproc): Implement RFE instruction for TX39.
	(mips.igen): Decode RFE instruction as such.
start-sanitize-tx3904
	* configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
	* interp.c: Define "jmr3904" and "jmr3904debug" board types and
	bbegin to implement memory map.
	* dv-tx3904cpu.c: New file.
	* dv-tx3904irc.c: New file.
end-sanitize-tx3904
1998-05-18 15:55:05 +00:00
Andrew Cagney 1a89994e08 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
Document a replacement.
1998-05-12 05:36:47 +00:00
Tom Tromey 5da9ce07eb * configure: Regenerated to track ../common/aclocal.m4 changes.
* config.in: Ditto.
	* acconfig.h: New file.
	* configure.in: Reverted change of Apr 24; use sinclude again.
1998-04-26 22:03:55 +00:00
Tom Tromey b1df34b9ed * configure: Regenerated to track ../common/aclocal.m4 changes.
* config.in: Ditto.
	* configure.in: Don't call sinclude.
1998-04-24 20:39:48 +00:00
James Lemke 3e5fbf91b5 Add configure option --with-sim-funit for sim & gdb. 1998-04-21 21:14:09 +00:00
Andrew Cagney c58fa2cc43 TX19 uses igen by default. 1998-04-15 23:17:16 +00:00
Andrew Cagney 64ed8b6a8c aclocal.m4: Don't enable inlining when cross-compiling.
mips/*: Tune mips simulator - allow all memory transfer code to be inlined.
1998-04-05 07:16:54 +00:00
Andrew Cagney 69d5a56645 Re-do load/store operations so that they work for both 32 and 64 bit
ISAs.
Enable tx39 as igen again.
1998-04-02 19:35:39 +00:00
Gavin Romig-Koch 34f51d8723 * configure.in (mipstx39*-*-*): Use gencode simulator rather
than igen one.
	* configure : Rebuild.
1998-03-30 19:54:15 +00:00
Frank Ch. Eigler 9b23b76d68 * Added --with-sim-gpu2=<path> option for linking SCEI's GPU2 library with
the stand-alone executable.


[in ChangeLog.sky:]

	* sky-gpuif.c (call_gs): Call properly into GPU2 library if
 	configured --with-sim-gpu2.  Use SKY_GPU2_REFRESH symbol as
 	placeholder for future GPU2-refresh policy.

[in ChangeLog:]

	* Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
 	configurable settings for stand-alone simulator.

start-sanitize-sky
	* configure.in: Added --with-sim-gpu2 option to specify path of
 	sky GPU2 library.  Triggers -DSKY_GPU2 for sky-gpuif.c, and
 	links/compiles stand-alone simulator with this library.

	* interp.c (MEM_SIZE): Increased default sky memory size to 16MB.
end-sanitize-sky

	* configure.in: Added X11 search, just in case.

	* configure: Regenerated.
1998-03-18 00:20:40 +00:00
Gavin Romig-Koch dd15abd5a6 * vr4320.igen: New file.
* Makefile.in (vr4320.igen) : Added.
	* configure.in (mips64vr4320-*-*): Added.
	* configure : Rebuilt.
	* mips.igen : Correct the bfd-names in the mips-ISA model entries.
	Add the vr4320 model entry and mark the vr4320 insn as necessary.
1998-03-03 17:03:57 +00:00
Andrew Cagney a48e8c8d21 sim-main.h: Re-arange r5900 registers so that they have their own
little struct.
interp.c: Update.  Also add floating point Max/Min functions.
mips.igen: Remove r5900 tag from any floating point instructions.
r5900.igen: Rewrite.  Implement *all* floating point insns (except ld/st).
r5400.igen: Tag mdmx functions as being mdmx specific.
1998-02-23 16:55:38 +00:00
John Metzler 180d1f0b50 Fall back from using igen to using gencode for the mips64vr4100 because
igen is not ready yet.
1998-02-19 21:28:50 +00:00
Ron Unrau 97908603a4 configure.in: add -DTARGET_SKY for mips64r5900-sky-elf configure.
sim-main.h: Define regs for sky if -DTARGET_SKY
interp.c: Initial register upload/download support for sky.
1998-02-15 21:33:13 +00:00
Ian Carmichael 2c88fae9ad * Add hardware_init hook. 1998-02-09 23:53:33 +00:00
Doug Evans 5759734b2c * Makefile.in (SIM_SKY_OBJS,MIPS_EXTRA_OBJS): New vars.
(SIM_OBJS): Add $(MIPS_EXTRA_OBJS).
	* configure.in: Set mips_extra_objs to sky files if mips64r59*-sky-*.
	* configure: Regenerated.
1998-02-06 03:19:56 +00:00
Andrew Cagney 37379a256b IGEN - Replace IMEM (IMEM_IMMED) macro with IMEM<insn-size> macro,
update v850, tic80 and mips simulators.
IGEN - Prepend prefix to more generated symbols and macros
(idecode_issue, instruction_word).
IGEN - Add -Wnowith option to supress warnings about word size
inflicts in input files.
MIPS - Clean up Makefile.in, m16.igen, m16.dc (new), m16run.c (new) so
that a mips16 simulator built using IGEN can be compiled.
1998-02-03 05:39:15 +00:00
Andrew Cagney 4634263c4c Make IGEN the generator for all but mips16 simulators.
Clean up botched merge in interp.c:sim_open().
1998-02-02 14:14:17 +00:00
Andrew Cagney 01737f42d8 mips: Add multi-processor support for r5900. Others might work.
common, igen: Fix MP related bugs.
1998-02-01 03:29:48 +00:00
Andrew Cagney c4db5b04f8 mips - for r5900 generate igen simulator.
igen - stop crash when simulator isn't multi-sim'ed
1998-01-31 06:56:13 +00:00
Andrew Cagney 2d44e12a27 Use macro GPR_SET(N,VAL) to clear zero registers. 1998-01-21 22:08:37 +00:00
Jeff Law 255cbbf190 * configure.in (sim_igen_filter): Multi-sim vr5000 - vr5000 or
vr5400 with the vr5000 as the default.
1997-12-12 19:24:34 +00:00
Andrew Cagney c02ed6a8a3 For bfd, add vr5400 and vr5000 mips machine variants to list of machines.
For sim/mips, enable multi-sim support when mips64vr5400-elf is target.
For sim/igen, allow specification of a default machine (will need
more work later).
1997-12-09 04:01:06 +00:00
Andrew Cagney f23e93dab0 * mips.igen: Tag vr5000 instructions.
(ANDI): Was missing mipsIV model, fix assembler syntax.
        (do_c_cond_fmt): New function.
        (C.cond.fmt): Handle mips I-III which do not support CC field
        separatly.
        (bc1): Handle mips IV which do not have a delaed FCC separatly.
        (SDR): Mask paddr when BigEndianMem, not the converse as specified
        in IV3.2 spec.
        (DMULT, DMULTU): Force use of hosts 64bit multiplication.  Handle
        vr5000 which saves LO in a GPR separatly.
        * configure.in (enable-sim-igen): For vr5000, select vr5000
        specific instructions.
        * configure: Re-generate.
1997-11-14 08:27:38 +00:00
Andrew Cagney 44b8585a3d Add option --enable-sim-igen to mips configuration. Allows user to
attempt a build of an older MIPS simulator using igen.
1997-11-05 09:43:34 +00:00