This patch updates arc-dis.c:parse_disassembler_options to use a macro
FOR_EACH_DISASSEMBLER_OPTION, which has been introduced in [1], instead of a
homegrown solution to split option string.
[1] https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=65b48a81
opcodes/ChangeLog:
yyyy-mm-dd Anton Kolesov <Anton.Kolesov@synopsys.com>
* arc-dis.c (parse_disassembler_options): Use
FOR_EACH_DISASSEMBLER_OPTION.
There is a bug in handling of cpu=... disassembler option in case there are
other options after it, for example, `cpu=EM,dsp'. In this case `EM,dsp' is
treated as an option value, and strcasecmp reports is as non-equal to "EM".
This is fixed by using disassembler_options_cmp function, which compares string
treating `,' the same way as `\0'.
This function also solves a problem with option order in parse_option.
Previously, if several option had same prefix (e.g. fpud, fpuda), then the
longer one should have been compared first, otherwise when longer option is
passed it would be treated as a short one, because
CONST_STRNEQ ("fpud", "fpuda")
would be true. The order of options was correct for ARC, so there were no
bugs per se, but with disassembler_option_cmp there is no risk of such a bug
being introduced in the future.
opcodes/ChangeLog:
yyyy-mm-dd Anton Kolesov <Anton.Kolesov@synopsys.com>
* arc-dis.c (parse_option): Use disassembler_options_cmp to compare
disassembler option strings.
(parse_cpu_option): Likewise.
binutils/ChangeLog
yyyy-mm-dd Anton Kolesov <Anton.Kolesov@synopsys.com>
* testsuite/binutils-all/arc/double_store.s: New file.
* testsuite/binutils-all/arc/objdump.exp: Tests for disassembler
options.
(do_objfile): New function.
(check_assembly): Likewise.
Currently print_insn_arc relies on BFD mach and ELF private headers to
distinguish between various ARC architectures. Sometimes those values are not
correct or available, mainly in the case of debugging targets without and ELF
file available. Changing a BFD mach is not a problem for the debugger, because
this is a generic BFD field, and GDB, for example, already sets it according to
information provided in XML target description or specified via GDB 'set arch'
command. However, things are more complicated for ELF private headers, since
it requires existing of an actual ELF file. To workaround this problem this
patch allows CPU model to be specified via disassemble info options. If CPU is
specified in options, then it will take a higher precedence than whatever might
be specified in ELF file.
This is mostly needed for ARC EM and ARC HS, because they have the same
"architecture" (mach) ARCv2 and differ in their private ELF headers. Other ARC
architectures can be distinguished between each other purely via "mach" field.
Proposed disassemble option format is "cpu=<CPU>", where CPU can be any valid
ARC CPU name as supported by GAS. Note that this creates a seeming redundancy
with objdump -m/--architecture option, however -mEM and -mHS still result in
"ARCv2" architecture internally, while -Mcpu={HS,EM} would have an actual
effect on disassembler.
opcodes/ChangeLog:
yyyy-mm-dd Anton Kolesov <anton.kolesov@synopsys.com>
* arc-dis.c (enforced_isa_mask): Declare.
(cpu_types): Likewise.
(parse_cpu_option): New function.
(parse_disassembler_options): Use it.
(print_insn_arc): Use enforced_isa_mask.
(print_arc_disassembler_options): Document new options.
binutils/ChangeLog:
yyyy-mm-dd Anton Kolesov <anton.kolesov@synopsys.com>
* doc/binutils.texi: Document new cpu=... disassembler options for ARC.
enter/leave mnemonics are enhanced to not only accept register ranges
but also single register (i.e., r13) or even no GPR register at all.
gas/
2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/leave_enter.d: Update test.
* testsuite/gas/arc/leave_enter.s: Likewise.
opcodes/
2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
* arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
* arc-opc.c (insert_r13el): New function.
(R13_EL): Define.
* arc-tbl.h: Add new enter/leave variants.
The memory disassemble_info::disassembler_options points to is always
owned by the client. I.e., that field is an non-owning, observing
pointer. Thus const makes sense.
Are the include/ and opcodes/ bits OK?
Tested on x86_64 Fedora 23, built with --enable-targets=all.
include/ChangeLog:
2017-04-05 Pedro Alves <palves@redhat.com>
* dis-asm.h (disassemble_info) <disassembler_options>: Now a
"const char *".
(next_disassembler_option): Constify.
opcodes/ChangeLog:
2017-04-05 Pedro Alves <palves@redhat.com>
* arc-dis.c (parse_option, parse_disassembler_options): Constify.
* arm-dis.c (parse_arm_disassembler_options): Constify.
* ppc-dis.c (powerpc_init_dialect): Constify local.
* vax-dis.c (parse_disassembler_options): Constify.
gdb/ChangeLog:
2017-04-05 Pedro Alves <palves@redhat.com>
* arm-tdep.c (show_disassembly_style_sfunc): Constify local.
* disasm.c (set_disassembler_options): Constify local.
* i386-tdep.c (i386_print_insn): Remove cast and FIXME comment.
This patch fixes:
- fpus and fpud are swaped.
- quarkse_em doesn't include FPX extensions.
- auto guessed opcode mechanism may ignore the option passed via -M<feature> option.
opcodes/
2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
* arc-dis.c (is_compatible_p): Remove function.
(skip_this_opcode): Don't add any decoding class to decode list.
Remove warning.
(find_format_from_table): Go through all opcodes, and warn if we
use a guessed mnemonic.
binutils/
2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/binutils-all/arc/objdump.exp (Warning test): Update
test.
The current handling for arc instructions longer than 32-bits is all
handled as a special case in both the assembler and disassembler.
The problem with this approach is that it leads to code duplication,
selecting a long instruction is exactly the same process as selecting a
short instruction, except over more bits, in both cases we select based
on bit comparison, and initial operand insertion and extraction.
This commit unifies both the long and short instruction worlds,
converting the core opcodes library from being largely 32-bit focused,
to being largely 64-bit focused.
The changes are, on the whole, not too much. There's obviously a lot of
type changes but otherwise the bulk of the code just works. Most of the
actual functional changes are to code that previously handled the longer
48 or 64 bit instructions. The insert/extract handlers for these have
now been brought into line with the short instruction insert/extract
handlers.
All of the special case handling code that was previously added has now
been removed again. Overall, this commit reduces the amount of code in
the arc assembler and disassembler.
gas/ChangeLog:
* config/tc-arc.c (struct arc_insn): Change type of insn field.
(md_number_to_chars_midend): Support 6- and 8-byte values.
(emit_insn0): Update debug output.
(find_opcode_match): Likewise.
(build_fake_opcode_hash_entry): Delete.
(find_special_case_long_opcode): Delete.
(find_special_case): Remove long format special case handling.
(insert_operand): Change instruction type and update debug print
format.
(assemble_insn): Change instruction type, update debug print
formats, and remove unneeded assert.
include/ChangeLog:
* opcode/arc.h (struct arc_opcode): Change type of opcode and mask
fields.
(struct arc_long_opcode): Delete.
(struct arc_operand): Change types for insert and extract
handlers.
opcodes/ChangeLog:
* arc-dis.c (struct arc_operand_iterator): Remove all fields
relating to long instruction processing, add new limm field.
(OPCODE): Rename to...
(OPCODE_32BIT_INSN): ...this.
(OPCODE_AC): Delete.
(skip_this_opcode): Handle different instruction lengths, update
macro name.
(special_flag_p): Update parameter type.
(find_format_from_table): Update for more instruction lengths.
(find_format_long_instructions): Delete.
(find_format): Update for more instruction lengths.
(arc_insn_length): Likewise.
(extract_operand_value): Update for more instruction lengths.
(operand_iterator_next): Remove code relating to long
instructions.
(arc_opcode_to_insn_type): New function.
(print_insn_arc):Update for more instructions lengths.
* arc-ext.c (extInstruction_t): Change argument type.
* arc-ext.h (extInstruction_t): Change argument type.
* arc-fxi.h: Change type unsigned to unsigned long long
extensively throughout.
* arc-nps400-tbl.h: Add long instructions taken from
arc_long_opcodes table in arc-opc.c.
* arc-opc.c: Update parameter types on insert/extract handlers.
(arc_long_opcodes): Delete.
(arc_num_long_opcodes): Delete.
(arc_opcode_len): Update for more instruction lengths.
highbyte and lowbyte actually refer to the low byte and the high
byte respectively, but are used consistently in this swapped
order. This commit swaps them round so that highbyte refers to the
high byte and lowbyte refers to the low byte.
There should be no functional change after this commit.
opcodes/ChangeLog:
* arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
In preparation for moving to a world where arc instructions can be 2, 4,
6, or 8 bytes in length, replace the ARC_SHORT macro (which is either
true of false) with an arc_opcode_len function that returns a length in
bytes.
There should be no functional change after this commit.
gas/ChangeLog:
* config/tc-arc.c (assemble_insn): Replace use of ARC_SHORT with
arc_opcode_len.
include/ChangeLog:
* opcode/arc.h (arc_opcode_len): Declare.
(ARC_SHORT): Delete.
opcodes/ChangeLog:
* arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
with arc_opcode_len.
(find_format_long_instructions): Likewise.
* arc-opc.c (arc_opcode_len): New function.
The ARC (short) instructions are using a special register number to
indicate is the instruction uses a long immediate (LIMM). In the case
of short instruction, this LIMM indicator depends on the ISA version
used. Thus, for ARCv1 processors, the LIMM indicator is 0x3E, the same
value used in "long" instructions. However, for the ARCv2 processors,
this LIMM indicator is 0x1E.
This patch fixes the LIMM detection for ARCv1 ISA and adds two tests.
gas/
2016-10-13 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/shortlimm_a7.d: New file.
* testsuite/gas/arc/shortlimm_a7.s: Likewise.
* testsuite/gas/arc/shortlimm_hs.d: Likewise.
* testsuite/gas/arc/shortlimm_hs.s: Likewise.
include/
2016-10-13 Claudiu Zissulescu <claziss@synopsys.com>
* opcode/arc.h (ARC_OPCODE_ARCV2): New define.
opcodes/
2016-10-13 Claudiu Zissulescu <claziss@synopsys.com>
* arc-dis.c (find_format_from_table): Discriminate LIMM indicator
usage on ISA basis.
For each MAJOR-MINOR opcode tuple, we can have either a 3-operand, or
2-operand, or a single operand instruction format, depending on the
values present in i-field, and a-field.
The disassembler is reading the section containing the extension
instruction format and stores them in a table. Each table element
represents a linked list with encodings for a particular MAJOR-MINOR
tuple.
The current implementation checks only against the first element of
the list, hence, the issue.
This patch is walking the linked list until empty or finds an opcode
match. It also adds a test outlining the found problem.
opcodes/
2016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
* arc-dis.c (find_format): Walk the linked list pointed by einsn.
gas/
2016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/textinsnxop.d: New file.
* testsuite/gas/arc/textinsnxop.s: Likewise.
Variable "header" in function is set conditionally, but was accessed without
verifying if pointer was NULL.
opcodes/ChangeLog:
Cupertino Miranda <cmiranda@synopsys.com>
* opcodes/arc-dis.c (print_insn_arc): Changed.
opcodes * arc-nps400-tbl.h: Change block comments to GNU format.
* arc-dis.c: Add new globals addrtypenames,
addrtypenames_max, and addtypeunknown.
(get_addrtype): New function.
(print_insn_arc): Print colons and address types when
required.
* arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
define insert and extract functions for all address types.
(arc_operands): Add operands for colon and all address
types.
* arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
* arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
* arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
* arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
include * opcode/arc.h: Add ARC_OPERAND_ADDRTYPE,
ARC_OPERAND_COLON. Add the arc_nps_address_type enum and
ARC_NUM_ADDRTYPES.
* opcode/arc.h: Add BMU to insn_class_t enum.
* opcode/arc.h: Add PMU to insn_class_t enum.
gas * config/tc-arc.c: Add new global arc_addrtype_hash.
Define O_colon and O_addrtype.
(debug_exp): Add O_colon and O_addrtype.
(tokenize_arguments): Handle colon and address type
tokens.
(declare_addrtype): New function.
(md_begin): Initialise arc_addrtype_hash.
(arc_parse_name): Add lookup of address types.
(assemble_insn): Handle colons and address types by
ignoring them.
* testsuite/gas/arc/nps400-8.s: New file.
* testsuite/gas/arc/nps400-8.d: New file.
* testsuite/gas/arc/nps400-8.s: Add PMU instruction tests.
* testsuite/gas/arc/nps400-8.d: Add expected PMU
instruction output.
gas * config/tc-arc.c (parse_opcode_flags): New function.
(find_opcode_match): Move flag parsing code out to new function.
Ignore operands marked IGNORE.
(build_fake_opcode_hash_entry): New function.
(find_special_case_long_opcode): New function.
(find_special_case): Lookup long opcodes.
* testsuite/gas/arc/nps400-7.d: New file.
* testsuite/gas/arc/nps400-7.s: New file.
include * opcode/arc.h (MAX_INSN_ARGS): Increase to 16.
(struct arc_long_opcode): New structure.
(arc_long_opcodes): Declare.
(arc_num_long_opcodes): Declare.
opcodes * arc-dis.c (struct arc_operand_iterator): New structure.
(find_format_from_table): All the old content from find_format,
with some minor adjustments, and parameter renaming.
(find_format_long_instructions): New function.
(find_format): Rewritten.
(arc_insn_length): Add LSB parameter.
(extract_operand_value): New function.
(operand_iterator_next): New function.
(print_insn_arc): Use new functions to find opcode, and iterator
over operands.
* arc-opc.c (insert_nps_3bit_dst_short): New function.
(extract_nps_3bit_dst_short): New function.
(insert_nps_3bit_src2_short): New function.
(extract_nps_3bit_src2_short): New function.
(insert_nps_bitop1_size): New function.
(extract_nps_bitop1_size): New function.
(insert_nps_bitop2_size): New function.
(extract_nps_bitop2_size): New function.
(insert_nps_bitop_mod4_msb): New function.
(extract_nps_bitop_mod4_msb): New function.
(insert_nps_bitop_mod4_lsb): New function.
(extract_nps_bitop_mod4_lsb): New function.
(insert_nps_bitop_dst_pos3_pos4): New function.
(extract_nps_bitop_dst_pos3_pos4): New function.
(insert_nps_bitop_ins_ext): New function.
(extract_nps_bitop_ins_ext): New function.
(arc_operands): Add new operands.
(arc_long_opcodes): New global array.
(arc_num_long_opcodes): New global.
* arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
Move the logic that calculates the instruction length out to a new
function. Restructure the code to make it simpler.
opcodes/ChangeLog:
* arc-dis.c (arc_insn_length): New function.
(print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
(find_format): Change insnLen parameter to unsigned.
This commit introduces the nps400 machine type as a variant of arc.
There's a new flag in the assembler to select this machine type. All
other changes are just adding handling of the new machine type into the
relevant places.
The nps400 is an arc700 variant with some vendor specific instructions
added into the instruction set. This commit does not add any of the new
instructions, this is just laying the groundwork for future commits.
However, in preparation for these new instructions a new opcode define for
nps400 has been added to include/opcode/arc.h, this new opcode define is
used in the assembler and disassembler along with the existing define
for arc700 such that when assembling and disassembling for nps400 the
user will have access to all arc700 instructions and all the nps400
vendor extension instructions.
bfd/ChangeLog:
* archures.c (bfd_mach_arc_nps400): Define.
* bfd-in2.h: Regenerate.
* cpu-arc.c (arch_info_struct): New entry for nps400, renumber
some existing entries to make space.
* elf32-arc.c (arc_elf_object_p): Add nps400 case.
(arc_elf_final_write_processing): Likewise.
binutils/ChangeLog:
* readelf.c (decode_ARC_machine_flags): Handle nps400.
gas/ChangeLog:
* config/tc-arc.c (cpu_types): Add nps400 entry.
(check_zol): Handle nps400.
include/ChangeLog:
* elf/arc.h (E_ARC_MACH_NPS400): Define.
* opcode/arc.h (ARC_OPCODE_NPS400): Define.
opcodes/ChangeLog:
* arc-dis.c (print_insn_arc): Handle nps400.
value with a default.
(do_special_encoding): Likewise.
(aarch64_ins_ldst_elemlist): Pre-initialize QSsize, and opcodeh2
variables with default.
* arc-dis.c (write_comments_): Don't use strncat due
size of state->commentBuffer pointer isn't predictable.
* opcodes/arc-dis.c:Add enum a4_decoding_class.
(dsmOneArcInst): Use the enum values for the decoding class
Remove redundant case in the switch for decodingClass value 11
