binutils-gdb/opcodes
Tamar Christina 793a194839 Add assembler and disassembler support for the new Armv8.4-a registers for AArch64.
Some of these instructions have been back-ported as optional extensions to
Armv8.2-a and higher, but others are only available for Armv8.4-a.

opcodes/

	* aarch64-opc.c (aarch64_sys_regs): Add ARMv8.4-a registers;
	dit, vstcr_el2, vsttbr_el2, cnthvs_tval_el2, cnthvs_cval_el2,
	cnthvs_ctl_el2, cnthps_tval_el2, cnthps_cval_el2, cnthps_ctl_el2,
	sder32_el2, vncr_el2.
	(aarch64_sys_reg_supported_p): Likewise.
	(aarch64_pstatefields): Add dit register.
	(aarch64_pstatefield_supported_p): Likewise.
	(aarch64_sys_regs_tlbi): Add vmalle1os, vae1os, aside1os, vaae1os,
	vale1os, vaale1os, ipas2e1os, ipas2le1os, vae2os, vale2os, vmalls12e1os,
	vae3os, vale3os, alle2os, alle1os, alle3os, rvae1, rvaae1, rvale1,
	rvaale1, rvae1is, rvaae1is, rvale1is, rvaale1is, rvae1os, rvaae1os,
	rvale1os, rvaale1os, ripas2e1is, ripas2le1is, ripas2e1, ripas2le1,
	ripas2e1os, ripas2le1os, rvae2, rvale2, rvae2is, rvale2is, rvae2os,
	rvale2os, rvae3, rvale3, rvae3is, rvale3is, rvae3os, rvale3os.

gas/testsuite

	* gas/aarch64/armv8_4-a-registers-illegal.d: New.
	* gas/aarch64/armv8_4-a-registers-illegal.l: New.
	* gas/aarch64/armv8_4-a-registers-illegal.s: New.
	* gas/aarch64/armv8_4-a-registers.d: New.
	* gas/aarch64/armv8_4-a-registers.s: New.
2017-11-09 16:29:16 +00:00
..
po Add updated French translations for opcodes and gprof 2017-08-31 14:33:56 +01:00
.gitignore
ChangeLog Add assembler and disassembler support for the new Armv8.4-a registers for AArch64. 2017-11-09 16:29:16 +00:00
ChangeLog-0001
ChangeLog-0203
ChangeLog-2004
ChangeLog-2005
ChangeLog-2006
ChangeLog-2007
ChangeLog-2008
ChangeLog-2009
ChangeLog-2010
ChangeLog-2011
ChangeLog-2012
ChangeLog-2013
ChangeLog-2014
ChangeLog-2015
ChangeLog-2016
ChangeLog-9297
ChangeLog-9899
MAINTAINERS
Makefile.am
Makefile.in
aarch64-asm-2.c Adds the new Fields and Operand types for the new instructions in Armv8.4-a. 2017-11-09 16:29:04 +00:00
aarch64-asm.c Adds the new Fields and Operand types for the new instructions in Armv8.4-a. 2017-11-09 16:29:04 +00:00
aarch64-asm.h Adds the new Fields and Operand types for the new instructions in Armv8.4-a. 2017-11-09 16:29:04 +00:00
aarch64-dis-2.c Adds the new Fields and Operand types for the new instructions in Armv8.4-a. 2017-11-09 16:29:04 +00:00
aarch64-dis.c Adds the new Fields and Operand types for the new instructions in Armv8.4-a. 2017-11-09 16:29:04 +00:00
aarch64-dis.h Adds the new Fields and Operand types for the new instructions in Armv8.4-a. 2017-11-09 16:29:04 +00:00
aarch64-gen.c [AArch64] Fix the bit pattern order in the comments in auto-generated file 2017-07-24 14:59:06 +01:00
aarch64-opc-2.c Adds the new Fields and Operand types for the new instructions in Armv8.4-a. 2017-11-09 16:29:04 +00:00
aarch64-opc.c Add assembler and disassembler support for the new Armv8.4-a registers for AArch64. 2017-11-09 16:29:16 +00:00
aarch64-opc.h Adds the new Fields and Operand types for the new instructions in Armv8.4-a. 2017-11-09 16:29:04 +00:00
aarch64-tbl.h Add the operand encoding types for the new Armv8.2-a back-ported instructions. These are to be used later when the new instructions are added. 2017-11-09 16:29:07 +00:00
aclocal.m4
alpha-dis.c
alpha-opc.c
arc-dis.c [ARC] Force the disassam to use the hexadecimal number for printing 2017-11-03 15:36:54 +01:00
arc-dis.h
arc-ext-tbl.h
arc-ext.c
arc-ext.h
arc-fxi.h
arc-nps400-tbl.h opcodes/arc: Fix incorrect insn_class for some nps insns 2017-11-07 20:24:21 +00:00
arc-opc.c Fix typos in error and option messages in OPCODES library. 2017-07-25 12:12:16 +01:00
arc-regs.h [ARC] Add SecureShield AUX registers 2017-07-19 09:56:55 +02:00
arc-tbl.h [ARC] Sync opcode data base. 2017-11-03 14:38:05 +01:00
arm-dis.c Adds command line support for Armv8.4-A, via the new command line option -march=armv8.4-a. Add support for "+dotprod" ARM feature (required for ARMv8.4-A). Add assembler and disassembler support for new FP16 instructions introduced in Armv8.4-A 2017-11-08 13:15:12 +00:00
avr-dis.c
bfin-dis.c
cgen-asm.c
cgen-asm.in
cgen-bitset.c
cgen-dis.c
cgen-dis.in
cgen-ibld.in
cgen-opc.c
cgen.sh
config.in
configure
configure.ac
configure.com
cr16-dis.c PR22348, conflicting global vars in crx and cr16 2017-10-25 22:14:58 +10:30
cr16-opc.c
cris-dis.c
cris-opc.c
crx-dis.c PR22348, conflicting global vars in crx and cr16 2017-10-25 22:14:58 +10:30
crx-opc.c PR22348, conflicting global vars in crx and cr16 2017-10-25 22:14:58 +10:30
d10v-dis.c
d10v-opc.c
d30v-dis.c
d30v-opc.c
dep-in.sed
dis-buf.c binutils/objdump: Fix disassemble for huge elf sections 2017-07-14 22:51:01 +09:30
dis-init.c
disassemble.c Mark big and mach with ATTRIBUTE_UNUSED 2017-08-07 08:07:26 -07:00
disassemble.h
dlx-dis.c
epiphany-asm.c
epiphany-desc.c
epiphany-desc.h
epiphany-dis.c
epiphany-ibld.c
epiphany-opc.c
epiphany-opc.h
fr30-asm.c
fr30-desc.c
fr30-desc.h
fr30-dis.c
fr30-ibld.c
fr30-opc.c
fr30-opc.h
frv-asm.c
frv-desc.c
frv-desc.h
frv-dis.c
frv-ibld.c
frv-opc.c
frv-opc.h
ft32-dis.c FT32: support for FT32B processor - part 1 2017-10-12 18:41:29 -07:00
ft32-opc.c FT32: support for FT32B processor - part 1 2017-10-12 18:41:29 -07:00
h8300-dis.c
h8500-dis.c
h8500-opc.h
hppa-dis.c
i370-dis.c
i370-opc.c
i386-dis-evex.h Enable Intel AVX512_BITALG instructions. 2017-10-23 15:58:18 +03:00
i386-dis.c Enable Intel AVX512_BITALG instructions. 2017-10-23 15:58:18 +03:00
i386-gen.c Enable Intel AVX512_BITALG instructions. 2017-10-23 15:58:18 +03:00
i386-init.h Fix the master due to bad regenerated files 2017-10-23 19:58:03 +03:00
i386-opc.c
i386-opc.h Enable Intel AVX512_BITALG instructions. 2017-10-23 15:58:18 +03:00
i386-opc.tbl Enable Intel AVX512_BITALG instructions. 2017-10-23 15:58:18 +03:00
i386-reg.tbl
i386-tbl.h Fix the master due to bad regenerated files 2017-10-23 19:58:03 +03:00
i860-dis.c
i960-dis.c
ia64-asmtab.c
ia64-asmtab.h
ia64-dis.c
ia64-gen.c
ia64-ic.tbl
ia64-opc-a.c
ia64-opc-b.c
ia64-opc-d.c
ia64-opc-f.c
ia64-opc-i.c
ia64-opc-m.c
ia64-opc-x.c
ia64-opc.c
ia64-opc.h
ia64-raw.tbl
ia64-war.tbl
ia64-waw.tbl
ip2k-asm.c
ip2k-desc.c
ip2k-desc.h
ip2k-dis.c
ip2k-ibld.c
ip2k-opc.c
ip2k-opc.h
iq2000-asm.c
iq2000-desc.c
iq2000-desc.h
iq2000-dis.c
iq2000-ibld.c
iq2000-opc.c
iq2000-opc.h
lm32-asm.c
lm32-desc.c
lm32-desc.h
lm32-dis.c
lm32-ibld.c
lm32-opc.c
lm32-opc.h
lm32-opinst.c
m32c-asm.c
m32c-desc.c
m32c-desc.h
m32c-dis.c
m32c-ibld.c
m32c-opc.c
m32c-opc.h
m32r-asm.c
m32r-desc.c
m32r-desc.h
m32r-dis.c
m32r-ibld.c
m32r-opc.c
m32r-opc.h
m32r-opinst.c
m68hc11-dis.c
m68hc11-opc.c
m68k-dis.c
m68k-opc.c Allow the macw and macl instructions to be used on CPUs that have emacs support. 2017-09-26 10:36:23 +01:00
m88k-dis.c
m10200-dis.c
m10200-opc.c
m10300-dis.c
m10300-opc.c
makefile.vms
mcore-dis.c
mcore-opc.h
mep-asm.c
mep-desc.c
mep-desc.h
mep-dis.c
mep-ibld.c
mep-opc.c
mep-opc.h
metag-dis.c
microblaze-dis.c
microblaze-dis.h
microblaze-opc.h
microblaze-opcm.h
micromips-opc.c
mips-dis.c
mips-formats.h
mips-opc.c
mips16-opc.c
mmix-dis.c
mmix-opc.c
moxie-dis.c
moxie-opc.c
msp430-decode.c
msp430-decode.opc
msp430-dis.c
mt-asm.c
mt-desc.c
mt-desc.h
mt-dis.c
mt-ibld.c
mt-opc.c
mt-opc.h
nds32-asm.c nds32: Rename __BIT() to N32_BIT(). 2017-09-11 13:46:27 +08:00
nds32-asm.h nds32: Rename __BIT() to N32_BIT(). 2017-09-11 13:46:27 +08:00
nds32-dis.c nds32: Rename __BIT() to N32_BIT(). 2017-09-11 13:46:27 +08:00
nds32-opc.h
nios2-dis.c
nios2-opc.c
ns32k-dis.c
opc2c.c
opintl.h ngettext support 2017-11-07 15:52:52 +10:30
or1k-asm.c
or1k-desc.c
or1k-desc.h
or1k-dis.c
or1k-ibld.c
or1k-opc.c
or1k-opc.h
or1k-opinst.c
pdp11-dis.c
pdp11-opc.c
pj-dis.c
pj-opc.c
ppc-dis.c [PowerPC VLE] Add SPE2 and EFS2 instructions support 2017-08-24 17:30:31 +09:30
ppc-opc.c Add new mnemonics for VLE multiple load instructions 2017-10-01 19:35:06 +10:30
pru-dis.c
pru-opc.c
riscv-dis.c Fix typos in error and option messages in OPCODES library. 2017-07-25 12:12:16 +01:00
riscv-opc.c RISC-V: Fix disassembly of c.addi4spn, c.addi16sp, c.lui when imm=0 2017-10-24 09:47:36 -07:00
rl78-decode.c
rl78-decode.opc
rl78-dis.c
rx-decode.c
rx-decode.opc
rx-dis.c
s390-dis.c
s390-mkopc.c S/390: Support z14 as CPU name. 2017-07-21 10:54:06 +02:00
s390-opc.c S/390: Sync with IBM z14 POP - SI_RD format 2017-10-09 18:37:53 +02:00
s390-opc.txt S/390: Sync with latest POP - 3 new instructions 2017-10-09 18:37:53 +02:00
score-dis.c
score-opc.h
score7-dis.c
sh-dis.c
sh-opc.h
sh64-dis.c
sh64-opc.c
sh64-opc.h
sparc-dis.c
sparc-opc.c
spu-dis.c
spu-opc.c
stamp-h.in
sysdep.h
tic4x-dis.c
tic6x-dis.c
tic30-dis.c
tic54x-dis.c
tic54x-opc.c
tic80-dis.c
tic80-opc.c
tilegx-dis.c
tilegx-opc.c
tilepro-dis.c
tilepro-opc.c
v850-dis.c
v850-opc.c
vax-dis.c
visium-dis.c [Visium] Disassemble the operands of the stop instruction. 2017-10-18 16:30:24 +02:00
visium-opc.c
w65-dis.c
w65-opc.h
wasm32-dis.c
xc16x-asm.c
xc16x-desc.c
xc16x-desc.h
xc16x-dis.c
xc16x-ibld.c
xc16x-opc.c
xc16x-opc.h
xgate-dis.c
xgate-opc.c
xstormy16-asm.c
xstormy16-desc.c
xstormy16-desc.h
xstormy16-dis.c
xstormy16-ibld.c
xstormy16-opc.c
xstormy16-opc.h
xtensa-dis.c
z8k-dis.c
z8k-opc.h
z8kgen.c
z80-dis.c