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Author SHA1 Message Date
Manuel López-Ibáñez
3aac09524b line-map.h (linemap_location_from_macro_expansion_p): const struct line_maps * argument. 
libcpp/ChangeLog:

2014-10-14  Manuel López-Ibáñez  <manu@gcc.gnu.org>

	* include/line-map.h (linemap_location_from_macro_expansion_p):
	const struct line_maps * argument.
	(linemap_position_for_line_and_column): const struct line_map *
	argument.
	* line-map.c (linemap_add_macro_token): Use correct argument name
	in comment.
	(linemap_position_for_line_and_column): const struct line_map *
	argument.
	(linemap_macro_map_loc_to_def_point): Fix comment. Make static.
	(linemap_location_from_macro_expansion_p): const struct line_maps *
	argument.
	(linemap_resolve_location): Fix argument names in comment.

From-SVN: r216205
 2014-10-14 14:45:36 +00:00
Marc Glisse
48d3af1259 typeck.c (cp_build_unary_op): Accept float vectors. 
2014-10-14  Marc Glisse  <marc.glisse@inria.fr>

gcc/cp/
	* typeck.c (cp_build_unary_op) [TRUTH_NOT_EXPR]: Accept float vectors.
gcc/testsuite/
	* g++.dg/ext/vector9.C: Test ! with float vectors.

From-SVN: r216201
 2014-10-14 13:40:36 +00:00
Alexander Ivchenko
ebe87abf2b AVX-512. 77/n. Use blend for cond-set V32HI and V64QI. 
gcc/
	* config/i386/i386.c
	(ix86_expand_sse_movcc): Handle V64QI and V32HI mode.
	(ix86_expand_int_vcond): Ditto.

Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com>
Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com>
Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com>
Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com>
Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com>
Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>

From-SVN: r216193
 2014-10-14 08:56:56 +00:00
Alexander Ivchenko
0ab03ea08c AVX-512. 74/n. Add byte/word max/mix reduction. 
gcc/
	* config/i386/i386.c
	(emit_reduc_half): Handle V64QI and V32HI mode.
	* config/i386/sse.md
	(define_mode_iterator VI_AVX512BW): New.
	(define_expand "reduc_<code>_<mode>"): Use VI512_48F_12BW.

Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com>
Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com>
Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com>
Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com>
Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com>
Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>

From-SVN: r216192
 2014-10-14 08:52:11 +00:00
Alexander Ivchenko
805e20ad38 AVX-512. 73/n. Extend reduc min/max autogen. 
gcc/
        * config/i386/sse.md
        (define_mode_iterator REDUC_SMINMAX_MODE): Add V64QI and V32HI modes.

Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com>
Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com>
Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com>
Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com>
Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com>
Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>

From-SVN: r216191
 2014-10-14 08:50:43 +00:00
Alexander Ivchenko
9945a4328a AVX-512. 72/n. Extend VI itterator. 
gcc/
	* config/i386/i386.c
	(ix86_expand_vector_logical_operator): Handle V16SF and V8DF modes.
	* config/i386/sse.md
	(define_mode_iterator VI): Add V64QI and V32HI modes.

Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com>
Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com>
Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com>
Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com>
Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com>
Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>

From-SVN: r216190
 2014-10-14 08:49:23 +00:00
Alexander Ivchenko
7c3a34ae94 AVX-512. 71/n. Remove redudant iterator attribute. 
gcc/
	* config/i386/sse.md (define_mode_attr avx2_avx512f): Remove.

Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com>
Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com>
Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com>
Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com>
Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com>
Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>

From-SVN: r216189
 2014-10-14 08:47:55 +00:00
Paolo Carlini
181e036880 typedefs.cc: Rename to alias_decl.cc. 
2014-10-14  Paolo Carlini  <paolo.carlini@oracle.com>

	* testsuite/20_util/add_lvalue_reference/requirements/typedefs.cc:
	Rename to alias_decl.cc.
	* testsuite/20_util/add_rvalue_reference/requirements/typedefs.cc:
	Likewise.
	* testsuite/20_util/common_type/requirements/typedefs-3.cc: Likewise.
	* testsuite/20_util/conditional/requirements/typedefs-2.cc: Likewise.
	* testsuite/20_util/decay/requirements/typedefs-2.cc: Likewise.
	* testsuite/20_util/enable_if/requirements/typedefs-2.cc: Likewise.
	* testsuite/20_util/make_signed/requirements/typedefs-3.cc: Likewise.
	* testsuite/20_util/make_unsigned/requirements/typedefs-3.cc:
	Likewise.
	* testsuite/20_util/remove_reference/requirements/typedefs.cc:
	Likewise.
	* testsuite/20_util/result_of/requirements/typedefs.cc: Likewise.
	* testsuite/20_util/underlying_type/requirements/typedefs-3.cc:
	Likewise.

From-SVN: r216188
 2014-10-14 08:45:38 +00:00
Alexander Ivchenko
c305ca7f62 AVX-512. 70/n. Add vpmaxmin. 
gcc/
	* config/i386/sse.md
	(define_insn "*sse4_1_<code><mode>3<mask_name>"): Add masking.
	(define_insn "*sse4_1_<code><mode>3<mask_name>"): Ditto.

Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com>
Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com>
Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com>
Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com>
Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com>
Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>

From-SVN: r216187
 2014-10-14 08:45:17 +00:00
Alexander Ivchenko
cf25c30945 AVX-512. 69/n. Add vpmulhrsw insn support. 
gcc/
        * config/i386/sse.md
        (define_insn "avx512bw_umulhrswv32hi3<mask_name>"): New.
        (define_expand "<ssse3_avx2>_pmulhrsw<mode>3_mask"): Ditto.

Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com>
Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com>
Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com>
Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com>
Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com>
Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>

From-SVN: r216186
 2014-10-14 08:42:02 +00:00
Alexander Ivchenko
ed3e611e05 AVX-512. 68/n. Add vpmullw, vpacksdw, pmaddwd insn. 
gcc/
	* config/i386/sse.md
	(define_c_enum "unspec"): Add UNSPEC_PMADDWD512.
	(define_mode_iterator VI2_AVX2): Add V32HI mode.
	(define_expand "mul<mode>3<mask_name>"): Add masking.
	(define_insn "*mul<mode>3<mask_name>"): Ditto.
	(define_expand "<s>mul<mode>3_highpart<mask_name>"): Ditto.
	(define_insn "*<s>mul<mode>3_highpart<mask_name>"): Ditto.
	(define_insn "avx512bw_pmaddwd512<mode><mask_name>"): New.
	(define_mode_attr SDOT_PMADD_SUF): Ditto.
	(define_expand "sdot_prod<mode>"): Add <SDOT_PMADD_SUF>.
	(define_insn "<sse2_avx2>_packssdw<mask_name>"): Add masking.
	(define_insn "*<ssse3_avx2>_pmulhrsw<mode>3<mask_name>"): Ditto.
	(define_insn "avx2_packusdw"): Delete.
	(define_insn "sse4_1_packusdw"): Ditto.
	(define_insn "<sse4_1_avx2>_packusdw<mask_name>"): New.

Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com>
Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com>
Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com>
Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com>
Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com>
Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>

From-SVN: r216185
 2014-10-14 08:40:34 +00:00
Alexander Ivchenko
1aff6f9a2f AVX-512. 67/n. Update constraints in vec_dup insn. 
gcc/
	* config/i386/sse.md
	(define_insn "vec_dup<mode>"): Update constraints.

Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com>
Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com>
Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com>
Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com>
Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com>
Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>

From-SVN: r216184
 2014-10-14 08:38:47 +00:00
Alexander Ivchenko
b99ba39a84 AVX-512. 66/n. Extend vpalignr insn patterns. 
gcc/
	* config/i386/sse.md
	(define_mode_iterator SSESCALARMODE): Add V4TI mode.
	(define_insn "<ssse3_avx2>_palignr<mode>_mask"): New.
	(define_insn "<ssse3_avx2>_palignr<mode>"): Add EVEX version.

Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com>
Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com>
Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com>
Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com>
Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com>
Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>

From-SVN: r216183
 2014-10-14 08:35:12 +00:00
Alexander Ivchenko
2ac7a566e8 AVX-512. 65/n. Add rest of VI1-AVX2: mul insn pattern. 
gcc/
	* config/i386/sse.md
	(define_expand "mul<mode>3<mask_name>"): Add masking.

Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com>
Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com>
Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com>
Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com>
Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com>
Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>

From-SVN: r216182
 2014-10-14 08:33:01 +00:00
Alexander Ivchenko
d281ef4281 AVX-512. 64/n. Add rest of VI1-AVX2: vpack[us]wb. 
gcc/
	* config/i386/sse.md
	(define_insn "<sse2_avx2>_packsswb<mask_name>"): Add masking.
	(define_insn "<sse2_avx2>_packuswb<mask_name>"): Ditto.

Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com>
Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com>
Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com>
Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com>
Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com>
Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>

From-SVN: r216181
 2014-10-14 08:28:33 +00:00
Alexander Ivchenko
5f64b49668 AVX-512. 62/n. Add vpmaddubsw,vdbpsadbw insn patterns. 
gcc/
	* config/i386/sse.md
	(define_c_enum "unspec"): Add UNSPEC_DBPSADBW, UNSPEC_PMADDUBSW512.
	(define_insn "avx512bw_pmaddubsw512<mode><mask_name>"): New.
	(define_insn "<mask_codefor>avx512bw_dbpsadbw<mode><mask_name>"):
	Ditto.

Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com>
Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com>
Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com>
Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com>
Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com>
Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>

From-SVN: r216180
 2014-10-14 08:26:09 +00:00
Alexander Ivchenko
26358fb6a0 AVX-512. 61/n. Update FP logic insn patterns. 
gcc/
	* config/i386/sse.md
	(define_insn "<sse>_andnot<VF_128_256:mode>3<mask_name>"): Add masking,
	use VF_128_256 mode iterator and update assembler emit code.
	(define_insn "<sse>_andnot<VF_512:mode>3<mask_name>"): New.
	(define_expand "<any_logic:code><VF_128_256:mode>3<mask_name>"):
	Add masking, use VF_128_256 mode iterator.
	(define_expand "<any_logic:code><VF_512:mode>3<mask_name>"): New.
	(define_insn "*<any_logic:code><VF_128_256:mode>3<mask_name>"):
	Add masking, use VF_128_256 mode iterator and update assembler emit
	code.
	(define_insn "*<any_logic:code><VF_512:mode>3<mask_name>"): New.
	(define_mode_attr avx512flogicsuff): Delete.
	(define_insn "avx512f_<logic><mode>"): Ditto.
	(define_insn "*andnot<mode>3<mask_name>"): Update MODE_XI, MODE_OI,
	MODE_TI.
	(define_insn "<mask_codefor><code><mode>3<mask_name>"): Ditto.

Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com>
Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com>
Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com>
Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com>
Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com>
Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>

From-SVN: r216179
 2014-10-14 08:20:43 +00:00
Alexander Ivchenko
06ba0585d6 AVX-512. 60/n. Update 128bit ashrv insn pattern. 
gcc/
	* config/i386/sse.md
	(define_mode_iterator VI128_128 [V16QI V8HI V2DI]): Delete.
	(define_expand "vashr<mode>3<mask_name>"): Add masking,
	use VI12_128 mode iterator.
	(define_expand "ashrv2di3<mask_name>"): New.

Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com>
Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com>
Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com>
Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com>
Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com>
Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>

From-SVN: r216178
 2014-10-14 08:19:17 +00:00
Alexander Ivchenko
54967fb0c8 AVX-512. 59/n. Add vptest[n]m, ucmp, cmpeq insn patterns. 
gcc/
	* config/i386/i386.c
	(ix86_expand_args_builtin): Handle CODE_FOR_avx512vl_cmpv4di3_mask,
	CODE_FOR_avx512vl_cmpv8si3_mask, CODE_FOR_avx512vl_ucmpv4di3_mask,
	CODE_FOR_avx512vl_ucmpv8si3_mask, CODE_FOR_avx512vl_cmpv2di3_mask,
	CODE_FOR_avx512vl_cmpv4si3_mask, CODE_FOR_avx512vl_ucmpv2di3_mask,
	CODE_FOR_avx512vl_ucmpv4si3_mask.
	* config/i386/sse.md
	(define_insn "avx512f_ucmp<mode>3<mask_scalar_merge_name>"): Delete.
	"<avx512>_ucmp<VI12_AVX512VL:mode>3<mask_scalar_merge_name>"):New.
	(define_insn
	"<avx512>_ucmp<VI48_AVX512VL:mode>3<mask_scalar_merge_name>"):Ditto.
	(define_expand "<avx512>_eq<mode>3<mask_scalar_merge_name>"): Ditto.
	(define_insn "<avx512>_eq<mode>3<mask_scalar_merge_name>_1"): Ditto.
	(define_insn "<avx512>_gt<mode>3<mask_scalar_merge_name>"): Ditto.
	(define_insn "<avx512>_testm<mode>3<mask_scalar_merge_name>"): Ditto.
	(define_insn "<avx512>_testnm<mode>3<mask_scalar_merge_name>"): Ditto.

Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com>
Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com>
Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com>
Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com>
Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com>
Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>

From-SVN: r216177
 2014-10-14 08:15:32 +00:00
Alexander Ivchenko
f1df7a1c52 AVX-512. 58/n. Add vpmul[u]dq insn patterns. 
gcc/
	* config/i386/sse.md
	(define_expand "vec_widen_umult_even_v8si<mask_name>"): Add masking.
	(define_insn "*vec_widen_umult_even_v8si<mask_name>"): Ditto.
	(define_expand "vec_widen_umult_even_v4si<mask_name>"): Ditto.
	(define_insn "*vec_widen_umult_even_v4si<mask_name>"): Ditto.
	(define_expand "vec_widen_smult_even_v8si<mask_name>"): Ditto.
	(define_insn "*vec_widen_smult_even_v8si<mask_name>"): Ditto.
	(define_expand "sse4_1_mulv2siv2di3<mask_name>"): Ditto.
	(define_insn "*sse4_1_mulv2siv2di3<mask_name>"): Ditto.
	(define_insn "avx512dq_mul<mode>3<mask_name>"): New.

Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com>
Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com>
Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com>
Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com>
Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com>
Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>

From-SVN: r216176
 2014-10-14 08:13:31 +00:00
Alexander Ivchenko
51e14b0572 AVX-512. 57/n. Extend blend/cmp/brodcast insn patterns. 
gcc/
	* config/i386/sse.md
	(define_insn "avx512f_blendm<mode>"): Delete.
	(define_insn "<avx512>_blendm<VI48_AVX512VL:mode>"): New.
	(define_insn "<avx512>_blendm<VI12_AVX512VL:mode>"): Ditto..
	(define_mode_attr cmp_imm_predicate): Add V8SF, V4DF, V8SI, V4DI, V4SF,
	V2DF, V4SI, V2DI, V32HI, V64QI, V16HI, V32QI, V8HI, V16QI modes.
	(define_insn
	"avx512f_cmp<mode>3<mask_scalar_merge_name><round_saeonly_name>"):
	Remove.
	(define_insn
	"<avx512>_cmp<VI48_AVX512VL:mode>3<mask_scalar_merge_name><round_saeonly_name>"):
	New.
	(define_insn
	"<avx512>_cmp<VI12_AVX512VL:mode>3<mask_scalar_merge_name><round_saeonly_name>"):
	Ditto.
	(define_insn "<mask_codefor>avx512f_vec_dup<mode><mask_name>"): Delete.
	(define_insn "<avx512>_vec_dup<V48_AVX512VL:mode><mask_name>"): New.
	(define_insn "<avx512>_vec_dup<V12_AVX512VL:mode><mask_name>"): Ditto.
	(define_insn "<mask_codefor>avx512f_vec_dup_gpr<mode><mask_name>"):
	Delete.
	(define_insn
	"<mask_codefor><avx512>_vec_dup_gpr<VI48_AVX512VL:mode><mask_name>"):
	New.
	(define_insn
	"<mask_codefor><avx512>_vec_dup_gpr<VI12_AVX512VL:mode><mask_name>"):
	Ditto.
	(define_insn·"<mask_codefor>avx512f_vec_dup_mem<mode><mask_name>"):
	Delete.
	(define_insn
	"<mask_codefor><avx512>_vec_dup_mem<VI48_AVX512VL:mode><mask_name>"):
	New.
	(define_insn
	"<mask_codefor><avx512>_vec_dup_mem<VI12_AVX512VL:mode><mask_name>"):
	Ditto.

Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com>
Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com>
Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com>
Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com>
Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com>
Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>

From-SVN: r216175
 2014-10-14 08:10:42 +00:00
Richard Biener
b6fed550a3 re PR tree-optimization/63512 (ICE: error: virtual use of statement not up-to-date) 
2014-10-14  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/63512
	* tree-ssa-pre.c (create_expression_by_pieces): Mark stmts
	modified.

	* g++.dg/torture/pr63512.C: New testcase.

From-SVN: r216174
 2014-10-14 07:36:02 +00:00
Oleg Endo
340232b7e4 re PR target/63260 ([SH] fabs, fneg do not need fp-mode setting and do not use fpscr) 
gcc/
	PR target/63260
	* config/sh/sh.md (negsf2, negsf2_i, negdf2, negdf2_i, abssf2,
	abssf2_i, absdf2, absdf2_i): Remove fp_mode attribute.  Remove use
	of FPSCR.
	(negsf2_i): Rename to *negsf2_i.
	(abssf2_i): Rename to *abssf2_i.
	(negdf2_i): Rename to *negdf2_i.
	(absdf2_i): Rename to *absdf2_i.

gcc/testsuite/
	PR target/63260
	* gcc.target/sh/pr63260.c: New.

From-SVN: r216173
 2014-10-14 00:50:18 +00:00
GCC Administrator
f0a81c69c9 Daily bump. 
From-SVN: r216172
 2014-10-14 00:16:25 +00:00
Felix Yang
5ffa4e6a76 ira.c (struct equivalence): Change member "is_arg_equivalence" and "replace" into boolean bitfields... 
gcc/
        * ira.c (struct equivalence): Change member "is_arg_equivalence" and
        "replace" into boolean bitfields; turn member "loop_depth" into a short
        integer; add new member "no_equiv" and "reserved".
        (no_equiv): Set no_equiv of struct equivalence if register is marked
        as having no known equivalence.
        (update_equiv_regs): Check all definitions for a multiple-set
        register to make sure that the RHS have the same value.

Co-Authored-By: Jeff Law <law@redhat.com>

From-SVN: r216169
 2014-10-14 00:12:51 +00:00
Anthony Brandon
74d98c1e9b c-parser.c (c_parser_all_labels): New function to replace the duplicate code. 
gcc/c/ChangeLog:

2014-10-13  Anthony Brandon  <anthony.brandon@gmail.com>

        * c-parser.c (c_parser_all_labels): New function to replace
	the duplicate code.
        (c_parser_statement): Call the new function.

From-SVN: r216165
 2014-10-13 21:00:55 +00:00
Richard Henderson
3dce09649d Handle cfa adjustments in csa pass 
* combine-stack-adj.c (no_unhandled_cfa): New.
(maybe_merge_cfa_adjust): New.
(combine_stack_adjustments_for_block): Use them.

From-SVN: r216161
 2014-10-13 13:20:44 -07:00
Aldy Hernandez
e3c891c7cf * Makefile.in (TAGS): Tag ../include files. 
From-SVN: r216160
 2014-10-13 19:57:14 +00:00
Ulrich Weigand
3d36d470d8 rs6000.h (DBX_REGISTER_NUMBER): Pass format argument to rs6000_dbx_register_number. 
* config/rs6000/rs6000.h (DBX_REGISTER_NUMBER): Pass format argument
	to rs6000_dbx_register_number.
	(DWARF_FRAME_REGNUM): Redefine as identity map.
	(DWARF2_FRAME_REG_OUT): Call rs6000_dbx_register_number.
	* config/rs6000/rs6000-protos.h (rs6000_dbx_register_number): Update.
	* config/rs6000/rs6000.c (rs6000_dbx_register_number): Add format
	argument to handle .debug_frame and .eh_frame directly.  Always
	translate SPE high register numbers.  Add special treatment for CR,
	but only in .debug_frame.  Respect RS6000_USE_DWARF_NUMBERING.

	* config/rs6000/sysv.h (DBX_REGISTER_NUMBER): Do not undefine.
	* config/rs6000/freebsd.h (DBX_REGISTER_NUMBER): Remove.
	(RS6000_USE_DWARF_NUMBERING): Define.
	* config/rs6000/freebsd64.h (DBX_REGISTER_NUMBER): Remove.
	(RS6000_USE_DWARF_NUMBERING): Define.
	* config/rs6000/netbsd.h (DBX_REGISTER_NUMBER): Remove.
	(RS6000_USE_DWARF_NUMBERING): Define.
	* config/rs6000/lynx.h (DBX_REGISTER_NUMBER): Remove.
	(RS6000_USE_DWARF_NUMBERING): Define.
	* config/rs6000/aix.h (RS6000_USE_DWARF_NUMBERING): Define.
	* config/rs6000/darwin.h (RS6000_USE_DWARF_NUMBERING): Define.

From-SVN: r216157
 2014-10-13 17:47:20 +00:00
Kirill Yukhin
d91684adfb Add missing in r216154 test. 
From-SVN: r216156
 2014-10-13 17:29:31 +00:00
Evgeny Stupachenko
fa53ca7196 i386.c (ix86_address_cost): Lower cost for when address contains GOT register. 
gcc/
	* config/i386/i386.c (ix86_address_cost): Lower cost for
	when address contains GOT register.

From-SVN: r216155
 2014-10-13 17:28:24 +00:00
Kirill Yukhin
bcb21886b9 re PR target/8340 (ICE on x86 inline asm w/ -fPIC) 
gcc/
	PR target/8340
	PR middle-end/47602
	PR rtl-optimization/55458
	* config/i386/i386.c (ix86_use_pseudo_pic_reg): New.
	(ix86_init_pic_reg): New.
	(ix86_select_alt_pic_regnum): Add check on pseudo register.
	(ix86_save_reg): Likewise.
	(ix86_expand_prologue): Remove PIC register initialization
	now performed in ix86_init_pic_reg.
	(ix86_output_function_epilogue): Add check on pseudo register.
	(set_pic_reg_ever_alive): New.
	(legitimize_pic_address): Replace df_set_regs_ever_live with new
	set_pic_reg_ever_alive.
	(legitimize_tls_address): Likewise.
	(ix86_pic_register_p): New check.
	(ix86_delegitimize_address): Add check on pseudo register.
	(ix86_expand_call): Insert move from pseudo PIC register to ABI
	defined REAL_PIC_OFFSET_TABLE_REGNUM.
	(TARGET_INIT_PIC_REG): New.
	(TARGET_USE_PSEUDO_PIC_REG): New.
	* config/i386/i386.h (PIC_OFFSET_TABLE_REGNUM): Return INVALID_REGNUM
	if pic_offset_table_rtx exists.
	* doc/tm.texi.in (TARGET_USE_PSEUDO_PIC_REG, TARGET_INIT_PIC_REG):
	Document.
	* doc/tm.texi: Regenerate.
	* function.c (assign_parms): Generate pseudo register for PIC.
	* init-regs.c (initialize_uninitialized_regs): Ignor pseudo PIC
	register.
	* ira-color.c (color_pass): Add check on pseudo register.
	* ira-emit.c (change_loop): Don't create copies for PIC pseudo
	register.
	* ira.c (split_live_ranges_for_shrink_wrap): Add check on pseudo
	register.
	(ira): Add target specific PIC register initialization.
	(do_reload): Keep PIC pseudo register.
	* lra-assigns.c (spill_for): Add checks on pseudo register.
	* lra-constraints.c (contains_symbol_ref_p): New.
	(lra_constraints): Enable lra risky transformations when PIC is pseudo
	register.
	* shrink-wrap.c (try_shrink_wrapping): Add check on pseudo register.
	* target.def (use_pseudo_pic_reg): New.
	(init_pic_reg): New.

gcc/testsuite/
	PR target/8340
	PR middle-end/47602
	PR rtl-optimization/55458
	* gcc.target/i386/pic-1.c: Remove dg-error as test should pass now.
	* gcc.target/i386/pr55458.c: Likewise.
	* gcc.target/i386/pr47602.c: New.
	* gcc.target/i386/pr23098.c: Move to XFAIL.

From-SVN: r216154
 2014-10-13 17:26:49 +00:00
Evgeny Stupachenko
8d99ad36b3 x86-tune.def (X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY): Remove m_SILVERMONT and m_INTEL from the tune. 
gcc/
	* config/i386/x86-tune.def (X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY):
	Remove m_SILVERMONT and m_INTEL from the tune.

From-SVN: r216153
 2014-10-13 17:22:32 +00:00
John David Anglin
e28c760633 re PR libfortran/63471 (unix.c:1906:10: error: implicit declaration of function 'ttyname_r') 
PR libfortran/63471
        * config/pa/pa-hpux11.h (TARGET_OS_CPP_BUILTINS): Define _REENTRANT
        when _HPUX_SOURCE is defined.

From-SVN: r216152
 2014-10-13 17:02:35 +00:00
H.J. Lu
aaf7bd8a50 Cast size and elements to long for %l 
* mangle.c (mangle_conv_op_name_for_type): Cast elements to
	unsigned long.
	(print_template_statistics): Cast size and elements to long.

From-SVN: r216151
 2014-10-13 09:01:40 -07:00
Jan Hubicka
daaf6209a4 re PR c++/62127 (ICE with VLA in constructor) 
PR tree-optimization/62127
	* g++.dg/torture/pr62127.C: New testcase.
	* tree.c (remap_type_1): When remapping array, remap
	also its type.

From-SVN: r216150
 2014-10-13 14:43:24 +00:00
Jonathan Wakely
01d6452fe5 re PR libstdc++/57350 (std::align missing) 
PR libstdc++/57350
	* include/std/memory (align): Do not adjust correctly aligned address.
	* testsuite/20_util/align/2.cc: New.

From-SVN: r216149
 2014-10-13 15:08:44 +01:00
Christophe Lyon
270cc99ec8 Update ChangeLog for previous commit. 
From-SVN: r216148
 2014-10-13 16:01:19 +02:00
Christophe Lyon
83022253ad Makefile.in: (check-%): Update comment, as RUNTESTFLAGS no longer impact parallelization. 
2014-10-13  Christophe Lyon  <christophe.lyon@linaro.org>

	gcc/
	* Makefile.in: (check-%): Update comment, as RUNTESTFLAGS no
	longer impact parallelization.

From-SVN: r216147
 2014-10-13 15:56:34 +02:00
Jan Hubicka
176dc0927d re PR bootstrap/63496 (../../gcc/ipa-polymorphic-call.c:2117:1: error: assuming signed overflow does not occur when assuming that (X + c) < X is always false [-Werror=strict-overflow]) 
PR bootstrap/63496
	* ipa-polymorphic-call.c (extr_type_from_vtbl_ptr_store): Fix pasto.

From-SVN: r216146
 2014-10-13 12:44:00 +00:00
Siva Chandra Reddy
4027b0158d xmethods.py: Add xmethods for std::array, std::deque, std::forward_list, std::list, std::vector. 
2014-10-13  Siva Chandra Reddy  <sivachandra@google.com>

	* python/libstdcxx/v6/xmethods.py: Add xmethods for std::array,
	std::deque, std::forward_list, std::list, std::vector.
	* testsuite/libstdc++-xmethods/array.cc: New file.
	* testsuite/libstdc++-xmethods/deque.cc: Likewise.
	* testsuite/libstdc++-xmethods/forwardlist.cc: Likewise.
	* testsuite/libstdc++-xmethods/list.cc: Likewise.
	* testsuite/libstdc++-xmethods/vector.cc: Add tests.

From-SVN: r216145
 2014-10-13 12:23:10 +01:00
Marat Zakirov
913f32a121 asan.c (instrument_derefs): BIT_FIELD_REF added. 
gcc/ChangeLog:

2014-09-19  Marat Zakirov  <m.zakirov@samsung.com>

	* asan.c (instrument_derefs): BIT_FIELD_REF added.

gcc/testsuite/ChangeLog:

2014-09-19  Marat Zakirov  <m.zakirov@samsung.com>

	* c-c++-common/asan/bitfield-5.c: New test.

From-SVN: r216144
 2014-10-13 10:44:45 +00:00
Rüdiger Sonderfeld
2f6ca9d317 memory (align): Define. 
2014-10-13  Rüdiger Sonderfeld  <ruediger@c-plusplus.de>

	* include/std/memory (align): Define.
	* testsuite/20_util/align/1.cc: New.

From-SVN: r216143
 2014-10-13 11:05:21 +01:00
Marc Glisse
2a52738350 re PR libstdc++/61347 (std::distance(list.first(),list.end()) in O(1)) 
2014-10-13  Marc Glisse  <marc.glisse@inria.fr>

	PR libstdc++/61347
	PR libstdc++/63345
	* include/bits/list.tcc (_List_base::_M_clear()): Delay cast so it
	isn't done for the sentinel.
	* include/bits/stl_list.h (_List_base::_M_size): Move...
	(_List_base::_List_impl::_M_node): ... here.
	(_List_base::_M_get_size(), _List_base::_M_set_size(size_t),
	_List_base::_M_inc_size(size_t), _List_base::_M_dec_size(size_t),
	_List_base::_M_node_count): Adapt to the move.
	* 23_containers/list/requirements/dr438/assign_neg.cc: Update
	line number.
	* 23_containers/list/requirements/dr438/constructor_1_neg.cc: Likewise.
	* 23_containers/list/requirements/dr438/constructor_2_neg.cc: Likewise.
	* 23_containers/list/requirements/dr438/insert_neg.cc: Likewise.

From-SVN: r216142
 2014-10-13 10:00:27 +00:00
Eric Botcazou
e7da0c235e re PR ada/63225 (ada bootstrap failure when -fno-inline in STAGE1_CFLAGS) 
PR ada/63225
	* uintp.adb (Vector_To_Uint): Move from here to...
	* uintp.ads (UI_Vector): Make public.
	(Vector_To_Uint): ...here.

Co-Authored-By: Alan Modra <amodra@gmail.com>

From-SVN: r216139
 2014-10-13 08:19:45 +00:00
Richard Biener
d4f5cd5e82 re PR c++/63419 (verify_gimple failed: "vector CONSTRUCTOR element is not a GIMPLE value") 
2014-10-13  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/63419
	* gimple-fold.h (gimple_convert): New function.
	* gimple-fold.c (gimple_convert): Likewise.
	* tree-ssa-pre.c (create_expression_by_pieces): Use gimple_convert
	to split out required conversions early.

	* g++.dg/torture/pr63419.C: New testcase.

From-SVN: r216138
 2014-10-13 07:58:05 +00:00
Richard Sandiford
641123eb5e rtlanal.c (generic_subrtx_iterator <T>::add_subrtxes_to_queue): Add the parts of an insn in reverse order, with the pattern at the top of the queue. 
gcc/
	* rtlanal.c (generic_subrtx_iterator <T>::add_subrtxes_to_queue):
	Add the parts of an insn in reverse order, with the pattern at
	the top of the queue.  Detect when we're iterating over a SEQUENCE
	pattern and in that case just consider patterns of subinstructions.

From-SVN: r216137
 2014-10-13 07:05:46 +00:00
GCC Administrator
eaa89fd82a Daily bump. 
From-SVN: r216131
 2014-10-13 00:16:27 +00:00
Oleg Endo
4eac9c2b02 re PR target/59401 ([SH] GBR addressing mode optimization produces wrong code) 
gcc/
	PR target/59401
	* config/sh/sh-protos (sh_find_equiv_gbr_addr): Use rtx_insn* instead
	of rtx.
	* config/sh/sh.c (sh_find_equiv_gbr_addr): Use def chains instead of
	insn walking.
	(sh_find_equiv_gbr_addr): Do nothing if input mem is already a GBR
	address.  Use def chains to handle GBR clobbering call insns.

gcc/testsuite/
	PR target/59401
	PR target/54760
	* gcc.target/pr54760-5.c: New.
	* gcc.target/pr54760-6.c: New.
	* gcc.target/sh/pr59401-1.c: New.

From-SVN: r216128
 2014-10-12 23:14:07 +00:00
Trevor Saunders
2a22f99cb1 move many gc hashtab to hash_table 
gcc/

* asan.c, cfgloop.c, cfgloop.h, cgraph.c, cgraph.h,
	config/darwin.c, config/m32c/m32c.c, config/mep/mep.c,
	config/mips/mips.c, config/rs6000/rs6000.c, dwarf2out.c,
	function.c, function.h, gimple-ssa.h, libfuncs.h, optabs.c,
	output.h, rtl.h, sese.c, symtab.c, tree-cfg.c, tree-dfa.c,
	tree-ssa.c, varasm.c: Use hash-table instead of hashtab.
	* doc/gty.texi (for_user): Document new option.
	* gengtype.c (create_user_defined_type): Don't try to get a struct for
	char.
	(walk_type): Don't error out on for_user option.
	(write_func_for_structure): Emit user marking routines if requested by
	for_user option.
	(write_local_func_for_structure): Likewise.
	(main): Mark types with for_user option as used.
	* ggc.h (gt_pch_nx): Add overload for unsigned int.
	* hash-map.h (hash_map::hash_entry::pch_nx_helper): AddOverloads.
	* hash-table.h (ggc_hasher): New struct.
	(hash_table::create_ggc): New function.
	(gt_pch_nx): New overload for hash_table.

java/

	* class.c, decl.c, except.c, expr.c, java-tree.h, lang.c: Use
	hash_table instead of hashtab.

objc/

	* objc-act.c: use hash_table instead of hashtab.

cp/

	* cp-gimplify.c, cp-tree.h, decl.c, mangle.c, name-lookup.c,
	pt.c, semantics.c, tree.c, typeck2.c: Use hash_table instead of
	hashtab.

fortran/

	* trans-decl.c, trans.c, trans.h: Use hash_table instead of hashtab.

c-family/

	* c-common.c: Use hash_table instead of hashtab.

From-SVN: r216127
 2014-10-12 22:22:53 +00:00