2004-05-27 00:55:16 +02:00
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/*
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2007-10-29 00:42:18 +01:00
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* QEMU PowerPC CHRP (currently NewWorld PowerMac) hardware System Emulator
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2007-09-16 23:08:06 +02:00
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*
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2007-03-30 11:38:04 +02:00
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* Copyright (c) 2004-2007 Fabrice Bellard
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2007-10-29 00:42:18 +01:00
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* Copyright (c) 2007 Jocelyn Mayer
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2007-09-16 23:08:06 +02:00
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*
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2004-05-27 00:55:16 +02:00
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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2007-11-17 18:14:51 +01:00
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#include "hw.h"
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#include "ppc.h"
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2007-10-29 00:42:18 +01:00
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#include "ppc_mac.h"
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2007-11-17 18:14:51 +01:00
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#include "nvram.h"
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#include "pc.h"
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#include "pci.h"
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#include "net.h"
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#include "sysemu.h"
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#include "boards.h"
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2004-06-03 20:46:20 +02:00
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2007-12-02 05:51:10 +01:00
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#define MAX_IDE_BUS 2
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2005-06-05 17:11:17 +02:00
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/* UniN device */
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static void unin_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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}
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static uint32_t unin_readl (void *opaque, target_phys_addr_t addr)
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{
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return 0;
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}
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static CPUWriteMemoryFunc *unin_write[] = {
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&unin_writel,
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&unin_writel,
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&unin_writel,
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};
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static CPUReadMemoryFunc *unin_read[] = {
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&unin_readl,
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&unin_readl,
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&unin_readl,
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};
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2007-10-29 00:42:18 +01:00
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/* PowerPC Mac99 hardware initialisation */
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2007-10-31 02:54:04 +01:00
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static void ppc_core99_init (int ram_size, int vga_ram_size,
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const char *boot_device, DisplayState *ds,
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2007-10-29 00:42:18 +01:00
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const char *kernel_filename,
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const char *kernel_cmdline,
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const char *initrd_filename,
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const char *cpu_model)
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2004-05-27 00:55:16 +02:00
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{
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2007-11-10 16:15:54 +01:00
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CPUState *env = NULL, *envs[MAX_CPUS];
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2004-05-27 00:55:16 +02:00
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char buf[1024];
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2007-04-10 00:45:36 +02:00
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qemu_irq *pic, **openpic_irqs;
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2006-09-18 03:15:29 +02:00
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int unin_memory;
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2005-07-03 16:00:51 +02:00
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int linux_boot, i;
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unsigned long bios_offset, vga_bios_offset;
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2004-06-21 18:55:53 +02:00
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uint32_t kernel_base, kernel_size, initrd_base, initrd_size;
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2004-06-21 21:43:00 +02:00
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PCIBus *pci_bus;
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2007-10-29 00:42:18 +01:00
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nvram_t nvram;
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#if 0
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MacIONVRAMState *nvr;
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int nvram_mem_index;
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#endif
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m48t59_t *m48t59;
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2005-07-03 16:00:51 +02:00
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int vga_bios_size, bios_size;
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2007-04-07 20:14:41 +02:00
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qemu_irq *dummy_irq;
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2007-10-29 00:42:18 +01:00
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int pic_mem_index, dbdma_mem_index, cuda_mem_index;
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int ide_mem_index[2];
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2007-11-11 02:50:45 +01:00
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int ppc_boot_device;
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2007-12-02 05:51:10 +01:00
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int index;
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BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
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2004-06-21 21:43:00 +02:00
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2004-05-27 00:55:16 +02:00
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linux_boot = (kernel_filename != NULL);
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2005-11-22 00:33:12 +01:00
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/* init CPUs */
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2007-03-05 20:44:02 +01:00
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if (cpu_model == NULL)
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2007-09-29 13:51:08 +02:00
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cpu_model = "default";
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2007-04-10 00:45:36 +02:00
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for (i = 0; i < smp_cpus; i++) {
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2007-11-10 16:15:54 +01:00
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env = cpu_init(cpu_model);
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if (!env) {
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fprintf(stderr, "Unable to find PowerPC CPU definition\n");
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exit(1);
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}
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2007-04-10 00:45:36 +02:00
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/* Set time-base frequency to 100 Mhz */
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cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
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2007-10-29 00:42:18 +01:00
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#if 0
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2007-04-10 00:45:36 +02:00
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env->osi_call = vga_osi_call;
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2007-10-29 00:42:18 +01:00
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#endif
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2007-10-03 03:06:57 +02:00
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qemu_register_reset(&cpu_ppc_reset, env);
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register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
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2007-04-10 00:45:36 +02:00
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envs[i] = env;
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}
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2007-10-29 11:19:50 +01:00
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if (env->nip < 0xFFF80000) {
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/* Special test for PowerPC 601:
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* the boot vector is at 0xFFF00100, then we need a 1MB BIOS.
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* But the NVRAM is located at 0xFFF04000...
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*/
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cpu_abort(env, "Mac99 hardware can not handle 1 MB BIOS\n");
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}
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2005-11-22 00:33:12 +01:00
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2004-05-27 00:55:16 +02:00
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/* allocate RAM */
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cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
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/* allocate and load BIOS */
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bios_offset = ram_size + vga_ram_size;
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2007-10-05 15:08:35 +02:00
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if (bios_name == NULL)
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bios_name = BIOS_FILENAME;
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snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
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2005-07-03 16:00:51 +02:00
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bios_size = load_image(buf, phys_ram_base + bios_offset);
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if (bios_size < 0 || bios_size > BIOS_SIZE) {
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2007-04-19 10:42:21 +02:00
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cpu_abort(env, "qemu: could not load PowerPC bios '%s'\n", buf);
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2004-05-27 00:55:16 +02:00
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exit(1);
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}
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2005-07-03 16:00:51 +02:00
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bios_size = (bios_size + 0xfff) & ~0xfff;
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2007-10-29 11:19:50 +01:00
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if (bios_size > 0x00080000) {
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/* As the NVRAM is located at 0xFFF04000, we cannot use 1 MB BIOSes */
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cpu_abort(env, "Mac99 hardware can not handle 1 MB BIOS\n");
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}
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2007-04-19 10:42:21 +02:00
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cpu_register_physical_memory((uint32_t)(-bios_size),
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2005-07-03 16:00:51 +02:00
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bios_size, bios_offset | IO_MEM_ROM);
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2007-09-17 10:09:54 +02:00
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2005-07-03 16:00:51 +02:00
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/* allocate and load VGA BIOS */
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vga_bios_offset = bios_offset + bios_size;
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snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME);
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vga_bios_size = load_image(buf, phys_ram_base + vga_bios_offset + 8);
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if (vga_bios_size < 0) {
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/* if no bios is present, we can still work */
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fprintf(stderr, "qemu: warning: could not load VGA bios '%s'\n", buf);
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vga_bios_size = 0;
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} else {
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/* set a specific header (XXX: find real Apple format for NDRV
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drivers) */
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phys_ram_base[vga_bios_offset] = 'N';
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phys_ram_base[vga_bios_offset + 1] = 'D';
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phys_ram_base[vga_bios_offset + 2] = 'R';
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phys_ram_base[vga_bios_offset + 3] = 'V';
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2007-09-16 23:08:06 +02:00
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cpu_to_be32w((uint32_t *)(phys_ram_base + vga_bios_offset + 4),
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2005-07-03 16:00:51 +02:00
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vga_bios_size);
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vga_bios_size += 8;
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}
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vga_bios_size = (vga_bios_size + 0xfff) & ~0xfff;
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2007-09-17 10:09:54 +02:00
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2004-06-21 18:55:53 +02:00
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if (linux_boot) {
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kernel_base = KERNEL_LOAD_ADDR;
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/* now we can load the kernel */
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kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);
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if (kernel_size < 0) {
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2007-04-19 10:42:21 +02:00
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cpu_abort(env, "qemu: could not load kernel '%s'\n",
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kernel_filename);
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2004-06-21 18:55:53 +02:00
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exit(1);
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}
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/* load initrd */
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if (initrd_filename) {
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initrd_base = INITRD_LOAD_ADDR;
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initrd_size = load_image(initrd_filename,
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phys_ram_base + initrd_base);
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if (initrd_size < 0) {
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2007-04-19 10:42:21 +02:00
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cpu_abort(env, "qemu: could not load initial ram disk '%s'\n",
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initrd_filename);
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2004-06-21 18:55:53 +02:00
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exit(1);
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}
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} else {
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initrd_base = 0;
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initrd_size = 0;
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}
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2007-10-31 02:54:04 +01:00
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ppc_boot_device = 'm';
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2004-06-21 18:55:53 +02:00
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} else {
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kernel_base = 0;
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kernel_size = 0;
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initrd_base = 0;
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initrd_size = 0;
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2007-11-11 02:50:45 +01:00
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ppc_boot_device = '\0';
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/* We consider that NewWorld PowerMac never have any floppy drive
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* For now, OHW cannot boot from the network.
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*/
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2007-11-11 15:44:28 +01:00
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for (i = 0; boot_device[i] != '\0'; i++) {
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if (boot_device[i] >= 'c' && boot_device[i] <= 'f') {
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ppc_boot_device = boot_device[i];
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2007-11-11 02:50:45 +01:00
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break;
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2007-11-11 15:44:28 +01:00
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}
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2007-11-11 02:50:45 +01:00
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}
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if (ppc_boot_device == '\0') {
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fprintf(stderr, "No valid boot device for Mac99 machine\n");
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exit(1);
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}
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2004-06-21 18:55:53 +02:00
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}
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2005-06-05 17:11:17 +02:00
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2007-10-29 00:42:18 +01:00
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isa_mem_base = 0x80000000;
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2006-09-18 03:15:29 +02:00
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2007-10-29 00:42:18 +01:00
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/* Register 8 MB of ISA IO space */
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isa_mmio_init(0xf2000000, 0x00800000);
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2007-09-17 10:09:54 +02:00
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2007-10-29 00:42:18 +01:00
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/* UniN init */
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unin_memory = cpu_register_io_memory(0, unin_read, unin_write, NULL);
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cpu_register_physical_memory(0xf8000000, 0x00001000, unin_memory);
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2007-03-30 11:38:04 +02:00
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2007-10-29 00:42:18 +01:00
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openpic_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *));
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openpic_irqs[0] =
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qemu_mallocz(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
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for (i = 0; i < smp_cpus; i++) {
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/* Mac99 IRQ connection between OpenPIC outputs pins
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* and PowerPC input pins
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*/
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switch (PPC_INPUT(env)) {
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case PPC_FLAGS_INPUT_6xx:
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openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB);
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openpic_irqs[i][OPENPIC_OUTPUT_INT] =
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((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
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openpic_irqs[i][OPENPIC_OUTPUT_CINT] =
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((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
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openpic_irqs[i][OPENPIC_OUTPUT_MCK] =
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((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_MCP];
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/* Not connected ? */
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openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL;
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/* Check this */
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openpic_irqs[i][OPENPIC_OUTPUT_RESET] =
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((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_HRESET];
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break;
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2007-10-03 03:05:39 +02:00
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#if defined(TARGET_PPC64)
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2007-10-29 00:42:18 +01:00
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case PPC_FLAGS_INPUT_970:
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openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB);
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openpic_irqs[i][OPENPIC_OUTPUT_INT] =
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((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];
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openpic_irqs[i][OPENPIC_OUTPUT_CINT] =
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((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];
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openpic_irqs[i][OPENPIC_OUTPUT_MCK] =
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((qemu_irq *)env->irq_inputs)[PPC970_INPUT_MCP];
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/* Not connected ? */
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openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL;
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/* Check this */
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openpic_irqs[i][OPENPIC_OUTPUT_RESET] =
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((qemu_irq *)env->irq_inputs)[PPC970_INPUT_HRESET];
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break;
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2007-10-03 03:05:39 +02:00
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#endif /* defined(TARGET_PPC64) */
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2007-10-29 00:42:18 +01:00
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default:
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cpu_abort(env, "Bus model not supported on mac99 machine\n");
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exit(1);
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2005-06-05 17:11:17 +02:00
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}
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2007-10-29 00:42:18 +01:00
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}
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pic = openpic_init(NULL, &pic_mem_index, smp_cpus, openpic_irqs, NULL);
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pci_bus = pci_pmac_init(pic);
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/* init basic PC hardware */
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pci_vga_init(pci_bus, ds, phys_ram_base + ram_size,
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ram_size, vga_ram_size,
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vga_bios_offset, vga_bios_size);
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2007-11-24 03:56:36 +01:00
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2007-10-29 00:42:18 +01:00
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/* XXX: suppress that */
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dummy_irq = i8259_init(NULL);
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/* XXX: use Mac Serial port */
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serial_init(0x3f8, dummy_irq[4], serial_hds[0]);
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for(i = 0; i < nb_nics; i++) {
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if (!nd_table[i].model)
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nd_table[i].model = "ne2k_pci";
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pci_nic_init(pci_bus, &nd_table[i], -1);
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}
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2007-12-02 05:51:10 +01:00
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if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
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fprintf(stderr, "qemu: too many IDE bus\n");
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exit(1);
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|
}
|
|
|
|
for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
|
|
|
|
index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
|
|
|
|
if (index != -1)
|
|
|
|
hd[i] = drives_table[index].bdrv;
|
|
|
|
else
|
|
|
|
hd[i] = NULL;
|
|
|
|
}
|
2005-06-05 17:11:17 +02:00
|
|
|
#if 1
|
2007-12-02 05:51:10 +01:00
|
|
|
ide_mem_index[0] = pmac_ide_init(&hd[0], pic[0x13]);
|
|
|
|
ide_mem_index[1] = pmac_ide_init(&hd[2], pic[0x14]);
|
2005-06-05 17:11:17 +02:00
|
|
|
#else
|
2007-12-02 05:51:10 +01:00
|
|
|
pci_cmd646_ide_init(pci_bus, &hd[0], 0);
|
2005-06-05 17:11:17 +02:00
|
|
|
#endif
|
2007-10-29 00:42:18 +01:00
|
|
|
/* cuda also initialize ADB */
|
|
|
|
cuda_init(&cuda_mem_index, pic[0x19]);
|
2007-11-24 03:56:36 +01:00
|
|
|
|
2007-10-29 00:42:18 +01:00
|
|
|
adb_kbd_init(&adb_bus);
|
|
|
|
adb_mouse_init(&adb_bus);
|
2007-09-17 10:09:54 +02:00
|
|
|
|
2007-10-29 00:42:18 +01:00
|
|
|
dbdma_init(&dbdma_mem_index);
|
2007-09-17 10:09:54 +02:00
|
|
|
|
2007-10-29 00:42:18 +01:00
|
|
|
macio_init(pci_bus, 0x0022, 0, pic_mem_index, dbdma_mem_index,
|
2007-11-04 02:16:04 +01:00
|
|
|
cuda_mem_index, NULL, 2, ide_mem_index);
|
2006-05-21 18:30:15 +02:00
|
|
|
|
|
|
|
if (usb_enabled) {
|
2007-03-17 17:59:31 +01:00
|
|
|
usb_ohci_init_pci(pci_bus, 3, -1);
|
2006-05-21 18:30:15 +02:00
|
|
|
}
|
|
|
|
|
2004-06-21 18:55:53 +02:00
|
|
|
if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
|
|
|
|
graphic_depth = 15;
|
2007-10-29 00:42:18 +01:00
|
|
|
#if 0 /* XXX: this is ugly but needed for now, or OHW won't boot */
|
|
|
|
/* The NewWorld NVRAM is not located in the MacIO device */
|
2007-11-04 02:16:04 +01:00
|
|
|
nvr = macio_nvram_init(&nvram_mem_index, 0x2000);
|
2007-10-29 00:42:18 +01:00
|
|
|
pmac_format_nvram_partition(nvr, 0x2000);
|
2007-11-04 02:16:04 +01:00
|
|
|
macio_nvram_map(nvr, 0xFFF04000);
|
2007-10-29 00:42:18 +01:00
|
|
|
nvram.opaque = nvr;
|
|
|
|
nvram.read_fn = &macio_nvram_read;
|
|
|
|
nvram.write_fn = &macio_nvram_write;
|
|
|
|
#else
|
|
|
|
m48t59 = m48t59_init(dummy_irq[8], 0xFFF04000, 0x0074, NVRAM_SIZE, 59);
|
|
|
|
nvram.opaque = m48t59;
|
|
|
|
nvram.read_fn = &m48t59_read;
|
|
|
|
nvram.write_fn = &m48t59_write;
|
|
|
|
#endif
|
2007-10-31 02:54:04 +01:00
|
|
|
PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "MAC99", ram_size,
|
|
|
|
ppc_boot_device, kernel_base, kernel_size,
|
2004-06-21 18:55:53 +02:00
|
|
|
kernel_cmdline,
|
|
|
|
initrd_base, initrd_size,
|
2004-05-27 00:55:16 +02:00
|
|
|
/* XXX: need an option to load a NVRAM image */
|
2004-06-21 18:55:53 +02:00
|
|
|
0,
|
|
|
|
graphic_width, graphic_height, graphic_depth);
|
|
|
|
/* No PCI init: the BIOS will do it */
|
2005-06-05 17:11:17 +02:00
|
|
|
|
|
|
|
/* Special port to get debug messages from Open-Firmware */
|
|
|
|
register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);
|
2007-11-24 03:56:36 +01:00
|
|
|
}
|
2005-06-05 17:11:17 +02:00
|
|
|
|
|
|
|
QEMUMachine core99_machine = {
|
2005-07-03 18:00:32 +02:00
|
|
|
"mac99",
|
|
|
|
"Mac99 based PowerMAC",
|
2005-06-05 17:11:17 +02:00
|
|
|
ppc_core99_init,
|
|
|
|
};
|