2008-04-07 21:47:14 +02:00
|
|
|
/*
|
|
|
|
* QEMU MIPS Jazz support
|
|
|
|
*
|
|
|
|
* Copyright (c) 2007-2008 Hervé Poussineau
|
|
|
|
*
|
|
|
|
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
|
|
|
* of this software and associated documentation files (the "Software"), to deal
|
|
|
|
* in the Software without restriction, including without limitation the rights
|
|
|
|
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
|
|
|
* copies of the Software, and to permit persons to whom the Software is
|
|
|
|
* furnished to do so, subject to the following conditions:
|
|
|
|
*
|
|
|
|
* The above copyright notice and this permission notice shall be included in
|
|
|
|
* all copies or substantial portions of the Software.
|
|
|
|
*
|
|
|
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
|
|
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
|
|
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
|
|
|
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
|
|
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
|
|
|
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
|
|
|
* THE SOFTWARE.
|
|
|
|
*/
|
|
|
|
|
2016-01-18 18:35:00 +01:00
|
|
|
#include "qemu/osdep.h"
|
2019-05-23 16:35:08 +02:00
|
|
|
#include "qemu-common.h"
|
2013-02-05 17:06:20 +01:00
|
|
|
#include "hw/mips/mips.h"
|
|
|
|
#include "hw/mips/cpudevs.h"
|
|
|
|
#include "hw/i386/pc.h"
|
2018-03-08 23:39:23 +01:00
|
|
|
#include "hw/dma/i8257.h"
|
2013-02-05 17:06:20 +01:00
|
|
|
#include "hw/char/serial.h"
|
2018-03-08 23:39:22 +01:00
|
|
|
#include "hw/char/parallel.h"
|
2013-02-05 17:06:20 +01:00
|
|
|
#include "hw/isa/isa.h"
|
|
|
|
#include "hw/block/fdc.h"
|
2012-12-17 18:20:04 +01:00
|
|
|
#include "sysemu/sysemu.h"
|
|
|
|
#include "sysemu/arch_init.h"
|
2013-02-04 15:40:22 +01:00
|
|
|
#include "hw/boards.h"
|
2012-10-24 08:43:34 +02:00
|
|
|
#include "net/net.h"
|
2013-02-05 17:06:20 +01:00
|
|
|
#include "hw/scsi/esp.h"
|
|
|
|
#include "hw/mips/bios.h"
|
2013-02-04 15:40:22 +01:00
|
|
|
#include "hw/loader.h"
|
2019-10-04 01:03:53 +02:00
|
|
|
#include "hw/rtc/mc146818rtc.h"
|
2013-02-05 17:06:20 +01:00
|
|
|
#include "hw/timer/i8254.h"
|
2017-10-17 18:44:21 +02:00
|
|
|
#include "hw/display/vga.h"
|
2013-02-05 17:06:20 +01:00
|
|
|
#include "hw/audio/pcspk.h"
|
2018-03-08 23:39:24 +01:00
|
|
|
#include "hw/input/i8042.h"
|
2013-02-04 15:40:22 +01:00
|
|
|
#include "hw/sysbus.h"
|
2012-12-17 18:19:49 +01:00
|
|
|
#include "exec/address-spaces.h"
|
2013-07-29 16:05:32 +02:00
|
|
|
#include "sysemu/qtest.h"
|
2019-08-12 07:23:38 +02:00
|
|
|
#include "sysemu/reset.h"
|
2018-02-01 12:18:31 +01:00
|
|
|
#include "qapi/error.h"
|
2013-08-03 16:03:18 +02:00
|
|
|
#include "qemu/error-report.h"
|
2016-03-20 18:16:19 +01:00
|
|
|
#include "qemu/help_option.h"
|
2008-04-07 21:47:14 +02:00
|
|
|
|
2019-12-06 14:58:03 +01:00
|
|
|
enum jazz_model_e {
|
2008-04-07 21:47:14 +02:00
|
|
|
JAZZ_MAGNUM,
|
2008-04-08 21:51:06 +02:00
|
|
|
JAZZ_PICA61,
|
2008-04-07 21:47:14 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
static void main_cpu_reset(void *opaque)
|
|
|
|
{
|
2012-05-05 14:06:50 +02:00
|
|
|
MIPSCPU *cpu = opaque;
|
|
|
|
|
|
|
|
cpu_reset(CPU(cpu));
|
2008-04-07 21:47:14 +02:00
|
|
|
}
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static uint64_t rtc_read(void *opaque, hwaddr addr, unsigned size)
|
2008-04-07 21:47:14 +02:00
|
|
|
{
|
2015-02-01 09:12:52 +01:00
|
|
|
uint8_t val;
|
2015-04-26 17:49:24 +02:00
|
|
|
address_space_read(&address_space_memory, 0x90000071,
|
|
|
|
MEMTXATTRS_UNSPECIFIED, &val, 1);
|
2015-02-01 09:12:52 +01:00
|
|
|
return val;
|
2008-04-07 21:47:14 +02:00
|
|
|
}
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static void rtc_write(void *opaque, hwaddr addr,
|
2011-08-08 20:59:19 +02:00
|
|
|
uint64_t val, unsigned size)
|
2008-04-07 21:47:14 +02:00
|
|
|
{
|
2015-02-01 09:12:52 +01:00
|
|
|
uint8_t buf = val & 0xff;
|
2015-04-26 17:49:24 +02:00
|
|
|
address_space_write(&address_space_memory, 0x90000071,
|
|
|
|
MEMTXATTRS_UNSPECIFIED, &buf, 1);
|
2008-04-07 21:47:14 +02:00
|
|
|
}
|
|
|
|
|
2011-08-08 20:59:19 +02:00
|
|
|
static const MemoryRegionOps rtc_ops = {
|
|
|
|
.read = rtc_read,
|
|
|
|
.write = rtc_write,
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
2008-04-07 21:47:14 +02:00
|
|
|
};
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static uint64_t dma_dummy_read(void *opaque, hwaddr addr,
|
2011-08-08 20:59:19 +02:00
|
|
|
unsigned size)
|
2009-01-01 14:03:36 +01:00
|
|
|
{
|
2019-12-06 14:58:03 +01:00
|
|
|
/*
|
|
|
|
* Nothing to do. That is only to ensure that
|
|
|
|
* the current DMA acknowledge cycle is completed.
|
|
|
|
*/
|
2011-08-08 20:59:19 +02:00
|
|
|
return 0xff;
|
2009-01-01 14:03:36 +01:00
|
|
|
}
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static void dma_dummy_write(void *opaque, hwaddr addr,
|
2011-08-08 20:59:19 +02:00
|
|
|
uint64_t val, unsigned size)
|
|
|
|
{
|
2019-12-06 14:58:03 +01:00
|
|
|
/*
|
|
|
|
* Nothing to do. That is only to ensure that
|
|
|
|
* the current DMA acknowledge cycle is completed.
|
|
|
|
*/
|
2011-08-08 20:59:19 +02:00
|
|
|
}
|
2009-01-01 14:03:36 +01:00
|
|
|
|
2011-08-08 20:59:19 +02:00
|
|
|
static const MemoryRegionOps dma_dummy_ops = {
|
|
|
|
.read = dma_dummy_read,
|
|
|
|
.write = dma_dummy_write,
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
2009-01-01 14:03:36 +01:00
|
|
|
};
|
|
|
|
|
2008-04-07 21:47:14 +02:00
|
|
|
#define MAGNUM_BIOS_SIZE_MAX 0x7e000
|
2019-12-06 14:58:03 +01:00
|
|
|
#define MAGNUM_BIOS_SIZE \
|
|
|
|
(BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
|
hw/mips/mips_jazz: Override do_transaction_failed hook
The MIPS Jazz ('magnum' and 'pica61') boards have some code which
overrides the CPU's do_unassigned_access hook, so they can intercept
it and not raise exceptions on data accesses to invalid addresses,
only for instruction fetches.
We want to switch MIPS over to using the do_transaction_failed
hook instead, so add an intercept for that as well, and make
the board code install whichever hook the CPU is actually using.
Once we've changed the CPU implementation we can remove the
redundant code for the old hook.
Note: I am suspicious that the behaviour as implemented here may not
be what the hardware really does. It was added in commit
54e755588cf1e90f0b14 to restore the behaviour that was broken by
commit c658b94f6e8c206c59d. But prior to commit c658b94f6e8c206c59d
every MIPS board generated exceptions for instruction access to
invalid addresses but not for data accesses; and other boards,
notably Malta, were fixed by making all invalid accesses behave as
reads-as-zero (see the call to empty_slot_init() in
mips_malta_init()). Hardware that raises exceptions for instruction
access and not data access seems to me to be an unlikely design, and
it's possible that the right way to emulate this is to make the Jazz
boards do what we did with Malta (or some variation of that).
Nonetheless, since I don't have access to real hardware to test
against I have taken the approach of "make QEMU continue to behave
the same way it did before this commit". I have updated the comment
to correct the parts that are no longer accurate and note that
the hardware might behave differently.
The test case for the need for the hook-hijacking is in
https://bugs.launchpad.net/qemu/+bug/1245924 That BIOS will boot OK
either with this overriding of both hooks, or with a simple "global
memory region to ignore bad accesses of all types", so it doesn't
provide evidence either way, unfortunately.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Hervé Poussineau <hpoussin@reactos.org>
Message-Id: <20190802160458.25681-2-peter.maydell@linaro.org>
2019-08-02 18:04:56 +02:00
|
|
|
static void (*real_do_transaction_failed)(CPUState *cpu, hwaddr physaddr,
|
|
|
|
vaddr addr, unsigned size,
|
|
|
|
MMUAccessType access_type,
|
|
|
|
int mmu_idx, MemTxAttrs attrs,
|
|
|
|
MemTxResult response,
|
|
|
|
uintptr_t retaddr);
|
|
|
|
|
|
|
|
static void mips_jazz_do_transaction_failed(CPUState *cs, hwaddr physaddr,
|
|
|
|
vaddr addr, unsigned size,
|
|
|
|
MMUAccessType access_type,
|
|
|
|
int mmu_idx, MemTxAttrs attrs,
|
|
|
|
MemTxResult response,
|
|
|
|
uintptr_t retaddr)
|
|
|
|
{
|
|
|
|
if (access_type != MMU_INST_FETCH) {
|
|
|
|
/* ignore invalid access (ie do not raise exception) */
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
(*real_do_transaction_failed)(cs, physaddr, addr, size, access_type,
|
|
|
|
mmu_idx, attrs, response, retaddr);
|
|
|
|
}
|
|
|
|
|
2015-02-01 09:12:51 +01:00
|
|
|
static void mips_jazz_init(MachineState *machine,
|
2011-08-11 00:28:11 +02:00
|
|
|
enum jazz_model_e jazz_model)
|
2008-04-07 21:47:14 +02:00
|
|
|
{
|
2015-02-01 09:12:51 +01:00
|
|
|
MemoryRegion *address_space = get_system_memory();
|
2009-05-30 01:52:44 +02:00
|
|
|
char *filename;
|
2008-04-07 21:47:14 +02:00
|
|
|
int bios_size, n;
|
2012-05-05 14:05:42 +02:00
|
|
|
MIPSCPU *cpu;
|
2013-11-04 23:26:17 +01:00
|
|
|
CPUClass *cc;
|
2012-03-14 01:38:23 +01:00
|
|
|
CPUMIPSState *env;
|
2015-06-03 22:45:41 +02:00
|
|
|
qemu_irq *i8259;
|
2009-01-01 14:03:36 +01:00
|
|
|
rc4030_dma *dmas;
|
2017-07-11 05:56:19 +02:00
|
|
|
IOMMUMemoryRegion *rc4030_dma_mr;
|
2015-02-01 09:12:52 +01:00
|
|
|
MemoryRegion *isa_mem = g_new(MemoryRegion, 1);
|
|
|
|
MemoryRegion *isa_io = g_new(MemoryRegion, 1);
|
2011-08-08 20:59:19 +02:00
|
|
|
MemoryRegion *rtc = g_new(MemoryRegion, 1);
|
2011-08-11 00:28:17 +02:00
|
|
|
MemoryRegion *i8042 = g_new(MemoryRegion, 1);
|
2011-08-08 20:59:19 +02:00
|
|
|
MemoryRegion *dma_dummy = g_new(MemoryRegion, 1);
|
2009-04-15 16:57:54 +02:00
|
|
|
NICInfo *nd;
|
2015-06-03 22:45:41 +02:00
|
|
|
DeviceState *dev, *rc4030;
|
2011-07-18 23:34:22 +02:00
|
|
|
SysBusDevice *sysbus;
|
2011-12-15 22:09:51 +01:00
|
|
|
ISABus *isa_bus;
|
2011-02-13 20:54:40 +01:00
|
|
|
ISADevice *pit;
|
2009-09-22 13:53:18 +02:00
|
|
|
DriveInfo *fds[MAX_FD];
|
2011-08-08 20:59:19 +02:00
|
|
|
MemoryRegion *ram = g_new(MemoryRegion, 1);
|
|
|
|
MemoryRegion *bios = g_new(MemoryRegion, 1);
|
|
|
|
MemoryRegion *bios2 = g_new(MemoryRegion, 1);
|
2018-06-13 11:47:26 +02:00
|
|
|
SysBusESPState *sysbus_esp;
|
2018-03-07 10:24:04 +01:00
|
|
|
ESPState *esp;
|
2008-04-07 21:47:14 +02:00
|
|
|
|
|
|
|
/* init CPUs */
|
2017-10-05 15:51:12 +02:00
|
|
|
cpu = MIPS_CPU(cpu_create(machine->cpu_type));
|
2012-05-05 14:05:42 +02:00
|
|
|
env = &cpu->env;
|
2012-05-05 14:06:50 +02:00
|
|
|
qemu_register_reset(main_cpu_reset, cpu);
|
2008-04-07 21:47:14 +02:00
|
|
|
|
hw/mips/mips_jazz: Override do_transaction_failed hook
The MIPS Jazz ('magnum' and 'pica61') boards have some code which
overrides the CPU's do_unassigned_access hook, so they can intercept
it and not raise exceptions on data accesses to invalid addresses,
only for instruction fetches.
We want to switch MIPS over to using the do_transaction_failed
hook instead, so add an intercept for that as well, and make
the board code install whichever hook the CPU is actually using.
Once we've changed the CPU implementation we can remove the
redundant code for the old hook.
Note: I am suspicious that the behaviour as implemented here may not
be what the hardware really does. It was added in commit
54e755588cf1e90f0b14 to restore the behaviour that was broken by
commit c658b94f6e8c206c59d. But prior to commit c658b94f6e8c206c59d
every MIPS board generated exceptions for instruction access to
invalid addresses but not for data accesses; and other boards,
notably Malta, were fixed by making all invalid accesses behave as
reads-as-zero (see the call to empty_slot_init() in
mips_malta_init()). Hardware that raises exceptions for instruction
access and not data access seems to me to be an unlikely design, and
it's possible that the right way to emulate this is to make the Jazz
boards do what we did with Malta (or some variation of that).
Nonetheless, since I don't have access to real hardware to test
against I have taken the approach of "make QEMU continue to behave
the same way it did before this commit". I have updated the comment
to correct the parts that are no longer accurate and note that
the hardware might behave differently.
The test case for the need for the hook-hijacking is in
https://bugs.launchpad.net/qemu/+bug/1245924 That BIOS will boot OK
either with this overriding of both hooks, or with a simple "global
memory region to ignore bad accesses of all types", so it doesn't
provide evidence either way, unfortunately.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Hervé Poussineau <hpoussin@reactos.org>
Message-Id: <20190802160458.25681-2-peter.maydell@linaro.org>
2019-08-02 18:04:56 +02:00
|
|
|
/*
|
|
|
|
* Chipset returns 0 in invalid reads and do not raise data exceptions.
|
2013-11-04 23:26:17 +01:00
|
|
|
* However, we can't simply add a global memory region to catch
|
hw/mips/mips_jazz: Override do_transaction_failed hook
The MIPS Jazz ('magnum' and 'pica61') boards have some code which
overrides the CPU's do_unassigned_access hook, so they can intercept
it and not raise exceptions on data accesses to invalid addresses,
only for instruction fetches.
We want to switch MIPS over to using the do_transaction_failed
hook instead, so add an intercept for that as well, and make
the board code install whichever hook the CPU is actually using.
Once we've changed the CPU implementation we can remove the
redundant code for the old hook.
Note: I am suspicious that the behaviour as implemented here may not
be what the hardware really does. It was added in commit
54e755588cf1e90f0b14 to restore the behaviour that was broken by
commit c658b94f6e8c206c59d. But prior to commit c658b94f6e8c206c59d
every MIPS board generated exceptions for instruction access to
invalid addresses but not for data accesses; and other boards,
notably Malta, were fixed by making all invalid accesses behave as
reads-as-zero (see the call to empty_slot_init() in
mips_malta_init()). Hardware that raises exceptions for instruction
access and not data access seems to me to be an unlikely design, and
it's possible that the right way to emulate this is to make the Jazz
boards do what we did with Malta (or some variation of that).
Nonetheless, since I don't have access to real hardware to test
against I have taken the approach of "make QEMU continue to behave
the same way it did before this commit". I have updated the comment
to correct the parts that are no longer accurate and note that
the hardware might behave differently.
The test case for the need for the hook-hijacking is in
https://bugs.launchpad.net/qemu/+bug/1245924 That BIOS will boot OK
either with this overriding of both hooks, or with a simple "global
memory region to ignore bad accesses of all types", so it doesn't
provide evidence either way, unfortunately.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Hervé Poussineau <hpoussin@reactos.org>
Message-Id: <20190802160458.25681-2-peter.maydell@linaro.org>
2019-08-02 18:04:56 +02:00
|
|
|
* everything, as this would make all accesses including instruction
|
|
|
|
* accesses be ignored and not raise exceptions.
|
2019-08-02 18:04:58 +02:00
|
|
|
* So instead we hijack the do_transaction_failed method on the CPU, and
|
|
|
|
* do not raise exceptions for data access.
|
hw/mips/mips_jazz: Override do_transaction_failed hook
The MIPS Jazz ('magnum' and 'pica61') boards have some code which
overrides the CPU's do_unassigned_access hook, so they can intercept
it and not raise exceptions on data accesses to invalid addresses,
only for instruction fetches.
We want to switch MIPS over to using the do_transaction_failed
hook instead, so add an intercept for that as well, and make
the board code install whichever hook the CPU is actually using.
Once we've changed the CPU implementation we can remove the
redundant code for the old hook.
Note: I am suspicious that the behaviour as implemented here may not
be what the hardware really does. It was added in commit
54e755588cf1e90f0b14 to restore the behaviour that was broken by
commit c658b94f6e8c206c59d. But prior to commit c658b94f6e8c206c59d
every MIPS board generated exceptions for instruction access to
invalid addresses but not for data accesses; and other boards,
notably Malta, were fixed by making all invalid accesses behave as
reads-as-zero (see the call to empty_slot_init() in
mips_malta_init()). Hardware that raises exceptions for instruction
access and not data access seems to me to be an unlikely design, and
it's possible that the right way to emulate this is to make the Jazz
boards do what we did with Malta (or some variation of that).
Nonetheless, since I don't have access to real hardware to test
against I have taken the approach of "make QEMU continue to behave
the same way it did before this commit". I have updated the comment
to correct the parts that are no longer accurate and note that
the hardware might behave differently.
The test case for the need for the hook-hijacking is in
https://bugs.launchpad.net/qemu/+bug/1245924 That BIOS will boot OK
either with this overriding of both hooks, or with a simple "global
memory region to ignore bad accesses of all types", so it doesn't
provide evidence either way, unfortunately.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Hervé Poussineau <hpoussin@reactos.org>
Message-Id: <20190802160458.25681-2-peter.maydell@linaro.org>
2019-08-02 18:04:56 +02:00
|
|
|
*
|
|
|
|
* NOTE: this behaviour of raising exceptions for bad instruction
|
|
|
|
* fetches but not bad data accesses was added in commit 54e755588cf1e9
|
|
|
|
* to restore behaviour broken by c658b94f6e8c206, but it is not clear
|
|
|
|
* whether the real hardware behaves this way. It is possible that
|
|
|
|
* real hardware ignores bad instruction fetches as well -- if so then
|
|
|
|
* we could replace this hijacking of CPU methods with a simple global
|
|
|
|
* memory region that catches all memory accesses, as we do on Malta.
|
|
|
|
*/
|
2013-11-04 23:26:17 +01:00
|
|
|
cc = CPU_GET_CLASS(cpu);
|
2019-08-02 18:04:58 +02:00
|
|
|
real_do_transaction_failed = cc->do_transaction_failed;
|
|
|
|
cc->do_transaction_failed = mips_jazz_do_transaction_failed;
|
2013-11-04 23:26:17 +01:00
|
|
|
|
2008-04-07 21:47:14 +02:00
|
|
|
/* allocate RAM */
|
2015-03-24 22:28:15 +01:00
|
|
|
memory_region_allocate_system_memory(ram, NULL, "mips_jazz.ram",
|
|
|
|
machine->ram_size);
|
2011-08-08 20:59:19 +02:00
|
|
|
memory_region_add_subregion(address_space, 0, ram);
|
2009-04-09 22:05:49 +02:00
|
|
|
|
2017-07-07 16:42:53 +02:00
|
|
|
memory_region_init_ram(bios, NULL, "mips_jazz.bios", MAGNUM_BIOS_SIZE,
|
Fix bad error handling after memory_region_init_ram()
Symptom:
$ qemu-system-x86_64 -m 10000000
Unexpected error in ram_block_add() at /work/armbru/qemu/exec.c:1456:
upstream-qemu: cannot set up guest memory 'pc.ram': Cannot allocate memory
Aborted (core dumped)
Root cause: commit ef701d7 screwed up handling of out-of-memory
conditions. Before the commit, we report the error and exit(1), in
one place, ram_block_add(). The commit lifts the error handling up
the call chain some, to three places. Fine. Except it uses
&error_abort in these places, changing the behavior from exit(1) to
abort(), and thus undoing the work of commit 3922825 "exec: Don't
abort when we can't allocate guest memory".
The three places are:
* memory_region_init_ram()
Commit 4994653 (right after commit ef701d7) lifted the error
handling further, through memory_region_init_ram(), multiplying the
incorrect use of &error_abort. Later on, imitation of existing
(bad) code may have created more.
* memory_region_init_ram_ptr()
The &error_abort is still there.
* memory_region_init_rom_device()
Doesn't need fixing, because commit 33e0eb5 (soon after commit
ef701d7) lifted the error handling further, and in the process
changed it from &error_abort to passing it up the call chain.
Correct, because the callers are realize() methods.
Fix the error handling after memory_region_init_ram() with a
Coccinelle semantic patch:
@r@
expression mr, owner, name, size, err;
position p;
@@
memory_region_init_ram(mr, owner, name, size,
(
- &error_abort
+ &error_fatal
|
err@p
)
);
@script:python@
p << r.p;
@@
print "%s:%s:%s" % (p[0].file, p[0].line, p[0].column)
When the last argument is &error_abort, it gets replaced by
&error_fatal. This is the fix.
If the last argument is anything else, its position is reported. This
lets us check the fix is complete. Four positions get reported:
* ram_backend_memory_alloc()
Error is passed up the call chain, ultimately through
user_creatable_complete(). As far as I can tell, it's callers all
handle the error sanely.
* fsl_imx25_realize(), fsl_imx31_realize(), dp8393x_realize()
DeviceClass.realize() methods, errors handled sanely further up the
call chain.
We're good. Test case again behaves:
$ qemu-system-x86_64 -m 10000000
qemu-system-x86_64: cannot set up guest memory 'pc.ram': Cannot allocate memory
[Exit 1 ]
The next commits will repair the rest of commit ef701d7's damage.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <1441983105-26376-3-git-send-email-armbru@redhat.com>
Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
2015-09-11 16:51:43 +02:00
|
|
|
&error_fatal);
|
2011-08-08 20:59:19 +02:00
|
|
|
memory_region_set_readonly(bios, true);
|
2013-06-06 11:41:28 +02:00
|
|
|
memory_region_init_alias(bios2, NULL, "mips_jazz.bios", bios,
|
2011-08-08 20:59:19 +02:00
|
|
|
0, MAGNUM_BIOS_SIZE);
|
|
|
|
memory_region_add_subregion(address_space, 0x1fc00000LL, bios);
|
|
|
|
memory_region_add_subregion(address_space, 0xfff00000LL, bios2);
|
2008-04-07 21:47:14 +02:00
|
|
|
|
|
|
|
/* load the BIOS image. */
|
2019-12-06 14:58:03 +01:00
|
|
|
if (bios_name == NULL) {
|
2009-01-01 14:03:36 +01:00
|
|
|
bios_name = BIOS_FILENAME;
|
2019-12-06 14:58:03 +01:00
|
|
|
}
|
2009-05-30 01:52:44 +02:00
|
|
|
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
|
|
|
|
if (filename) {
|
|
|
|
bios_size = load_image_targphys(filename, 0xfff00000LL,
|
|
|
|
MAGNUM_BIOS_SIZE);
|
2011-08-21 05:09:37 +02:00
|
|
|
g_free(filename);
|
2009-05-30 01:52:44 +02:00
|
|
|
} else {
|
|
|
|
bios_size = -1;
|
|
|
|
}
|
2013-07-29 16:05:32 +02:00
|
|
|
if ((bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) && !qtest_enabled()) {
|
2013-08-03 16:03:18 +02:00
|
|
|
error_report("Could not load MIPS bios '%s'", bios_name);
|
|
|
|
exit(1);
|
2008-04-07 21:47:14 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Init CPU internal devices */
|
2016-03-15 14:32:19 +01:00
|
|
|
cpu_mips_irq_init_cpu(cpu);
|
|
|
|
cpu_mips_clock_init(cpu);
|
2008-04-07 21:47:14 +02:00
|
|
|
|
|
|
|
/* Chipset */
|
2015-06-03 22:45:41 +02:00
|
|
|
rc4030 = rc4030_init(&dmas, &rc4030_dma_mr);
|
|
|
|
sysbus = SYS_BUS_DEVICE(rc4030);
|
|
|
|
sysbus_connect_irq(sysbus, 0, env->irq[6]);
|
|
|
|
sysbus_connect_irq(sysbus, 1, env->irq[3]);
|
|
|
|
memory_region_add_subregion(address_space, 0x80000000,
|
|
|
|
sysbus_mmio_get_region(sysbus, 0));
|
|
|
|
memory_region_add_subregion(address_space, 0xf0000000,
|
|
|
|
sysbus_mmio_get_region(sysbus, 1));
|
2019-12-06 14:58:03 +01:00
|
|
|
memory_region_init_io(dma_dummy, NULL, &dma_dummy_ops,
|
|
|
|
NULL, "dummy_dma", 0x1000);
|
2011-08-08 20:59:19 +02:00
|
|
|
memory_region_add_subregion(address_space, 0x8000d000, dma_dummy);
|
2008-04-07 21:47:14 +02:00
|
|
|
|
2015-02-01 09:12:52 +01:00
|
|
|
/* ISA bus: IO space at 0x90000000, mem space at 0x91000000 */
|
|
|
|
memory_region_init(isa_io, NULL, "isa-io", 0x00010000);
|
|
|
|
memory_region_init(isa_mem, NULL, "isa-mem", 0x01000000);
|
|
|
|
memory_region_add_subregion(address_space, 0x90000000, isa_io);
|
|
|
|
memory_region_add_subregion(address_space, 0x91000000, isa_mem);
|
isa: Clean up error handling around isa_bus_new()
We can have at most one ISA bus. If you try to create another one,
isa_bus_new() complains to stderr and returns null.
isa_bus_new() is called in two contexts, machine's init() and device's
realize() methods. Since complaining to stderr is not proper in the
latter context, convert isa_bus_new() to Error.
Machine's init():
* mips_jazz_init(), called from the init() methods of machines
"magnum" and "pica"
* mips_r4k_init(), the init() method of machine "mips"
* pc_init1() called from the init() methods of non-q35 PC machines
* typhoon_init(), called from clipper_init(), the init() method of
machine "clipper"
These callers always create the first ISA bus, hence isa_bus_new()
can't fail. Simply pass &error_abort.
Device's realize():
* i82378_realize(), of PCI device "i82378"
* ich9_lpc_realize(), of PCI device "ICH9-LPC"
* pci_ebus_realize(), of PCI device "ebus"
* piix3_realize(), of PCI device "pci-piix3", abstract parent of
"PIIX3" and "PIIX3-xen"
* piix4_realize(), of PCI device "PIIX4"
* vt82c686b_realize(), of PCI device "VT82C686B"
Propagate the error. Note that these devices are typically created
only by machine init() methods with qdev_init_nofail() or similar. If
we screwed up and created an ISA bus before that call, we now give up
right away. Before, we'd hobble on, and typically die in
isa_bus_irqs(). Similar if someone finds a way to hot-plug one of
these critters.
Cc: Richard Henderson <rth@twiddle.net>
Cc: "Michael S. Tsirkin" <mst@redhat.com>
Cc: "Hervé Poussineau" <hpoussin@reactos.org>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Markus Armbruster <armbru@pond.sub.org>
Reviewed-by: Marcel Apfelbaum <marcel@redhat.com>
Reviewed-by: Hervé Poussineau <hpoussin@reactos.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <1450370121-5768-11-git-send-email-armbru@redhat.com>
2015-12-17 17:35:18 +01:00
|
|
|
isa_bus = isa_bus_new(NULL, isa_mem, isa_io, &error_abort);
|
2015-02-01 09:12:52 +01:00
|
|
|
|
2008-04-07 21:47:14 +02:00
|
|
|
/* ISA devices */
|
2011-12-15 22:09:51 +01:00
|
|
|
i8259 = i8259_init(isa_bus, env->irq[4]);
|
|
|
|
isa_bus_irqs(isa_bus, i8259);
|
2018-03-08 23:39:23 +01:00
|
|
|
i8257_dma_init(isa_bus, 0);
|
2017-10-17 18:44:15 +02:00
|
|
|
pit = i8254_pit_init(isa_bus, 0x40, 0, NULL);
|
2012-02-17 11:24:34 +01:00
|
|
|
pcspk_init(isa_bus, pit);
|
2008-04-07 21:47:14 +02:00
|
|
|
|
|
|
|
/* Video card */
|
|
|
|
switch (jazz_model) {
|
|
|
|
case JAZZ_MAGNUM:
|
2011-08-26 21:20:12 +02:00
|
|
|
dev = qdev_create(NULL, "sysbus-g364");
|
|
|
|
qdev_init_nofail(dev);
|
2013-01-20 02:47:33 +01:00
|
|
|
sysbus = SYS_BUS_DEVICE(dev);
|
2011-08-26 21:20:12 +02:00
|
|
|
sysbus_mmio_map(sysbus, 0, 0x60080000);
|
|
|
|
sysbus_mmio_map(sysbus, 1, 0x40000000);
|
2015-06-03 22:45:41 +02:00
|
|
|
sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 3));
|
2011-08-26 21:20:12 +02:00
|
|
|
{
|
|
|
|
/* Simple ROM, so user doesn't have to provide one */
|
2011-08-08 20:59:19 +02:00
|
|
|
MemoryRegion *rom_mr = g_new(MemoryRegion, 1);
|
2017-07-07 16:42:53 +02:00
|
|
|
memory_region_init_ram(rom_mr, NULL, "g364fb.rom", 0x80000,
|
Fix bad error handling after memory_region_init_ram()
Symptom:
$ qemu-system-x86_64 -m 10000000
Unexpected error in ram_block_add() at /work/armbru/qemu/exec.c:1456:
upstream-qemu: cannot set up guest memory 'pc.ram': Cannot allocate memory
Aborted (core dumped)
Root cause: commit ef701d7 screwed up handling of out-of-memory
conditions. Before the commit, we report the error and exit(1), in
one place, ram_block_add(). The commit lifts the error handling up
the call chain some, to three places. Fine. Except it uses
&error_abort in these places, changing the behavior from exit(1) to
abort(), and thus undoing the work of commit 3922825 "exec: Don't
abort when we can't allocate guest memory".
The three places are:
* memory_region_init_ram()
Commit 4994653 (right after commit ef701d7) lifted the error
handling further, through memory_region_init_ram(), multiplying the
incorrect use of &error_abort. Later on, imitation of existing
(bad) code may have created more.
* memory_region_init_ram_ptr()
The &error_abort is still there.
* memory_region_init_rom_device()
Doesn't need fixing, because commit 33e0eb5 (soon after commit
ef701d7) lifted the error handling further, and in the process
changed it from &error_abort to passing it up the call chain.
Correct, because the callers are realize() methods.
Fix the error handling after memory_region_init_ram() with a
Coccinelle semantic patch:
@r@
expression mr, owner, name, size, err;
position p;
@@
memory_region_init_ram(mr, owner, name, size,
(
- &error_abort
+ &error_fatal
|
err@p
)
);
@script:python@
p << r.p;
@@
print "%s:%s:%s" % (p[0].file, p[0].line, p[0].column)
When the last argument is &error_abort, it gets replaced by
&error_fatal. This is the fix.
If the last argument is anything else, its position is reported. This
lets us check the fix is complete. Four positions get reported:
* ram_backend_memory_alloc()
Error is passed up the call chain, ultimately through
user_creatable_complete(). As far as I can tell, it's callers all
handle the error sanely.
* fsl_imx25_realize(), fsl_imx31_realize(), dp8393x_realize()
DeviceClass.realize() methods, errors handled sanely further up the
call chain.
We're good. Test case again behaves:
$ qemu-system-x86_64 -m 10000000
qemu-system-x86_64: cannot set up guest memory 'pc.ram': Cannot allocate memory
[Exit 1 ]
The next commits will repair the rest of commit ef701d7's damage.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <1441983105-26376-3-git-send-email-armbru@redhat.com>
Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
2015-09-11 16:51:43 +02:00
|
|
|
&error_fatal);
|
2011-08-08 20:59:19 +02:00
|
|
|
memory_region_set_readonly(rom_mr, true);
|
|
|
|
uint8_t *rom = memory_region_get_ram_ptr(rom_mr);
|
|
|
|
memory_region_add_subregion(address_space, 0x60000000, rom_mr);
|
2011-08-26 21:20:12 +02:00
|
|
|
rom[0] = 0x10; /* Mips G364 */
|
|
|
|
}
|
2008-04-07 21:47:14 +02:00
|
|
|
break;
|
2008-04-08 21:51:06 +02:00
|
|
|
case JAZZ_PICA61:
|
2011-08-15 16:17:37 +02:00
|
|
|
isa_vga_mm_init(0x40000000, 0x60000000, 0, get_system_memory());
|
2008-04-08 21:51:06 +02:00
|
|
|
break;
|
2008-04-07 21:47:14 +02:00
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Network controller */
|
2009-04-15 16:57:54 +02:00
|
|
|
for (n = 0; n < nb_nics; n++) {
|
|
|
|
nd = &nd_table[n];
|
2019-12-06 14:58:03 +01:00
|
|
|
if (!nd->model) {
|
2011-08-21 05:09:37 +02:00
|
|
|
nd->model = g_strdup("dp83932");
|
2019-12-06 14:58:03 +01:00
|
|
|
}
|
2009-04-15 16:57:54 +02:00
|
|
|
if (strcmp(nd->model, "dp83932") == 0) {
|
2015-06-03 22:45:45 +02:00
|
|
|
qemu_check_nic_model(nd, "dp83932");
|
|
|
|
|
|
|
|
dev = qdev_create(NULL, "dp8393x");
|
|
|
|
qdev_set_nic_properties(dev, nd);
|
|
|
|
qdev_prop_set_uint8(dev, "it_shift", 2);
|
|
|
|
qdev_prop_set_ptr(dev, "dma_mr", rc4030_dma_mr);
|
|
|
|
qdev_init_nofail(dev);
|
|
|
|
sysbus = SYS_BUS_DEVICE(dev);
|
|
|
|
sysbus_mmio_map(sysbus, 0, 0x80001000);
|
2015-06-03 22:45:46 +02:00
|
|
|
sysbus_mmio_map(sysbus, 1, 0x8000b000);
|
2015-06-03 22:45:45 +02:00
|
|
|
sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 4));
|
2009-04-15 16:57:54 +02:00
|
|
|
break;
|
2012-08-02 14:45:54 +02:00
|
|
|
} else if (is_help_option(nd->model)) {
|
hw/mips: Replace fprintf(stderr, "*\n" with error_report()
Replace a large number of the fprintf(stderr, "*\n" calls with
error_report(). The functions were renamed with these commands and then
compiler issues where manually fixed.
find ./* -type f -exec sed -i \
'N;N;N;N;N;N;N;N;N;N;N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N;N;N;N;N;N;N;N;N;N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N;N;N;N;N;N;N;N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N;N;N;N;N;N;N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N;N;N;N;N;N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N;N;N;N;N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N;N;N;N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N;N;N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N;N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
Some lines where then manually tweaked to pass checkpatch.
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Yongbok Kim <yongbok.kim@imgtec.com>
Cc: "Hervé Poussineau" <hpoussin@reactos.org>
Conversions that aren't followed by exit() dropped, because they might
be inappropriate.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20180203084315.20497-6-armbru@redhat.com>
2018-02-03 09:43:06 +01:00
|
|
|
error_report("Supported NICs: dp83932");
|
2009-04-15 16:57:54 +02:00
|
|
|
exit(1);
|
|
|
|
} else {
|
hw/mips: Replace fprintf(stderr, "*\n" with error_report()
Replace a large number of the fprintf(stderr, "*\n" calls with
error_report(). The functions were renamed with these commands and then
compiler issues where manually fixed.
find ./* -type f -exec sed -i \
'N;N;N;N;N;N;N;N;N;N;N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N;N;N;N;N;N;N;N;N;N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N;N;N;N;N;N;N;N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N;N;N;N;N;N;N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N;N;N;N;N;N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N;N;N;N;N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N;N;N;N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N;N;N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N;N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
Some lines where then manually tweaked to pass checkpatch.
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Yongbok Kim <yongbok.kim@imgtec.com>
Cc: "Hervé Poussineau" <hpoussin@reactos.org>
Conversions that aren't followed by exit() dropped, because they might
be inappropriate.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20180203084315.20497-6-armbru@redhat.com>
2018-02-03 09:43:06 +01:00
|
|
|
error_report("Unsupported NIC: %s", nd->model);
|
2009-04-15 16:57:54 +02:00
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
}
|
2008-04-07 21:47:14 +02:00
|
|
|
|
|
|
|
/* SCSI adapter */
|
2018-06-13 11:47:26 +02:00
|
|
|
dev = qdev_create(NULL, TYPE_ESP);
|
|
|
|
sysbus_esp = ESP_STATE(dev);
|
|
|
|
esp = &sysbus_esp->esp;
|
|
|
|
esp->dma_memory_read = rc4030_dma_read;
|
|
|
|
esp->dma_memory_write = rc4030_dma_write;
|
|
|
|
esp->dma_opaque = dmas[0];
|
|
|
|
sysbus_esp->it_shift = 0;
|
|
|
|
/* XXX for now until rc4030 has been changed to use DMA enable signal */
|
|
|
|
esp->dma_enabled = 1;
|
|
|
|
qdev_init_nofail(dev);
|
|
|
|
|
|
|
|
sysbus = SYS_BUS_DEVICE(dev);
|
|
|
|
sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 5));
|
|
|
|
sysbus_mmio_map(sysbus, 0, 0x80002000);
|
|
|
|
|
2018-03-07 10:24:04 +01:00
|
|
|
scsi_bus_legacy_handle_cmdline(&esp->bus);
|
2008-04-07 21:47:14 +02:00
|
|
|
|
|
|
|
/* Floppy */
|
|
|
|
for (n = 0; n < MAX_FD; n++) {
|
2009-09-22 13:53:18 +02:00
|
|
|
fds[n] = drive_get(IF_FLOPPY, 0, n);
|
2008-04-07 21:47:14 +02:00
|
|
|
}
|
2016-02-03 17:28:57 +01:00
|
|
|
/* FIXME: we should enable DMA with a custom IsaDma device */
|
|
|
|
fdctrl_init_sysbus(qdev_get_gpio_in(rc4030, 1), -1, 0x80003000, fds);
|
2008-04-07 21:47:14 +02:00
|
|
|
|
|
|
|
/* Real time clock */
|
2017-10-17 18:44:16 +02:00
|
|
|
mc146818_rtc_init(isa_bus, 1980, NULL);
|
2013-06-06 11:41:28 +02:00
|
|
|
memory_region_init_io(rtc, NULL, &rtc_ops, NULL, "rtc", 0x1000);
|
2011-08-08 20:59:19 +02:00
|
|
|
memory_region_add_subregion(address_space, 0x80004000, rtc);
|
2008-04-07 21:47:14 +02:00
|
|
|
|
|
|
|
/* Keyboard (i8042) */
|
2015-06-03 22:45:41 +02:00
|
|
|
i8042_mm_init(qdev_get_gpio_in(rc4030, 6), qdev_get_gpio_in(rc4030, 7),
|
|
|
|
i8042, 0x1000, 0x1);
|
2011-08-11 00:28:17 +02:00
|
|
|
memory_region_add_subregion(address_space, 0x80005000, i8042);
|
2008-04-07 21:47:14 +02:00
|
|
|
|
|
|
|
/* Serial ports */
|
2018-04-20 16:52:43 +02:00
|
|
|
if (serial_hd(0)) {
|
2015-06-03 22:45:41 +02:00
|
|
|
serial_mm_init(address_space, 0x80006000, 0,
|
2019-12-06 14:58:03 +01:00
|
|
|
qdev_get_gpio_in(rc4030, 8), 8000000 / 16,
|
2018-04-20 16:52:43 +02:00
|
|
|
serial_hd(0), DEVICE_NATIVE_ENDIAN);
|
2010-03-21 20:47:11 +01:00
|
|
|
}
|
2018-04-20 16:52:43 +02:00
|
|
|
if (serial_hd(1)) {
|
2015-06-03 22:45:41 +02:00
|
|
|
serial_mm_init(address_space, 0x80007000, 0,
|
2019-12-06 14:58:03 +01:00
|
|
|
qdev_get_gpio_in(rc4030, 9), 8000000 / 16,
|
2018-04-20 16:52:43 +02:00
|
|
|
serial_hd(1), DEVICE_NATIVE_ENDIAN);
|
2010-03-21 20:47:11 +01:00
|
|
|
}
|
2008-04-07 21:47:14 +02:00
|
|
|
|
|
|
|
/* Parallel port */
|
|
|
|
if (parallel_hds[0])
|
2015-06-03 22:45:41 +02:00
|
|
|
parallel_mm_init(address_space, 0x80008000, 0,
|
|
|
|
qdev_get_gpio_in(rc4030, 0), parallel_hds[0]);
|
2008-04-07 21:47:14 +02:00
|
|
|
|
|
|
|
/* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */
|
|
|
|
|
2011-07-18 23:34:22 +02:00
|
|
|
/* NVRAM */
|
|
|
|
dev = qdev_create(NULL, "ds1225y");
|
|
|
|
qdev_init_nofail(dev);
|
2013-01-20 02:47:33 +01:00
|
|
|
sysbus = SYS_BUS_DEVICE(dev);
|
2011-07-18 23:34:22 +02:00
|
|
|
sysbus_mmio_map(sysbus, 0, 0x80009000);
|
2008-04-07 21:47:14 +02:00
|
|
|
|
|
|
|
/* LED indicator */
|
2012-02-17 20:27:16 +01:00
|
|
|
sysbus_create_simple("jazz-led", 0x8000f000, NULL);
|
2019-10-01 15:36:25 +02:00
|
|
|
|
|
|
|
g_free(dmas);
|
2008-04-07 21:47:14 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static
|
2014-05-07 16:42:57 +02:00
|
|
|
void mips_magnum_init(MachineState *machine)
|
2008-04-07 21:47:14 +02:00
|
|
|
{
|
2015-02-01 09:12:51 +01:00
|
|
|
mips_jazz_init(machine, JAZZ_MAGNUM);
|
2008-04-07 21:47:14 +02:00
|
|
|
}
|
|
|
|
|
2008-04-08 21:51:06 +02:00
|
|
|
static
|
2014-05-07 16:42:57 +02:00
|
|
|
void mips_pica61_init(MachineState *machine)
|
2008-04-08 21:51:06 +02:00
|
|
|
{
|
2015-02-01 09:12:51 +01:00
|
|
|
mips_jazz_init(machine, JAZZ_PICA61);
|
2008-04-08 21:51:06 +02:00
|
|
|
}
|
|
|
|
|
2015-09-19 10:49:44 +02:00
|
|
|
static void mips_magnum_class_init(ObjectClass *oc, void *data)
|
2015-09-04 20:37:08 +02:00
|
|
|
{
|
2015-09-19 10:49:44 +02:00
|
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
|
2015-09-04 20:37:08 +02:00
|
|
|
mc->desc = "MIPS Magnum";
|
|
|
|
mc->init = mips_magnum_init;
|
|
|
|
mc->block_default_type = IF_SCSI;
|
2017-10-05 15:51:12 +02:00
|
|
|
mc->default_cpu_type = MIPS_CPU_TYPE_NAME("R4000");
|
2015-09-04 20:37:08 +02:00
|
|
|
}
|
2008-04-08 21:51:06 +02:00
|
|
|
|
2015-09-19 10:49:44 +02:00
|
|
|
static const TypeInfo mips_magnum_type = {
|
|
|
|
.name = MACHINE_TYPE_NAME("magnum"),
|
|
|
|
.parent = TYPE_MACHINE,
|
|
|
|
.class_init = mips_magnum_class_init,
|
|
|
|
};
|
2009-05-21 01:38:09 +02:00
|
|
|
|
2015-09-19 10:49:44 +02:00
|
|
|
static void mips_pica61_class_init(ObjectClass *oc, void *data)
|
2009-05-21 01:38:09 +02:00
|
|
|
{
|
2015-09-19 10:49:44 +02:00
|
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
|
2015-09-04 20:37:08 +02:00
|
|
|
mc->desc = "Acer Pica 61";
|
|
|
|
mc->init = mips_pica61_init;
|
|
|
|
mc->block_default_type = IF_SCSI;
|
2017-10-05 15:51:12 +02:00
|
|
|
mc->default_cpu_type = MIPS_CPU_TYPE_NAME("R4000");
|
2009-05-21 01:38:09 +02:00
|
|
|
}
|
|
|
|
|
2015-09-19 10:49:44 +02:00
|
|
|
static const TypeInfo mips_pica61_type = {
|
|
|
|
.name = MACHINE_TYPE_NAME("pica61"),
|
|
|
|
.parent = TYPE_MACHINE,
|
|
|
|
.class_init = mips_pica61_class_init,
|
|
|
|
};
|
|
|
|
|
|
|
|
static void mips_jazz_machine_init(void)
|
|
|
|
{
|
|
|
|
type_register_static(&mips_magnum_type);
|
|
|
|
type_register_static(&mips_pica61_type);
|
|
|
|
}
|
|
|
|
|
2016-02-16 21:59:04 +01:00
|
|
|
type_init(mips_jazz_machine_init)
|