2007-09-16 23:08:06 +02:00
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/*
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2007-11-11 01:04:49 +01:00
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* ARM Generic/Distributed Interrupt Controller
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2006-09-23 19:40:58 +02:00
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*
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2007-11-11 01:04:49 +01:00
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* Copyright (c) 2006-2007 CodeSourcery.
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2006-09-23 19:40:58 +02:00
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* Written by Paul Brook
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*
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2011-06-26 04:21:35 +02:00
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* This code is licensed under the GPL.
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2006-09-23 19:40:58 +02:00
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*/
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2007-11-11 01:04:49 +01:00
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/* This file contains implementation code for the RealView EB interrupt
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2012-04-13 13:39:09 +02:00
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* controller, MPCore distributed interrupt controller and ARMv7-M
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* Nested Vectored Interrupt Controller.
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* It is compiled in two ways:
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* (1) as a standalone file to produce a sysbus device which is a GIC
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* that can be used on the realview board and as one of the builtin
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* private peripherals for the ARM MP CPUs (11MPCore, A9, etc)
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* (2) by being directly #included into armv7m_nvic.c to produce the
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* armv7m_nvic device.
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*/
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2006-09-23 19:40:58 +02:00
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2012-04-13 13:39:07 +02:00
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#include "sysbus.h"
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2012-01-17 11:54:07 +01:00
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/* Maximum number of possible interrupts, determined by the GIC architecture */
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#define GIC_MAXIRQ 1020
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2012-03-02 12:56:38 +01:00
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/* First 32 are private to each CPU (SGIs and PPIs). */
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#define GIC_INTERNAL 32
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2012-04-13 13:39:07 +02:00
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/* Maximum number of possible CPU interfaces, determined by GIC architecture */
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#ifdef NVIC
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#define NCPU 1
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#else
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#define NCPU 8
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#endif
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2006-09-23 19:40:58 +02:00
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//#define DEBUG_GIC
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#ifdef DEBUG_GIC
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2009-05-13 19:53:17 +02:00
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#define DPRINTF(fmt, ...) \
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do { printf("arm_gic: " fmt , ## __VA_ARGS__); } while (0)
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2006-09-23 19:40:58 +02:00
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#else
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2009-05-13 19:53:17 +02:00
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#define DPRINTF(fmt, ...) do {} while(0)
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2006-09-23 19:40:58 +02:00
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#endif
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2007-11-11 01:04:49 +01:00
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#ifdef NVIC
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static const uint8_t gic_id[] =
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{ 0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1 };
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/* The NVIC has 16 internal vectors. However these are not exposed
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through the normal GIC interface. */
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#define GIC_BASE_IRQ 32
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#else
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2006-09-23 19:40:58 +02:00
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static const uint8_t gic_id[] =
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{ 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
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2007-11-11 01:04:49 +01:00
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#define GIC_BASE_IRQ 0
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#endif
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2006-09-23 19:40:58 +02:00
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2009-05-14 23:35:08 +02:00
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#define FROM_SYSBUSGIC(type, dev) \
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DO_UPCAST(type, gic, FROM_SYSBUS(gic_state, dev))
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2006-09-23 19:40:58 +02:00
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typedef struct gic_irq_state
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{
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2011-11-06 17:01:08 +01:00
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/* The enable bits are only banked for per-cpu interrupts. */
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unsigned enabled:NCPU;
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2007-11-11 01:04:49 +01:00
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unsigned pending:NCPU;
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unsigned active:NCPU;
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2009-03-07 22:47:53 +01:00
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unsigned level:NCPU;
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2007-11-11 01:04:49 +01:00
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unsigned model:1; /* 0 = N:N, 1 = 1:N */
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2006-09-23 19:40:58 +02:00
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unsigned trigger:1; /* nonzero = edge triggered. */
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} gic_irq_state;
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2012-04-13 13:39:07 +02:00
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#define ALL_CPU_MASK ((unsigned)(((1 << NCPU) - 1)))
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2009-11-13 05:31:22 +01:00
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#if NCPU > 1
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#define NUM_CPU(s) ((s)->num_cpu)
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#else
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#define NUM_CPU(s) 1
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#endif
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2007-11-11 01:04:49 +01:00
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2011-11-06 17:01:08 +01:00
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#define GIC_SET_ENABLED(irq, cm) s->irq_state[irq].enabled |= (cm)
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#define GIC_CLEAR_ENABLED(irq, cm) s->irq_state[irq].enabled &= ~(cm)
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#define GIC_TEST_ENABLED(irq, cm) ((s->irq_state[irq].enabled & (cm)) != 0)
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2007-11-11 01:04:49 +01:00
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#define GIC_SET_PENDING(irq, cm) s->irq_state[irq].pending |= (cm)
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#define GIC_CLEAR_PENDING(irq, cm) s->irq_state[irq].pending &= ~(cm)
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#define GIC_TEST_PENDING(irq, cm) ((s->irq_state[irq].pending & (cm)) != 0)
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#define GIC_SET_ACTIVE(irq, cm) s->irq_state[irq].active |= (cm)
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#define GIC_CLEAR_ACTIVE(irq, cm) s->irq_state[irq].active &= ~(cm)
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#define GIC_TEST_ACTIVE(irq, cm) ((s->irq_state[irq].active & (cm)) != 0)
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2006-09-23 19:40:58 +02:00
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#define GIC_SET_MODEL(irq) s->irq_state[irq].model = 1
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#define GIC_CLEAR_MODEL(irq) s->irq_state[irq].model = 0
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#define GIC_TEST_MODEL(irq) s->irq_state[irq].model
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2007-11-11 01:04:49 +01:00
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#define GIC_SET_LEVEL(irq, cm) s->irq_state[irq].level = (cm)
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#define GIC_CLEAR_LEVEL(irq, cm) s->irq_state[irq].level &= ~(cm)
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2008-05-06 16:45:30 +02:00
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#define GIC_TEST_LEVEL(irq, cm) ((s->irq_state[irq].level & (cm)) != 0)
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2006-09-23 19:40:58 +02:00
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#define GIC_SET_TRIGGER(irq) s->irq_state[irq].trigger = 1
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#define GIC_CLEAR_TRIGGER(irq) s->irq_state[irq].trigger = 0
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#define GIC_TEST_TRIGGER(irq) s->irq_state[irq].trigger
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2012-03-02 12:56:38 +01:00
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#define GIC_GET_PRIORITY(irq, cpu) (((irq) < GIC_INTERNAL) ? \
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s->priority1[irq][cpu] : \
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s->priority2[(irq) - GIC_INTERNAL])
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2007-11-11 01:04:49 +01:00
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#ifdef NVIC
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#define GIC_TARGET(irq) 1
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#else
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#define GIC_TARGET(irq) s->irq_target[irq]
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#endif
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2006-09-23 19:40:58 +02:00
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typedef struct gic_state
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{
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2009-05-14 23:35:08 +02:00
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SysBusDevice busdev;
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2007-11-11 01:04:49 +01:00
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qemu_irq parent_irq[NCPU];
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2006-09-23 19:40:58 +02:00
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int enabled;
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2007-11-11 01:04:49 +01:00
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int cpu_enabled[NCPU];
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2006-09-23 19:40:58 +02:00
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2012-01-17 11:54:07 +01:00
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gic_irq_state irq_state[GIC_MAXIRQ];
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2007-11-11 01:04:49 +01:00
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#ifndef NVIC
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2012-01-17 11:54:07 +01:00
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int irq_target[GIC_MAXIRQ];
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2007-11-11 01:04:49 +01:00
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#endif
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2012-03-02 12:56:38 +01:00
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int priority1[GIC_INTERNAL][NCPU];
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int priority2[GIC_MAXIRQ - GIC_INTERNAL];
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2012-01-17 11:54:07 +01:00
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int last_active[GIC_MAXIRQ][NCPU];
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2007-11-11 01:04:49 +01:00
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int priority_mask[NCPU];
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int running_irq[NCPU];
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int running_priority[NCPU];
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int current_pending[NCPU];
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2009-11-13 05:31:22 +01:00
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#if NCPU > 1
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2012-04-13 13:39:07 +02:00
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uint32_t num_cpu;
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2009-11-13 05:31:22 +01:00
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#endif
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2011-12-05 13:52:33 +01:00
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MemoryRegion iomem; /* Distributor */
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#ifndef NVIC
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/* This is just so we can have an opaque pointer which identifies
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* both this GIC and which CPU interface we should be accessing.
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*/
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struct gic_state *backref[NCPU];
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MemoryRegion cpuiomem[NCPU+1]; /* CPU interfaces */
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#endif
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2012-01-17 11:54:07 +01:00
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uint32_t num_irq;
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2006-09-23 19:40:58 +02:00
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} gic_state;
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2012-04-13 13:39:07 +02:00
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static inline int gic_get_current_cpu(gic_state *s)
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{
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#if NCPU > 1
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if (s->num_cpu > 1) {
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return cpu_single_env->cpu_index;
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}
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#endif
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return 0;
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}
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2006-09-23 19:40:58 +02:00
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/* TODO: Many places that call this routine could be optimized. */
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/* Update interrupt status after enabled or pending bits have been changed. */
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static void gic_update(gic_state *s)
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{
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int best_irq;
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int best_prio;
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int irq;
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2007-11-11 01:04:49 +01:00
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int level;
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int cpu;
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int cm;
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2009-11-13 05:31:22 +01:00
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for (cpu = 0; cpu < NUM_CPU(s); cpu++) {
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2007-11-11 01:04:49 +01:00
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cm = 1 << cpu;
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s->current_pending[cpu] = 1023;
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if (!s->enabled || !s->cpu_enabled[cpu]) {
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2012-04-13 13:39:09 +02:00
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qemu_irq_lower(s->parent_irq[cpu]);
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2007-11-11 01:04:49 +01:00
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return;
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}
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best_prio = 0x100;
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best_irq = 1023;
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2012-01-17 11:54:07 +01:00
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for (irq = 0; irq < s->num_irq; irq++) {
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2011-11-06 17:01:08 +01:00
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if (GIC_TEST_ENABLED(irq, cm) && GIC_TEST_PENDING(irq, cm)) {
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2007-11-11 01:04:49 +01:00
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if (GIC_GET_PRIORITY(irq, cpu) < best_prio) {
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best_prio = GIC_GET_PRIORITY(irq, cpu);
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best_irq = irq;
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}
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2006-09-23 19:40:58 +02:00
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}
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}
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2007-11-11 01:04:49 +01:00
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level = 0;
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if (best_prio <= s->priority_mask[cpu]) {
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s->current_pending[cpu] = best_irq;
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if (best_prio < s->running_priority[cpu]) {
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DPRINTF("Raised pending IRQ %d\n", best_irq);
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level = 1;
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}
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2006-09-23 19:40:58 +02:00
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}
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2007-11-11 01:04:49 +01:00
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qemu_set_irq(s->parent_irq[cpu], level);
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2006-09-23 19:40:58 +02:00
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}
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}
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2012-04-13 13:39:09 +02:00
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#ifdef NVIC
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static void gic_set_pending_private(gic_state *s, int cpu, int irq)
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2007-11-11 01:04:49 +01:00
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{
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int cm = 1 << cpu;
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if (GIC_TEST_PENDING(irq, cm))
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return;
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DPRINTF("Set %d pending cpu %d\n", irq, cpu);
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GIC_SET_PENDING(irq, cm);
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gic_update(s);
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}
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2012-04-13 13:39:09 +02:00
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#endif
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2007-11-11 01:04:49 +01:00
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/* Process a change in an external IRQ input. */
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2006-09-23 19:40:58 +02:00
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static void gic_set_irq(void *opaque, int irq, int level)
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{
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2012-04-13 13:39:07 +02:00
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/* Meaning of the 'irq' parameter:
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* [0..N-1] : external interrupts
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* [N..N+31] : PPI (internal) interrupts for CPU 0
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* [N+32..N+63] : PPI (internal interrupts for CPU 1
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* ...
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*/
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2006-09-23 19:40:58 +02:00
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gic_state *s = (gic_state *)opaque;
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2012-04-13 13:39:07 +02:00
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int cm, target;
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if (irq < (s->num_irq - GIC_INTERNAL)) {
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/* The first external input line is internal interrupt 32. */
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cm = ALL_CPU_MASK;
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irq += GIC_INTERNAL;
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target = GIC_TARGET(irq);
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} else {
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int cpu;
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irq -= (s->num_irq - GIC_INTERNAL);
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cpu = irq / GIC_INTERNAL;
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irq %= GIC_INTERNAL;
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cm = 1 << cpu;
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target = cm;
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}
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if (level == GIC_TEST_LEVEL(irq, cm)) {
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2006-09-23 19:40:58 +02:00
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return;
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2012-04-13 13:39:07 +02:00
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}
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2006-09-23 19:40:58 +02:00
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if (level) {
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2012-04-13 13:39:07 +02:00
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GIC_SET_LEVEL(irq, cm);
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if (GIC_TEST_TRIGGER(irq) || GIC_TEST_ENABLED(irq, cm)) {
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DPRINTF("Set %d pending mask %x\n", irq, target);
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GIC_SET_PENDING(irq, target);
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2006-09-23 19:40:58 +02:00
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}
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} else {
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2012-04-13 13:39:07 +02:00
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GIC_CLEAR_LEVEL(irq, cm);
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2006-09-23 19:40:58 +02:00
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}
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gic_update(s);
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}
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2007-11-11 01:04:49 +01:00
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static void gic_set_running_irq(gic_state *s, int cpu, int irq)
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2006-09-23 19:40:58 +02:00
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{
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2007-11-11 01:04:49 +01:00
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s->running_irq[cpu] = irq;
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if (irq == 1023) {
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s->running_priority[cpu] = 0x100;
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} else {
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s->running_priority[cpu] = GIC_GET_PRIORITY(irq, cpu);
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}
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2006-09-23 19:40:58 +02:00
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gic_update(s);
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}
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2007-11-11 01:04:49 +01:00
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static uint32_t gic_acknowledge_irq(gic_state *s, int cpu)
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2006-09-23 19:40:58 +02:00
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{
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int new_irq;
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2007-11-11 01:04:49 +01:00
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int cm = 1 << cpu;
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new_irq = s->current_pending[cpu];
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if (new_irq == 1023
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|| GIC_GET_PRIORITY(new_irq, cpu) >= s->running_priority[cpu]) {
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2006-09-23 19:40:58 +02:00
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DPRINTF("ACK no pending IRQ\n");
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return 1023;
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}
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2007-11-11 01:04:49 +01:00
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s->last_active[new_irq][cpu] = s->running_irq[cpu];
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/* Clear pending flags for both level and edge triggered interrupts.
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Level triggered IRQs will be reasserted once they become inactive. */
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GIC_CLEAR_PENDING(new_irq, GIC_TEST_MODEL(new_irq) ? ALL_CPU_MASK : cm);
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gic_set_running_irq(s, cpu, new_irq);
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2006-09-23 19:40:58 +02:00
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DPRINTF("ACK %d\n", new_irq);
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return new_irq;
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}
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2007-11-11 01:04:49 +01:00
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static void gic_complete_irq(gic_state * s, int cpu, int irq)
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2006-09-23 19:40:58 +02:00
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{
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int update = 0;
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2007-11-11 01:04:49 +01:00
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int cm = 1 << cpu;
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2007-01-02 20:33:15 +01:00
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DPRINTF("EOI %d\n", irq);
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2012-01-17 11:54:07 +01:00
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|
|
if (irq >= s->num_irq) {
|
2011-12-01 19:37:17 +01:00
|
|
|
/* This handles two cases:
|
|
|
|
* 1. If software writes the ID of a spurious interrupt [ie 1023]
|
|
|
|
* to the GICC_EOIR, the GIC ignores that write.
|
|
|
|
* 2. If software writes the number of a non-existent interrupt
|
|
|
|
* this must be a subcase of "value written does not match the last
|
|
|
|
* valid interrupt value read from the Interrupt Acknowledge
|
|
|
|
* register" and so this is UNPREDICTABLE. We choose to ignore it.
|
|
|
|
*/
|
|
|
|
return;
|
|
|
|
}
|
2007-11-11 01:04:49 +01:00
|
|
|
if (s->running_irq[cpu] == 1023)
|
2006-09-23 19:40:58 +02:00
|
|
|
return; /* No active IRQ. */
|
2011-12-01 19:37:17 +01:00
|
|
|
/* Mark level triggered interrupts as pending if they are still
|
|
|
|
raised. */
|
|
|
|
if (!GIC_TEST_TRIGGER(irq) && GIC_TEST_ENABLED(irq, cm)
|
|
|
|
&& GIC_TEST_LEVEL(irq, cm) && (GIC_TARGET(irq) & cm) != 0) {
|
|
|
|
DPRINTF("Set %d pending mask %x\n", irq, cm);
|
|
|
|
GIC_SET_PENDING(irq, cm);
|
|
|
|
update = 1;
|
2006-09-23 19:40:58 +02:00
|
|
|
}
|
2007-11-11 01:04:49 +01:00
|
|
|
if (irq != s->running_irq[cpu]) {
|
2006-09-23 19:40:58 +02:00
|
|
|
/* Complete an IRQ that is not currently running. */
|
2007-11-11 01:04:49 +01:00
|
|
|
int tmp = s->running_irq[cpu];
|
|
|
|
while (s->last_active[tmp][cpu] != 1023) {
|
|
|
|
if (s->last_active[tmp][cpu] == irq) {
|
|
|
|
s->last_active[tmp][cpu] = s->last_active[irq][cpu];
|
2006-09-23 19:40:58 +02:00
|
|
|
break;
|
|
|
|
}
|
2007-11-11 01:04:49 +01:00
|
|
|
tmp = s->last_active[tmp][cpu];
|
2006-09-23 19:40:58 +02:00
|
|
|
}
|
|
|
|
if (update) {
|
|
|
|
gic_update(s);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
/* Complete the current running IRQ. */
|
2007-11-11 01:04:49 +01:00
|
|
|
gic_set_running_irq(s, cpu, s->last_active[s->running_irq[cpu]][cpu]);
|
2006-09-23 19:40:58 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-10-01 23:12:16 +02:00
|
|
|
static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset)
|
2006-09-23 19:40:58 +02:00
|
|
|
{
|
|
|
|
gic_state *s = (gic_state *)opaque;
|
|
|
|
uint32_t res;
|
|
|
|
int irq;
|
|
|
|
int i;
|
2007-11-11 01:04:49 +01:00
|
|
|
int cpu;
|
|
|
|
int cm;
|
|
|
|
int mask;
|
2006-09-23 19:40:58 +02:00
|
|
|
|
2012-04-13 13:39:07 +02:00
|
|
|
cpu = gic_get_current_cpu(s);
|
2007-11-11 01:04:49 +01:00
|
|
|
cm = 1 << cpu;
|
2006-09-23 19:40:58 +02:00
|
|
|
if (offset < 0x100) {
|
2007-11-11 01:04:49 +01:00
|
|
|
#ifndef NVIC
|
2006-09-23 19:40:58 +02:00
|
|
|
if (offset == 0)
|
|
|
|
return s->enabled;
|
|
|
|
if (offset == 4)
|
2012-01-17 11:54:07 +01:00
|
|
|
return ((s->num_irq / 32) - 1) | ((NUM_CPU(s) - 1) << 5);
|
2006-09-23 19:40:58 +02:00
|
|
|
if (offset < 0x08)
|
|
|
|
return 0;
|
2011-12-29 07:19:53 +01:00
|
|
|
if (offset >= 0x80) {
|
|
|
|
/* Interrupt Security , RAZ/WI */
|
|
|
|
return 0;
|
|
|
|
}
|
2007-11-11 01:04:49 +01:00
|
|
|
#endif
|
2006-09-23 19:40:58 +02:00
|
|
|
goto bad_reg;
|
|
|
|
} else if (offset < 0x200) {
|
|
|
|
/* Interrupt Set/Clear Enable. */
|
|
|
|
if (offset < 0x180)
|
|
|
|
irq = (offset - 0x100) * 8;
|
|
|
|
else
|
|
|
|
irq = (offset - 0x180) * 8;
|
2007-11-11 01:04:49 +01:00
|
|
|
irq += GIC_BASE_IRQ;
|
2012-01-17 11:54:07 +01:00
|
|
|
if (irq >= s->num_irq)
|
2006-09-23 19:40:58 +02:00
|
|
|
goto bad_reg;
|
|
|
|
res = 0;
|
|
|
|
for (i = 0; i < 8; i++) {
|
2011-11-06 17:01:08 +01:00
|
|
|
if (GIC_TEST_ENABLED(irq + i, cm)) {
|
2006-09-23 19:40:58 +02:00
|
|
|
res |= (1 << i);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
} else if (offset < 0x300) {
|
|
|
|
/* Interrupt Set/Clear Pending. */
|
|
|
|
if (offset < 0x280)
|
|
|
|
irq = (offset - 0x200) * 8;
|
|
|
|
else
|
|
|
|
irq = (offset - 0x280) * 8;
|
2007-11-11 01:04:49 +01:00
|
|
|
irq += GIC_BASE_IRQ;
|
2012-01-17 11:54:07 +01:00
|
|
|
if (irq >= s->num_irq)
|
2006-09-23 19:40:58 +02:00
|
|
|
goto bad_reg;
|
|
|
|
res = 0;
|
2012-03-02 12:56:38 +01:00
|
|
|
mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK;
|
2006-09-23 19:40:58 +02:00
|
|
|
for (i = 0; i < 8; i++) {
|
2007-11-11 01:04:49 +01:00
|
|
|
if (GIC_TEST_PENDING(irq + i, mask)) {
|
2006-09-23 19:40:58 +02:00
|
|
|
res |= (1 << i);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
} else if (offset < 0x400) {
|
|
|
|
/* Interrupt Active. */
|
2007-11-11 01:04:49 +01:00
|
|
|
irq = (offset - 0x300) * 8 + GIC_BASE_IRQ;
|
2012-01-17 11:54:07 +01:00
|
|
|
if (irq >= s->num_irq)
|
2006-09-23 19:40:58 +02:00
|
|
|
goto bad_reg;
|
|
|
|
res = 0;
|
2012-03-02 12:56:38 +01:00
|
|
|
mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK;
|
2006-09-23 19:40:58 +02:00
|
|
|
for (i = 0; i < 8; i++) {
|
2007-11-11 01:04:49 +01:00
|
|
|
if (GIC_TEST_ACTIVE(irq + i, mask)) {
|
2006-09-23 19:40:58 +02:00
|
|
|
res |= (1 << i);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
} else if (offset < 0x800) {
|
|
|
|
/* Interrupt Priority. */
|
2007-11-11 01:04:49 +01:00
|
|
|
irq = (offset - 0x400) + GIC_BASE_IRQ;
|
2012-01-17 11:54:07 +01:00
|
|
|
if (irq >= s->num_irq)
|
2006-09-23 19:40:58 +02:00
|
|
|
goto bad_reg;
|
2007-11-11 01:04:49 +01:00
|
|
|
res = GIC_GET_PRIORITY(irq, cpu);
|
|
|
|
#ifndef NVIC
|
2006-09-23 19:40:58 +02:00
|
|
|
} else if (offset < 0xc00) {
|
|
|
|
/* Interrupt CPU Target. */
|
2007-11-11 01:04:49 +01:00
|
|
|
irq = (offset - 0x800) + GIC_BASE_IRQ;
|
2012-01-17 11:54:07 +01:00
|
|
|
if (irq >= s->num_irq)
|
2006-09-23 19:40:58 +02:00
|
|
|
goto bad_reg;
|
2007-11-11 01:04:49 +01:00
|
|
|
if (irq >= 29 && irq <= 31) {
|
|
|
|
res = cm;
|
|
|
|
} else {
|
|
|
|
res = GIC_TARGET(irq);
|
|
|
|
}
|
2006-09-23 19:40:58 +02:00
|
|
|
} else if (offset < 0xf00) {
|
|
|
|
/* Interrupt Configuration. */
|
2007-11-11 01:04:49 +01:00
|
|
|
irq = (offset - 0xc00) * 2 + GIC_BASE_IRQ;
|
2012-01-17 11:54:07 +01:00
|
|
|
if (irq >= s->num_irq)
|
2006-09-23 19:40:58 +02:00
|
|
|
goto bad_reg;
|
|
|
|
res = 0;
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
|
|
if (GIC_TEST_MODEL(irq + i))
|
|
|
|
res |= (1 << (i * 2));
|
|
|
|
if (GIC_TEST_TRIGGER(irq + i))
|
|
|
|
res |= (2 << (i * 2));
|
|
|
|
}
|
2007-11-11 01:04:49 +01:00
|
|
|
#endif
|
2006-09-23 19:40:58 +02:00
|
|
|
} else if (offset < 0xfe0) {
|
|
|
|
goto bad_reg;
|
|
|
|
} else /* offset >= 0xfe0 */ {
|
|
|
|
if (offset & 3) {
|
|
|
|
res = 0;
|
|
|
|
} else {
|
|
|
|
res = gic_id[(offset - 0xfe0) >> 2];
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return res;
|
|
|
|
bad_reg:
|
2009-05-08 03:35:15 +02:00
|
|
|
hw_error("gic_dist_readb: Bad offset %x\n", (int)offset);
|
2006-09-23 19:40:58 +02:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-10-01 23:12:16 +02:00
|
|
|
static uint32_t gic_dist_readw(void *opaque, target_phys_addr_t offset)
|
2006-09-23 19:40:58 +02:00
|
|
|
{
|
|
|
|
uint32_t val;
|
|
|
|
val = gic_dist_readb(opaque, offset);
|
|
|
|
val |= gic_dist_readb(opaque, offset + 1) << 8;
|
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
2009-10-01 23:12:16 +02:00
|
|
|
static uint32_t gic_dist_readl(void *opaque, target_phys_addr_t offset)
|
2006-09-23 19:40:58 +02:00
|
|
|
{
|
|
|
|
uint32_t val;
|
2007-11-11 01:04:49 +01:00
|
|
|
#ifdef NVIC
|
|
|
|
gic_state *s = (gic_state *)opaque;
|
|
|
|
uint32_t addr;
|
2008-12-01 19:59:50 +01:00
|
|
|
addr = offset;
|
2007-11-11 01:04:49 +01:00
|
|
|
if (addr < 0x100 || addr > 0xd00)
|
2009-05-14 23:35:08 +02:00
|
|
|
return nvic_readl(s, addr);
|
2007-11-11 01:04:49 +01:00
|
|
|
#endif
|
2006-09-23 19:40:58 +02:00
|
|
|
val = gic_dist_readw(opaque, offset);
|
|
|
|
val |= gic_dist_readw(opaque, offset + 2) << 16;
|
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
2009-10-01 23:12:16 +02:00
|
|
|
static void gic_dist_writeb(void *opaque, target_phys_addr_t offset,
|
2006-09-23 19:40:58 +02:00
|
|
|
uint32_t value)
|
|
|
|
{
|
|
|
|
gic_state *s = (gic_state *)opaque;
|
|
|
|
int irq;
|
|
|
|
int i;
|
2007-11-11 01:04:49 +01:00
|
|
|
int cpu;
|
2006-09-23 19:40:58 +02:00
|
|
|
|
2012-04-13 13:39:07 +02:00
|
|
|
cpu = gic_get_current_cpu(s);
|
2006-09-23 19:40:58 +02:00
|
|
|
if (offset < 0x100) {
|
2007-11-11 01:04:49 +01:00
|
|
|
#ifdef NVIC
|
|
|
|
goto bad_reg;
|
|
|
|
#else
|
2006-09-23 19:40:58 +02:00
|
|
|
if (offset == 0) {
|
|
|
|
s->enabled = (value & 1);
|
|
|
|
DPRINTF("Distribution %sabled\n", s->enabled ? "En" : "Dis");
|
|
|
|
} else if (offset < 4) {
|
|
|
|
/* ignored. */
|
2011-12-29 07:19:53 +01:00
|
|
|
} else if (offset >= 0x80) {
|
|
|
|
/* Interrupt Security Registers, RAZ/WI */
|
2006-09-23 19:40:58 +02:00
|
|
|
} else {
|
|
|
|
goto bad_reg;
|
|
|
|
}
|
2007-11-11 01:04:49 +01:00
|
|
|
#endif
|
2006-09-23 19:40:58 +02:00
|
|
|
} else if (offset < 0x180) {
|
|
|
|
/* Interrupt Set Enable. */
|
2007-11-11 01:04:49 +01:00
|
|
|
irq = (offset - 0x100) * 8 + GIC_BASE_IRQ;
|
2012-01-17 11:54:07 +01:00
|
|
|
if (irq >= s->num_irq)
|
2006-09-23 19:40:58 +02:00
|
|
|
goto bad_reg;
|
2007-11-11 01:04:49 +01:00
|
|
|
if (irq < 16)
|
|
|
|
value = 0xff;
|
2006-09-23 19:40:58 +02:00
|
|
|
for (i = 0; i < 8; i++) {
|
|
|
|
if (value & (1 << i)) {
|
2012-03-02 12:56:38 +01:00
|
|
|
int mask = (irq < GIC_INTERNAL) ? (1 << cpu) : GIC_TARGET(irq);
|
|
|
|
int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
|
2011-11-06 17:01:08 +01:00
|
|
|
|
|
|
|
if (!GIC_TEST_ENABLED(irq + i, cm)) {
|
2006-09-23 19:40:58 +02:00
|
|
|
DPRINTF("Enabled IRQ %d\n", irq + i);
|
2011-11-06 17:01:08 +01:00
|
|
|
}
|
|
|
|
GIC_SET_ENABLED(irq + i, cm);
|
2006-09-23 19:40:58 +02:00
|
|
|
/* If a raised level triggered IRQ enabled then mark
|
|
|
|
is as pending. */
|
2007-11-11 01:04:49 +01:00
|
|
|
if (GIC_TEST_LEVEL(irq + i, mask)
|
|
|
|
&& !GIC_TEST_TRIGGER(irq + i)) {
|
|
|
|
DPRINTF("Set %d pending mask %x\n", irq + i, mask);
|
|
|
|
GIC_SET_PENDING(irq + i, mask);
|
|
|
|
}
|
2006-09-23 19:40:58 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
} else if (offset < 0x200) {
|
|
|
|
/* Interrupt Clear Enable. */
|
2007-11-11 01:04:49 +01:00
|
|
|
irq = (offset - 0x180) * 8 + GIC_BASE_IRQ;
|
2012-01-17 11:54:07 +01:00
|
|
|
if (irq >= s->num_irq)
|
2006-09-23 19:40:58 +02:00
|
|
|
goto bad_reg;
|
2007-11-11 01:04:49 +01:00
|
|
|
if (irq < 16)
|
|
|
|
value = 0;
|
2006-09-23 19:40:58 +02:00
|
|
|
for (i = 0; i < 8; i++) {
|
|
|
|
if (value & (1 << i)) {
|
2012-03-02 12:56:38 +01:00
|
|
|
int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
|
2011-11-06 17:01:08 +01:00
|
|
|
|
|
|
|
if (GIC_TEST_ENABLED(irq + i, cm)) {
|
2006-09-23 19:40:58 +02:00
|
|
|
DPRINTF("Disabled IRQ %d\n", irq + i);
|
2011-11-06 17:01:08 +01:00
|
|
|
}
|
|
|
|
GIC_CLEAR_ENABLED(irq + i, cm);
|
2006-09-23 19:40:58 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
} else if (offset < 0x280) {
|
|
|
|
/* Interrupt Set Pending. */
|
2007-11-11 01:04:49 +01:00
|
|
|
irq = (offset - 0x200) * 8 + GIC_BASE_IRQ;
|
2012-01-17 11:54:07 +01:00
|
|
|
if (irq >= s->num_irq)
|
2006-09-23 19:40:58 +02:00
|
|
|
goto bad_reg;
|
2007-11-11 01:04:49 +01:00
|
|
|
if (irq < 16)
|
|
|
|
irq = 0;
|
|
|
|
|
2006-09-23 19:40:58 +02:00
|
|
|
for (i = 0; i < 8; i++) {
|
|
|
|
if (value & (1 << i)) {
|
2007-11-11 01:04:49 +01:00
|
|
|
GIC_SET_PENDING(irq + i, GIC_TARGET(irq));
|
2006-09-23 19:40:58 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
} else if (offset < 0x300) {
|
|
|
|
/* Interrupt Clear Pending. */
|
2007-11-11 01:04:49 +01:00
|
|
|
irq = (offset - 0x280) * 8 + GIC_BASE_IRQ;
|
2012-01-17 11:54:07 +01:00
|
|
|
if (irq >= s->num_irq)
|
2006-09-23 19:40:58 +02:00
|
|
|
goto bad_reg;
|
|
|
|
for (i = 0; i < 8; i++) {
|
2007-11-11 01:04:49 +01:00
|
|
|
/* ??? This currently clears the pending bit for all CPUs, even
|
|
|
|
for per-CPU interrupts. It's unclear whether this is the
|
|
|
|
corect behavior. */
|
2006-09-23 19:40:58 +02:00
|
|
|
if (value & (1 << i)) {
|
2007-11-11 01:04:49 +01:00
|
|
|
GIC_CLEAR_PENDING(irq + i, ALL_CPU_MASK);
|
2006-09-23 19:40:58 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
} else if (offset < 0x400) {
|
|
|
|
/* Interrupt Active. */
|
|
|
|
goto bad_reg;
|
|
|
|
} else if (offset < 0x800) {
|
|
|
|
/* Interrupt Priority. */
|
2007-11-11 01:04:49 +01:00
|
|
|
irq = (offset - 0x400) + GIC_BASE_IRQ;
|
2012-01-17 11:54:07 +01:00
|
|
|
if (irq >= s->num_irq)
|
2006-09-23 19:40:58 +02:00
|
|
|
goto bad_reg;
|
2012-03-02 12:56:38 +01:00
|
|
|
if (irq < GIC_INTERNAL) {
|
2007-11-11 01:04:49 +01:00
|
|
|
s->priority1[irq][cpu] = value;
|
|
|
|
} else {
|
2012-03-02 12:56:38 +01:00
|
|
|
s->priority2[irq - GIC_INTERNAL] = value;
|
2007-11-11 01:04:49 +01:00
|
|
|
}
|
|
|
|
#ifndef NVIC
|
2006-09-23 19:40:58 +02:00
|
|
|
} else if (offset < 0xc00) {
|
|
|
|
/* Interrupt CPU Target. */
|
2007-11-11 01:04:49 +01:00
|
|
|
irq = (offset - 0x800) + GIC_BASE_IRQ;
|
2012-01-17 11:54:07 +01:00
|
|
|
if (irq >= s->num_irq)
|
2006-09-23 19:40:58 +02:00
|
|
|
goto bad_reg;
|
2007-11-11 01:04:49 +01:00
|
|
|
if (irq < 29)
|
|
|
|
value = 0;
|
2012-03-02 12:56:38 +01:00
|
|
|
else if (irq < GIC_INTERNAL)
|
2007-11-11 01:04:49 +01:00
|
|
|
value = ALL_CPU_MASK;
|
|
|
|
s->irq_target[irq] = value & ALL_CPU_MASK;
|
2006-09-23 19:40:58 +02:00
|
|
|
} else if (offset < 0xf00) {
|
|
|
|
/* Interrupt Configuration. */
|
2007-11-11 01:04:49 +01:00
|
|
|
irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ;
|
2012-01-17 11:54:07 +01:00
|
|
|
if (irq >= s->num_irq)
|
2006-09-23 19:40:58 +02:00
|
|
|
goto bad_reg;
|
2012-03-02 12:56:38 +01:00
|
|
|
if (irq < GIC_INTERNAL)
|
2007-11-11 01:04:49 +01:00
|
|
|
value |= 0xaa;
|
2006-09-23 19:40:58 +02:00
|
|
|
for (i = 0; i < 4; i++) {
|
|
|
|
if (value & (1 << (i * 2))) {
|
|
|
|
GIC_SET_MODEL(irq + i);
|
|
|
|
} else {
|
|
|
|
GIC_CLEAR_MODEL(irq + i);
|
|
|
|
}
|
|
|
|
if (value & (2 << (i * 2))) {
|
|
|
|
GIC_SET_TRIGGER(irq + i);
|
|
|
|
} else {
|
|
|
|
GIC_CLEAR_TRIGGER(irq + i);
|
|
|
|
}
|
|
|
|
}
|
2007-11-11 01:04:49 +01:00
|
|
|
#endif
|
2006-09-23 19:40:58 +02:00
|
|
|
} else {
|
2007-11-11 01:04:49 +01:00
|
|
|
/* 0xf00 is only handled for 32-bit writes. */
|
2006-09-23 19:40:58 +02:00
|
|
|
goto bad_reg;
|
|
|
|
}
|
|
|
|
gic_update(s);
|
|
|
|
return;
|
|
|
|
bad_reg:
|
2009-05-08 03:35:15 +02:00
|
|
|
hw_error("gic_dist_writeb: Bad offset %x\n", (int)offset);
|
2006-09-23 19:40:58 +02:00
|
|
|
}
|
|
|
|
|
2009-10-01 23:12:16 +02:00
|
|
|
static void gic_dist_writew(void *opaque, target_phys_addr_t offset,
|
2006-09-23 19:40:58 +02:00
|
|
|
uint32_t value)
|
|
|
|
{
|
|
|
|
gic_dist_writeb(opaque, offset, value & 0xff);
|
|
|
|
gic_dist_writeb(opaque, offset + 1, value >> 8);
|
|
|
|
}
|
|
|
|
|
2009-10-01 23:12:16 +02:00
|
|
|
static void gic_dist_writel(void *opaque, target_phys_addr_t offset,
|
2006-09-23 19:40:58 +02:00
|
|
|
uint32_t value)
|
|
|
|
{
|
2007-11-11 01:04:49 +01:00
|
|
|
gic_state *s = (gic_state *)opaque;
|
|
|
|
#ifdef NVIC
|
|
|
|
uint32_t addr;
|
2008-12-01 19:59:50 +01:00
|
|
|
addr = offset;
|
2007-11-11 01:04:49 +01:00
|
|
|
if (addr < 0x100 || (addr > 0xd00 && addr != 0xf00)) {
|
2009-05-14 23:35:08 +02:00
|
|
|
nvic_writel(s, addr, value);
|
2007-11-11 01:04:49 +01:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
#endif
|
2008-12-01 19:59:50 +01:00
|
|
|
if (offset == 0xf00) {
|
2007-11-11 01:04:49 +01:00
|
|
|
int cpu;
|
|
|
|
int irq;
|
|
|
|
int mask;
|
|
|
|
|
2012-04-13 13:39:07 +02:00
|
|
|
cpu = gic_get_current_cpu(s);
|
2007-11-11 01:04:49 +01:00
|
|
|
irq = value & 0x3ff;
|
|
|
|
switch ((value >> 24) & 3) {
|
|
|
|
case 0:
|
|
|
|
mask = (value >> 16) & ALL_CPU_MASK;
|
|
|
|
break;
|
|
|
|
case 1:
|
2011-03-05 13:51:42 +01:00
|
|
|
mask = ALL_CPU_MASK ^ (1 << cpu);
|
2007-11-11 01:04:49 +01:00
|
|
|
break;
|
|
|
|
case 2:
|
2011-03-05 13:51:42 +01:00
|
|
|
mask = 1 << cpu;
|
2007-11-11 01:04:49 +01:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
DPRINTF("Bad Soft Int target filter\n");
|
|
|
|
mask = ALL_CPU_MASK;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
GIC_SET_PENDING(irq, mask);
|
|
|
|
gic_update(s);
|
|
|
|
return;
|
|
|
|
}
|
2006-09-23 19:40:58 +02:00
|
|
|
gic_dist_writew(opaque, offset, value & 0xffff);
|
|
|
|
gic_dist_writew(opaque, offset + 2, value >> 16);
|
|
|
|
}
|
|
|
|
|
2011-08-15 16:17:17 +02:00
|
|
|
static const MemoryRegionOps gic_dist_ops = {
|
|
|
|
.old_mmio = {
|
|
|
|
.read = { gic_dist_readb, gic_dist_readw, gic_dist_readl, },
|
|
|
|
.write = { gic_dist_writeb, gic_dist_writew, gic_dist_writel, },
|
|
|
|
},
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
2006-09-23 19:40:58 +02:00
|
|
|
};
|
|
|
|
|
2007-11-11 01:04:49 +01:00
|
|
|
#ifndef NVIC
|
|
|
|
static uint32_t gic_cpu_read(gic_state *s, int cpu, int offset)
|
2006-09-23 19:40:58 +02:00
|
|
|
{
|
|
|
|
switch (offset) {
|
|
|
|
case 0x00: /* Control */
|
2007-11-11 01:04:49 +01:00
|
|
|
return s->cpu_enabled[cpu];
|
2006-09-23 19:40:58 +02:00
|
|
|
case 0x04: /* Priority mask */
|
2007-11-11 01:04:49 +01:00
|
|
|
return s->priority_mask[cpu];
|
2006-09-23 19:40:58 +02:00
|
|
|
case 0x08: /* Binary Point */
|
|
|
|
/* ??? Not implemented. */
|
|
|
|
return 0;
|
|
|
|
case 0x0c: /* Acknowledge */
|
2007-11-11 01:04:49 +01:00
|
|
|
return gic_acknowledge_irq(s, cpu);
|
2011-11-29 09:52:39 +01:00
|
|
|
case 0x14: /* Running Priority */
|
2007-11-11 01:04:49 +01:00
|
|
|
return s->running_priority[cpu];
|
2006-09-23 19:40:58 +02:00
|
|
|
case 0x18: /* Highest Pending Interrupt */
|
2007-11-11 01:04:49 +01:00
|
|
|
return s->current_pending[cpu];
|
2006-09-23 19:40:58 +02:00
|
|
|
default:
|
2009-05-08 03:35:15 +02:00
|
|
|
hw_error("gic_cpu_read: Bad offset %x\n", (int)offset);
|
2006-09-23 19:40:58 +02:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2007-11-11 01:04:49 +01:00
|
|
|
static void gic_cpu_write(gic_state *s, int cpu, int offset, uint32_t value)
|
2006-09-23 19:40:58 +02:00
|
|
|
{
|
|
|
|
switch (offset) {
|
|
|
|
case 0x00: /* Control */
|
2007-11-11 01:04:49 +01:00
|
|
|
s->cpu_enabled[cpu] = (value & 1);
|
2009-11-19 17:45:21 +01:00
|
|
|
DPRINTF("CPU %d %sabled\n", cpu, s->cpu_enabled ? "En" : "Dis");
|
2006-09-23 19:40:58 +02:00
|
|
|
break;
|
|
|
|
case 0x04: /* Priority mask */
|
2007-11-11 01:04:49 +01:00
|
|
|
s->priority_mask[cpu] = (value & 0xff);
|
2006-09-23 19:40:58 +02:00
|
|
|
break;
|
|
|
|
case 0x08: /* Binary Point */
|
|
|
|
/* ??? Not implemented. */
|
|
|
|
break;
|
|
|
|
case 0x10: /* End Of Interrupt */
|
2007-11-11 01:04:49 +01:00
|
|
|
return gic_complete_irq(s, cpu, value & 0x3ff);
|
2006-09-23 19:40:58 +02:00
|
|
|
default:
|
2009-05-08 03:35:15 +02:00
|
|
|
hw_error("gic_cpu_write: Bad offset %x\n", (int)offset);
|
2006-09-23 19:40:58 +02:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
gic_update(s);
|
|
|
|
}
|
2011-12-05 13:52:33 +01:00
|
|
|
|
|
|
|
/* Wrappers to read/write the GIC CPU interface for the current CPU */
|
|
|
|
static uint64_t gic_thiscpu_read(void *opaque, target_phys_addr_t addr,
|
|
|
|
unsigned size)
|
|
|
|
{
|
|
|
|
gic_state *s = (gic_state *)opaque;
|
2012-04-13 13:39:07 +02:00
|
|
|
return gic_cpu_read(s, gic_get_current_cpu(s), addr);
|
2011-12-05 13:52:33 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static void gic_thiscpu_write(void *opaque, target_phys_addr_t addr,
|
|
|
|
uint64_t value, unsigned size)
|
|
|
|
{
|
|
|
|
gic_state *s = (gic_state *)opaque;
|
2012-04-13 13:39:07 +02:00
|
|
|
gic_cpu_write(s, gic_get_current_cpu(s), addr, value);
|
2011-12-05 13:52:33 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Wrappers to read/write the GIC CPU interface for a specific CPU.
|
|
|
|
* These just decode the opaque pointer into gic_state* + cpu id.
|
|
|
|
*/
|
|
|
|
static uint64_t gic_do_cpu_read(void *opaque, target_phys_addr_t addr,
|
|
|
|
unsigned size)
|
|
|
|
{
|
|
|
|
gic_state **backref = (gic_state **)opaque;
|
|
|
|
gic_state *s = *backref;
|
|
|
|
int id = (backref - s->backref);
|
2012-03-14 16:37:53 +01:00
|
|
|
return gic_cpu_read(s, id, addr);
|
2011-12-05 13:52:33 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static void gic_do_cpu_write(void *opaque, target_phys_addr_t addr,
|
|
|
|
uint64_t value, unsigned size)
|
|
|
|
{
|
|
|
|
gic_state **backref = (gic_state **)opaque;
|
|
|
|
gic_state *s = *backref;
|
|
|
|
int id = (backref - s->backref);
|
2012-03-14 16:37:53 +01:00
|
|
|
gic_cpu_write(s, id, addr, value);
|
2011-12-05 13:52:33 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static const MemoryRegionOps gic_thiscpu_ops = {
|
|
|
|
.read = gic_thiscpu_read,
|
|
|
|
.write = gic_thiscpu_write,
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const MemoryRegionOps gic_cpu_ops = {
|
|
|
|
.read = gic_do_cpu_read,
|
|
|
|
.write = gic_do_cpu_write,
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
|
|
};
|
2007-11-11 01:04:49 +01:00
|
|
|
#endif
|
2006-09-23 19:40:58 +02:00
|
|
|
|
2012-04-13 13:39:09 +02:00
|
|
|
static void gic_reset(DeviceState *dev)
|
2006-09-23 19:40:58 +02:00
|
|
|
{
|
2012-04-13 13:39:09 +02:00
|
|
|
gic_state *s = FROM_SYSBUS(gic_state, sysbus_from_qdev(dev));
|
2006-09-23 19:40:58 +02:00
|
|
|
int i;
|
2012-01-17 11:54:07 +01:00
|
|
|
memset(s->irq_state, 0, GIC_MAXIRQ * sizeof(gic_irq_state));
|
2009-11-13 05:31:22 +01:00
|
|
|
for (i = 0 ; i < NUM_CPU(s); i++) {
|
2007-11-11 01:04:49 +01:00
|
|
|
s->priority_mask[i] = 0xf0;
|
|
|
|
s->current_pending[i] = 1023;
|
|
|
|
s->running_irq[i] = 1023;
|
|
|
|
s->running_priority[i] = 0x100;
|
|
|
|
#ifdef NVIC
|
|
|
|
/* The NVIC doesn't have per-cpu interfaces, so enable by default. */
|
|
|
|
s->cpu_enabled[i] = 1;
|
|
|
|
#else
|
|
|
|
s->cpu_enabled[i] = 0;
|
|
|
|
#endif
|
|
|
|
}
|
2007-11-24 04:09:07 +01:00
|
|
|
for (i = 0; i < 16; i++) {
|
2011-11-06 17:01:08 +01:00
|
|
|
GIC_SET_ENABLED(i, ALL_CPU_MASK);
|
2006-09-23 19:40:58 +02:00
|
|
|
GIC_SET_TRIGGER(i);
|
|
|
|
}
|
2007-11-11 01:04:49 +01:00
|
|
|
#ifdef NVIC
|
|
|
|
/* The NVIC is always enabled. */
|
|
|
|
s->enabled = 1;
|
|
|
|
#else
|
2006-09-23 19:40:58 +02:00
|
|
|
s->enabled = 0;
|
2007-11-11 01:04:49 +01:00
|
|
|
#endif
|
2006-09-23 19:40:58 +02:00
|
|
|
}
|
|
|
|
|
2008-07-02 18:48:32 +02:00
|
|
|
static void gic_save(QEMUFile *f, void *opaque)
|
|
|
|
{
|
|
|
|
gic_state *s = (gic_state *)opaque;
|
|
|
|
int i;
|
|
|
|
int j;
|
|
|
|
|
|
|
|
qemu_put_be32(f, s->enabled);
|
2009-11-13 05:31:22 +01:00
|
|
|
for (i = 0; i < NUM_CPU(s); i++) {
|
2008-07-02 18:48:32 +02:00
|
|
|
qemu_put_be32(f, s->cpu_enabled[i]);
|
2012-03-02 12:56:38 +01:00
|
|
|
for (j = 0; j < GIC_INTERNAL; j++)
|
2008-07-02 18:48:32 +02:00
|
|
|
qemu_put_be32(f, s->priority1[j][i]);
|
2012-01-17 11:54:07 +01:00
|
|
|
for (j = 0; j < s->num_irq; j++)
|
2008-07-02 18:48:32 +02:00
|
|
|
qemu_put_be32(f, s->last_active[j][i]);
|
|
|
|
qemu_put_be32(f, s->priority_mask[i]);
|
|
|
|
qemu_put_be32(f, s->running_irq[i]);
|
|
|
|
qemu_put_be32(f, s->running_priority[i]);
|
|
|
|
qemu_put_be32(f, s->current_pending[i]);
|
|
|
|
}
|
2012-03-02 12:56:38 +01:00
|
|
|
for (i = 0; i < s->num_irq - GIC_INTERNAL; i++) {
|
2008-07-02 18:48:32 +02:00
|
|
|
qemu_put_be32(f, s->priority2[i]);
|
|
|
|
}
|
2012-01-17 11:54:07 +01:00
|
|
|
for (i = 0; i < s->num_irq; i++) {
|
2011-10-20 12:48:35 +02:00
|
|
|
#ifndef NVIC
|
|
|
|
qemu_put_be32(f, s->irq_target[i]);
|
|
|
|
#endif
|
2008-07-02 18:48:32 +02:00
|
|
|
qemu_put_byte(f, s->irq_state[i].enabled);
|
|
|
|
qemu_put_byte(f, s->irq_state[i].pending);
|
|
|
|
qemu_put_byte(f, s->irq_state[i].active);
|
|
|
|
qemu_put_byte(f, s->irq_state[i].level);
|
|
|
|
qemu_put_byte(f, s->irq_state[i].model);
|
|
|
|
qemu_put_byte(f, s->irq_state[i].trigger);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static int gic_load(QEMUFile *f, void *opaque, int version_id)
|
|
|
|
{
|
|
|
|
gic_state *s = (gic_state *)opaque;
|
|
|
|
int i;
|
|
|
|
int j;
|
|
|
|
|
2011-10-20 12:48:35 +02:00
|
|
|
if (version_id != 2)
|
2008-07-02 18:48:32 +02:00
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
s->enabled = qemu_get_be32(f);
|
2009-11-13 05:31:22 +01:00
|
|
|
for (i = 0; i < NUM_CPU(s); i++) {
|
2008-07-02 18:48:32 +02:00
|
|
|
s->cpu_enabled[i] = qemu_get_be32(f);
|
2012-03-02 12:56:38 +01:00
|
|
|
for (j = 0; j < GIC_INTERNAL; j++)
|
2008-07-02 18:48:32 +02:00
|
|
|
s->priority1[j][i] = qemu_get_be32(f);
|
2012-01-17 11:54:07 +01:00
|
|
|
for (j = 0; j < s->num_irq; j++)
|
2008-07-02 18:48:32 +02:00
|
|
|
s->last_active[j][i] = qemu_get_be32(f);
|
|
|
|
s->priority_mask[i] = qemu_get_be32(f);
|
|
|
|
s->running_irq[i] = qemu_get_be32(f);
|
|
|
|
s->running_priority[i] = qemu_get_be32(f);
|
|
|
|
s->current_pending[i] = qemu_get_be32(f);
|
|
|
|
}
|
2012-03-02 12:56:38 +01:00
|
|
|
for (i = 0; i < s->num_irq - GIC_INTERNAL; i++) {
|
2008-07-02 18:48:32 +02:00
|
|
|
s->priority2[i] = qemu_get_be32(f);
|
|
|
|
}
|
2012-01-17 11:54:07 +01:00
|
|
|
for (i = 0; i < s->num_irq; i++) {
|
2011-10-20 12:48:35 +02:00
|
|
|
#ifndef NVIC
|
|
|
|
s->irq_target[i] = qemu_get_be32(f);
|
|
|
|
#endif
|
2008-07-02 18:48:32 +02:00
|
|
|
s->irq_state[i].enabled = qemu_get_byte(f);
|
|
|
|
s->irq_state[i].pending = qemu_get_byte(f);
|
|
|
|
s->irq_state[i].active = qemu_get_byte(f);
|
|
|
|
s->irq_state[i].level = qemu_get_byte(f);
|
|
|
|
s->irq_state[i].model = qemu_get_byte(f);
|
|
|
|
s->irq_state[i].trigger = qemu_get_byte(f);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-11-13 05:31:22 +01:00
|
|
|
#if NCPU > 1
|
2012-01-17 11:54:07 +01:00
|
|
|
static void gic_init(gic_state *s, int num_cpu, int num_irq)
|
2009-11-13 05:31:22 +01:00
|
|
|
#else
|
2012-01-17 11:54:07 +01:00
|
|
|
static void gic_init(gic_state *s, int num_irq)
|
2009-11-13 05:31:22 +01:00
|
|
|
#endif
|
2006-09-23 19:40:58 +02:00
|
|
|
{
|
2007-11-11 01:04:49 +01:00
|
|
|
int i;
|
2006-09-23 19:40:58 +02:00
|
|
|
|
2009-11-13 05:31:22 +01:00
|
|
|
#if NCPU > 1
|
|
|
|
s->num_cpu = num_cpu;
|
2012-04-13 13:39:07 +02:00
|
|
|
if (s->num_cpu > NCPU) {
|
|
|
|
hw_error("requested %u CPUs exceeds GIC maximum %d\n",
|
|
|
|
num_cpu, NCPU);
|
|
|
|
}
|
2009-11-13 05:31:22 +01:00
|
|
|
#endif
|
2012-01-17 11:54:07 +01:00
|
|
|
s->num_irq = num_irq + GIC_BASE_IRQ;
|
|
|
|
if (s->num_irq > GIC_MAXIRQ) {
|
|
|
|
hw_error("requested %u interrupt lines exceeds GIC maximum %d\n",
|
|
|
|
num_irq, GIC_MAXIRQ);
|
|
|
|
}
|
2012-03-02 12:56:38 +01:00
|
|
|
/* ITLinesNumber is represented as (N / 32) - 1 (see
|
|
|
|
* gic_dist_readb) so this is an implementation imposed
|
|
|
|
* restriction, not an architectural one:
|
|
|
|
*/
|
|
|
|
if (s->num_irq < 32 || (s->num_irq % 32)) {
|
|
|
|
hw_error("%d interrupt lines unsupported: not divisible by 32\n",
|
|
|
|
num_irq);
|
|
|
|
}
|
|
|
|
|
2012-04-13 13:39:07 +02:00
|
|
|
i = s->num_irq - GIC_INTERNAL;
|
|
|
|
#ifndef NVIC
|
|
|
|
/* For the GIC, also expose incoming GPIO lines for PPIs for each CPU.
|
|
|
|
* GPIO array layout is thus:
|
|
|
|
* [0..N-1] SPIs
|
|
|
|
* [N..N+31] PPIs for CPU 0
|
|
|
|
* [N+32..N+63] PPIs for CPU 1
|
|
|
|
* ...
|
|
|
|
*/
|
|
|
|
i += (GIC_INTERNAL * num_cpu);
|
|
|
|
#endif
|
|
|
|
qdev_init_gpio_in(&s->busdev.qdev, gic_set_irq, i);
|
2009-11-13 05:31:22 +01:00
|
|
|
for (i = 0; i < NUM_CPU(s); i++) {
|
2009-05-14 23:35:08 +02:00
|
|
|
sysbus_init_irq(&s->busdev, &s->parent_irq[i]);
|
2006-09-23 19:40:58 +02:00
|
|
|
}
|
2011-08-15 16:17:17 +02:00
|
|
|
memory_region_init_io(&s->iomem, &gic_dist_ops, s, "gic_dist", 0x1000);
|
2011-12-05 13:52:33 +01:00
|
|
|
#ifndef NVIC
|
|
|
|
/* Memory regions for the CPU interfaces (NVIC doesn't have these):
|
|
|
|
* a region for "CPU interface for this core", then a region for
|
|
|
|
* "CPU interface for core 0", "for core 1", ...
|
|
|
|
* NB that the memory region size of 0x100 applies for the 11MPCore
|
|
|
|
* and also cores following the GIC v1 spec (ie A9).
|
|
|
|
* GIC v2 defines a larger memory region (0x1000) so this will need
|
|
|
|
* to be extended when we implement A15.
|
|
|
|
*/
|
|
|
|
memory_region_init_io(&s->cpuiomem[0], &gic_thiscpu_ops, s,
|
|
|
|
"gic_cpu", 0x100);
|
|
|
|
for (i = 0; i < NUM_CPU(s); i++) {
|
|
|
|
s->backref[i] = s;
|
|
|
|
memory_region_init_io(&s->cpuiomem[i+1], &gic_cpu_ops, &s->backref[i],
|
|
|
|
"gic_cpu", 0x100);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2011-10-20 12:48:35 +02:00
|
|
|
register_savevm(NULL, "arm_gic", -1, 2, gic_save, gic_load, s);
|
2006-09-23 19:40:58 +02:00
|
|
|
}
|
2012-04-13 13:39:07 +02:00
|
|
|
|
2012-04-13 13:39:09 +02:00
|
|
|
#ifndef NVIC
|
2012-04-13 13:39:07 +02:00
|
|
|
|
|
|
|
static int arm_gic_init(SysBusDevice *dev)
|
|
|
|
{
|
|
|
|
/* Device instance init function for the GIC sysbus device */
|
|
|
|
int i;
|
|
|
|
gic_state *s = FROM_SYSBUS(gic_state, dev);
|
|
|
|
gic_init(s, s->num_cpu, s->num_irq);
|
|
|
|
/* Distributor */
|
|
|
|
sysbus_init_mmio(dev, &s->iomem);
|
|
|
|
/* cpu interfaces (one for "current cpu" plus one per cpu) */
|
|
|
|
for (i = 0; i <= NUM_CPU(s); i++) {
|
|
|
|
sysbus_init_mmio(dev, &s->cpuiomem[i]);
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static Property arm_gic_properties[] = {
|
|
|
|
DEFINE_PROP_UINT32("num-cpu", gic_state, num_cpu, 1),
|
|
|
|
DEFINE_PROP_UINT32("num-irq", gic_state, num_irq, 32),
|
|
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
|
|
};
|
|
|
|
|
|
|
|
static void arm_gic_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
|
|
|
|
sbc->init = arm_gic_init;
|
|
|
|
dc->props = arm_gic_properties;
|
2012-04-13 13:39:09 +02:00
|
|
|
dc->reset = gic_reset;
|
2012-04-13 13:39:07 +02:00
|
|
|
dc->no_user = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
static TypeInfo arm_gic_info = {
|
|
|
|
.name = "arm_gic",
|
|
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
|
|
.instance_size = sizeof(gic_state),
|
|
|
|
.class_init = arm_gic_class_init,
|
|
|
|
};
|
|
|
|
|
|
|
|
static void arm_gic_register_types(void)
|
|
|
|
{
|
|
|
|
type_register_static(&arm_gic_info);
|
|
|
|
}
|
|
|
|
|
|
|
|
type_init(arm_gic_register_types)
|
|
|
|
|
|
|
|
#endif
|