Commit Graph

325 Commits

Author SHA1 Message Date
Blue Swirl
b11ebf64b6 Replace REGX with PRIx64
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-08-16 11:54:37 +00:00
Blue Swirl
90e189ece1 Replace local ADDRX/PADDRX macros with TARGET_FMT_lx/plx
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-08-16 11:13:18 +00:00
Blue Swirl
636aa20056 Replace always_inline with inline
We define inline as always_inline.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-08-16 09:06:54 +00:00
Nathan Froyd
4425265beb target-ppc: add exceptions for conditional stores
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: malc <av1474@comtv.ru>
2009-08-03 20:33:41 +04:00
Nathan Froyd
18b21a2f83 target-ppc: retain l{w,d}arx loaded value
We do this so we can check on the corresponding stc{w,d}x. whether the
value has changed.  It's a poor man's form of implementing atomic
operations and is valid only for NPTL usermode Linux emulation.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: malc <av1474@comtv.ru>
2009-08-03 20:33:41 +04:00
Juan Quintela
e2542fe2bc rename WORDS_BIGENDIAN to HOST_WORDS_BIGENDIAN
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-07-27 14:09:21 -05:00
Blue Swirl
8167ee8839 Update to a hopefully more future proof FSF address
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-07-16 20:47:01 +00:00
Baojun Wang
fbe73008f2 ppc tcg: fix wrong bit/mask of wrteei
Signed-off-by: Baojun Wang <wangbj@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-07-13 01:51:17 +02:00
Nathan Froyd
33890b3e0d target-ppc: fix evmergelo and evmergelohi
For 32-bit PPC targets, we translated:

evmergelo rX, rX, rY

as:

rX-lo = rY-lo
rX-hi = rX-lo

which is wrong, because we should be transferring rX-lo first.  This
problem is fixed by swapping the order in which we write the parts of
rX.

Similarly, we translated:

evmergelohi rX, rX, rY

as:

rX-lo = rY-hi
rX-hi = rX-lo

In this case, we can't swap the assignment statements, because that
would just cause problems for:

evmergelohi rX, rY, rX

Instead, we detect the first case and save rX-lo in a temporary
variable:

tmp = rX-lo
rX-lo = rY-hi
rX-hi = tmp

These problems don't occur on PPC64 targets because we don't split the
SPE registers into hi/lo parts for such targets.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-07-12 23:36:21 +02:00
malc
d2e9fd8f70 Apply TCGV_UNUSED on variables that GCC mistakenly thinks can be used
uninitialized
2009-06-20 05:51:47 +04:00
Blue Swirl
5c55ff99fa Replace ELF section hack with normal table
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-06-17 15:22:31 +00:00
Blue Swirl
2e6100507a Concentrate rest of table entries to top
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-06-17 15:22:24 +00:00
Blue Swirl
5462327761 Concentrate most table entries to top
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-06-17 15:22:19 +00:00
Blue Swirl
e8eaa2c012 Clean up GEN_HANDLER2
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-06-17 15:22:14 +00:00
Blue Swirl
99e300ef3f Clean up GEN_HANDLER
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-06-17 15:22:09 +00:00
Nathan Froyd
c29b735c50 target-ppc: expose cpu capability flags
Do this so other pieces of code can make decisions based on the
capabilities of the CPU we're emulating.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: malc <av1474@comtv.ru>
2009-05-16 01:36:08 +04:00
blueswir1
2dc766dafc Fix ppc-softmmu warnings on OpenBSD host
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7099 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-13 16:06:19 +00:00
aurel32
1b530a6dfc Add new command line option -singlestep for tcg single stepping.
This replaces a compile time option for some targets and adds
this feature to targets which did not have a compile time option.

Add monitor command to enable or disable single step mode.

Modify monitor command "info status" to display single step mode.

Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7004 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-05 20:08:59 +00:00
aurel32
af4b6c54c1 target-ppc: avoid nop to override next instruction
While searching PC, always store the pc of a new instruction.
Instructions that didn't generate tcg code (such as nop) prevented the
next one to be referenced.

Based on patch for target-alpha, r6930.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6931 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-29 01:18:03 +00:00
aurel32
fa3966a3dc target-ppc: use the new bswap* TCG ops
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6835 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-13 09:35:34 +00:00
aurel32
66896cb803 tcg: rename bswap_i32/i64 functions
Rename bswap_i32 into bswap32_i32 and bswap_i64 into bswap64_i64

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6829 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-13 09:34:48 +00:00
aurel32
651721b2a5 targe-ppc: optimize mfcr and mtcrf
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6793 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-09 18:50:24 +00:00
aurel32
0497d2f4e4 Fix mfcr on ppc64-softmmu
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6758 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-07 20:57:47 +00:00
blueswir1
4911012d26 Implement mtfsf.L encoding
Mtfsf can have the L bit set, so all the register contents get stored
in FPSCR. Linux uses it, so let's implement it.

Signed-off-by: Alexander Graf <alex@csgraf.de>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6753 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-07 20:55:31 +00:00
blueswir1
bf14b1cef1 Implment tlbiel
Linux uses tlbiel to flush TLB entries in PPC64 mode. This special TLB
flush opcode only flushes an entry for the CPU it runs on, not across
all CPUs in the system.

Signed-off-by: Alexander Graf <alex@csgraf.de>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6749 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-07 20:52:22 +00:00
blueswir1
f6b868fc58 Implement slbmte
In order to modify SLB entries on recent PPC64 machines, the slbmte
instruction is used.

This patch implements the slbmte instruction and makes the "bridge"
mode code use the slb set functions, so we can move the SLB into
the CPU struct later.

This is required for Linux to run on PPC64.

Signed-off-by: Alexander Graf <alex@csgraf.de>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6747 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-07 20:50:01 +00:00
blueswir1
50773fd23d Sparse fixes: add extern to ELF opcode tables to avoid warnings
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6740 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-07 15:59:09 +00:00
aurel32
0cfe11ea5f target-ppc: improve mfcr/mtcrf
- use ctz32 instead of ffs - 1
- small optimisation of mtcrf
- add the name of both opcodes

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6669 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-03 06:12:14 +00:00
malc
8dd640e49d Fix mtcrf/mfcr
Noticed by Alexander Graf

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6667 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-02 22:39:39 +00:00
blueswir1
a457e7ee3d Fix typo in gen_qemu_ld32s
When the CPU is in little endian mode, it should load values from RAM
in byte swapped manner. This check is in all the ld and st functions,
but misspelled in gen_qemu_ld32s.

This patch fixes the misspelling and makes ppc64 Linux happier.

Signed-off-by: Alexander Graf <alex@csgraf.de>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6654 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-28 08:25:29 +00:00
blueswir1
5518f3a636 Fix branch debugging
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6629 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-19 20:17:09 +00:00
aurel32
40569b7edc target-ppc: Model SPE floating-point instructions more accurately
Single-precision and double-precision floating-point instructions should
be separated into their own categories, since some chips only support
single-precision instructions.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6575 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-09 16:49:50 +00:00
aurel32
071fc3b1cd target-ppc: Add vrsqrtefp instruction
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6574 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-09 16:49:40 +00:00
aurel32
bdfbac3512 target-ppc: Add vrefp instruction
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6573 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-09 16:49:29 +00:00
aurel32
875b31db7f target-ppc: Add vct{u,s}xs instructions
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6572 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-09 16:49:20 +00:00
aurel32
819ca12127 target-ppc: Add vcmp{eq, ge, gt, b}fp{, .} instructions
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6571 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-09 16:49:10 +00:00
aurel32
35cf7c7e18 target-ppc: Add vmaddfp and vnmsubfp instructions
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6570 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-09 16:48:59 +00:00
aurel32
56fdd213ef target-ppc: Add v{add,sub}fp instructions
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6569 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-09 16:48:51 +00:00
aurel32
1536ff641f target-ppc: Add v{max,min}fp instructions
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6568 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-09 16:48:39 +00:00
aurel32
b580763f86 target-ppc: change instruction name vrlogefp into vlogefp
Thanks to Nathan Froyd for noticing that.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6532 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-05 22:33:36 +00:00
aurel32
f586ce09e2 target-ppc: add vrlogefp instruction
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6519 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-05 13:42:57 +00:00
aurel32
e140632e87 Add vcf{u,s}x instructions
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6513 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-04 13:52:17 +00:00
aurel32
f6b1964548 Add vrfi{m,n,p,z} instructions
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6512 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-04 13:52:03 +00:00
aurel32
6e87b7c7bf Make mtvscr use a helper
Do this so we can set float statuses once per mtvscr, rather than once
per Altivec instruction.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6508 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-03 19:56:09 +00:00
aurel32
fce5ecb780 Fix compilation of PPC64 targets with DEBUG_TCGV enabled
The attached patch fixes compilation of PPC64 targets with DEBUG_TCGV
enabled.

Signed-off-by: Stuart Brady <stuart.brady@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6502 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-03 19:55:13 +00:00
aliguori
8fec2b8c45 global s/loglevel & X/qemu_loglevel_mask(X)/ (Eduardo Habkost)
These are references to 'loglevel' that aren't on a simple 'if (loglevel &
X) qemu_log()' statement.

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6340 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-15 22:36:53 +00:00
aliguori
93fcfe39a0 Convert references to logfile/loglevel to use qemu_log*() macros
This is a large patch that changes all occurrences of logfile/loglevel
global variables to use the new qemu_log*() macros.

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6338 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-15 22:34:14 +00:00
aliguori
d12d51d5ba Clean up debugging code #ifdefs (Eduardo Habkost)
Use macros to avoid #ifdefs on debugging code.

This patch doesn't try to merge logging macros from different files,
but just unify the debugging code #ifdefs onto a macro on each file. A
further cleanup can unify the debugging macros on a common header, later

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6332 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-15 21:48:06 +00:00
aurel32
1b6e5f9906 target-ppc: fix wrteei instruction
Patch by Andrew May

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6308 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-14 19:40:54 +00:00
aurel32
ae1c1a3d68 target-ppc: add altivec cache instructions
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6275 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-12 21:33:02 +00:00