Commit Graph

48 Commits

Author SHA1 Message Date
Peter Maydell c79981ceec hw/arm_gic: Remove stray hardcoded tab
Remove the single instance of a hardcoded tab from hw/arm_gic.c.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-13 12:29:04 +00:00
Peter Maydell b7dc1a597a hw/arm_gic: gic_set_pending_private() is NVIC only
The function gic_set_pending_private() is now used by the NVIC
only (for the GIC we now set PPI interrupts via gpio lines and
gic_set_irq()). So make it #ifdef NVIC and remove the 'attribute
unused' annotation.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-13 12:29:04 +00:00
Peter Maydell 0d256bdc8f hw/arm_gic: Use NVIC instead of LEGACY_INCLUDED_GIC define
Now all the A profile cores have been switched to use the standalone
sysbus GIC, the only remaining code which #includes arm_gic.c is
the v7M NVIC. The coupling is much closer here so it's not so
easily disentangled. For now, add a comment about how arm_gic.c
is compiled, and assume that the NVIC always includes arm_gic.c
and the non-NVIC GIC is always compiled standalone.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-13 12:29:04 +00:00
Peter Maydell aecff6924d hw/arm_gic: Make gic_reset a sysbus reset function
Make gic_reset a sysbus reset function, so we actually
reset the GIC on system reset rather than only at init.
For the NVIC this requires us also to implement reset
of the SysTick.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-13 12:29:04 +00:00
Peter Maydell 496dbcd1a3 hw/arm_gic: Make the GIC its own sysbus device
Compile arm_gic.c as a standalone C file to produce a self contained
sysbus GIC device. Support the legacy usage by #include of the .c file
by making those users #define LEGACY_INCLUDED_GIC, so we can convert
them one by one.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Evgeny Voevodin <e.voevodin@samsung.com>
2012-04-13 11:39:07 +00:00
Peter Maydell 544d1afa70 hw/arm_gic: Expose PPI inputs as gpio inputs
Expose the Private Peripheral Interrupt inputs as GPIO inputs.
The layout of the GPIO array is thus:
  [0..N-1] SPIs
  [N..N+31] PPIs for CPU 0
  [N+32..N+63] PPIs for CPU 1
  ...

Treating PPIs as being another kind of input line is in line with the
GIC architecture specification, where they are clearly described that
way. The 11MPCore TRM is a bit more ambiguous, but there is no practical
difference between "set PPI X as pending" and "0->1 transition on a
PPI input line configured as edge triggered", and PPIs are always
edge triggered, so this change won't affect behaviour.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-13 11:39:07 +00:00
Peter Maydell 926c4aff6e hw/arm_gic: Move gic_get_current_cpu into arm_gic.c
Move the gic_get_current_cpu() function into arm_gic.c.
There are only two implementations: (1) "get the index
of the currently executing CPU", used by all multicore
GICs, and (2) "always 0", used by all GICs instantiated
with a single CPU interface (the Realview board GIC and
the v7M NVIC). So we can move this into the main GIC
source file.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Evgeny Voevodin <e.voevodin@samsung.com>
2012-04-13 11:39:07 +00:00
Peter Maydell 386e29554e hw/arm_gic: Move NCPU definition to arm_gic.c
Move the NCPU definition to arm_gic.c: the maximum number
of CPU interfaces is defined by the GIC architecture specification
to be 8, so we don't need to have this #define in each of the
sources files which currently includes arm_gic.c.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Evgeny Voevodin <e.voevodin@samsung.com>
2012-04-13 11:39:07 +00:00
Peter Maydell 0e4a398ab2 ARM: Remove unnecessary subpage workarounds
In the ARM per-CPU peripherals (GIC, private timers, SCU, etc),
remove workarounds for subpage memory region read/write functions
being passed offsets from the start of the page rather than the
start of the region. Following commit 5312bd8b3 the masking off
of high bits of the address offset is now harmless but unnecessary.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Andreas Färber <afaerber@suse.de>
2012-03-16 18:09:55 +00:00
Rusty Russell 41c1e2f54e arm: make sure that number of irqs can be represented in GICD_TYPER.
We currently assume that the number of interrupts (ITLinesNumber in
the architecture reference manual) is divisible by 32, since we
present it to the guest when it reads GICD_TYPER (in gic_dist_readb())
as (N / 32) - 1.

Signed-off-by: Rusty Russell <rusty@rustcorp.com.au>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-03-02 11:56:38 +00:00
Rusty Russell 6925380062 arm: clean up GIC constants
Interrupts numbers 0-31 are private to the processor interface, 32-1019 are
general interrupts.  Add GIC_INTERNAL and substitute everywhere.

Signed-off-by: Rusty Russell <rusty@rustcorp.com.au>
[Peter Maydell: converted some tabs to spaces]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-03-02 11:56:38 +00:00
Mark Langsdorf a32134aad8 arm: make the number of GIC interrupts configurable
Increase the maximum number of GIC interrupts for a9mp and a11mp to 1020,
and create a configurable property for each defaulting to 96 and 64
(respectively) so that device modelers can set the value appropriately
for their SoC. Other ARM processors also set their maximum number of
used IRQs appropriately.

Set the maximum theoretical number of GIC interrupts to 1020 and
update the save/restore code to only use the appropriate number for
each SoC.

Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com>
Reviewed-by: Andreas Färber <afaerber@suse.de>
[Peter Maydell: fixed minor whitespace snafu]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-01-17 10:54:07 +00:00
Rob Herring b79f22656f arm: add dummy gic security registers
Implement handling for the RAZ/WI gic security registers.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-01-04 13:41:42 +00:00
Anthony Liguori 9423a2e8dd Merge remote-tracking branch 'stefanha/trivial-patches-next' into staging 2011-12-14 07:59:21 -06:00
Peter Maydell e2c564657c hw/arm_gic: Expose GIC CPU interfaces as sysbus memory regions
Expose the ARM GIC CPU interfaces as memory regions, rather than
just providing read and write functions for them.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-12-12 10:26:31 +00:00
Dong Xu Wang 66a0a2cb81 fix spelling in hw sub directory
Correct obvious spelling errors in qemu/hw directory.

Signed-off-by: Dong Xu Wang <wdongxu@linux.vnet.ibm.com>
Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2011-12-06 09:56:41 +00:00
Peter Maydell 217bfb445b hw/arm_gic.c: Ignore attempts to complete nonexistent IRQs
Ignore attempts to complete non-existent IRQs; this fixes a buffer
overrun if the guest writes a bad value to the GICC_EOIR register.
(This case is UNPREDICTABLE so ignoring it is a valid choice.)
Note that doing nothing if the guest writes 1023 to this register
is not in fact a change in behaviour: the old code would also
always do nothing in this case but in a non-obvious way.
(The buffer overrun was noted by Coverity, see bug 887883.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2011-12-05 21:38:56 +01:00
Rabin Vincent 41bf234d8e arm_gic: handle banked enable bits for per-cpu interrupts
The first enable set/clear register (which controls the PPIs and SGIs)
is supposed to be banked for each processor.  Currently it is just
handled globally and this prevents recent SMP Linux kernels from
booting, because CPU0 stops receiving localtimer interrupts when CPU1
disables them locally.

To fix this, allow the enable bits to be enabled per-cpu.  For SPIs,
always enable/disable ALL_CPU_MASK.

Signed-off-by: Rabin Vincent <rabin@rab.in>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-11-06 16:01:08 +00:00
Dmitry Koshelev c2e2343e1f hw/arm_gic.c: Fix save/load of irq_target array
irq_target array saving/loading is in the wrong loop.
Version bump.

Signed-off-by: Dmitry Koshelev <karaghiozis@gmail.com>
Acked-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2011-10-21 17:19:56 +02:00
Avi Kivity 755c080225 arm_gic: convert to memory API
Signed-off-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2011-08-22 10:20:10 -05:00
Matthew Fernandez 8e31bf388e Correct spelling of licensed
Correct typos of "licenced" to "licensed".

Reviewed-by: Stefan Weil <weil@mail.berlios.de>
Reviewed-by: Andreas F=E4rber <andreas.faerber@web.de>
Signed-off-by: Matthew Fernandez <matthew.fernandez@gmail.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2011-07-23 11:26:12 -05:00
Adam Lackorzynski fa25014441 target-arm: Fix soft interrupt in GIC distributor
Fix selection of target list filter mode.

Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-06 23:37:17 +01:00
Alexander Graf 2507c12ab0 Add endianness as io mem parameter
As stated before, devices can be little, big or native endian. The
target endianness is not of their concern, so we need to push things
down a level.

This patch adds a parameter to cpu_register_io_memory that allows a
device to choose its endianness. For now, all devices simply choose
native endian, because that's the same behavior as before.

Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-12-11 15:24:25 +00:00
Alex Williamson 0be71e324f savevm: Add DeviceState param
When available, we'd like to be able to access the DeviceState
when registering a savevm.  For buses with a get_dev_path()
function, this will allow us to create more unique savevm
id strings.

Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2010-07-06 10:36:28 -05:00
Paul Brook f7c703250c ARM PBX-A9 board support
Implement ARM RealView PBX-A9 board support.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-11-19 16:45:21 +00:00
Paul Brook c988bfadc9 ARM MPCore tweaks
Allow the user to specify the number of cores present on the
RealView EB + ARM11MPCore board.  Also split into its own config
rather than guessing from the CPU name.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-11-13 04:31:22 +00:00
Anthony Liguori c227f0995e Revert "Get rid of _t suffix"
In the very least, a change like this requires discussion on the list.

The naming convention is goofy and it causes a massive merge problem.  Something
like this _must_ be presented on the list first so people can provide input
and cope with it.

This reverts commit 99a0949b72.

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-01 16:12:16 -05:00
malc 99a0949b72 Get rid of _t suffix
Some not so obvious bits, slirp and Xen were left alone for the time
being.

Signed-off-by: malc <av1474@comtv.ru>
2009-10-01 22:45:02 +04:00
Blue Swirl d60efc6b0d Make CPURead/WriteFunc structure 'const'
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-08-25 18:29:31 +00:00
Avi Kivity 1eed09cb4a Remove io_index argument from cpu_register_io_memory()
The parameter is always zero except when registering the three internal
io regions (ROM, unassigned, notdirty).  Remove the parameter to reduce
the API's power, thus facilitating future change.

Signed-off-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-06-16 15:18:37 -05:00
Paul Brook 067a3ddc88 Remove qdev irq sink handling
We have both IRQ sinks and GPIO inputs.  These are in principle exactly
the same thing, so remove the former.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-05-26 14:56:11 +01:00
Paul Brook fe7e8758d0 ARM GIC qdev conversion
Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-05-14 22:35:08 +01:00
Blue Swirl 001faf3269 Replace gcc variadic macro extension with C99 version
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-05-13 17:53:17 +00:00
Paul Brook 2ac711791b Replace cpu_abort with hw_error
Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-05-08 02:35:15 +01:00
aurel32 a45db6c6fd arm: Fix gic_irq_state.level bitfield type
Found while cleaning up compiler warnings: GIC_*_LEVEL macros strongly
suggest that gic_irq_state.level is intended to be per-CPU and not just
a single, global bit. I'm unable to test the effect, but it seems to be
the most reasonable fix for the apparent brokenness.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6765 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-07 21:47:53 +00:00
aliguori 487414f1cb hw: remove error handling from qemu_malloc() callers (Avi Kivity)
Signed-off-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6529 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-05 22:06:05 +00:00
pbrook 8da3ff1809 Change MMIO callbacks to use offsets, not absolute addresses.
Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5849 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-01 18:59:50 +00:00
pbrook 23e3929403 Save/restore for stellaris boards.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4824 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-02 16:48:32 +00:00
balrog 57d69a91c4 Force correct evaluation order in a a == b != c condition.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4358 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-06 14:45:30 +00:00
pbrook e57ec0168c ARMv7-M SysTick fix.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3727 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-24 03:09:07 +00:00
pbrook 9ee6e8bb85 ARMv7 support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3572 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-11 00:04:49 +00:00
ths 5fafdf24ef find -type f | xargs sed -i 's/[\t ]$//g' # on most files
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3173 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-16 21:08:06 +00:00
ths bea6030dcf arm_gic.c error message fix, by Adam Lackorzynski.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3153 c046a42c-6fe2-441c-8c8c-71466251a162
2007-08-26 17:50:07 +00:00
pbrook 187337f8b0 Fix off-by-one memory region sizes.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2931 c046a42c-6fe2-441c-8c8c-71466251a162
2007-06-03 15:19:33 +00:00
pbrook d537cf6c86 Unify IRQ handling.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2635 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-07 18:14:41 +00:00
pbrook df628ff14e Arm GIC stuck interrupt fix.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2286 c046a42c-6fe2-441c-8c8c-71466251a162
2007-01-02 19:33:15 +00:00
pbrook 326199c270 ARM GIC bug.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2187 c046a42c-6fe2-441c-8c8c-71466251a162
2006-10-01 13:03:52 +00:00
pbrook e69954b9fc Add ARM RealView Emulation Baseboard.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2164 c046a42c-6fe2-441c-8c8c-71466251a162
2006-09-23 17:40:58 +00:00