qemu-e2k/target/riscv
Christoph Müllner af99aa72ef RISC-V: Adding T-Head MemPair extension
This patch adds support for the T-Head MemPair instructions.
The patch uses the T-Head specific decoder and translation.

Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230131202013.2541053-9-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-02-07 08:19:23 +10:00
..
insn_trans RISC-V: Adding T-Head MemPair extension 2023-02-07 08:19:23 +10:00
arch_dump.c dump: Replace opaque DumpState pointer with a typed one 2022-10-06 19:30:43 +04:00
bitmanip_helper.c
common-semi-target.h
cpu_bits.h target/riscv: Add smstateen support 2023-01-06 10:42:55 +10:00
cpu_helper.c target/riscv: set tval for triggered watchpoints 2023-02-07 08:19:23 +10:00
cpu_user.h
cpu-param.h
cpu.c RISC-V: Adding T-Head MemPair extension 2023-02-07 08:19:23 +10:00
cpu.h RISC-V: Adding T-Head MemPair extension 2023-02-07 08:19:23 +10:00
crypto_helper.c
csr.c target/riscv: Update VS timer whenever htimedelta changes 2023-02-07 08:19:22 +10:00
debug.c target/riscv: set tval for triggered watchpoints 2023-02-07 08:19:23 +10:00
debug.h target/riscv: Add itrigger support when icount is enabled 2023-01-06 10:42:55 +10:00
fpu_helper.c target/riscv: Remove helper_set_rod_rounding_mode 2023-01-20 10:14:14 +10:00
gdbstub.c target/riscv: Check the correct exception cause in vector GDB stub 2022-09-27 07:04:38 +10:00
helper.h RISC-V: Adding XTheadSync ISA extension 2023-02-07 08:19:23 +10:00
insn16.decode
insn32.decode RISC-V: Add Zawrs ISA extension support 2023-01-06 10:42:55 +10:00
instmap.h
internals.h
Kconfig
kvm_riscv.h
kvm-stub.c
kvm.c kvm: allow target-specific accelerator properties 2022-10-10 09:23:16 +02:00
m128_helper.c
machine.c hw/char: riscv_htif: Move registers from CPUArchState to HTIFState 2023-01-20 10:14:13 +10:00
meson.build RISC-V: Adding XTheadCmo ISA extension 2023-02-07 08:19:23 +10:00
monitor.c bulk: Rename TARGET_FMT_plx -> HWADDR_FMT_plx 2023-01-18 11:14:34 +01:00
op_helper.c RISC-V: Adding XTheadSync ISA extension 2023-02-07 08:19:23 +10:00
pmp.c target/riscv: Fix PMP propagation for tlb 2023-01-06 10:42:55 +10:00
pmp.h target/riscv: Fix PMP propagation for tlb 2023-01-06 10:42:55 +10:00
pmu.c hw/riscv: virt: Add PMU DT node to the device tree 2022-09-07 09:19:15 +02:00
pmu.h hw/riscv: virt: Add PMU DT node to the device tree 2022-09-07 09:19:15 +02:00
sbi_ecall_interface.h
time_helper.c target/riscv: No need to re-start QEMU timer when timecmp == UINT64_MAX 2023-02-07 08:19:23 +10:00
time_helper.h
trace-events
trace.h
translate.c RISC-V: Adding T-Head MemPair extension 2023-02-07 08:19:23 +10:00
vector_helper.c cleanup: Tweak and re-run return_directly.cocci 2022-12-14 16:19:35 +01:00
xthead.decode RISC-V: Adding T-Head MemPair extension 2023-02-07 08:19:23 +10:00
XVentanaCondOps.decode