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include/opcode/ * mips.h: Document MIPS16 "I" opcode. opcodes/ * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands in macros. gas/ * config/tc-mips.c (mips16_ip): Handle "I".
2013-07-14 15:11:03 +02:00
2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
* mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
in macros.
opcodes/ * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for ADDA.S, MULA.S and SUBA.S.
2013-07-14 15:07:50 +02:00
2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
* mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
ADDA.S, MULA.S and SUBA.S.
Replace Xmmword with Qword on cvttps2pi gas/testsuite/ PR gas/13572 * gas/i386/simd.s: Add a test for cvttps2pi. * gas/i386/simd-intel.d: Updated. * gas/i386/simd.d: Likewise. opcodes/ PR gas/13572 * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi. * i386-tbl.h: Regenerated.
2013-07-08 18:24:21 +02:00
2013-07-08 H.J. Lu <hongjiu.lu@intel.com>
PR gas/13572
* i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
* i386-tbl.h: Regenerated.
include/opcode/ * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB) (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB) (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A) (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB) (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB) (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB) (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB) (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB) (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A) (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A) (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB) (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete. (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A): Rename to... (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB) (M_USD_AB): ...these. opcodes/ * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD and SD A(B) macros up. * micromips-opc.c (micromips_opcodes): Likewise. gas/ * config/tc-mips.c (gprel16_reloc_p): New function. (macro_read_relocs): Assume BFD_RELOC_LO16 if all relocs are BFD_RELOC_UNUSED. (offset_high_part, small_offset_p): New functions. (nacro): Use them. Remove *_OB and *_DOB cases. For single- register load and store macros, handle the 16-bit offset case first. If a 16-bit offset is not suitable for the instruction we're generating, load it into the temporary register using ADDRESS_ADDI_INSN. Make the M_LI_DD code fall through into the M_L_DAB code once the address has been constructed. For double load and store macros, again handle the 16-bit offset case first. If the second register cannot be accessed from the same high part as the first, load it into AT using ADDRESS_ADDI_INSN. Fix the handling of LD in cases where the first register is the same as the base. Also handle the case where the offset is not 16 bits and the second register cannot be accessed from the same high part as the first. For unaligned loads and stores, fuse the offbits == 12 and old "ab" handling. Apply this handling whenever the second offset needs a different high part from the first. Construct the offset using ADDRESS_ADDI_INSN where possible, for offbits == 16 as well as offbits == 12. Use offset_reloc when constructing the individual loads and stores. (mips_ip): Set up imm_expr, imm2_expr, offset_expr, imm_reloc and offset_reloc before matching against a particular opcode. Handle elided 'A' constants. Allow 'A' constants to use relocation operators. gas/testsuite/ * gas/mips/ldstla-32.d: Avoid "lui at,0x0" sequences for truncated constants. * gas/mips/ldstla-32-shared.d: Likewise. * gas/mips/mcu.d: Use ADDIU in preference to LI+ADDU when adding 16-bit constants to the base. * gas/mips/micromips@mcu.d: Likewise. * gas/mips/micromips@cache.d: Likewise. * gas/mips/micromips@pref.d: Likewise. * gas/mips/micromips.d, gas/mips/micromips-insn32.d, gas/mips/micromips-noinsn32.d, gas/mips/micromips-trap.d: Likewise. Allow the full 16-bit offset range to be used for SB, LB and LBU in USH and ULH sequences. Fix the expected output for LD and SD when the two LW and SW offsets need different high parts. * gas/mips/eva.s: Test PREFE with relocation operators. * gas/mips/eva.d: Use ADDIU in preference to LI+ADDU for 16-bit constants. Update after eva.s change. * gas/mips/micromips@eva.d: Likewise. * gas/mips/ld-reloc.s, gas/mips/ld-reloc.d, gas/mips/l_d-reloc.s, gas/mips/l_d-reloc.d, gas/mips/ulw-reloc.s, gas/mips/ulw-reloc.d, gas/mips/micromips@ulw-reloc.d, gas/mips/ulh-reloc.s, gas/mips/ulh-reloc.d: New tests. * gas/mips/mips.exp: Run them.
2013-07-07 13:32:32 +02:00
2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
* mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD
and SD A(B) macros up.
* micromips-opc.c (micromips_opcodes): Likewise.
opcodes/ * mips16-opc.c: Add entries for argumentless "entry" and "exit" instructions. gas/testsuite/ * gas/mips/mips16.d, gas/mips/mips16-64.d: Remove trailing whitespace from ENTRY and EXIT lines.
2013-07-07 12:27:32 +02:00
2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
* mips16-opc.c: Add entries for argumentless "entry" and "exit"
instructions.
include/opcode/ * mips.h: Remove documentation of "[" and "]". Update documentation of "k" and the MDMX formats. opcodes/ * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400 MDMX-like instructions. * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when printing "Q" operands for INSN_5400 instructions. gas/ * config/tc-mips.c (validate_mips_insn): Remove "[" and "]" handling. (mips_ip): Likewise. Do not set is_mdmx for INSN_5400 instructions. Check constraints on the VR5400 RZU.OB, SLL.OB and SRL.OB instructions. gas/testsuite/ * gas/mips/vr5400-ill.s, gas/mips/vr5400-ill.l: New test. * gas/mips/mips.exp: Run it.
2013-07-07 12:15:09 +02:00
2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
* mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
MDMX-like instructions.
* mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
printing "Q" operands for INSN_5400 instructions.
include/opcode/ * mips.h: Update documentation of "+s" and "+S". opcodes/ * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and "+S" for "cins". * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments. Combine cases. gas/ * config/tc-mips.c (mips_ip): Preserve the real bit number for "+p". Require the msb to be <= 31 for "+s". Check that the size is <= 31 for both "+s" and "+S".
2013-07-07 12:00:43 +02:00
2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
* mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
"+S" for "cins".
* mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
Combine cases.
include/opcode/ * mips.h: Document "+i". opcodes/ * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for "jalx". * mips16-opc.c (mips16_opcodes): Likewise. * micromips-opc.c (micromips_opcodes): Likewise. * mips-dis.c (print_insn_args, print_mips16_insn_arg) (print_insn_mips16): Handle "+i". (print_insn_micromips): Likewise. Conditionally preserve the ISA bit for "a" but not for "+i". gas/ * config/tc-mips.c (validate_mips_insn, validate_micromips_insn): (mips_ip, mips16_ip): Handle "+i".
2013-07-07 11:50:43 +02:00
2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
* mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
"jalx".
* mips16-opc.c (mips16_opcodes): Likewise.
* micromips-opc.c (micromips_opcodes): Likewise.
* mips-dis.c (print_insn_args, print_mips16_insn_arg)
(print_insn_mips16): Handle "+i".
(print_insn_micromips): Likewise. Conditionally preserve the
ISA bit for "a" but not for "+i".
include/opcode/ * mips.h: Remove "mi" documentation. Update "mh" documentation. (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI): Delete. (INSN2_WRITE_GPR_MHI): Rename to... (INSN2_WRITE_GPR_MH): ...this. opcodes/ * micromips-opc.c (WR_mhi): Rename to.. (WR_mh): ...this. (micromips_opcodes): Update "movep" entry accordingly. Replace "mh,mi" with "mh". * mips-dis.c (micromips_to_32_reg_h_map): Rename to... (micromips_to_32_reg_h_map1): ...this. (micromips_to_32_reg_i_map): Rename to... (micromips_to_32_reg_h_map2): ...this. (print_micromips_insn): Remove "mi" case. Print both registers in the pair for "mh". gas/ * config/tc-mips.c (mips32_to_micromips_reg_h_map): Delete. (micromips_to_32_reg_h_map): Rename to... (micromips_to_32_reg_h_map1): ...this. (micromips_to_32_reg_i_map): Rename to... (micromips_to_32_reg_h_map2): ...this. (mips_lookup_reg_pair): New function. (gpr_write_mask, macro): Adjust after above renaming. (validate_micromips_insn): Remove "mi" handling. (mips_ip): Likewise. Parse both registers in a pair for "mh".
2013-07-07 11:41:04 +02:00
2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
* micromips-opc.c (WR_mhi): Rename to..
(WR_mh): ...this.
(micromips_opcodes): Update "movep" entry accordingly. Replace
"mh,mi" with "mh".
* mips-dis.c (micromips_to_32_reg_h_map): Rename to...
(micromips_to_32_reg_h_map1): ...this.
(micromips_to_32_reg_i_map): Rename to...
(micromips_to_32_reg_h_map2): ...this.
(print_micromips_insn): Remove "mi" case. Print both registers
in the pair for "mh".
include/opcode/ * mips.h: Remove documentation of "+D" and "+T". opcodes/ * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries. * micromips-opc.c (micromips_opcodes): Likewise. * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D" and "+T" handling. Check for a "0" suffix when deciding whether to use coprocessor 0 names. In that case, also check for ",H" selectors. gas/ * config/tc-mips.c (validate_mips_insn, validate_micromips_insn) (mips_ip): Remove "+D" and "+T" handling. gas/testsuite/ * gas/mips/lb.d, gas/mips/sb.d: Use coprocessor register names for LWC0 and SWC0.
2013-07-07 11:32:55 +02:00
2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
* mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
* micromips-opc.c (micromips_opcodes): Likewise.
* mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
and "+T" handling. Check for a "0" suffix when deciding whether to
use coprocessor 0 names. In that case, also check for ",H" selectors.
2013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> opcodes/ * s390-opc.c (J12_12, J24_24): New macros. (INSTR_MII_UPI): Rename to INSTR_MII_UPP. (MASK_MII_UPI): Rename to MASK_MII_UPP. * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction. include/elf/ * s390.h: Add new relocs R_390_PC12DBL, R_390_PLT12DBL, R_390_PC24DBL, and R_390_PLT24DBL. gas/testsuite/ * gas/s390/zarch-zEC12.s: Change bprp second operand and add variants requiring relocations. * gas/s390/zarch-zEC12.d: Likewise. gas/ * config/tc-s390.c (md_gather_operands, md_apply_fix): Support new relocs. bfd/ * elf32-s390.c: Add new relocation definitions R_390_PC12DBL, R_390_PLT12DBL, R_390_PC24DBL, and R_390_PLT24DBL. (elf_s390_reloc_type_lookup, elf_s390_check_relocs) (elf_s390_gc_sweep_hook, elf_s390_relocate_section): Support new relocations. * elf64-s390.c: See elf32-s390.c * bfd-in2.h: Add new relocs to enum bfd_reloc_code_real. * libbfd.h: Add new reloc strings.
2013-07-05 11:45:44 +02:00
2013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* s390-opc.c (J12_12, J24_24): New macros.
(INSTR_MII_UPI): Rename to INSTR_MII_UPP.
(MASK_MII_UPI): Rename to MASK_MII_UPP.
* s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
* ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
2013-07-04 03:42:08 +02:00
2013-07-04 Alan Modra <amodra@gmail.com>
* ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
* rx-decode.opc (rx_decode_opcode): Check sd field as well as ss field when checking for type 2 nop. * rx-decode.c: Regenerate.
2013-06-26 12:31:38 +02:00
2013-06-26 Nick Clifton <nickc@redhat.com>
* rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
field when checking for type 2 nop.
* rx-decode.c: Regenerate.
bfd/ * elfxx-mips.h (_bfd_mips_elf_insn32): New prototype. * elfxx-mips.c (mips_elf_link_hash_table): Add insn32 member. (STUB_MOVE32_MICROMIPS, STUB_JALR32_MICROMIPS): New macros. (MICROMIPS_INSN32_FUNCTION_STUB_NORMAL_SIZE): Likewise. (MICROMIPS_INSN32_FUNCTION_STUB_BIG_SIZE): Likewise. (micromips_insn32_o32_exec_plt0_entry): New variable. (micromips_insn32_o32_exec_plt_entry): Likewise. (_bfd_mips_elf_adjust_dynamic_symbol): Handle insn32 mode. (mips_elf_estimate_stub_size): Likewise. (_bfd_mips_elf_size_dynamic_sections): Likewise. (_bfd_mips_elf_finish_dynamic_symbol): Likewise. (mips_finish_exec_plt): Likewise. (_bfd_mips_elf_relax_section): Likewise. (_bfd_mips_elf_insn32): New function. (_bfd_mips_elf_get_synthetic_symtab): Handle insn32 PLT. gas/ * config/tc-mips.c (mips_set_options): Add insn32 member. (mips_opts): Initialize it. (NOP_INSN, NOP_INSN_SIZE): Handle insn32 mode. (options): Add OPTION_INSN32 and OPTION_NO_INSN32 enum values. (md_longopts): Add "minsn32" and "mno-insn32" options. (is_size_valid): Handle insn32 mode. (md_assemble): Pass instruction string down to macro. (brk_fmt): Add second dimension and insn32 mode initializers. (mfhl_fmt): Likewise. (BRK_FMT, MFHL_FMT): Handle insn32 mode. (macro_build) <'c'>: Handle microMIPS 32-bit BREAK encoding. (macro_build_jalr, move_register): Handle insn32 mode. (macro_build_branch_rs): Likewise. (macro): Handle insn32 mode. <M_JRADDIUSP>, <M_JRC>, <M_MOVEP>: New cases. (mips_ip): Handle insn32 mode. (md_parse_option): Handle OPTION_INSN32 and OPTION_NO_INSN32. (s_mipsset): Handle "insn32" and "noinsn32" pseudo-ops. (mips_handle_align): Handle insn32 mode. (md_show_usage): Add -minsn32 and -mno-insn32. * doc/as.texinfo (Target MIPS options): Add -minsn32 and -mno-insn32 options. (-minsn32, -mno-insn32): New options. * doc/c-mips.texi (MIPS Opts): Add -minsn32 and -mno-insn32 options. (MIPS assembly options): New node. Document .set insn32 and .set noinsn32. (MIPS-Dependent): List the new node. gas/testsuite/ * gas/mips/micromips-insn32.d: New test. * gas/mips/micromips-noinsn32.d: Likewise. * gas/mips/micromips.l: Rename to... * gas/mips/micromips-warn.l: ... this. * gas/mips/micromips.d: Update accordingly. * gas/mips/micromips-trap.d: Likewise. * gas/mips/micromips.l: New list test. * gas/mips/micromips.s: Add conditionals. * gas/mips/mips.exp: Run the new tests. include/opcode/ * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum values. ld/ * emultempl/mipself.em (insn32): New variable. (mips_create_output_section_statements): Handle insn32 mode. (PARSE_AND_LIST_PROLOGUE): New macro. (PARSE_AND_LIST_LONGOPTS): Likewise. (PARSE_AND_LIST_OPTIONS): Likewise. * gen-doc.texi: Set MIPS. * ld.texinfo: Likewise. (Options specific to MIPS targets): New section. (ld and MIPS family): New node. (Top, Machine Dependent): List the new node. opcodes/ * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc" and "movep" macros.
2013-06-25 20:02:34 +02:00
2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
* micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
and "movep" macros.
bfd/ * elfxx-mips.h (_bfd_mips_elf_get_synthetic_symtab): New prototype. * elf32-mips.c (elf_backend_plt_sym_val): Remove macro. (bfd_elf32_get_synthetic_symtab): New macro. * elfxx-mips.c (plt_entry): New structure. (mips_elf_link_hash_entry): Add use_plt_entry member. (mips_elf_link_hash_table): Rename plt_entry_size member to plt_mips_entry_size. Add plt_comp_entry_size, plt_mips_offset, plt_comp_offset, plt_got_index entries and plt_header_is_comp members. (STUB_LW_MICROMIPS, STUB_MOVE_MICROMIPS): New macros. (STUB_LUI_MICROMIPS, STUB_JALR_MICROMIPS): Likewise. (STUB_ORI_MICROMIPS, STUB_LI16U_MICROMIPS): Likewise. (STUB_LI16S_MICROMIPS): Likewise. (MICROMIPS_FUNCTION_STUB_NORMAL_SIZE): Likewise. (MICROMIPS_FUNCTION_STUB_BIG_SIZE): Likewise. (micromips_o32_exec_plt0_entry): New variable. (mips16_o32_exec_plt_entry): Likewise. (micromips_o32_exec_plt_entry): Likewise. (mips_elf_link_hash_newfunc): Initialize use_plt_entry. (mips_elf_output_extsym): Update to use gotplt_union's plist member rather than offset. (mips_elf_gotplt_index): Likewise. Remove the VxWorks restriction. Use MIPS_ELF_GOT_SIZE to calculate GOT address. (mips_elf_count_got_symbols): Update to use gotplt_union's plist member rather than offset. (mips_elf_calculate_relocation): Handle MIPS16/microMIPS PLT entries. (_bfd_mips_elf_create_dynamic_sections): Don't set PLT sizes here. (mips_elf_make_plt_record): New function. (_bfd_mips_elf_check_relocs): Update comment. Record occurences of JAL relocations that might need a PLT entry. (_bfd_mips_elf_adjust_dynamic_symbol): Update to use gotplt_union's plist member rather than offset. Set individual PLT entry sizes here. Handle MIPS16/microMIPS PLT entries. Don't set the symbol's value in the symbol table for PLT references here. Don't set the PLT or PLT GOT section sizes here. (mips_elf_estimate_stub_size): Handle microMIPS stubs. (mips_elf_allocate_lazy_stub): Likewise. (mips_elf_lay_out_lazy_stubs): Likewise. Define a _MIPS_STUBS_ magic symbol. (mips_elf_set_plt_sym_value): New function. (_bfd_mips_elf_size_dynamic_sections): Set PLT header size and PLT and PLT GOT section sizes here. Set the symbol values in the symbol table for PLT references here. Handle microMIPS annotation of the _PROCEDURE_LINKAGE_TABLE_ magic symbol. (_bfd_mips_elf_finish_dynamic_symbol): Update to use gotplt_union's plist member rather than offset. Handle MIPS16/microMIPS PLT entries. Handle microMIPS stubs. (_bfd_mips_vxworks_finish_dynamic_symbol): Update to use gotplt_union's plist member rather than offset. Use MIPS_ELF_GOT_SIZE to calculate GOT address. (mips_finish_exec_plt): Handle microMIPS PLT. Return status. (_bfd_mips_elf_finish_dynamic_sections): Handle result from mips_finish_exec_plt. (_bfd_mips_elf_link_hash_table_create): Update to use gotplt_union's plist member rather than offset. (_bfd_mips_elf_get_synthetic_symtab): New function. include/elf/ * mips.h (ELF_ST_IS_MIPS_PLT): Respect STO_MIPS16 setting. (ELF_ST_SET_MIPS_PLT): Likewise. gdb/ * mips-tdep.c (mips_elf_make_msymbol_special): Handle MIPS16 and microMIPS synthetic symbols. ld/ * emulparams/elf32btsmip.sh: Arrange for .got.plt to be placed as close to .plt as possible. * scripttempl/elf.sc: Handle $INITIAL_READWRITE_SECTIONS and $PLT_NEXT_DATA variables. ld/testsuite/ * ld-mips-elf/jalx-2.dd: Update for microMIPS PLT support. * ld-mips-elf/pic-and-nonpic-3a.dd: Update for the _MIPS_STUBS_ magic symbol. * ld-mips-elf/pic-and-nonpic-3b.dd: Likewise. * ld-mips-elf/pic-and-nonpic-6-n32.dd: Likewise. * ld-mips-elf/pic-and-nonpic-6-n64.dd: Likewise. * ld-mips-elf/pic-and-nonpic-6-o32.dd: Likewise. * ld-mips-elf/stub-dynsym-1-10000.d: Likewise. * ld-mips-elf/stub-dynsym-1-2fe80.d: Likewise. * ld-mips-elf/stub-dynsym-1-7fff.d: Likewise. * ld-mips-elf/stub-dynsym-1-8000.d: Likewise. * ld-mips-elf/stub-dynsym-1-fff0.d: Likewise. * ld-mips-elf/tlslib-o32.d: Likewise. opcodes/ * mips-dis.c (is_mips16_plt_tail): New function. (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address word. (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
2013-06-25 01:55:46 +02:00
2013-06-24 Maciej W. Rozycki <macro@codesourcery.com>
* mips-dis.c (is_mips16_plt_tail): New function.
(print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
word.
(is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
* msp430-decode.opc: New. * msp430-decode.c: New/generated. * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c. (MAINTAINER_CLEANFILES): Likewise. Add rule to build msp430-decode.c frommsp430decode.opc using the opc2c program. * Makefile.in: Regenerate. * configure.in: Add msp430-decode.lo to msp430 architecture files. * configure: Regenerate. * msp430-decode.h: New.
2013-06-21 17:01:57 +02:00
2013-06-21 DJ Delorie <dj@redhat.com>
* msp430-decode.opc: New.
* msp430-decode.c: New/generated.
* Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
(MAINTAINER_CLEANFILES): Likewise.
Add rule to build msp430-decode.c frommsp430decode.opc
using the opc2c program.
* Makefile.in: Regenerate.
* configure.in: Add msp430-decode.lo to msp430 architecture files.
* configure: Regenerate.
bfd/ * bfd-in.h (bfd_elf64_aarch64_set_options): Add 'extern'. * bfd-in2.h: Re-generated. * elf64-aarch64.c (RELOC_SECTION): Removed. (SWAP_RELOC_IN, SWAP_RELOC_OUT): Ditto. (AARCH64_ELF_OS_ABI_VERSION): Ditto. (elf64_aarch64_link_hash_traverse): Ditto. (elf64_aarch64_size_stubs): Change 'Aarch64' to 'AArch64' in the comment. opcodes/ * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it. (SYMTAB_AVAILABLE): Removed. (#include "elf/aarch64.h): Ditto.
2013-06-20 18:01:35 +02:00
2013-06-20 Yufeng Zhang <yufeng.zhang@arm.com>
* aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
(SYMTAB_AVAILABLE): Removed.
(#include "elf/aarch64.h): Ditto.
2013-06-17 Catherine Moore <clm@codesourcery.com> Maciej W. Rozycki <macro@codesourcery.com> Chao-Ying Fu <fu@mips.com> gas/testsuite/ * gas/mips/mips.exp: Run new tests. * gas/mips/eva.d: New. * gas/mips/eva.s: New. * gas/mips/micromips@eva.d: New. gas/ * config/tc-mips.c (mips_set_options): Add ase_eva. (mips_set_options mips_opts): Add ase_eva. (file_ase_eva): Declare. (ISA_SUPPORTS_EVA_ASE): Define. (IS_SEXT_9BIT_NUM): Define. (MIPS_CPU_ASE_EVA): Define. (is_opcode_valid): Add support for ase_eva. (macro_build): Likewise. (macro): Likewise. (validate_mips_insn): Likewise. (validate_micromips_insn): Likewise. (mips_ip): Likewise. (options): Add OPTION_EVA and OPTION_NO_EVA. (md_longopts): Add -meva and -mno-eva. (md_parse_option): Process new options. (mips_after_parse_args): Check for valid EVA combinations. (s_mipsset): Likewise. include/ * opcode/mips.h (OP_SH_EVAOFFSET): Define. (OP_MASK_EVAOFFSET): Define. (INSN_ASE_MASK): Delete. (ASE_EVA): Define. (M_CACHEE_AB, M_CACHEE_OB): New. (M_LBE_OB, M_LBE_AB): New. (M_LBUE_OB, M_LBUE_AB): New. (M_LHE_OB, M_LHE_AB): New. (M_LHUE_OB, M_LHUE_AB): New. (M_LLE_AB, M_LLE_OB): New. (M_LWE_OB, M_LWE_AB): New. (M_LWLE_AB, M_LWLE_OB): New. (M_LWRE_AB, M_LWRE_OB): New. (M_PREFE_AB, M_PREFE_OB): New. (M_SCE_AB, M_SCE_OB): New. (M_SBE_OB, M_SBE_AB): New. (M_SHE_OB, M_SHE_AB): New. (M_SWE_OB, M_SWE_AB): New. (M_SWLE_AB, M_SWLE_OB): New. (M_SWRE_AB, M_SWRE_OB): New. (MICROMIPSOP_SH_EVAOFFSET): Define. (MICROMIPSOP_MASK_EVAOFFSET): Define. opcodes/ * micromips-opc.c (EVA): Define. (TLBINV): Define. (micromips_opcodes): Add EVA opcodes. * mips-dis.c (mips_arch_choices): Update for ASE_EVA. (print_insn_args): Handle EVA offsets. (print_insn_micromips): Likewise. * mips-opc.c (EVA): Define. (TLBINV): Define. (mips_builtin_opcodes): Add EVA opcodes.
2013-06-18 00:59:10 +02:00
2013-06-17 Catherine Moore <clm@codesourcery.com>
Maciej W. Rozycki <macro@codesourcery.com>
Chao-Ying Fu <fu@mips.com>
* micromips-opc.c (EVA): Define.
(TLBINV): Define.
(micromips_opcodes): Add EVA opcodes.
* mips-dis.c (mips_arch_choices): Update for ASE_EVA.
(print_insn_args): Handle EVA offsets.
(print_insn_micromips): Likewise.
* mips-opc.c (EVA): Define.
(TLBINV): Define.
(mips_builtin_opcodes): Add EVA opcodes.
* Makefile.am (mips-opc.lo): Add rules to create automatic dependency files. Pass archdefs. (micromips-opc.lo, mips16-opc.lo): Likewise. * Makefile.in: Regenerate.
2013-06-17 13:51:13 +02:00
2013-06-17 Alan Modra <amodra@gmail.com>
* Makefile.am (mips-opc.lo): Add rules to create automatic
dependency files. Pass archdefs.
(micromips-opc.lo, mips16-opc.lo): Likewise.
* Makefile.in: Regenerate.
* rx-decode.opc (rx_decode_opcode): Bit operations on registers are 32-bit operations, not 8-bit operations. * rx-decode.c: Regenerate.
2013-06-14 21:57:10 +02:00
2013-06-14 DJ Delorie <dj@redhat.com>
* rx-decode.opc (rx_decode_opcode): Bit operations on
registers are 32-bit operations, not 8-bit operations.
* rx-decode.c: Regenerate.
2013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com> * micromips-opc.c (IVIRT): New define. (IVIRT64): New define. (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0, tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions. * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0, dmtgc0 to print cp0 names.
2013-06-13 23:01:44 +02:00
2013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
* micromips-opc.c (IVIRT): New define.
(IVIRT64): New define.
(micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
* mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
dmtgc0 to print cp0 names.
2013-06-09 Sandra Loosemore <sandra@codesourcery.com> opcodes/ * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b" argument. gas/ * config/tc-nios2.c (nios2_parse_args): Allow trap argument to omitted. gas/testsuite/ * gas/nios2/trap.s: Add additional test cases for optional argument. * gas/nios2/trap.d: Likewise.
2013-06-10 03:04:42 +02:00
2013-06-09 Sandra Loosemore <sandra@codesourcery.com>
* nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
argument.
gas/ 2013-06-08 Catherine Moore <clm@codesourcery.com> * config/tc-mips.c (is_opcode_valid): Build ASE mask. (is_opcode_valid_16): Pass ase value to opcode_is_member. (append_insn): Change INSN_xxxx to ASE_xxxx. include/ 2013-06-08 Catherine Moore <clm@codesourcery.com> * opcode/mips.h (mips_opcode): Add ase field. (INSN_ASE_MASK): Delete. (INSN_DSP): Rename to ASE_DSP. Provide new value. (INSN_DSPR2): Rename to ASE_DSPR2. Provide new value. (INSN_MCU): Rename to ASE_MCU. Provide new value. (INSN_MDMX): Rename to ASE_MDMX. Provide new value. (INSN_MIPS3d): Rename to ASE_MIPS3D. Provide new value. (INSN_MT): Rename to ASE_MT. Provide new value. (INSN_SMARTMIPS): Rename to ASE_SMARTMIPS. Provide new value. (INSN_VIRT): Rename to ASE_VIRT. Provide new value. (INSN_VIRT64): Rename to ASE_VIRT64. Provide new value. (opcode_is_member): Add ase argument. Check ase. opcodes/ 2013-06-08 Catherine Moore <clm@codesourcery.com> Richard Sandiford <rdsandiford@googlemail.com> * micromips-opc.c (D32, D33, MC): Update definitions. (micromips_opcodes): Initialize ase field. * mips-dis.c (mips_arch_choice): Add ase field. (mips_arch_choices): Initialize ase field. (set_default_mips_dis_options): Declare and setup mips_ase. * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64, MT32, MC): Update definitions. (mips_builtin_opcodes): Initialize ase field.
2013-06-08 12:22:55 +02:00
2013-06-08 Catherine Moore <clm@codesourcery.com>
Richard Sandiford <rdsandiford@googlemail.com>
* micromips-opc.c (D32, D33, MC): Update definitions.
(micromips_opcodes): Initialize ase field.
* mips-dis.c (mips_arch_choice): Add ase field.
(mips_arch_choices): Initialize ase field.
(set_default_mips_dis_options): Declare and setup mips_ase.
* mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
MT32, MC): Update definitions.
(mips_builtin_opcodes): Initialize ase field.
opcodes/ * s390-opc.txt (flogr): Require a register pair destination. gas/testsuite/ * gas/s390/zarch-z9-109-err.s, gas/s390/zarch-z9-109-err.l: New test. * gas/s390/s390.exp: Run it.
2013-05-24 19:13:49 +02:00
2013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
* s390-opc.txt (flogr): Require a register pair destination.
2013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU instruction format. 2013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * gas/s390/zarch-zEC12.d: Adjust length operands for cdzt, cxzt, czdt, and czxt. * gas/s390/zarch-zEC12.d: Likewise.
2013-05-23 17:48:47 +02:00
2013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
instruction format.
include/opcode/ 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de> * mips.h (M_LQC2_AB, M_SQC2_AB): New macros. opcodes/ 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de> * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions. gas/ 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de> * config/tc-mips.c (macro): Handle M_LQC2_AB and M_SQC2_AB. gas/testsuite/ 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de> * gas/mips/r5900-full.s, gas/mips/r5900-full.d: Add tests for LQ and SQ macros. * gas/mips/r5900-vu0.s, gas/mips/r5900-vu0.d: New test. * gas/mips/mips.exp: Run it.
2013-05-22 20:08:26 +02:00
2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
* mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
opcodes/ * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8. * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK, XLS_MASK, PPCVSX2): New defines. (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb, fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe, mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp, mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd, mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx, vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher, vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd., vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd, vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw, vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor, vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh, vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox, vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq, vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp, xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp, xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp, xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp, xssubsp, xxleqv, xxlnand, xxlorc>: New instructions. <lxvx, stxvx>: New extended mnemonics. gas/ * config/tc-ppc.c (ppc_setup_opcodes): Use new_seg to fix error and clean up warning when using PRINT_OPCODE_TABLE. gas/testsuite/ * gas/ppc/altivec2.d <bcdadd., bcdadd., vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher, vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd., vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd, vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw, vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor, vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh, vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox, vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq, vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw>: Add new tests. * gas/ppc/altivec2.s: Likewise. * gas/ppc/power8.d <bcdadd., bcdsub., bctar, bctarl, clrbhrb, fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe, mfvsrd, mfvsrwz, msgclrp, msgsndp, mtsle, mtvsrd, mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx, vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher, vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd., vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd, vmaxud, vminsd, vminud, vmrgow, vmulesw, vmuleuw, vmulosw, vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor, vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh, vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox, vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq, vsubeuqm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp, xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp, xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp, xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp, xssubsp, xxleqv, xxlnand, xxlorc>: Add new tests. * gas/ppc/power8.s Likewise. * gas/ppc/vsx.d <lxvd2x, stxvd2x>: Add new tests. * gas/ppc/vsx.s Likewise. * gas/ppc/vsx2.d: New test file. * gas/ppc/vsx2.s: Likewise. * gas/ppc/ppc.exp: Run it.
2013-05-21 03:36:46 +02:00
2013-05-20 Peter Bergner <bergner@vnet.ibm.com>
* ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
* ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
XLS_MASK, PPCVSX2): New defines.
(powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
<lxvx, stxvx>: New extended mnemonics.
* ia64-raw.tbl: Replace non-ASCII char. * ia64-waw.tbl: Likewise. * ia64-asmtab.c: Regenerate.
2013-05-17 14:57:16 +02:00
2013-05-17 Alan Modra <amodra@gmail.com>
* ia64-raw.tbl: Replace non-ASCII char.
* ia64-waw.tbl: Likewise.
* ia64-asmtab.c: Regenerate.
gas/ * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS. * i386-init.h: Regenerated.
2013-05-15 07:06:23 +02:00
2013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
* i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
* i386-init.h: Regenerated.
gas/ * testsuite/gas/aarch64/diagnostic.s: Update. * testsuite/gas/aarch64/diagnostic.l: Ditto. * testsuite/gas/aarch64/movi.s: Add new tests. * testsuite/gas/aarch64/movi.d: Update. opcodes/ * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion. * aarch64-opc.c (operand_general_constraint_met_p): Relax the range check from [0, 255] to [-128, 255].
2013-05-14 00:28:27 +02:00
2013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
* aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
* aarch64-opc.c (operand_general_constraint_met_p): Relax the range
check from [0, 255] to [-128, 255].
binutils/ChangeLog: * doc/binutils.texi: Document -Mvirt disassembler option. gas/ChangeLog: * config/tc-mips.c (struct mips_set_options): New ase_virt field. (mips_opts): Update for the new field. (file_ase_virt): New variable. (ISA_SUPPORTS_VIRT_ASE): New macro. (ISA_SUPPORTS_VIRT64_ASE): New macro. (MIPS_CPU_ASE_VIRT): New define. (is_opcode_valid): Handle ase_virt. (macro_build): Handle "+J". (validate_mips_insn): Likewise. (mips_ip): Likewise. (enum options): Add OPTION_VIRT and OPTION_NO_VIRT. (md_longopts): Add mvirt and mnovirt (md_parse_option): Handle OPTION_VIRT and OPTION_NO_VIRT. (mips_after_parse_args): Handle ase_virt field. (s_mipsset): Handle "virt" and "novirt". (mips_elf_final_processing): Add a comment about virt ASE might need a new flag. (md_show_usage): Print out the usage of -mvirt and mno-virt options. * doc/c-mips.texi: Document -mvirt and -mno-virt. Document ".set virt" and ".set novirt". gas/testsuite/ChangeLog: * gas/mips/mips.exp: Run virt and virt64 testcases. * gas/mips/virt.d: New file. * gas/mips/virt.s: New file. * gas/mips/virt64.d: New file. * gas/mips/virt64.s: New file. include/opcode/ChangeLog: * mips.h (OP_MASK_CODE10): Correct definition. (OP_SH_CODE10): Likewise. Add a comment that "+J" is used now for OP_*CODE10. (INSN_ASE_MASK): Update. (INSN_VIRT): New macro. (INSN_VIRT64): New macro opcodes/ChangeLog: * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2 . Add INSN_VIRT and INSN_VIRT64 to mips64r2. (parse_mips_dis_option): Handle the virt option. (print_insn_args): Handle "+J". (print_mips_disassembler_options): Print out message about virt64. * mips-opc.c (IVIRT): New define. (IVIRT64): New define. (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0, tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions. Move rfe to the bottom as it conflicts with tlbgp.
2013-05-10 03:08:48 +02:00
2013-05-09 Andrew Pinski <apinski@cavium.com>
* mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
Add INSN_VIRT and INSN_VIRT64 to mips64r2.
(parse_mips_dis_option): Handle the virt option.
(print_insn_args): Handle "+J".
(print_mips_disassembler_options): Print out message about virt64.
* mips-opc.c (IVIRT): New define.
(IVIRT64): New define.
(mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
Move rfe to the bottom as it conflicts with tlbgp.
* ppc-opc.c (extract_vlesi): Properly sign extend. (extract_vlensi): Likewise. Comment reason for setting invalid.
2013-05-09 06:32:55 +02:00
2013-05-09 Alan Modra <amodra@gmail.com>
* ppc-opc.c (extract_vlesi): Properly sign extend.
(extract_vlensi): Likewise. Comment reason for setting invalid.
* archures.c: Add some more MSP430 machine numbers. * config.bfd (msp430): Define targ_selvecs. * configure.in: Add bfd_elf32_msp430_ti_vec. * cpu-msp430.c: Add some more MSP430 machine numbers. * elf32-msp430.c Add support for MSP430X relocations. Add support for TI compiler generated relocations. Add support for sym_diff relocations. Add support for relaxing out of range short branches into long branches. Add support for MSP430 attribute section. * reloc.c: Add MSP430X relocations. * targets.c: Add bfd_elf32_msp430_ti_vec. * bfd-in2.h: Regenerate. * configure: Regenerate. * libbfd.h: Regenerate. * readelf.c: Add support for MSP430X architecture. * readelf.exp: Expect -wi test to fail for the MSP430. * config/tc-msp430.c: Add support for the MSP430X architecture. Add code to insert a NOP instruction after any instruction that might change the interrupt state. Add support for the LARGE memory model. Add code to initialise the .MSP430.attributes section. * config/tc-msp430.h: Add support for the MSP430X architecture. * doc/c-msp430.texi: Document the new -mL and -mN command line options. * NEWS: Mention support for the MSP430X architecture. * gas/all/gas.exp: Skip the DIFF1 test for the MSP430. Expect the FORWARD test to pass for the MSP430. Skip the REDEF tests for the MSP430. Expect the 930509A test to fail for the MSP430. * gas/all/sleb128-4.d: Skip for the MSP430. * gas/elf/elf.exp: Set target_machine to msp430 for the MSP430. Skip the EHOPT0 test for the MSP430. Skip the REDEF and EQU-RELOC tests for the MSP430. * gas/elf/section2.e-msp430: New file. * gas/lns/lns-big-delta.d: Remove expectation of 20-bit addresses. * gas/lns/lns.exp: Use alternate LNS COMMON test for the MSP430. * gas/msp430/msp430x.s: New test. * gas/msp430/msp430x.d: Expected disassembly. * gas/msp430/msp430.exp: Run new test. * gas/msp430/opcode.d: Update expected disassembly. * msp430.h: Add MSP430X relocs. Add some more MSP430 machine numbers. Add values used by .MSP430.attributes section. * msp430.h: Add patterns for MSP430X instructions. * Makefile.am: Add emsp430X.c * Makefine.in: Regenerate. * configure.tgt (msp430): Add msp430X emulation. * ldmain.c (multiple_definition): Only disable relaxation if it was enabled by the user. * ldmain.h (RELAXATION_ENABLED_BY_USER): New macro. * emulparams/msp430all.sh: Add support for MSP430X. * emultempl/generic.em: (before_parse): Enable relaxation for the MSP430. * scripttempl/msp430.sc: Reorganize sections. Add .rodata section. * scripttempl/msp430_3.sc: Likewise. * NEWS: Mention support for MSP430X. * ld-elf/flags1.d: Expect this test to pass on the MSP430. * ld-elf/init-fini-arrays.d: Expect this test to fail on the MSP430. * ld-elf/merge.d: Expect this test to pass on the MSP430. * ld-elf/sec64k.exp: Skip these tests for the MSP430. * ld-gc/pr13683.d: Expect this test to fail on the MSP430. * ld-srec/srec.exp: Expect these tests to fail on the MSP430. * ld-undefined/undefined.exp: Expect the UNDEFINED LINE test to fail on the MSP430. * msp430-dis.c: Add support for MSP430X instructions.
2013-05-02 23:06:15 +02:00
2013-05-02 Nick Clifton <nickc@redhat.com>
* msp430-dis.c: Add support for MSP430X instructions.
2013-04-24 Sandra Loosemore <sandra@codesourcery.com> gas/ * config/tc-nios2.c (nios2_control_register_arg_p): Rename "fstatus" control register to "eccinj". opcodes/ * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register to "eccinj".
2013-04-24 22:51:58 +02:00
2013-04-24 Sandra Loosemore <sandra@codesourcery.com>
* nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
to "eccinj".
PR binutils/15369 * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead of CGEN_CPU_ENDIAN. (hash_insns_list): Likewise.
2013-04-17 16:09:49 +02:00
2013-04-17 Wei-chen Wang <cole945@gmail.com>
PR binutils/15369
* cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
of CGEN_CPU_ENDIAN.
(hash_insns_list): Likewise.
opcodes/ * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false warning workaround.
2013-04-10 21:16:45 +02:00
2013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
* rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
warning workaround.
gas/testsuite/ 2013-04-08 Jan Beulich <jbeulich@suse.com> * gas/i386/x86-64-opcode.s: Flesh out LOOP and J*CXZ sections. Correct comments in Jcc section. * gas/i386/x86-64-opcode.d: Refresh. * gas/i386/ilp32/x86-64-opcode.d: Refresh. opcodes/ 2013-04-08 Jan Beulich <jbeulich@suse.com> * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries. * i386-tbl.h: Re-generate.
2013-04-08 17:48:38 +02:00
2013-04-08 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
* i386-tbl.h: Re-generate.
Increase the accuracy of sparc instruction aliases. Make current with UA2011 specification. Add an F_PREFERRED opcode flag that indicates a preferred alias when multiple aliases for the same opcode exists. For 'lzd': Add 'lzcnt' as primary instruction, and make 'lzd' an alias. Add 'ldtw', 'ldtwa', 'sttw', 'sttwa': The modern opcode for for 'ldd', 'ldda', 'std', and 'stda' on integer registers. Mark the latter now as aliases. For 'flush': Support "[address]" syntax as well as plain "address". Rework 'mov' aliases for 'wr': Eliminate bogus three operand moves, and encode the instructions properly for the "mov REG, %ASR" cases, specifically we should encode the register in rs2 not rs1 as per The SPARC V8 Architecture Manual. Add missing cbcond aliases: c{w,x}bz, c{w,x}blu, c{w,x}bnz, c{w,x}bgeu Add 'd' suffix VIS logical ops: The primary opcode for 'fzero' is now 'fzerod' (compare with 'fzeros'), for example. And thus 'fzero' is now an alias. Add modern opcodes for condition code setting edge instructions: They are now edgeN{,l}cc instead of plain edgeN{,l}. Add modern opcodes for VIS comparisons: All VIS comparisons now start with prefix "fp", retain the older variants as aliases. The signed variants for equal and not-equal have "u" aliases to show that these comparisons are equally suited for unsigned compares. Update existing test cases as needed, and add several new ones. include/opcode/ * sparc.h (F_PREFERRED): Define. (F_PREF_ALIAS): Define. opcodes/ * sparc-dis.c (compare_opcodes): When encountering multiple aliases of an opcode, prefer the one with F_PREFERRED set. * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa, lzcnt, flush with '[address]' syntax, and missing cbcond pseudo ops. Make 64-bit VIS logical ops have "d" suffix in their names, mark existing mnenomics as aliases. Add "cc" suffix to edge instructions generating condition codes, mark existing mnenomics as aliases. Add "fp" prefix to VIS compare instructions, mark existing mnenomics as aliases. gas/testsuite/ * gas/sparc/cbcond.s: Add tests for new opcode aliases. * gas/sparc/cbcond.d: Updated. * gas/sparc/hpcvis3.s: Add tests for new opcode aliases. * gas/sparc/hpcvis3.d: Updated. * gas/sparc/v8-movwr-imm.d: Fix expected disassembly. * gas/sparc/edge.s: New test. * gas/sparc/edge.d: Expected disassembly. * gas/sparc/flush.s: New test. * gas/sparc/flush.d: Expected disassembly. * gas/sparc/ldd_std.s: New test. * gas/sparc/ldd_std.d: Expected disassembly. * gas/sparc/ldtw_sttw.s: New test. * gas/sparc/ldtw_sttw.d: Expected disassembly. * gas/sparc/sparc.exp: Run new tests.
2013-04-07 00:22:03 +02:00
2013-04-06 David S. Miller <davem@davemloft.net>
* sparc-dis.c (compare_opcodes): When encountering multiple aliases
of an opcode, prefer the one with F_PREFERRED set.
* sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
ops. Make 64-bit VIS logical ops have "d" suffix in their names,
mark existing mnenomics as aliases. Add "cc" suffix to edge
instructions generating condition codes, mark existing mnenomics
as aliases. Add "fp" prefix to VIS compare instructions, mark
existing mnenomics as aliases.
* elf32-v850.c (v850_elf_is_target_special_symbol): New function. (bfd_elf32_bfd_is_target_special_symbol): Define. * v850.h (V850_INVERSE_PCREL): Define. * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the destination address by subtracting the operand from the current address. * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store a positive value in the insn. (extract_u16_loop): Do not negate the returned value. (D16_LOOP): Add V850_INVERSE_PCREL flag. (ceilf.sw): Remove duplicate entry. (cvtf.hs): New entry. (cvtf.sh): Likewise. (fmaf.s): Likewise. (fmsf.s): Likewise. (fnmaf.s): Likewise. (fnmsf.s): Likewise. (maddf.s): Restrict to E3V5 architectures. (msubf.s): Likewise. (nmaddf.s): Likewise. (nmsubf.s): Likewise.
2013-04-03 16:42:10 +02:00
2013-04-03 Nick Clifton <nickc@redhat.com>
* v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
destination address by subtracting the operand from the current
address.
* v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
a positive value in the insn.
(extract_u16_loop): Do not negate the returned value.
(D16_LOOP): Add V850_INVERSE_PCREL flag.
(ceilf.sw): Remove duplicate entry.
(cvtf.hs): New entry.
(cvtf.sh): Likewise.
(fmaf.s): Likewise.
(fmsf.s): Likewise.
(fnmaf.s): Likewise.
(fnmsf.s): Likewise.
(maddf.s): Restrict to E3V5 architectures.
(msubf.s): Likewise.
(nmaddf.s): Likewise.
(nmsubf.s): Likewise.
Properly check address mode for SIB gas/testsuite/ * gas/i386/addr32.s: Add an SIB test. * gas/i386/addr32.d: Updated. opcodes/ * i386-dis.c (get_sib): Add the sizeflag argument. Properly check address mode. (print_insn): Pass sizeflag to get_sib.
2013-03-27 19:49:10 +01:00
2013-03-27 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (get_sib): Add the sizeflag argument. Properly
check address mode.
(print_insn): Pass sizeflag to get_sib.
PR binutils/15068 * tic6x-dis.c: Add support for displaying 16-bit insns. * tic6xc-insn-formats.h (FLD): Add use of bitfield array. Add 16-bit opcodes. * tic6xc-opcode-table.h: Add 16-bit insns. * tic6x.h: Add support for 16-bit insns. * config/tc-tic6x.c (tic6x_try_encode): Add use of bitfields array. * gas/tic6x/insns16-d-unit.s: New test. * gas/tic6x/insns16-d-unit.d: Expected disassembly. * gas/tic6x/insns16-ddec.s: New test. * gas/tic6x/insns16-ddec.d: Expected disassembly. * gas/tic6x/insns16-dinc.s: New test. * gas/tic6x/insns16-dinc.d: Expected disassembly. * gas/tic6x/insns16-dind.s: New test. * gas/tic6x/insns16-dind.d: Expected disassembly. * gas/tic6x/insns16-doff4.s: New test. * gas/tic6x/insns16-doff4.d: Expected disassembly. * gas/tic6x/insns16-l-unit.s: New test. * gas/tic6x/insns16-l-unit.d: Expected disassembly. * gas/tic6x/insns16-lsd-unit.s: New test. * gas/tic6x/insns16-lsd-unit.d: Expected disassembly. * gas/tic6x/insns16-m-unit.s: New test. * gas/tic6x/insns16-m-unit.d: Expected disassembly. * gas/tic6x/insns16-s-unit-pcrel.s: New test. * gas/tic6x/insns16-s-unit-pcrel.d: Expected disassembly. * gas/tic6x/insns16-s-unit: New test. * gas/tic6x/insns16-s-unit.d: Expected disassembly.
2013-03-27 12:43:37 +01:00
2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
PR binutils/15068
* tic6x-dis.c: Add support for displaying 16-bit insns.
* include/opcode/tic6x.h: add tic6x_coding_dreg_(msb|lsb) field coding type in order to encode separately the msb and lsb of a register pair ; this will be needed to encode the opcodes the same way as Ti assembler does. * gas/config/tc-tic6x.c: handle tic6x_coding_dreg_(msb|lsb) field coding types and use it to encode register pair numbers when required. * opcodes/tic6x-dis.c: decodes opcodes that have individual msb and lsb halves in src1 & src2 fields ; discard the src1 (lsb) value and only use src2 (msb), discarding bit 0, to follow what Ti SDK does in that case as any value in the src1 field yields the same output with SDK disassembler. * include/opcode/tic6x-opcode-table.h: modify absdp, dpint, dpsp, dptrunc, rcpdp and rsqrdp opcodes to use the new field coding types. * gas/testsuite/gas/tic6x/insns-c674x.d, gas/testsuite/gas/tic6x/insns-c674x.s : add test case for the newly generated opcode but keep the old ones as they seem legit as per Ti disassembler output.
2013-03-20 17:36:34 +01:00
2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
PR gas/15095
* tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
individual msb and lsb halves in src1 & src2 fields. Discard the
src1 (lsb) value and only use src2 (msb), discarding bit 0, to
follow what Ti SDK does in that case as any value in the src1
field yields the same output with SDK disassembler.
Eliminate warning message. * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
2013-03-12 16:19:23 +01:00
2013-03-12 Michael Eager <eager@eagercon.com>
* include/opcode/tic6x.h: add tic6x_coding_dreg_(msb|lsb) field coding type in order to encode separately the msb and lsb of a register pair ; this will be needed to encode the opcodes the same way as Ti assembler does. * gas/config/tc-tic6x.c: handle tic6x_coding_dreg_(msb|lsb) field coding types and use it to encode register pair numbers when required. * opcodes/tic6x-dis.c: decodes opcodes that have individual msb and lsb halves in src1 & src2 fields ; discard the src1 (lsb) value and only use src2 (msb), discarding bit 0, to follow what Ti SDK does in that case as any value in the src1 field yields the same output with SDK disassembler. * include/opcode/tic6x-opcode-table.h: modify absdp, dpint, dpsp, dptrunc, rcpdp and rsqrdp opcodes to use the new field coding types. * gas/testsuite/gas/tic6x/insns-c674x.d, gas/testsuite/gas/tic6x/insns-c674x.s : add test case for the newly generated opcode but keep the old ones as they seem legit as per Ti disassembler output.
2013-03-20 17:36:34 +01:00
* opcodes/mips-dis.c (print_insn_args): Modify def of reg.
Eliminate warning message. * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
2013-03-12 16:19:23 +01:00
2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de> include/ * opcode/nios2.h (OPX_WRPRS): New define. (OP_MATCH_WRPRS): Likewise. opcodes/ * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs. gas/ * config/tc-nios2.c (nios2_assemble_args_ds): New function. (nios2_arg_info_structs): Add "d,s" and "d,s,E" entries. gas/testsuite/ * gas/nios2/nios2.exp: Run wrprs. * gas/nios2/wrprs.d: New file. * gas/nios2/wrprs.s: Likewise.
2013-03-12 03:41:26 +01:00
2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
* nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de> include/ * opcode/nios2.h (OP_RDPRS): New define. (OP_MATCH_RDPRS): Likewise. opcodes/ * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs. gas/testsuite/ * gas/nios2/nios2.exp: Run rdprs. * gas/nios2/rdprs.d: New file. * gas/nios2/rdprs.s: Likewise.
2013-03-12 03:20:08 +01:00
2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
* nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de> opcodes/ * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register. gas/testsuite/ * gas/nios2/nios2.exp: Run registers. * gas/nios2/registers.d: New file. * gas/nios2/registers.s: Likewise.
2013-03-12 02:41:41 +01:00
2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
* nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
Add support for AArch32 CRC instruction in ARMv8. gas/ChangeLog 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * config/tc-arm.c (crc_ext_armv8): New feature set. (UNPRED_REG): New macro. (do_crc32_1): New function. (do_crc32b, do_crc32h, do_crc32w, do_crc32cb, do_crc32ch, do_crc32cw): Likewise. (TUEc): New macro. (insns): Add entries for crc32 mnemonics. (arm_extensions): Add entry for crc. include/opcode/ChangeLog 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * arm.h (CRC_EXT_ARMV8): New constant. (ARCH_CRC_ARMV8): New macro. opcodes/ChangeLog 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * arm-dis.c (arm_opcodes): Add entries for CRC instructions. (thumb32_opcodes): Likewise. (print_insn_thumb32): Handle 'S' control char. gas/testsuite/ChangeLog 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * gas/arm/crc32-bad.d: New file. * gas/arm/crc32-bad.l: Likewise. * gas/arm/crc32-bad.s: Likewise. * gas/arm/crc32.d: Likewise. * gas/arm/crc32.s: Likewise.
2013-03-11 12:09:33 +01:00
2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* arm-dis.c (arm_opcodes): Add entries for CRC instructions.
(thumb32_opcodes): Likewise.
(print_insn_thumb32): Handle 'S' control char.
PR binutils/15241 * lm32.cpu (Control and status registers): Add CFG2, PSW, TLBVADDR, TLBPADDR and TLBBADVADDR. * lm32-desc.c: Regenerate.
2013-03-08 18:25:12 +01:00
2013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
* lm32-desc.c: Regenerate.
Add RegRex64 to riz * i386-reg.tbl (riz): Add RegRex64. * i386-tbl.h: Regenerated.
2013-03-02 02:57:48 +01:00
2013-03-01 H.J. Lu <hongjiu.lu@intel.com>
* i386-reg.tbl (riz): Add RegRex64.
* i386-tbl.h: Regenerated.
include/opcode/ * aarch64.h (AARCH64_FEATURE_CRC): New macro. opcodes/ * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros. (aarch64_feature_crc): New static. (CRC): New macro. (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w, crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions. * aarch64-asm-2.c: Re-generate. * aarch64-dis-2.c: Ditto. * aarch64-opc-2.c: Ditto. gas/ * config/tc-aarch64.c (aarch64_features): Add the 'crc' option. gas/testsuite/ * gas/aarch64/crc32.s: New test. * gas/aarch64/crc32.d: Ditto.
2013-02-28 20:18:40 +01:00
2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
* aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
(aarch64_feature_crc): New static.
(CRC): New macro.
(aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
* aarch64-asm-2.c: Re-generate.
* aarch64-dis-2.c: Ditto.
* aarch64-opc-2.c: Ditto.
* rl78-decode.opc (rl78_decode_opcode): Fix typo. * rl78-decode.c: Regenerate.
2013-02-27 04:00:44 +01:00
2013-02-27 Alan Modra <amodra@gmail.com>
* rl78-decode.opc (rl78_decode_opcode): Fix typo.
* rl78-decode.c: Regenerate.
* rl78-decode.opc: Fix encoding of DIVWU insn. * rl78-decode.c: Regenerate. * config/rl78-parse.y: Fix encoding of DIVWU insn.
2013-02-25 19:41:06 +01:00
2013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
* rl78-decode.opc: Fix encoding of DIVWU insn.
* rl78-decode.c: Regenerate.
Implement Intel SMAP instructions gas/ PR gas/15159 * config/tc-i386.c (cpu_arch): Add ".smap". * doc/c-i386.texi: Document smap. gas/testsuite/ PR gas/15159 * gas/i386/i386.exp: Run smap and x86-64-smap. * gas/i386/smap.d: New file. * gas/i386/smap.s: likewise. * gas/i386/x86-64-smap.d: likewise. opcodes/ PR gas/15159 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1. * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS. (cpu_flags): Add CpuSMAP. * i386-opc.h (CpuSMAP): New. (i386_cpu_flags): Add cpusmap. * i386-opc.tbl: Add clac and stac. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2013-02-19 20:10:31 +01:00
2013-02-19 H.J. Lu <hongjiu.lu@intel.com>
PR gas/15159
* i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
* i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
(cpu_flags): Add CpuSMAP.
* i386-opc.h (CpuSMAP): New.
(i386_cpu_flags): Add cpusmap.
* i386-opc.tbl: Add clac and stac.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
* metag-dis.c: Initialize outf->bytes_per_chunk to 4 which also makes the disassembler output be in little endian like it should be. * metag/labelarithmetic.d: Fix the expected disassembler output to be in little endian format * metag/metacore12.d: likewise * metag/metacore21.d: likewise * metag/metacore21ext.d: likewise * metag/metadsp21.d: likewise * metag/metadsp21ext.d: likewise * metag/metafpu.d: likewise * metag/metafpuext.d: likewise * metag/tls.d: likewise * ld-metag/pcrel.d: Fix the expected disassembler output to be in little endian format * ld-metag/shared.d: likewise * ld-metag/stub.d: likewise * ld-metag/stub_pic_app.d: likewise * ld-metag/stub_pic_shared.d: likewise * ld-metag/stub_shared.d: likewise
2013-02-15 15:54:28 +01:00
2013-02-15 Markos Chandras <markos.chandras@imgtec.com>
* metag-dis.c: Initialize outf->bytes_per_chunk to 4
which also makes the disassembler output be in little
endian like it should be.
opcodes/ * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name' fields to NULL. (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP. gas/ * config/tc-aarch64.c (md_begin): Change to check if 'name' is NULL. gas/testsuite/ * gas/aarch64/system.s: Add tests. * gas/aarch64/system.d: Update.
2013-02-14 19:12:51 +01:00
2013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
* aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
fields to NULL.
(aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
Correct ChangeLog dates.
2013-02-13 20:36:10 +01:00
2013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
opcodes/ * mips-dis.c (is_compressed_mode_p): Only match symbols from the section disassembled. binutils/testsuite/ * binutils-all/mips/mixed-micromips.d: New test. * binutils-all/mips/mixed-mips16.d: New test. * binutils-all/mips/mixed-micromips.s: New test source. * binutils-all/mips/mixed-mips16.s: New test source. * binutils-all/mips/mips.exp: New file.
2013-02-13 18:09:09 +01:00
* mips-dis.c (is_compressed_mode_p): Only match symbols from the
section disassembled.
2013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * arm-dis.c: Update strht pattern. * gas/arm/archv6t2.s: Add strht and ldrht tests. * gas/arm/archv6t2.d: Add disassembly patterns for the above.
2013-02-11 11:15:52 +01:00
2013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* arm-dis.c: Update strht pattern.
gas/ 2013-02-09 Jürgen Urban <JuergenUrban@gmx.de> * config/tc-mips.c (CPU_HAS_LDC1_SDC1): New macro. (macro): Use it. Assert that trunc.w.s is not used for r5900. opcodes/ 2013-02-09 Jürgen Urban <JuergenUrban@gmx.de> * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for single-float. Disable ll, lld, sc and scd for EE. Disable the trunc.w.s macro for EE. gas/testsuite/ 2013-02-09 Jürgen Urban <JuergenUrban@gmx.de> * gas/mips/24k-triple-stores-2.d, gas/mips/24k-triple-stores-2.s, gas/mips/micromips@24k-triple-stores-2.d: Move "sc" tests to... * gas/mips/24k-triple-stores-2-llsc.d, gas/mips/24k-triple-stores-2-llsc.s, gas/mips/micromips@24k-triple-stores-2-llsc.d: ...these new tests. * gas/mips/r5900-full.d, gas/mips/r5900-full.s: Verify that the MIPS ISA level can be upgraded to support ll, sc, lld and scd. * gas/mips/l_d-single.d, gas/mips/s_d-single.d, gas/mips/r5900-nollsc.l, gas/mips/r5900-nollsc.s: New tests. * gas/mips/mips.exp: Update accordingly. Add "nollsc" to r5900 properties.
2013-02-09 11:24:20 +01:00
2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
* mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
single-float. Disable ll, lld, sc and scd for EE. Disable the
trunc.w.s macro for EE.
2013-02-06 Sandra Loosemore <sandra@codesourcery.com> Andrew Jenner <andrew@codesourcery.com> Based on patches from Altera Corporation. bfd/ * Makefile.am (ALL_MACHINES): Add cpu-nios2.lo. (ALL_MACHINES_CFILES): Add cpu-nios2.c. (BFD_BACKENDS): Add elf32-nios2.lo. (BFD32_BACKENDS_CFILES): Add elf32-nios2.c. * Makefile.in: Regenerated. * configure.in: Add entries for bfd_elf32_bignios2_vec and bfd_elf32_littlenios2_vec. * configure: Regenerated. * config.bfd: Add cases for nios2. * archures.c (enum bfd_architecture): Add bfd_arch_nios2. (bfd_mach_nios2): Define. (bfd_nios2_arch): Declare. (bfd_archures_list): Add bfd_nios2_arch. * targets.c (bfd_elf32_bignios2_vec): Declare. (bfd_elf32_littlenios2_vec): Declare. (_bfd_target_vector): Add entries for bfd_elf32_bignios2_vec and bfd_elf32_littlenios2_vec. * elf-bfd.h (enum elf_target_id): Add NIOS2_ELF_DATA. * reloc.c (enum bfd_reloc_code_real): Add Nios II relocations. * bfd-in2.h: Regenerated. * libbfd.h: Regenerated. * cpu-nios2.c: New file. * elf32-nios2.c: New file. opcodes/ * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and nios2-opc.c. * Makefile.in: Regenerated. * configure.in: Add case for bfd_nios2_arch. * configure: Regenerated. * disassemble.c (ARCH_nios2): Define. (disassembler): Add case for bfd_arch_nios2. * nios2-dis.c: New file. * nios2-opc.c: New file. include/ * dis-asm.h (print_insn_big_nios2): Declare. (print_insn_little_nios2): Declare. include/elf * nios2.h: New file. include/opcode/ * nios2.h: New file. gas/ * Makefile.am (TARGET_CPU_CFILES): Add config/tc-nios2.c. (TARGET_CPU_HFILES): Add config/tc-nios2.h. * Makefile.in: Regenerated. * configure.tgt: Add case for nios2*-linux*. * config/obj-elf.c: Conditionally include elf/nios2.h. * config/tc-nios2.c: New file. * config/tc-nios2.h: New file. * doc/Makefile.am (CPU_DOCS): Add c-nios2.texi. * doc/Makefile.in: Regenerated. * doc/all.texi: Set NIOSII. * doc/as.texinfo (Overview): Add Nios II options. (Machine Dependencies): Include c-nios2.texi. * doc/c-nios2.texi: New file. * NEWS: Note Altera Nios II support. gas/testsuite/ * gas/nios2/add.d: New. * gas/nios2/add.s: New. * gas/nios2/align_fill.d: New. * gas/nios2/align_fill.s: New. * gas/nios2/align_text.d: New. * gas/nios2/align_text.s: New. * gas/nios2/and.d: New. * gas/nios2/and.s: New. * gas/nios2/branch.d: New. * gas/nios2/branch.s: New. * gas/nios2/break.d: New. * gas/nios2/break.s: New. * gas/nios2/bret.d: New. * gas/nios2/bret.s: New. * gas/nios2/cache.d: New. * gas/nios2/cache.s: New. * gas/nios2/call26.d: New. * gas/nios2/call26.s: New. * gas/nios2/call.d: New. * gas/nios2/call.s: New. * gas/nios2/cmp.d: New. * gas/nios2/cmp.s: New. * gas/nios2/comments.d: New. * gas/nios2/comments.s: New. * gas/nios2/complex.d: New. * gas/nios2/complex.s: New. * gas/nios2/ctl.d: New. * gas/nios2/ctl.s: New. * gas/nios2/custom.d: New. * gas/nios2/custom.s: New. * gas/nios2/etbt.d: New. * gas/nios2/etbt.s: New. * gas/nios2/flushda.d: New. * gas/nios2/flushda.s: New. * gas/nios2/illegal.l: New. * gas/nios2/illegal.s: New. * gas/nios2/jmp.d: New. * gas/nios2/jmp.s: New. * gas/nios2/ldb.d: New. * gas/nios2/ldb.s: New. * gas/nios2/ldh.d: New. * gas/nios2/ldh.s: New. * gas/nios2/ldw.d: New. * gas/nios2/ldw.s: New. * gas/nios2/lineseparator.d: New. * gas/nios2/lineseparator.s: New. * gas/nios2/mov.d: New. * gas/nios2/movia.d: New. * gas/nios2/movia.s: New. * gas/nios2/movi.d: New. * gas/nios2/movi.s: New. * gas/nios2/mov.s: New. * gas/nios2/mul.d: New. * gas/nios2/mul.s: New. * gas/nios2/nios2.exp: New. * gas/nios2/nor.d: New. * gas/nios2/nor.s: New. * gas/nios2/or.d: New. * gas/nios2/or.s: New. * gas/nios2/ret.d: New. * gas/nios2/ret.s: New. * gas/nios2/rol.d: New. * gas/nios2/rol.s: New. * gas/nios2/rotate.d: New. * gas/nios2/rotate.s: New. * gas/nios2/stb.d: New. * gas/nios2/stb.s: New. * gas/nios2/sth.d: New. * gas/nios2/sth.s: New. * gas/nios2/stw.d: New. * gas/nios2/stw.s: New. * gas/nios2/sub.d: New. * gas/nios2/sub.s: New. * gas/nios2/sync.d: New. * gas/nios2/sync.s: New. * gas/nios2/trap.d: New. * gas/nios2/trap.s: New. * gas/nios2/tret.d: New. * gas/nios2/tret.s: New. * gas/nios2/warn_noat.l: New. * gas/nios2/warn_noat.s: New. * gas/nios2/warn_nobreak.l: New. * gas/nios2/warn_nobreak.s: New. * gas/nios2/xor.d: New. * gas/nios2/xor.s: New. ld/ * Makefile.am (enios2elf.c): New rule. * Makefile.in: Regenerated. * configure.tgt: Add case for nios2*-*-*. * emulparams/nios2elf.sh: New file. * NEWS: Note Altera Nios II support. ld/testsuite/ * ld-nios2/emit-relocs-1a.s: New. * ld-nios2/emit-relocs-1b.s: New. * ld-nios2/emit-relocs-1.d: New. * ld-nios2/emit-relocs-1.ld: New. * ld-nios2/gprel.d: New. * ld-nios2/gprel.s: New. * ld-nios2/hilo16.d: New. * ld-nios2/hilo16.s: New. * ld-nios2/hilo16_symbol.s: New. * ld-nios2/imm5.d: New. * ld-nios2/imm5.s: New. * ld-nios2/imm5_symbol.s: New. * ld-nios2/nios2.exp: New. * ld-nios2/pcrel16.d: New. * ld-nios2/pcrel16_label.s: New. * ld-nios2/pcrel16.s: New. * ld-nios2/relax_callr.d: New. * ld-nios2/relax_callr.ld: New. * ld-nios2/relax_callr.s: New. * ld-nios2/relax_cjmp.d: New. * ld-nios2/relax_cjmp.s: New. * ld-nios2/relax_jmp.ld: New. * ld-nios2/relax_section.d: New. * ld-nios2/relax_section.s: New. * ld-nios2/relax_ujmp.d: New. * ld-nios2/relax_ujmp.s: New. * ld-nios2/reloc.d: New. * ld-nios2/reloc.s: New. * ld-nios2/reloc_symbol.s: New. * ld-nios2/s16.d: New. * ld-nios2/s16.s: New. * ld-nios2/s16_symbol.s: New. * ld-nios2/u16.d: New. * ld-nios2/u16.s: New. * ld-nios2/u16_symbol.s: New. * ld-elf/indirect.exp: Skip on targets that don't support -shared -fPIC. * ld-elfcomm/elfcomm.exp: Build with -G0 for nios2. * ld-plugin/lto.exp: Skip shared library tests on targets that don't support them. Skip execution tests on non-native targets. binutils/ * readelf.c: Include elf/nios2.h. (dump_relocations): Add case for EM_ALTERA_NIOS2. (get_nios2_dynamic_type): New. (get_dynamic_type): Add case for EM_ALTERA_NIOS2. (is_32bit_abs_reloc): Fix EM_ALTERA_NIOS2 case. (is_16bit_abs_reloc): Likewise. (is_none_reloc): Add EM_ALTERA_NIOS2 and EM_NIOS32 cases. * NEWS: Note Altera Nios II support. * MAINTAINERS: Add Nios II maintainers.
2013-02-07 00:22:26 +01:00
2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
Andrew Jenner <andrew@codesourcery.com>
Based on patches from Altera Corporation.
* Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
nios2-opc.c.
* Makefile.in: Regenerated.
* configure.in: Add case for bfd_nios2_arch.
* configure: Regenerated.
* disassemble.c (ARCH_nios2): Define.
(disassembler): Add case for bfd_arch_nios2.
* nios2-dis.c: New file.
* nios2-opc.c: New file.
* po/POTFILES.in: Regenerate. * rl78-decode.c: Regenerate. * rx-decode.c: Regenerate.
2013-02-04 07:04:33 +01:00
2013-02-04 Alan Modra <amodra@gmail.com>
* po/POTFILES.in: Regenerate.
* rl78-decode.c: Regenerate.
* rx-decode.c: Regenerate.
include/opcode/ 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com> * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2. opcodes/ 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com> * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2. * aarch64-asm.c (convert_xtl_to_shll): New function. (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by calling convert_xtl_to_shll. * aarch64-dis.c (convert_shll_to_xtl): New function. (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by calling convert_shll_to_xtl. * aarch64-gen.c: Update copyright year. * aarch64-asm-2.c: Re-generate. * aarch64-dis-2.c: Re-generate. * aarch64-opc-2.c: Re-generate. gas/testsuite/ 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com> * gas/aarch64/alias.s: Add new tests. * gas/aarch64/alias.d: Update. * gas/aarch64/no-aliases.d: Update.
2013-01-30 16:43:32 +01:00
2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
* aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
* aarch64-asm.c (convert_xtl_to_shll): New function.
(convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
calling convert_xtl_to_shll.
* aarch64-dis.c (convert_shll_to_xtl): New function.
(convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
calling convert_shll_to_xtl.
* aarch64-gen.c: Update copyright year.
* aarch64-asm-2.c: Re-generate.
* aarch64-dis-2.c: Re-generate.
* aarch64-opc-2.c: Re-generate.
Add support for V850E3V5 architecture
2013-01-24 12:14:05 +01:00
2013-01-24 Nick Clifton <nickc@redhat.com>
* v850-dis.c: Add support for e3v5 architecture.
* v850-opc.c: Likewise.
include/opcode/ 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com> * aarch64.h (aarch64_op): Remove OP_V_MOVI_B. opcodes/ 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com> * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI. * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise. * aarch64-opc.c (operand_general_constraint_met_p): For AARCH64_MOD_LSL, move the range check on the shift amount before the alignment check; change to call set_sft_amount_out_of_range_error instead of set_imm_out_of_range_error. * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL. (aarch64_opcode_table): Remove the OP enumerator from the asimdimm 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to SIMD_IMM_SFT. gas/ 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com> * config/tc-aarch64.c (output_operand_error_record): Change to output the out-of-range error message as value-expected message if there is only one single value in the expected range. (programmer_friendly_fixup): Remove the handling of 8-bit MOVI with LSL #0 as a programmer-friendly feature. gas/testsuite/ 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com> * gas/aarch64/diagnostic.l: Update. * gas/aarch64/movi.s: Add tests. * gas/aarch64/movi.d: Update. * gas/aarch64/programmer-friendly.s: Add comment.
2013-01-17 17:09:44 +01:00
2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
* aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
* aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
* aarch64-opc.c (operand_general_constraint_met_p): For
Add support for V850E3V5 architecture
2013-01-24 12:14:05 +01:00
AARCH64_MOD_LSL, move the range check on the shift amount before the
include/opcode/ 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com> * aarch64.h (aarch64_op): Remove OP_V_MOVI_B. opcodes/ 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com> * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI. * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise. * aarch64-opc.c (operand_general_constraint_met_p): For AARCH64_MOD_LSL, move the range check on the shift amount before the alignment check; change to call set_sft_amount_out_of_range_error instead of set_imm_out_of_range_error. * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL. (aarch64_opcode_table): Remove the OP enumerator from the asimdimm 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to SIMD_IMM_SFT. gas/ 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com> * config/tc-aarch64.c (output_operand_error_record): Change to output the out-of-range error message as value-expected message if there is only one single value in the expected range. (programmer_friendly_fixup): Remove the handling of 8-bit MOVI with LSL #0 as a programmer-friendly feature. gas/testsuite/ 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com> * gas/aarch64/diagnostic.l: Update. * gas/aarch64/movi.s: Add tests. * gas/aarch64/movi.d: Update. * gas/aarch64/programmer-friendly.s: Add comment.
2013-01-17 17:09:44 +01:00
alignment check; change to call set_sft_amount_out_of_range_error
instead of set_imm_out_of_range_error.
* aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
(aarch64_opcode_table): Remove the OP enumerator from the asimdimm
8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
SIMD_IMM_SFT.
Add OPERAND_TYPE_IMM32_64 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2013-01-16 23:11:05 +01:00
2013-01-16 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
* config/tc-v850.c (md_assemble): Allow signed values for V850E_IMMEDIATE. * gas/v850/basic.exp: Allow for variations in reloc names. * gas/v850/split-lo16.d: Likewise. * gas/v850/v850e1.s: Add more tests of the PREPARE insn. * gas/v850/v850e1.d: Update expected disassembly. * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE values. * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
2013-01-15 09:45:45 +01:00
2013-01-15 Nick Clifton <nickc@redhat.com>
* v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
values.
* v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
* metag-dis.c (REG_WIDTH): Increase to 64. * gas/metag/metadsp21.d: Fix expected MMOV disassembly.
2013-01-14 12:22:06 +01:00
2013-01-14 Will Newton <will.newton@imgtec.com>
* metag-dis.c (REG_WIDTH): Increase to 64.
include/opcode/ * ppc.h (PPC_OPCODE_POWER8): New define. (PPC_OPCODE_HTM): Likewise. opcodes/ * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries. * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK, XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines. (SH6): Update. <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.", "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.", "treclaim.", "tsr.">: Add POWER8 HTM opcodes. <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes. gas/ * doc/as.texinfo (Target PowerPC): Document -mpower8 and -mhtm. * doc/c-ppc.texi (PowerPC-Opts): Likewise. * config/tc-ppc.c (md_show_usage): Likewise. (ppc_handle_align): Handle power8's group ending nop. gas/testsuite/ * gas/ppc/htm.d: New test. * gas/ppc/htm.s: Likewise. * gas/ppc/power8.d: Likewise. * gas/ppc/power8.s: Likewise. * gas/ppc/ppc.exp: Run them.
2013-01-11 03:25:36 +01:00
2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
* ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
* ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
(SH6): Update.
<"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
"tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
"treclaim.", "tsr.">: Add POWER8 HTM opcodes.
<"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
* common.h: Fix case of "Meta". * metag.h: New file. * dis-asm.h (print_insn_metag): New declaration. * metag.h: New file. * Makefile.am: Add Meta. * Makefile.in: Regenerate. * configure: Regenerate. * configure.in: Add Meta. * disassemble.c: Add Meta support. * metag-dis.c: New file. * Makefile.am: Add Meta. * Makefile.in: Regenerate. * archures.c (bfd_mach_metag): New. * bfd-in2.h: Regenerate. * config.bfd: Add Meta. * configure: Regenerate. * configure.in: Add Meta. * cpu-metag.c: New file. * elf-bfd.h: Add Meta. * elf32-metag.c: New file. * elf32-metag.h: New file. * libbfd.h: Regenerate. * reloc.c: Add Meta relocations. * targets.c: Add Meta. * Makefile.am: Add Meta. * Makefile.in: Regenerate. * config/tc-metag.c: New file. * config/tc-metag.h: New file. * configure.tgt: Add Meta. * doc/Makefile.am: Add Meta. * doc/Makefile.in: Regenerate. * doc/all.texi: Add Meta. * doc/as.texiinfo: Document Meta options. * doc/c-metag.texi: New file. * gas/metag/labelarithmetic.d: New file. * gas/metag/labelarithmetic.s: New file. * gas/metag/metacore12.d: New file. * gas/metag/metacore12.s: New file. * gas/metag/metacore21-invalid.l: New file. * gas/metag/metacore21-invalid.s: New file. * gas/metag/metacore21.d: New file. * gas/metag/metacore21.s: New file. * gas/metag/metacore21ext.d: New file. * gas/metag/metacore21ext.s: New file. * gas/metag/metadsp21-invalid.l: New file. * gas/metag/metadsp21-invalid.s: New file. * gas/metag/metadsp21.d: New file. * gas/metag/metadsp21.s: New file. * gas/metag/metadsp21ext.d: New file. * gas/metag/metadsp21ext.s: New file. * gas/metag/metafpu21.d: New file. * gas/metag/metafpu21.s: New file. * gas/metag/metafpu21ext.d: New file. * gas/metag/metafpu21ext.s: New file. * gas/metag/metag.exp: New file. * gas/metag/tls.d: New file. * gas/metag/tls.s: New file. * Makefile.am: Add Meta. * Makefile.in: Regenerate. * configure.tgt: Add Meta. * emulparams/elf32metag.sh: New file. * emultempl/metagelf.em: New file. * ld-elf/merge.d: Mark Meta as xfail. * ld-gc/start.d: Skip this test on Meta. * ld-gc/personality.d: Skip this test on Meta. * ld-metag/external.s: New file. * ld-metag/metag.exp: New file. * ld-metag/pcrel.d: New file. * ld-metag/pcrel.s: New file. * ld-metag/shared.d: New file. * ld-metag/shared.r: New file. * ld-metag/shared.s: New file. * ld-metag/stub.d: New file. * ld-metag/stub.s: New file. * ld-metag/stub_pic_app.d: New file. * ld-metag/stub_pic_app.r: New file. * ld-metag/stub_pic_app.s: New file. * ld-metag/stub_pic_shared.d: New file. * ld-metag/stub_pic_shared.s: New file. * ld-metag/stub_shared.d: New file. * ld-metag/stub_shared.r: New file. * ld-metag/stub_shared.s: New file. * binutils/readelf.c: (guess_is_rela): Add EM_METAG. (dump_relocations): Add EM_METAG. (get_machine_name): Correct case for Meta. (is_32bit_abs_reloc): Add support for Meta ADDR32 reloc. (is_none_reloc): Add support for Meta NONE reloc.
2013-01-10 10:49:22 +01:00
2013-01-10 Will Newton <will.newton@imgtec.com>
* Makefile.am: Add Meta.
* configure.in: Add Meta.
* disassemble.c: Add Meta support.
* metag-dis.c: New file.
* Makefile.in: Regenerate.
* configure: Regenerate.
(make_instruction): Rename to cr16_make_instruction. (match_opcode): Rename to cr16_match_opcode.
2013-01-07 16:09:07 +01:00
2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
* cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
(match_opcode): Rename to cr16_match_opcode.
* archures.c: Add support for MIPS r5900 * bfd-in2.h: Add support for MIPS r5900 * config.bfd: Add support for Sony Playstation 2 * cpu-mips.c: Add support for MIPS r5900 * elfxx-mips.c: Add support for MIPS r5900 (extension of r4000) * config/tc-mips.c: Add support for MIPS r5900 Add M_LQ_AB and M_SQ_AB to support large values for instructions lq and sq. * config/tc-mips.c (can_swap_branch_p, get_append_method): Detect some conditional short loops to fix a bug on the r5900 by NOP in the branch delay slot. * config/tc-mips.c (M_MUL): Support 3 operands in multu on r5900. * config/tc-mips.c (M_TRUNCWS): Support trunc.w.s on r5900 in MIPS ISA I. * config/tc-mips.c (s_mipsset): Force 32 bit floating point on r5900. * configure.in: Detect CPU type when target string contains r5900 (e.g. mips64r5900el-linux-gnu). * config/tc-mips.c (mips_ip): Check parameter range of instructions mfps and mtps on r5900. * elf/mips.h: Add MIPS machine variant number for r5900 which is compatible with old Playstation 2 software. * opcode/mips.h: Add support for r5900 instructions including lq and sq. * configure.tgt: Support ELF files for Sony Playstation 2 (for ps2dev and ps2sdk). * emulparams/elf32lr5900n32.sh: Create linker script for Sony Playstation 2 ELF files using MIPS ABI n32. * emulparams/elf32lr5900.sh: Create linker script for Sony Playstation 2 ELF files using MIPS ABI o32. * Makefile.am: Add linker scripts for Sony Playstation 2 ELF files. * opcodes/mips-dis.c: Add names for CP0 registers of r5900. * opcodes/mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for instructions sq and lq. * opcodes/mips-opc.c: Add support for MIPS r5900 CPU. Add support for 128 bit MMI (Multimedia Instructions). Add support for EE instructions (Emotion Engine). Disable unsupported floating point instructions (64 bit and undefined compare operations). Enable instructions of MIPS ISA IV which are supported by r5900. Disable 64 bit co processor instructions. Disable 64 bit multiplication and division instructions. Disable instructions for co-processor 2 and 3, because these are not supported (preparation for later VU0 support (Vector Unit)). Disable cvt.w.s because this behaves like trunc.w.s and the correct execution can't be ensured on r5900. Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This will confuse less developers and compilers.
2013-01-04 18:22:53 +01:00
2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
* mips-dis.c: Add names for CP0 registers of r5900.
* mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
instructions sq and lq.
Add support for MIPS r5900 CPU.
Add support for 128 bit MMI (Multimedia Instructions).
Add support for EE instructions (Emotion Engine).
Disable unsupported floating point instructions (64 bit and
undefined compare operations).
Enable instructions of MIPS ISA IV which are supported by r5900.
Disable 64 bit co processor instructions.
Disable 64 bit multiplication and division instructions.
Disable instructions for co-processor 2 and 3, because these are
not supported (preparation for later VU0 support (Vector Unit)).
Disable cvt.w.s because this behaves like trunc.w.s and the
correct execution can't be ensured on r5900.
Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
will confuse less developers and compilers.
* aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP, PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM. * gas/aarch64/system.d: Update.
2013-01-04 14:32:06 +01:00
2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
opcodes/ 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com> * aarch64-opc.c (aarch64_print_operand): Change to print AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal in comment. * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and OP_MOV_IMM_WIDE. gas/testsuite/ 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com> * gas/aarch64/int-insns.d: Update. * gas/aarch64/mov.d: Update. * gas/aarch64/reloc-insn.d: Update. ld/testsuite/ 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com> * ld-aarch64/emit-relocs-264.d: Append the '-Mno-aliases' option to the objdump directive. * ld-aarch64/emit-relocs-266.d: Ditto. * ld-aarch64/emit-relocs-268.d: Ditto. * ld-aarch64/emit-relocs-269.d: Ditto. * ld-aarch64/emit-relocs-270.d: Ditto. * ld-aarch64/emit-relocs-271.d: Ditto. * ld-aarch64/emit-relocs-272.d: Ditto.
2013-01-04 15:59:33 +01:00
* aarch64-opc.c (aarch64_print_operand): Change to print
AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
in comment.
* aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
OP_MOV_IMM_WIDE.
2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
* aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
* aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP, PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM. * gas/aarch64/system.d: Update.
2013-01-04 14:32:06 +01:00
Update copyright year to 2013 binutils/ 2013-01-02 H.J. Lu <hongjiu.lu@intel.com> * version.c (print_version): Update copyright year to 2013. gas/ 2013-01-02 H.J. Lu <hongjiu.lu@intel.com> * as.c (parse_args): Update copyright year to 2013. ld/ 2013-01-02 H.J. Lu <hongjiu.lu@intel.com> * ldver.c (ldversion): Update copyright year to 2013. opcodes/ 2013-01-02 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (process_copyright): Update copyright year to 2013.
2013-01-02 18:15:38 +01:00
2013-01-02 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (process_copyright): Update copyright year to 2013.
opcodes/ChangeLog * cr16-dis.c (match_opcode,make_instruction: Remove static declaration. (dwordU,wordU): Moved typedefs to opcode/cr16.h (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_' bfd/Changelog * config.bfd (cr16*-*-uclinux*): New target support. include/opcode/ChangeLog * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c (make_instruction,match_opcode): Added function prototypes. (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
2013-01-02 14:13:36 +01:00
2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
Add copyright notices
2012-12-17 17:56:12 +01:00
opcodes/ChangeLog * cr16-dis.c (match_opcode,make_instruction: Remove static declaration. (dwordU,wordU): Moved typedefs to opcode/cr16.h (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_' bfd/Changelog * config.bfd (cr16*-*-uclinux*): New target support. include/opcode/ChangeLog * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c (make_instruction,match_opcode): Added function prototypes. (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
2013-01-02 14:13:36 +01:00
* cr16-dis.c (match_opcode,make_instruction): Remove static
declaration.
(dwordU,wordU): Moved typedefs to opcode/cr16.h
(cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
Add copyright notices
2012-12-17 17:56:12 +01:00
opcodes/ChangeLog * cr16-dis.c (match_opcode,make_instruction: Remove static declaration. (dwordU,wordU): Moved typedefs to opcode/cr16.h (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_' bfd/Changelog * config.bfd (cr16*-*-uclinux*): New target support. include/opcode/ChangeLog * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c (make_instruction,match_opcode): Added function prototypes. (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
2013-01-02 14:13:36 +01:00
For older changes see ChangeLog-2012
19990502 sourceware import
1999-05-03 09:29:11 +02:00
opcodes/ChangeLog * cr16-dis.c (match_opcode,make_instruction: Remove static declaration. (dwordU,wordU): Moved typedefs to opcode/cr16.h (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_' bfd/Changelog * config.bfd (cr16*-*-uclinux*): New target support. include/opcode/ChangeLog * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c (make_instruction,match_opcode): Added function prototypes. (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
2013-01-02 14:13:36 +01:00
Copyright (C) 2013 Free Software Foundation, Inc.
Add copyright notices
2012-12-10 13:48:03 +01:00
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved.
19990502 sourceware import
1999-05-03 09:29:11 +02:00
Local Variables:
Rotate ChangeLogs
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mode: change-log
left-margin: 8
fill-column: 74
19990502 sourceware import
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version-control: never
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