2019-05-09 11:29:22 +02:00
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2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
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* opcode/aarch64.h (enum aarch64_opnd): New SVE_SHRIMM_UNPRED_22
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operand.
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(enum aarch64_insn_class): Add sve_shift_tsz_hsd iclass.
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2019-05-09 11:29:21 +02:00
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2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
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* opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_013 iclass.
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2019-05-09 11:29:20 +02:00
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2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
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* opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_bh iclass.
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2019-05-09 11:29:19 +02:00
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2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
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* opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_sd2 iclass.
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2019-05-09 11:29:18 +02:00
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2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
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* opcode/aarch64.h (enum aarch64_opnd): New SVE_ADDR_ZX operand.
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2019-05-09 11:29:17 +02:00
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2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
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* opcode/aarch64.h (enum aarch64_opnd): New SVE_Zm3_11_INDEX operand.
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2019-05-09 11:29:16 +02:00
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2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
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* opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_hsd2 iclass.
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2019-05-09 11:29:15 +02:00
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2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
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* opcode/aarch64.h (enum aarch64_opnd): New SVE_IMM_ROT3 operand.
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[binutils][aarch64] SVE2 feature extension flags.
Include all feature flag macros.
The "sve2" extension that enables the core sve2 instructions.
This also enables the sve extension, since sve is a requirement of sve2.
Extra optional sve2 features are the bitperm, sm4, aes, and sha3 extensions.
These are all given extra feature flags, "bitperm", "sve2-sm4",
"sve2-aes", and "sve2-sha3" respectively.
The sm4, aes, and sha3 extensions are explicitly marked as sve2
extensions to distinguish them from the corresponding NEON extensions.
Rather than continue extending the current feature flag numbers, I used
some bits that have been skipped.
gas/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c: Add command line architecture feature flags
"sve2", "sve2-sm4", "sve2-aes", "sve2-sha3", "bitperm".
* doc/c-aarch64.texi: Document new architecture feature flags.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_SVE2
AARCH64_FEATURE_SVE2_AES, AARCH64_FEATURE_SVE2_BITPERM,
AARCH64_FEATURE_SVE2_SM4, AARCH64_FEATURE_SVE2_SHA3): New
feature macros.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-tbl.h
(aarch64_feature_sve2, aarch64_feature_sve2aes,
aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
aarch64_feature_sve2bitperm): New feature sets.
(SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
for feature set addresses.
(SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
2019-05-09 11:29:12 +02:00
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2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
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* opcode/aarch64.h (AARCH64_FEATURE_SVE2
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AARCH64_FEATURE_SVE2_AES, AARCH64_FEATURE_SVE2_BITPERM,
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AARCH64_FEATURE_SVE2_SM4, AARCH64_FEATURE_SVE2_SHA3): New
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feature macros.
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Add load-link, store-conditional paired EVA instructions
Add paired load-link and store-conditional instructions to the
EVA ASE for MIPS32R6[1]. These instructions are optional within
the EVA ASE. Their presence is indicated by the XNP bit in the
Config5 register.
[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
Instruction Set Manual", Imagination Technologies Ltd., Document
Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2
"Alphabetical List of Instructions", pp. 230-231, pp. 357-360.
gas/
* config/tc-mips.c (mips_set_ase): Handle ASE_EVA_R6.
(macro) <M_LLWPE_AB, M_SCWPE_AB>: New cases.
(mips_after_parse_args): Translate EVA to EVA_R6.
* testsuite/gas/mips/ase-errors-1.s: Add new instructions.
* testsuite/gas/mips/eva.s: Likewise.
* testsuite/gas/mips/ase-errors-1.l: Check errors for
new instructions.
* testsuite/gas/mips/mipsr6@eva.d: Check new test cases.
include/
* opcode/mips.h (ASE_EVA_R6): New macro.
(M_LLWPE_AB, M_SCWPE_AB): New enum values.
opcodes/
* mips-dis.c (mips_calculate_combination_ases): Add ISA
argument and set ASE_EVA_R6 appropriately.
(set_default_mips_dis_options): Pass ISA to above.
(parse_mips_dis_option): Likewise.
* mips-opc.c (EVAR6): New macro.
(mips_builtin_opcodes): Add llwpe, scwpe.
Derived from patch authored by Andrew Bennett <andrew.bennett@imgtec.com>
2019-04-29 03:21:00 +02:00
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2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
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Faraz Shahbazker <fshahbazker@wavecomp.com>
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* opcode/mips.h (ASE_EVA_R6): New macro.
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(M_LLWPE_AB, M_SCWPE_AB): New enum values.
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2019-05-01 18:14:01 +02:00
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2019-05-01 Sudakshina Das <sudi.das@arm.com>
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* opcode/aarch64.h (AARCH64_FEATURE_TME): New.
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(enum aarch64_opnd): Add AARCH64_OPND_TME_UIMM16.
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[MIPS] Add load-link, store-conditional paired instructions
Add several baseline MIPS32R6[1] and MIPS64R6[2] instructions
that were omitted from the initial spec. These instructions
are optional in implementations but not associated with any
ASE or pseudo-ASE. Their presence is indicated by the XNP bit
in the Config5 register.
[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
Instruction Set Manual", Imagination Technologies Ltd., Document
Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2
"Alphabetical List of Instructions", pp. 228-229, pp. 354-357.
[2] "MIPS Architecture for Programmers Volume II-A: The MIPS64
Instruction Set Manual", Imagination Technologies Ltd., Document
Number: MD00087, Revision 6.06, December 15, 2016, Section 3.2
"Alphabetical List of Instructions", pp. 289-290 and pp. 458-460.
gas/
* config/tc-mips.c (macro) <M_LLWP_AB, M_LLDP_AB, M_SCWP_AB,
M_SCDP_AB>: New cases and expansions for paired instructions.
* testsuite/gas/mips/llpscp-32.s: New test source.
* testsuite/gas/mips/llpscp-64.s: Likewise.
* testsuite/gas/mips/llpscp-32.d: New test.
* testsuite/gas/mips/llpscp-64.d: Likewise.
* testsuite/gas/mips/mips.exp: Run the new tests.
* testsuite/gas/mips/r6.s: Add new instructions to test source.
* testsuite/gas/mips/r6-64.s: Likewise.
* testsuite/gas/mips/r6-64-n32.d: Check new instructions.
* testsuite/gas/mips/r6-64-n64.d: Likewise.
* testsuite/gas/mips/r6-n32.d: Likewise.
* testsuite/gas/mips/r6-n64.d: Likwwise.
* testsuite/gas/mips/r6.d: Likewise.
include/
* opcode/mips.h (M_LLWP_AB, M_LLDP_AB): New enum values.
(M_SCWP_AB, M_SCDP_AB): Likewise.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
2019-04-23 00:12:09 +02:00
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2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
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Faraz Shahbazker <fshahbazker@wavecomp.com>
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* opcode/mips.h (M_LLWP_AB, M_LLDP_AB): New enum values.
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(M_SCWP_AB, M_SCDP_AB): Likewise.
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2019-04-25 02:28:49 +02:00
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2019-04-25 Maciej W. Rozycki <macro@linux-mips.org>
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* opcode/mips.h: Update comment for MIPS32 CODE20 operand.
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2019-04-15 12:46:54 +02:00
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2019-04-15 Sudakshina Das <sudi.das@arm.com>
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* elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF12.
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2019-04-15 12:37:51 +02:00
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2019-04-15 Sudakshina Das <sudi.das@arm.com>
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* elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF18.
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2019-04-15 12:18:57 +02:00
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2019-04-15 Sudakshina Das <sudi.das@arm.com>
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* elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF16.
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2019-04-15 11:54:42 +02:00
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2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
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* elf/arm.h (TAG_CPU_ARCH_V8_1M_MAIN): new macro.
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(MAX_TAG_CPU_ARCH): Set value to above macro.
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* opcode/arm.h (ARM_EXT2_V8_1M_MAIN): New macro.
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(ARM_AEXT_V8_1M_MAIN): Likewise.
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(ARM_AEXT2_V8_1M_MAIN): Likewise.
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(ARM_ARCH_V8_1M_MAIN): Likewise.
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[BINUTILS, AArch64, 2/2] Update Store Allocation Tag instructions
This patch updates the Store allocation tags instructions in
Armv8.5-A Memory Tagging Extension. This is part of the changes
that have been introduced recently in the 00bet10 release
All of these instructions have an updated register operand (Xt -> <Xt|SP>)
- STG <Xt|SP>, [<Xn|SP>, #<simm>]
- STG <Xt|SP>, [<Xn|SP>, #<simm>]!
- STG <Xt|SP>, [<Xn|SP>], #<simm>
- STZG <Xt|SP>, [<Xn|SP>, #<simm>]
- STZG <Xt|SP>, [<Xn|SP>, #<simm>]!
- STZG <Xt|SP>, [<Xn|SP>], #<simm>
- ST2G <Xt|SP>, [<Xn|SP>, #<simm>]
- ST2G <Xt|SP>, [<Xn|SP>, #<simm>]!
- ST2G <Xt|SP>, [<Xn|SP>], #<simm>
- STZ2G <Xt|SP>, [<Xn|SP>, #<simm>]
- STZ2G <Xt|SP>, [<Xn|SP>, #<simm>]!
- STZ2G <Xt|SP>, [<Xn|SP>], #<simm>
In order to accept <Rt|SP> a new operand type Rt_SP is introduced which has
the same field as FLD_Rt but follows other semantics of Rn_SP.
*** gas/ChangeLog ***
2019-04-11 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (process_omitted_operand): Add case for
AARCH64_OPND_Rt_SP.
(parse_operands): Likewise.
* testsuite/gas/aarch64/armv8_5-a-memtag.d: Update tests.
* testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
*** include/ChangeLog ***
2019-04-11 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rt_SP.
*** opcodes/ChangeLog ***
2019-04-11 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.c (aarch64_print_operand): Add case for
AARCH64_OPND_Rt_SP.
(verify_constraints): Likewise.
* aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
(struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
to accept Rt|SP as first operand.
(AARCH64_OPERANDS): Add new Rt_SP.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
2019-04-11 11:19:37 +02:00
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2019-04-11 Sudakshina Das <sudi.das@arm.com>
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* opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rt_SP.
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2019-04-09 02:04:01 +02:00
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2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
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* elf/common.h (GNU_PROPERTY_X86_ISA_1_AVX512_BF16): New.
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2019-04-07 13:11:49 +02:00
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2019-04-07 Alan Modra <amodra@gmail.com>
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Merge from gcc.
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2019-04-03 Vineet Gupta <vgupta@synopsys.com>
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PR89877
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* longlong.h [__arc__] (add_ssaaaa): Add cc clobber.
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(sub_ddmmss): Likewise.
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2019-04-06 16:25:10 +02:00
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2019-04-06 H.J. Lu <hongjiu.lu@intel.com>
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* bfdlink.h (bfd_link_info): Remove x86-specific linker options.
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[GAS, Arm] CLI with architecture sensitive extensions
This patch adds a new framework to add architecture sensitive extensions, like
GCC does. This patch also implements all architecture extensions currently
available in GCC.
This framework works as follows. To enable architecture sensitive extensions
for a particular architecture, that architecture must contain an ARM_ARCH_OPT2
entry in the 'arm_archs' table. All fields here are the same as previous, with
the addition of a new extra field at the end to <name> it's extension table.
This <name>, corresponds to a <name>_ext_table of type 'struct arm_ext_table'.
This struct can be filled with three types of entries:
ARM_ADD (string <ext>, arm_feature_set <enable_bits>), which means +<ext> will
enable <enable_bits>
ARM_REMOVE (string <ext>, arm_feature_set <disable_bits>), which means
+no<ext> will disable <disable_bits>
ARM_EXT (string <ext>, arm_feature_set <enable_bits>, arm_feature_set
<disable_bits>), which means +<ext> will enable <enable_bits> and +no<ext>
will disable <disable_bits> (this is to be used instead of adding an
ARM_ADD and ARM_REMOVE for the same <ext>)
This patch does not disable the use of the old extensions, even if some of them
are duplicated in the new tables. This is a "in-between-step" as we may want to
deprecate the old table of extensions in later patches. For now, GAS will first
look for the +<ext> or +no<ext> in the new table and if no entry is found it
will continue searching in the old table, following old behaviour. If only an
ARM_ADD or an ARM_REMOVE is defined for <ext> and +no<ext> or +<ext> resp. is
used then it also continues to search the old table for it.
A couple of caveats:
- This patch does not enable the use of these architecture extensions with the
'.arch_extension' directive. This is future work that I will tend to later.
- This patch does not enable the use of these architecture extensions with the
-mcpu option. This is future work that I will tend to later.
- This patch does not change the current behaviour when combining an
architecture extension and using -mfpu on the command-line. The current
behaviour of GAS is to stage the union of feature bits enabled by both -march
and -mfpu. GCC behaves differently here, so this is something we may want to
revisit on a later date.
2019-04-01 11:43:32 +02:00
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|
2019-04-01 Andre Vieira <andre.simoesdiasvieira@arm.com>
|
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|
* opcode/arm.h (FPU_NEON_ARMV8_1): New.
|
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|
|
(FPU_ARCH_NEON_VFP_ARMV8_1): Use FPU_NEON_ARMV8_1.
|
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(FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): Likewise.
|
|
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|
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(FPU_ARCH_DOTPROD_NEON_VFP_ARMV8): Likewise.
|
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|
|
(FPU_ARCH_NEON_VFP_ARMV8_2_FP16): New.
|
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|
|
(FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML): New.
|
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|
|
(FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML): New.
|
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|
|
(FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4): New.
|
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|
2019-03-28 01:06:55 +01:00
|
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|
2019-03-28 Alan Modra <amodra@gmail.com>
|
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|
PR 24390
|
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|
* opcode/ppc.h (PPC_OPERAND_CR_REG): Comment.
|
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|
2019-03-25 13:08:53 +01:00
|
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|
2019-03-25 Tamar Christina <tamar.christina@arm.com>
|
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|
* dis-asm.h (struct disassemble_info): Add stop_offset.
|
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2019-03-13 12:09:10 +01:00
|
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|
2019-03-13 Sudakshina Das <sudi.das@arm.com>
|
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* elf/aarch64.h (DT_AARCH64_PAC_PLT): New.
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|
[BFD, LD, AArch64, 2/3] Add --force-bti to enable BTI and to select BTI enabled PLTs
This is part of the patch series to add support for BTI and
PAC in AArch64 linker.
1) This patch adds a new ld command line option: --force-bti.
In the presence of this option, the linker enables BTI with the
GNU_PROPERTY_AARCH64_FEATURE_1_BTI feature. This gives out warning
in case of missing gnu notes for BTI in inputs.
2) It also defines a new set of BTI enabled PLTs. These are used either
when all the inputs are marked with GNU_PROPERTY_AARCH64_FEATURE_1_BTI
or when the new --force-bti option is used. This required adding new
fields in elf_aarch64_link_hash_table so that we could make the PLT
related information more generic.
3) It also defines a dynamic tag DT_AARCH64_BTI_PLT. The linker uses
this whenever it picks BTI enabled PLTs.
All these are made according to the new AArch64 ELF ABI
https://developer.arm.com/docs/ihi0056/latest/elf-for-the-arm-64-bit-architecture-aarch64-abi-2018q4
*** bfd/ChangeLog ***
2019-03-13 Sudakshina Das <sudi.das@arm.com>
Szabolcs Nagy <szabolcs.nagy@arm.com>
* bfd-in.h (aarch64_plt_type, aarch64_enable_bti_type): New.
(aarch64_bti_pac_info): New.
(bfd_elf64_aarch64_set_options): Add aarch64_bti_pac_info argument.
(bfd_elf32_aarch64_set_options): Likewise.
* bfd-in2.h: Regenerate
* elfnn-aarch64.c (PLT_BTI_ENTRY_SIZE): New.
(PLT_BTI_SMALL_ENTRY_SIZE, PLT_BTI_TLSDESC_ENTRY_SIZE): New.
(elfNN_aarch64_small_plt0_bti_entry): New.
(elfNN_aarch64_small_plt_bti_entry): New.
(elfNN_aarch64_tlsdesc_small_plt_bti_entry): New.
(elf_aarch64_obj_tdata): Add no_bti_warn and plt_type fields.
(elf_aarch64_link_hash_table): Add plt0_entry, plt_entry and
tlsdesc_plt_entry_size fields.
(elfNN_aarch64_link_hash_table_create): Initialise the new fields.
(setup_plt_values): New helper function.
(bfd_elfNN_aarch64_set_options): Use new bp_info to set plt sizes and
bti enable type.
(elfNN_aarch64_allocate_dynrelocs): Use new size members instead of
fixed macros.
(elfNN_aarch64_size_dynamic_sections): Likewise and add checks.
(elfNN_aarch64_create_small_pltn_entry): Use new generic pointers
to plt stubs instead of fixed ones and update filling them according
to the need for bti.
(elfNN_aarch64_init_small_plt0_entry): Likewise.
(elfNN_aarch64_finish_dynamic_sections): Likewise.
(get_plt_type, elfNN_aarch64_get_synthetic_symtab): New.
(elfNN_aarch64_plt_sym_val): Update size accordingly.
(elfNN_aarch64_link_setup_gnu_properties): Set up plts if BTI GNU NOTE
is set.
(bfd_elfNN_get_synthetic_symtab): Define.
(elfNN_aarch64_merge_gnu_properties): Give out warning with --force-bti
and mising BTI NOTE SECTION.
*** binutils/ChangeLog ***
2019-03-13 Sudakshina Das <sudi.das@arm.com>
Szabolcs Nagy <szabolcs.nagy@arm.com>
* readelf.c (get_aarch64_dynamic_type): New.
(get_dynamic_type): Use above for EM_AARCH64.
(dynamic_section_aarch64_val): New.
(process_dynamic_section): Use above for EM_AARCH64.
*** include/ChangeLog ***
2019-03-13 Sudakshina Das <sudi.das@arm.com>
Szabolcs Nagy <szabolcs.nagy@arm.com>
* elf/aarch64.h (DT_AARCH64_BTI_PLT): New.
*** ld/ChangeLog ***
2019-03-13 Sudakshina Das <sudi.das@arm.com>
Szabolcs Nagy <szabolcs.nagy@arm.com>
* NEWS: Document --force-bti.
* emultempl/aarch64elf.em (plt_type, bti_type, OPTION_FORCE_BTI): New.
(PARSE_AND_LIST_SHORTOPTS, PARSE_AND_LIST_OPTIONS): Add force-bti.
(PARSE_AND_LIST_ARGS_CASES): Handle OPTION_FORCE_BTI.
* testsuite/ld-aarch64/aarch64-elf.exp: Add all the tests below.
* testsuite/ld-aarch64/bti-plt-1.d: New test.
* testsuite/ld-aarch64/bti-plt-1.s: New test.
* testsuite/ld-aarch64/bti-plt-2.s: New test.
* testsuite/ld-aarch64/bti-plt-2.d: New test.
* testsuite/ld-aarch64/bti-plt-3.d: New test.
* testsuite/ld-aarch64/bti-plt-4.d: New test.
* testsuite/ld-aarch64/bti-plt-5.d: New test.
* testsuite/ld-aarch64/bti-plt-6.d: New test.
* testsuite/ld-aarch64/bti-plt-7.d: New test.
* testsuite/ld-aarch64/bti-plt-so.s: New test.
* testsuite/ld-aarch64/bti-plt.ld: New test.
2019-03-13 11:54:30 +01:00
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2019-03-13 Sudakshina Das <sudi.das@arm.com>
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Szabolcs Nagy <szabolcs.nagy@arm.com>
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* elf/aarch64.h (DT_AARCH64_BTI_PLT): New.
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2019-03-13 11:42:27 +01:00
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2019-03-13 Sudakshina Das <sudi.das@arm.com>
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* elf/common.h (GNU_PROPERTY_AARCH64_FEATURE_1_AND): New.
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(GNU_PROPERTY_AARCH64_FEATURE_1_BTI): New.
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(GNU_PROPERTY_AARCH64_FEATURE_1_PAC): New.
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2019-02-20 11:39:28 +01:00
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2019-02-20 Alan Hayward <alan.hayward@arm.com>
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* elf/common.h (NT_ARM_PAC_MASK): Add define.
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2019-02-15 13:50:52 +01:00
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2019-02-15 Saagar Jha <saagar@saagarjha.com>
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* mach-o/loader.h: Use new OS names in comments.
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2019-02-12 14:02:48 +01:00
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2019-02-11 Philippe Waroquiers <philippe.waroquiers@skynet.be>
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* splay-tree.h (splay_tree_delete_key_fn): Update comment.
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(splay_tree_delete_value_fn): Likewise.
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2019-01-31 17:01:27 +01:00
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2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
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* opcode/s390.h (enum s390_opcode_cpu_val): Add
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S390_OPCODE_ARCH13.
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2019-01-25 14:57:14 +01:00
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2019-01-25 Sudakshina Das <sudi.das@arm.com>
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Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
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* opcode/aarch64.h (enum aarch64_opnd): Remove
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AARCH64_OPND_ADDR_SIMPLE_2.
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(enum aarch64_insn_class): Remove ldstgv_indexed.
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2019-01-21 22:50:24 +01:00
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2019-01-22 Tom Tromey <tom@tromey.com>
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* coff/ecoff.h: Include coff/sym.h.
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2019-01-19 16:55:50 +01:00
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2018-06-24 Nick Clifton <nickc@redhat.com>
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2.32 branch created.
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2019-01-16 22:14:59 +01:00
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2019-01-16 Kito Cheng <kito@andestech.com>
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* elf/riscv.h (SHT_RISCV_ATTRIBUTES): Define.
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(Tag_RISCV_arch): Likewise.
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(Tag_RISCV_priv_spec): Likewise.
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(Tag_RISCV_priv_spec_minor): Likewise.
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(Tag_RISCV_priv_spec_revision): Likewise.
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(Tag_RISCV_unaligned_access): Likewise.
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(Tag_RISCV_stack_align): Likewise.
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2019-01-11 10:47:42 +01:00
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2019-01-14 Pavel I. Kryukov <kryukov@frtk.ru>
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* dis-asm.h: include <string.h>
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Sync libiberty sources with gcc master versions.
. * libiberty: Sync with gcc. Bring in:
2019-01-09 Sandra Loosemore <sandra@codesourcery.com>
PR other/16615
* cp-demangle.c: Mechanically replace "can not" with "cannot".
* floatformat.c: Likewise.
* strerror.c: Likewise.
2018-12-22 Jason Merrill <jason@redhat.com>
Remove support for demangling GCC 2.x era mangling schemes.
* cplus-dem.c: Remove cplus_mangle_opname, cplus_demangle_opname,
internal_cplus_demangle, and all subroutines.
(libiberty_demanglers): Remove entries for ancient GNU (pre-3.0),
Lucid, ARM, HP, and EDG demangling styles.
(cplus_demangle): Remove 'work' variable. Don't call
internal_cplus_demangle.
include * Merge from GCC:
2018-12-22 Jason Merrill <jason@redhat.com>
* demangle.h: Remove support for ancient GNU (pre-3.0), Lucid,
ARM, HP, and EDG demangling styles.
2019-01-10 10:44:13 +01:00
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2019-01-10 Nick Clifton <nickc@redhat.com>
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* Merge from GCC:
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2018-12-22 Jason Merrill <jason@redhat.com>
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* demangle.h: Remove support for ancient GNU (pre-3.0), Lucid,
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ARM, HP, and EDG demangling styles.
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2019-01-09 22:59:16 +01:00
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2019-01-09 Sandra Loosemore <sandra@codesourcery.com>
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Merge from GCC:
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PR other/16615
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* libiberty.h: Mechanically replace "can not" with "cannot".
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* plugin-api.h: Likewise.
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2018-12-25 12:44:15 +01:00
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2018-12-25 Yoshinori Sato <ysato@users.sourceforge.jp>
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* elf/rx.h (EF_RX_CPU_MASK): Update new bits.
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(E_FLAG_RX_V3): New RXv3 type.
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* opcode/rx.h (RX_Size): Add double size.
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(RX_Operand_Type): Add double FPU registers.
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(RX_Opcode_ID): Add new instuctions.
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2019-01-01 11:31:27 +01:00
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2019-01-01 Alan Modra <amodra@gmail.com>
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Update year range in copyright notice of all files.
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2019-01-01 11:53:15 +01:00
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For older changes see ChangeLog-2018
|
2016-01-01 11:44:31 +01:00
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2019-01-01 11:53:15 +01:00
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Copyright (C) 2019 Free Software Foundation, Inc.
|
2016-01-01 11:44:31 +01:00
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Copying and distribution of this file, with or without modification,
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are permitted in any medium without royalty provided the copyright
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notice and this notice are preserved.
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Local Variables:
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mode: change-log
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left-margin: 8
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fill-column: 74
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version-control: never
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End:
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