2004-01-09 03:34:04 +01:00
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@c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1999, 2000, 2001,
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2010-02-25 12:15:48 +01:00
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@c 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
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2001-03-09 00:24:26 +01:00
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@c Free Software Foundation, Inc.
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1999-05-03 09:29:11 +02:00
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@c This is part of the GAS manual.
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@c For copying conditions, see the file as.texinfo.
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@ifset GENERIC
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@page
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@node MIPS-Dependent
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@chapter MIPS Dependent Features
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@end ifset
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@ifclear GENERIC
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@node Machine Dependencies
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@chapter MIPS Dependent Features
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@end ifclear
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@cindex MIPS processor
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@sc{gnu} @code{@value{AS}} for @sc{mips} architectures supports several
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2000-12-02 01:55:22 +01:00
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different @sc{mips} processors, and MIPS ISA levels I through V, MIPS32,
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2000-12-12 20:36:32 +01:00
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and MIPS64. For information about the @sc{mips} instruction set, see
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@cite{MIPS RISC Architecture}, by Kane and Heindrich (Prentice-Hall).
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For an overview of @sc{mips} assembly conventions, see ``Appendix D:
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Assembly Language Programming'' in the same work.
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1999-05-03 09:29:11 +02:00
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@menu
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* MIPS Opts:: Assembler options
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* MIPS Object:: ECOFF object code
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* MIPS Stabs:: Directives for debugging information
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* MIPS ISA:: Directives to override the ISA level
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2005-03-04 10:51:11 +01:00
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* MIPS symbol sizes:: Directives to override the size of symbols
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1999-05-03 09:29:11 +02:00
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* MIPS autoextend:: Directives for extending MIPS 16 bit instructions
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* MIPS insn:: Directive to mark data as an instruction
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* MIPS option stack:: Directives to save and restore options
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2002-03-16 11:00:43 +01:00
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* MIPS ASE instruction generation overrides:: Directives to control
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generation of MIPS ASE instructions
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* config/tc-mips.c (file_mips_soft_float, file_mips_single_float):
New statics.
(OPTION_ELF_BASE): Make room for new option macros.
(OPTION_SOFT_FLOAT, OPTION_HARD_FLOAT, OPTION_SINGLE_FLOAT,
OPTION_DOUBLE_FLOAT): New option macros.
(md_longopts): Add msoft-float, mhard-float, msingle-float and
mdouble-float.
(md_parse_option): Handle OPTION_SINGLE_FLOAT,
OPTION_DOUBLE_FLOAT, OPTION_SOFT_FLOAT and OPTION_HARD_FLOAT.
(md_show_usage): Add -msoft-float, -mhard-float, -msingle-float
and -mdouble-float.
(struct mips_set_options): New fields soft_float and single_float.
(mips_opts): Initialized them. Add comment for each field
initializer.
(mips_after_parse_args): Set them based on file_mips_soft_float
and file_mips_single_float.
(s_mipsset): Add support for `.set softfloat', `.set hardfloat',
`.set singlefloat' and `.set doublefloat'.
(is_opcode_valid): New function to invoke OPCODE_IS_MEMBER.
Handle single-float and soft-float instructions here.
(macro_build, mips_ip): Use it instead of OPCODE_IS_MEMBER.
(is_opcode_valid_16): New function.
(mips16_ip): Use it instead of OPCODE_IS_MEMBER.
(macro) <M_LDC1_AB, M_SDC1_AB, M_L_DOB, M_L_DAB, M_S_DAB,
M_S_DOB>: Remove special-casing of r4650.
* doc/c-mips.texi (-march=): Add Octeon.
(MIPS Opts): Document -msoft-float and -mhard-float. Document
-msingle-float and -mdouble-float.
(MIPS floating-point): New section. Document `.set softfloat' and
`.set hardfloat'. Document `.set singlefloat' and `.set
doublefloat'.
2008-04-28 19:06:28 +02:00
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* MIPS floating-point:: Directives to override floating-point options
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1999-05-03 09:29:11 +02:00
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@end menu
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@node MIPS Opts
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@section Assembler options
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The @sc{mips} configurations of @sc{gnu} @code{@value{AS}} support these
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special options:
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@table @code
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@cindex @code{-G} option (MIPS)
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@item -G @var{num}
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This option sets the largest size of an object that can be referenced
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implicitly with the @code{gp} register. It is only accepted for targets
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that use @sc{ecoff} format. The default value is 8.
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@cindex @code{-EB} option (MIPS)
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@cindex @code{-EL} option (MIPS)
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@cindex MIPS big-endian output
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@cindex MIPS little-endian output
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@cindex big-endian output, MIPS
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@cindex little-endian output, MIPS
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@item -EB
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@itemx -EL
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Any @sc{mips} configuration of @code{@value{AS}} can select big-endian or
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little-endian output at run time (unlike the other @sc{gnu} development
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tools, which must be configured for one or the other). Use @samp{-EB}
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to select big-endian output, and @samp{-EL} for little-endian.
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2007-04-02 16:25:27 +02:00
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@item -KPIC
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@cindex PIC selection, MIPS
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@cindex @option{-KPIC} option, MIPS
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Generate SVR4-style PIC. This option tells the assembler to generate
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SVR4-style position-independent macro expansions. It also tells the
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assembler to mark the output file as PIC.
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@item -mvxworks-pic
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@cindex @option{-mvxworks-pic} option, MIPS
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Generate VxWorks PIC. This option tells the assembler to generate
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VxWorks-style position-independent macro expansions.
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1999-05-03 09:29:11 +02:00
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@cindex MIPS architecture options
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@item -mips1
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@itemx -mips2
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@itemx -mips3
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@itemx -mips4
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2010-02-25 12:15:48 +01:00
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@itemx -mips5xo
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2000-12-01 22:35:38 +01:00
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@itemx -mips32
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[ bfd/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* aoutx.h (NAME(aout,machine_type)): Add bfd_mach_mipsisa32r2 case.
* archures.c (bfd_mach_mipsisa32r2): New define.
* bfd-in2.h: Regenerate.
* cpu-mips.c (I_mipsisa32r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa32r2.
* elfxx-mips.c (elf_mips_isa, _bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_32R2.
(_bfd_mips_elf_final_write_processing): Add
bfd_mach_mipsisa32r2 case.
(_bfd_mips_elf_merge_private_bfd_data): Handle merging of
binaries marked as using MIPS32 Release 2.
[ binutils/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* doc/binutils.texi (objdump): Note MIPS HWR (Hardware Register)
changes in MIPS -M options.
[ gas/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* configure.in: Recognize mipsisa32r2, mipsisa32r2el, and
CPU variants.
* configure: Regenerate.
* config/tc-mips.c (ISA_HAS_DROR, ISA_HAS_ROR): New defines.
(macro_build): Handle "K" operand.
(macro2): Use ISA_HAS_DROR and ISA_HAS_ROR in the places where
CPU_HAS_DROR and CPU_HAS_ROR are currently used.
(mips_ip): New variable "lastpos", and implement "+A", "+B",
and "+C" operands for MIPS32 Release 2 ins/ext instructions.
Implement "K" operand for MIPS32 Release 2 rdhwr instruction.
(validate_mips_insn): Implement "+" as a way to extend the
allowed operands, and implement "K", "+A", "+B", and "+C"
operands.
(OPTION_MIPS32R2): New define.
(md_longopts): Add entry for OPTION_MIPS32R2.
(OPTION_ELF_BASE): Adjust to accomodate OPTIONS_MIPS32R2.
(md_parse_option): Handle OPTION_MIPS32R2.
(s_mipsset): Reimplement handling of ".set mipsN" options
and add support for ".set mips32r2".
(mips_cpu_info_table): Add entry for "mips32r2" (MIPS32 Release 2).
(md_show_usage): Document "-mips32r2" option.
* doc/as.texinfo: Document "-mips32r2" option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips32r2.d: New test.
* gas/mips/hwr-names-mips32r2.d: New test.
* gas/mips/hwr-names-numeric.d: New test.
* gas/mips/hwr-names.s: New test source file.
* gas/mips/mips32r2.d: New test.
* gas/mips/mips32r2.s: New test source file.
* gas/mips/mips32r2-ill.l: New test.
* gas/mips/mips32r2-ill.s: New test source file.
* gas/mips/mips.exp: Add mips32r2 architecture data array
entry. Run new tests mentioned above.
[ include/elf/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_32R2): New define.
[ include/opcode/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document "+" as the start of two-character operand
type names, and add new "K", "+A", "+B", and "+C" operand types.
(OP_MASK_INSMSB, OP_SH_INSMSB, OP_MASK_EXTMSB)
(OP_SH_EXTMSB, INSN_ISA32R2, ISA_MIPS32R2, CPU_MIPS32R2): New
defines.
[ opcodes/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_cp0_names_mips3264r2, mips_hwr_names_numeric)
(mips_hwr_names_mips3264r2): New arrays.
(mips_arch_choice): New "hwr_names" member.
(mips_arch_choices): Adjust for structure change, and add a new
entry for "mips32r2" ISA.
(mips_hwr_names): New variable.
(set_default_mips_dis_options): Set mips_hwr_names.
(parse_mips_dis_option): New "hwr-names" option which sets
mips_hwr_names, and adjust "reg-names=ARCH" to set mips_hwr_names.
(print_insn_arg): Change return type to "int"
and use that to indicate number of characters consumed.
Add support for "+" operand extension character, "+A", "+B",
"+C", and "K" operands.
(print_insn_mips): Adjust for changes to print_insn_arg.
(print_mips_disassembler_options): Adjust for "hwr-names"
addition and "reg-names" change.
* mips-opc (I33): New define (shorthand for INSN_ISA32R2).
(mips_builtin_opcodes): Note that "nop" and "ssnop" are special
forms of "sll". Add new MIPS32 Release 2 instructions: ehb,
di, ei, ext, ins, jr.hb, jalr.hb, mfhc1, mfhc2, mthc1, mthc2,
rdhwr, rdpgpr, seb, seh, synci, wrpgpr, wsbh.
Note that hardware rotate instructions (ror, rorv) can be
used on MIPS32 Release 2, and add the official mnemonics
for them (rotr, rotrv) and the similar "rotl" mnemonic for
left-rotate.
2002-12-31 08:29:29 +01:00
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@itemx -mips32r2
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2000-12-02 01:55:22 +01:00
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@itemx -mips64
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[ bfd/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* archures.c (bfd_mach_mipsisa64r2): New define.
* bfd-in2.h: Regenerate.
* aoutx.h (NAME(aout,machine_type)): Handle bfd_mach_mipsisa64r2.
* cpu-mips.c (I_mipsisa64r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa64r2.
* elfxx-mips.c (_bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_64R2.
(mips_set_isa_flags): Add bfd_mach_mipsisa64r2 case.
(mips_mach_extensions): Add entry for bfd_mach_mipsisa64r2.
[ binutils/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* readelf.c (get_machine_flags): Handle E_MIPS_ARCH_64R2.
[ gas/Changelog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa64r2, mipsisa64r2el, mipsisa64r2*): New CPUs.
* configure: Regenerate.
* config/tc-mips.c (imm2_expr): New variable.
(md_assemble, mips16_ip): Initialize imm2_expr.
(ISA_HAS_64BIT_REGS, ISA_HAS_DROR, ISA_HAS_ROR): Add ISA_MIPS64R2.
(macro_build): Handle +A, +B, +C, +E, +F, +G, and +H format operands.
(macro): Handle M_DEXT and M_DINS.
(validate_mips_insn): Handle +E, +F, +G, +H, and +I format operands.
(mips_ip): Likewise.
(OPTION_MIPS64R2): New define.
(md_longopts): New entry for -mips64r2 (OPTION_MIPS64R2).
OPTION_ASE_BASE): Increase to compensate for OPTION_MIPS64R2.
(md_parse_option): Handle OPTION_MIPS64R2.
(s_mipsset): Handle setting "mips64r2" ISA.
(mips_cpu_info_table): Add mips64r2.
(md_show_usage): Document -mips64r2 option.
* doc/as.texinfo: Docuemnt -mips64r2 option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips64r2.d: New file.
* gas/mips/cp0sel-names-mips64r2.d: New file.
* gas/mips/elf_arch_mips64r2.d: New file.
* gas/mips/hwr-names-mips64r2.d: New file.
* gas/mips/mips32r2-ill-fp64.l: New file.
* gas/mips/mips32r2-ill-fp64.s: New file.
* gas/mips/mips64r2-ill.l: New file.
* gas/mips/mips64r2-ill.s: New file.
* gas/mips/mips64r2.d: New file.
* gas/mips/mips64r2.s: New file.
* gas/mips/mips.exp: Define "mips64r2" arch, and run new tests.
[ include/elf/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_64R2): New define.
[ include/opcode/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document +E, +F, +G, +H, and +I operand types.
Update documentation of I, +B and +C operand types.
(INSN_ISA64R2, ISA_MIPS64R2, CPU_MIPS64R2): New defines.
(M_DEXT, M_DINS): New enum values.
[ ld/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ldmain.c (get_emulation): Ignore "-mips64r2".
[ ld/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ld-mips-elf/mips-elf-flags.exp: Add tests for combinations
with MIPS64r2.
[ opcodes/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_arch_choices): Add entry for "mips64r2"
(print_insn_args): Add handing for +E, +F, +G, and +H.
* mips-opc.c (I65): New define for MIPS64r2.
(mips_builtin_opcodes): Add "dext", "dextm", "dextu", "dins",
"dinsm", "dinsu", "drotl", "drotr", "drotr32", "drotrv", "dsbh",
and "dshd" for MIPS64r2. Adjust "dror", "dror32", and "drorv" to
be supported on MIPS64r2.
2003-09-30 18:17:15 +02:00
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@itemx -mips64r2
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1999-05-03 09:29:11 +02:00
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Generate code for a particular MIPS Instruction Set Architecture level.
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@samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors,
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@samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the
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2000-12-02 01:55:22 +01:00
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@sc{r4000} processor, and @samp{-mips4} to the @sc{r8000} and
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[ bfd/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* archures.c (bfd_mach_mipsisa64r2): New define.
* bfd-in2.h: Regenerate.
* aoutx.h (NAME(aout,machine_type)): Handle bfd_mach_mipsisa64r2.
* cpu-mips.c (I_mipsisa64r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa64r2.
* elfxx-mips.c (_bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_64R2.
(mips_set_isa_flags): Add bfd_mach_mipsisa64r2 case.
(mips_mach_extensions): Add entry for bfd_mach_mipsisa64r2.
[ binutils/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* readelf.c (get_machine_flags): Handle E_MIPS_ARCH_64R2.
[ gas/Changelog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa64r2, mipsisa64r2el, mipsisa64r2*): New CPUs.
* configure: Regenerate.
* config/tc-mips.c (imm2_expr): New variable.
(md_assemble, mips16_ip): Initialize imm2_expr.
(ISA_HAS_64BIT_REGS, ISA_HAS_DROR, ISA_HAS_ROR): Add ISA_MIPS64R2.
(macro_build): Handle +A, +B, +C, +E, +F, +G, and +H format operands.
(macro): Handle M_DEXT and M_DINS.
(validate_mips_insn): Handle +E, +F, +G, +H, and +I format operands.
(mips_ip): Likewise.
(OPTION_MIPS64R2): New define.
(md_longopts): New entry for -mips64r2 (OPTION_MIPS64R2).
OPTION_ASE_BASE): Increase to compensate for OPTION_MIPS64R2.
(md_parse_option): Handle OPTION_MIPS64R2.
(s_mipsset): Handle setting "mips64r2" ISA.
(mips_cpu_info_table): Add mips64r2.
(md_show_usage): Document -mips64r2 option.
* doc/as.texinfo: Docuemnt -mips64r2 option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips64r2.d: New file.
* gas/mips/cp0sel-names-mips64r2.d: New file.
* gas/mips/elf_arch_mips64r2.d: New file.
* gas/mips/hwr-names-mips64r2.d: New file.
* gas/mips/mips32r2-ill-fp64.l: New file.
* gas/mips/mips32r2-ill-fp64.s: New file.
* gas/mips/mips64r2-ill.l: New file.
* gas/mips/mips64r2-ill.s: New file.
* gas/mips/mips64r2.d: New file.
* gas/mips/mips64r2.s: New file.
* gas/mips/mips.exp: Define "mips64r2" arch, and run new tests.
[ include/elf/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_64R2): New define.
[ include/opcode/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document +E, +F, +G, +H, and +I operand types.
Update documentation of I, +B and +C operand types.
(INSN_ISA64R2, ISA_MIPS64R2, CPU_MIPS64R2): New defines.
(M_DEXT, M_DINS): New enum values.
[ ld/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ldmain.c (get_emulation): Ignore "-mips64r2".
[ ld/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ld-mips-elf/mips-elf-flags.exp: Add tests for combinations
with MIPS64r2.
[ opcodes/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_arch_choices): Add entry for "mips64r2"
(print_insn_args): Add handing for +E, +F, +G, and +H.
* mips-opc.c (I65): New define for MIPS64r2.
(mips_builtin_opcodes): Add "dext", "dextm", "dextu", "dins",
"dinsm", "dinsu", "drotl", "drotr", "drotr32", "drotrv", "dsbh",
and "dshd" for MIPS64r2. Adjust "dror", "dror32", and "drorv" to
be supported on MIPS64r2.
2003-09-30 18:17:15 +02:00
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@sc{r10000} processors. @samp{-mips5}, @samp{-mips32}, @samp{-mips32r2},
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@samp{-mips64}, and @samp{-mips64r2}
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correspond to generic
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@sc{MIPS V}, @sc{MIPS32}, @sc{MIPS32 Release 2}, @sc{MIPS64},
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and @sc{MIPS64 Release 2}
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ISA processors, respectively. You can also switch
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2000-12-12 20:36:32 +01:00
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instruction sets during the assembly; see @ref{MIPS ISA, Directives to
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2001-06-29 23:27:43 +02:00
|
|
|
override the ISA level}.
|
1999-05-03 09:29:11 +02:00
|
|
|
|
2000-02-22 19:55:30 +01:00
|
|
|
@item -mgp32
|
2001-08-02 12:15:24 +02:00
|
|
|
@itemx -mfp32
|
|
|
|
Some macros have different expansions for 32-bit and 64-bit registers.
|
|
|
|
The register sizes are normally inferred from the ISA and ABI, but these
|
|
|
|
flags force a certain group of registers to be treated as 32 bits wide at
|
|
|
|
all times. @samp{-mgp32} controls the size of general-purpose registers
|
|
|
|
and @samp{-mfp32} controls the size of floating-point registers.
|
|
|
|
|
[ gas/ChangeLog ]
* config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS): Rename.
(ISA_SUPPORTS_DSP_ASE, ISA_SUPPORTS_MT_ASE, ISA_HAS_64BIT_FPRS,
ISA_HAS_MXHC1): New macros.
(HAVE_32BIT_FPRS): Use ISA_HAS_64BIT_FPRS instead of
ISA_HAS_64BIT_REGS. Formatting fixes. Improved comments.
(mips_cpu_info): Change to use combined ASE/IS_ISA flag.
(MIPS_CPU_IS_ISA, MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP,
MIPS_CPU_ASE_MT, MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX): New defines.
(mips_after_parse_args): Change default handling of float register
size to account for 32bit code with 64bit FP. Better sanity checking
of ISA/ASE/ABI option combinations.
(s_mipsset): Support switching of GPR and FPR sizes via
.set {g,f}p={32,64,default}. Better sanity checking for .set ASE
options.
(mips_elf_final_processing): We should record the use of 64bit FP
registers in 32bit code but we don't, because ELF header flags are
a scarce ressource.
(mips_cpu_info_table): Add ASE flags for CPUs with mandatory ASE
extensions. Add 4ksc, 4kec, 4kem, 4kep, 4ksd, m4kp, 24kec, 24kef,
24kex, 34kc, 34kf, 34kx, 25kf CPU definitions.
(mips_cpu_info_from_isa): Use MIPS_CPU_IS_ISA.
* doc/c-mips.texi: Document .set {g,f}p={32,64,default}. Document
missing -march options. Document .set arch=CPU. Move .set smartmips
to ASE page. Use @code for .set FOO examples.
[ gas/testsuite/Changelog ]
* gas/mips/mips-gp32-fp64-pic.d, mips/mips-gp32-fp64.d,
gas/mips/mips-gp64-fp32-pic.d, gas/mips/mips-gp64-fp32.l,
gas/mips/mips-gp64-fp64.d: Adjust test cases to the changes assembler
output.
* gas/mips/mips-gp32-fp64.l, gas/mips/mips-gp64-fp32-pic.l: New files,
catch assembler warnings.
2006-05-23 17:37:20 +02:00
|
|
|
The @code{.set gp=32} and @code{.set fp=32} directives allow the size
|
|
|
|
of registers to be changed for parts of an object. The default value is
|
|
|
|
restored by @code{.set gp=default} and @code{.set fp=default}.
|
|
|
|
|
2001-08-02 12:15:24 +02:00
|
|
|
On some MIPS variants there is a 32-bit mode flag; when this flag is
|
|
|
|
set, 64-bit instructions generate a trap. Also, some 32-bit OSes only
|
|
|
|
save the 32-bit registers on a context switch, so it is essential never
|
|
|
|
to use the 64-bit registers.
|
2000-02-22 19:55:30 +01:00
|
|
|
|
|
|
|
@item -mgp64
|
[ gas/ChangeLog ]
* config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS): Rename.
(ISA_SUPPORTS_DSP_ASE, ISA_SUPPORTS_MT_ASE, ISA_HAS_64BIT_FPRS,
ISA_HAS_MXHC1): New macros.
(HAVE_32BIT_FPRS): Use ISA_HAS_64BIT_FPRS instead of
ISA_HAS_64BIT_REGS. Formatting fixes. Improved comments.
(mips_cpu_info): Change to use combined ASE/IS_ISA flag.
(MIPS_CPU_IS_ISA, MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP,
MIPS_CPU_ASE_MT, MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX): New defines.
(mips_after_parse_args): Change default handling of float register
size to account for 32bit code with 64bit FP. Better sanity checking
of ISA/ASE/ABI option combinations.
(s_mipsset): Support switching of GPR and FPR sizes via
.set {g,f}p={32,64,default}. Better sanity checking for .set ASE
options.
(mips_elf_final_processing): We should record the use of 64bit FP
registers in 32bit code but we don't, because ELF header flags are
a scarce ressource.
(mips_cpu_info_table): Add ASE flags for CPUs with mandatory ASE
extensions. Add 4ksc, 4kec, 4kem, 4kep, 4ksd, m4kp, 24kec, 24kef,
24kex, 34kc, 34kf, 34kx, 25kf CPU definitions.
(mips_cpu_info_from_isa): Use MIPS_CPU_IS_ISA.
* doc/c-mips.texi: Document .set {g,f}p={32,64,default}. Document
missing -march options. Document .set arch=CPU. Move .set smartmips
to ASE page. Use @code for .set FOO examples.
[ gas/testsuite/Changelog ]
* gas/mips/mips-gp32-fp64-pic.d, mips/mips-gp32-fp64.d,
gas/mips/mips-gp64-fp32-pic.d, gas/mips/mips-gp64-fp32.l,
gas/mips/mips-gp64-fp64.d: Adjust test cases to the changes assembler
output.
* gas/mips/mips-gp32-fp64.l, gas/mips/mips-gp64-fp32-pic.l: New files,
catch assembler warnings.
2006-05-23 17:37:20 +02:00
|
|
|
@itemx -mfp64
|
|
|
|
Assume that 64-bit registers are available. This is provided in the
|
|
|
|
interests of symmetry with @samp{-mgp32} and @samp{-mfp32}.
|
|
|
|
|
|
|
|
The @code{.set gp=64} and @code{.set fp=64} directives allow the size
|
|
|
|
of registers to be changed for parts of an object. The default value is
|
|
|
|
restored by @code{.set gp=default} and @code{.set fp=default}.
|
2000-02-22 19:55:30 +01:00
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
@item -mips16
|
|
|
|
@itemx -no-mips16
|
|
|
|
Generate code for the MIPS 16 processor. This is equivalent to putting
|
[ gas/ChangeLog ]
* config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS): Rename.
(ISA_SUPPORTS_DSP_ASE, ISA_SUPPORTS_MT_ASE, ISA_HAS_64BIT_FPRS,
ISA_HAS_MXHC1): New macros.
(HAVE_32BIT_FPRS): Use ISA_HAS_64BIT_FPRS instead of
ISA_HAS_64BIT_REGS. Formatting fixes. Improved comments.
(mips_cpu_info): Change to use combined ASE/IS_ISA flag.
(MIPS_CPU_IS_ISA, MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP,
MIPS_CPU_ASE_MT, MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX): New defines.
(mips_after_parse_args): Change default handling of float register
size to account for 32bit code with 64bit FP. Better sanity checking
of ISA/ASE/ABI option combinations.
(s_mipsset): Support switching of GPR and FPR sizes via
.set {g,f}p={32,64,default}. Better sanity checking for .set ASE
options.
(mips_elf_final_processing): We should record the use of 64bit FP
registers in 32bit code but we don't, because ELF header flags are
a scarce ressource.
(mips_cpu_info_table): Add ASE flags for CPUs with mandatory ASE
extensions. Add 4ksc, 4kec, 4kem, 4kep, 4ksd, m4kp, 24kec, 24kef,
24kex, 34kc, 34kf, 34kx, 25kf CPU definitions.
(mips_cpu_info_from_isa): Use MIPS_CPU_IS_ISA.
* doc/c-mips.texi: Document .set {g,f}p={32,64,default}. Document
missing -march options. Document .set arch=CPU. Move .set smartmips
to ASE page. Use @code for .set FOO examples.
[ gas/testsuite/Changelog ]
* gas/mips/mips-gp32-fp64-pic.d, mips/mips-gp32-fp64.d,
gas/mips/mips-gp64-fp32-pic.d, gas/mips/mips-gp64-fp32.l,
gas/mips/mips-gp64-fp64.d: Adjust test cases to the changes assembler
output.
* gas/mips/mips-gp32-fp64.l, gas/mips/mips-gp64-fp32-pic.l: New files,
catch assembler warnings.
2006-05-23 17:37:20 +02:00
|
|
|
@code{.set mips16} at the start of the assembly file. @samp{-no-mips16}
|
1999-05-03 09:29:11 +02:00
|
|
|
turns off this option.
|
|
|
|
|
2006-05-08 17:57:05 +02:00
|
|
|
@item -msmartmips
|
|
|
|
@itemx -mno-smartmips
|
|
|
|
Enables the SmartMIPS extensions to the MIPS32 instruction set, which
|
|
|
|
provides a number of new instructions which target smartcard and
|
|
|
|
cryptographic applications. This is equivalent to putting
|
[ gas/ChangeLog ]
* config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS): Rename.
(ISA_SUPPORTS_DSP_ASE, ISA_SUPPORTS_MT_ASE, ISA_HAS_64BIT_FPRS,
ISA_HAS_MXHC1): New macros.
(HAVE_32BIT_FPRS): Use ISA_HAS_64BIT_FPRS instead of
ISA_HAS_64BIT_REGS. Formatting fixes. Improved comments.
(mips_cpu_info): Change to use combined ASE/IS_ISA flag.
(MIPS_CPU_IS_ISA, MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP,
MIPS_CPU_ASE_MT, MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX): New defines.
(mips_after_parse_args): Change default handling of float register
size to account for 32bit code with 64bit FP. Better sanity checking
of ISA/ASE/ABI option combinations.
(s_mipsset): Support switching of GPR and FPR sizes via
.set {g,f}p={32,64,default}. Better sanity checking for .set ASE
options.
(mips_elf_final_processing): We should record the use of 64bit FP
registers in 32bit code but we don't, because ELF header flags are
a scarce ressource.
(mips_cpu_info_table): Add ASE flags for CPUs with mandatory ASE
extensions. Add 4ksc, 4kec, 4kem, 4kep, 4ksd, m4kp, 24kec, 24kef,
24kex, 34kc, 34kf, 34kx, 25kf CPU definitions.
(mips_cpu_info_from_isa): Use MIPS_CPU_IS_ISA.
* doc/c-mips.texi: Document .set {g,f}p={32,64,default}. Document
missing -march options. Document .set arch=CPU. Move .set smartmips
to ASE page. Use @code for .set FOO examples.
[ gas/testsuite/Changelog ]
* gas/mips/mips-gp32-fp64-pic.d, mips/mips-gp32-fp64.d,
gas/mips/mips-gp64-fp32-pic.d, gas/mips/mips-gp64-fp32.l,
gas/mips/mips-gp64-fp64.d: Adjust test cases to the changes assembler
output.
* gas/mips/mips-gp32-fp64.l, gas/mips/mips-gp64-fp32-pic.l: New files,
catch assembler warnings.
2006-05-23 17:37:20 +02:00
|
|
|
@code{.set smartmips} at the start of the assembly file.
|
2006-05-08 17:57:05 +02:00
|
|
|
@samp{-mno-smartmips} turns off this option.
|
|
|
|
|
2002-03-16 04:09:19 +01:00
|
|
|
@item -mips3d
|
|
|
|
@itemx -no-mips3d
|
|
|
|
Generate code for the MIPS-3D Application Specific Extension.
|
|
|
|
This tells the assembler to accept MIPS-3D instructions.
|
|
|
|
@samp{-no-mips3d} turns off this option.
|
|
|
|
|
[ gas/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* config/tc-mips.c (mips_set_options): New "ase_mdmx" member.
(mips_opts): Initialize "ase_mdmx" member.
(file_ase_mdmx): New variable.
(CPU_HAS_MDMX): New macro.
(md_begin): Initialize mips_opts.ase_mdmx and file_ase_mdmx
based on command line options and configuration defaults.
(macro_build): Note in comment that use of MDMX in macros is
not currently allowed.
(validate_mips_insn): Add support for the "O", "Q", "X", "Y", and
"Z" MDMX operand types.
(mips_ip): Accept MDMX instructions if mips_opts.ase_mdmx is set,
and add support for the "O", "Q", "X", "Y", and "Z" MDMX operand
types.
(OPTION_MDMX, OPTION_NO_MDMX, md_longopts, md_parse_option):
Add support for "-mdmx" and "-no-mdmx" options.
(OPTION_ELF_BASE): Move to accomodate new options.
(s_mipsset): Support ".set mdmx" and ".set nomdmx".
(mips_elf_final_processing): Set MDMX ASE ELF header flag if
file_ase_mdmx was set.
* doc/as.texinfo: Document -mdmx and -no-mdmx options.
* doc/c-mips.texi: Likewise, and document ".set mdmx" and ".set
nomdmx" directives.
[ gas/testsuite/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
* gas/mips/mips64-mdmx.s: New file.
* gas/mips/mips64-mdmx.d: Likewise.
* gas/mips/mips.exp: Run new "mips64-mdmx" test.
[ include/opcode/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
* mips.h (OP_SH_ALN, OP_MASK_ALN, OP_SH_VSEL, OP_MASK_VSEL)
(MDMX_FMTSEL_IMM_QH, MDMX_FMTSEL_IMM_OB, MDMX_FMTSEL_VEC_QH)
(MDMX_FMTSEL_VEC_OB, INSN_READ_MDMX_ACC, INSN_WRITE_MDMX_ACC)
(INSN_MDMX): New constants, for MDMX support.
(opcode character list): Add "O", "Q", "X", "Y", and "Z" for MDMX.
[ opcodes/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* mips-dis.c (print_insn_arg): Add support for 'O', 'Q', 'X', 'Y',
and 'Z' formats, for MDMX.
(mips_isa_type): Add MDMX instructions to the ISA
bit mask for bfd_mach_mipsisa64.
* mips-opc.c: Add support for MDMX instructions.
(MX): New definition.
* mips-dis.c: Update copyright years to include 2002.
2002-05-31 03:17:18 +02:00
|
|
|
@item -mdmx
|
|
|
|
@itemx -no-mdmx
|
|
|
|
Generate code for the MDMX Application Specific Extension.
|
|
|
|
This tells the assembler to accept MDMX instructions.
|
|
|
|
@samp{-no-mdmx} turns off this option.
|
|
|
|
|
2005-09-08 20:05:15 +02:00
|
|
|
@item -mdsp
|
|
|
|
@itemx -mno-dsp
|
[ gas/ChangeLog ]
* config/tc-mips.c (mips_set_options, mips_opts, file_ase_dspr2,
ISA_SUPPORTS_DSPR2_ASE, MIPS_CPU_ASE_DSPR2): Add DSP R2 ASE support.
(macro_build): Add case '2'.
(macro): Expand M_BALIGN to nop, packrl.ph or balign.
(validate_mips_insn): Add support for balign instruction.
(mips_ip): Handle DSP R2 instructions. Support balign instruction.
(OPTION_DSPR2, OPTION_NO_DSPR2, OPTION_COMPAT_ARCH_BASE,
md_parse_option, mips_after_parse_args): Add -mdspr2 and -mno-dspr2
command line options.
(s_mipsset): Add support for .set dspr2 and .set nodspr2 directives.
(md_show_usage): Add -mdspr2 and -mno-dspr2 help output.
* doc/c-mips.texi, doc/as.texinfo: Document -mdspr2, -mno-dspr2,
.set dspr2, .set nodspr2.
[ gas/testsuite/ChangeLog ]
* gas/mips/mips32-dspr2.s, gas/mips/mips32-dspr2.d: New test for
DSP R2.
* gas/mips/mips.exp: Run new test.
[ include/opcode/Changelog ]
* mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
(INSN_DSPR2): Add flag for DSP R2 instructions.
(M_BALIGN): New macro.
[ opcodes/ChangeLog ]
* mips-dis.c (mips_arch_choices): Add DSP R2 support.
(print_insn_args): Add support for balign instruction.
* mips-opc.c (D33): New shortcut for DSP R2 instructions.
(mips_builtin_opcodes): Add DSP R2 instructions.
[ sim/mips/ChangeLog ]
* Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
* configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
Add dsp2 to sim_igen_machine.
* configure: Regenerate.
* dsp.igen (do_ph_op): Add MUL support when op = 2.
(do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
(mulq_rs.ph): Use do_ph_mulq.
(MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
* mips.igen: Add dsp2 model and include dsp2.igen.
(MFHI, MFLO, MTHI, MTLO): Extend these instructions for
for *mips32r2, *mips64r2, *dsp.
(MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
for *mips32r2, *mips64r2, *dsp2.
* dsp2.igen: New file for MIPS DSP REV 2 ASE.
[ sim/testsuite/sim/mips/ChangeLog ]
* basic.exp: Run the dsp2 test.
* utils-dsp.inc (dspckacc_astio, dspck_tsimm): New macro.
* mips32-dsp2.s: New test.
2007-02-20 14:28:56 +01:00
|
|
|
Generate code for the DSP Release 1 Application Specific Extension.
|
|
|
|
This tells the assembler to accept DSP Release 1 instructions.
|
2005-09-08 20:05:15 +02:00
|
|
|
@samp{-mno-dsp} turns off this option.
|
|
|
|
|
[ gas/ChangeLog ]
* config/tc-mips.c (mips_set_options, mips_opts, file_ase_dspr2,
ISA_SUPPORTS_DSPR2_ASE, MIPS_CPU_ASE_DSPR2): Add DSP R2 ASE support.
(macro_build): Add case '2'.
(macro): Expand M_BALIGN to nop, packrl.ph or balign.
(validate_mips_insn): Add support for balign instruction.
(mips_ip): Handle DSP R2 instructions. Support balign instruction.
(OPTION_DSPR2, OPTION_NO_DSPR2, OPTION_COMPAT_ARCH_BASE,
md_parse_option, mips_after_parse_args): Add -mdspr2 and -mno-dspr2
command line options.
(s_mipsset): Add support for .set dspr2 and .set nodspr2 directives.
(md_show_usage): Add -mdspr2 and -mno-dspr2 help output.
* doc/c-mips.texi, doc/as.texinfo: Document -mdspr2, -mno-dspr2,
.set dspr2, .set nodspr2.
[ gas/testsuite/ChangeLog ]
* gas/mips/mips32-dspr2.s, gas/mips/mips32-dspr2.d: New test for
DSP R2.
* gas/mips/mips.exp: Run new test.
[ include/opcode/Changelog ]
* mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
(INSN_DSPR2): Add flag for DSP R2 instructions.
(M_BALIGN): New macro.
[ opcodes/ChangeLog ]
* mips-dis.c (mips_arch_choices): Add DSP R2 support.
(print_insn_args): Add support for balign instruction.
* mips-opc.c (D33): New shortcut for DSP R2 instructions.
(mips_builtin_opcodes): Add DSP R2 instructions.
[ sim/mips/ChangeLog ]
* Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
* configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
Add dsp2 to sim_igen_machine.
* configure: Regenerate.
* dsp.igen (do_ph_op): Add MUL support when op = 2.
(do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
(mulq_rs.ph): Use do_ph_mulq.
(MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
* mips.igen: Add dsp2 model and include dsp2.igen.
(MFHI, MFLO, MTHI, MTLO): Extend these instructions for
for *mips32r2, *mips64r2, *dsp.
(MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
for *mips32r2, *mips64r2, *dsp2.
* dsp2.igen: New file for MIPS DSP REV 2 ASE.
[ sim/testsuite/sim/mips/ChangeLog ]
* basic.exp: Run the dsp2 test.
* utils-dsp.inc (dspckacc_astio, dspck_tsimm): New macro.
* mips32-dsp2.s: New test.
2007-02-20 14:28:56 +01:00
|
|
|
@item -mdspr2
|
|
|
|
@itemx -mno-dspr2
|
|
|
|
Generate code for the DSP Release 2 Application Specific Extension.
|
|
|
|
This option implies -mdsp.
|
|
|
|
This tells the assembler to accept DSP Release 2 instructions.
|
|
|
|
@samp{-mno-dspr2} turns off this option.
|
|
|
|
|
* config/tc-mips.c (mips_set_options): Add ase_mt for MT instructions.
(mips_opts): Add -1 to initialize ase_mt.
(file_ase_mt): New variable for -mmt.
(CPU_HAS_MT): New define.
(validate_mips_insn): Add supports for +t, +T, !, $, *, &, g operand
formats.
(mips_ip): Check ase_mt to enable MT instructions.
Handle !, $, *, &, +T, +t, g operand formats.
For "mftc1", "mfthc1", "cftc1", "mttc1", "mtthc1", "cttc1", we allow
odd float registers.
(OPTION_MT, OPTION_NO_MT): New define.
(OPTION_COMPAT_ARCH_BASE): Change because of inserting MT define.
(md_parse_option): Parse OPTION_MT and OPTION_NO_MT.
(mips_after_parse_args): Set ase_mt based on CPU.
(s_mipsset): Handle ".set mt" and ".set nomt".
(mips_elf_final_processing): Remind of adding new flag for MT ASE.
(md_show_usage): Show usage of -mmt and -mno-mt.
* doc/as.texinfo: Document -mmt and -mno-mt options.
* doc/c-mips.texi: Likewise, and document ".set mt" and ".set nomt"
directives.
2005-09-06 20:53:03 +02:00
|
|
|
@item -mmt
|
|
|
|
@itemx -mno-mt
|
|
|
|
Generate code for the MT Application Specific Extension.
|
|
|
|
This tells the assembler to accept MT instructions.
|
|
|
|
@samp{-mno-mt} turns off this option.
|
|
|
|
|
2000-02-21 21:00:33 +01:00
|
|
|
@item -mfix7000
|
2002-05-31 01:38:19 +02:00
|
|
|
@itemx -mno-fix7000
|
2000-02-21 21:00:33 +01:00
|
|
|
Cause nops to be inserted if the read of the destination register
|
|
|
|
of an mfhi or mflo instruction occurs in the following two instructions.
|
|
|
|
|
2010-02-25 12:15:48 +01:00
|
|
|
@item -mfix-loongson2f-jump
|
|
|
|
@itemx -mno-fix-loongson2f-jump
|
|
|
|
Eliminate instruction fetch from outside 256M region to work around the
|
|
|
|
Loongson2F @samp{jump} instructions. Without it, under extreme cases,
|
|
|
|
the kernel may crash. The issue has been solved in latest processor
|
|
|
|
batches, but this fix has no side effect to them.
|
|
|
|
|
|
|
|
@item -mfix-loongson2f-nop
|
|
|
|
@itemx -mno-fix-loongson2f-nop
|
|
|
|
Replace nops by @code{or at,at,zero} to work around the Loongson2F
|
|
|
|
@samp{nop} errata. Without it, under extreme cases, cpu might
|
|
|
|
deadlock. The issue has been solved in latest loongson2f batches, but
|
|
|
|
this fix has no side effect to them.
|
|
|
|
|
2004-04-14 09:48:49 +02:00
|
|
|
@item -mfix-vr4120
|
2009-10-25 03:11:13 +01:00
|
|
|
@itemx -mno-fix-vr4120
|
2004-04-14 09:48:49 +02:00
|
|
|
Insert nops to work around certain VR4120 errata. This option is
|
|
|
|
intended to be used on GCC-generated code: it is not designed to catch
|
|
|
|
all problems in hand-written assembler code.
|
[gas/]
* doc/c-mips.texi: Add entries for -march=vr4120,vr4130,vr4181,
vr5400 and vr5500. Add entry for -mfix-vr4122-bugs.
* config/tc-mips.c (CPU_HAS_DROR, CPU_HAS_ROR): New macros.
(hilo_interlocks): True for CPU_VR5500.
(gpr_interlocks, cop_interlocks): True for CPU_VR5400 and CPU_VR5500.
(mips_fix_vr4122_bugs): New.
(append_insn): Work around 4122 errors if mips_fix_vr4122_bugs.
(mips_emit_delays): Likewise.
(macro2) [M_DROLI]: Use dror or dror32 if CPU_HAS_DROR.
[M_ROLI]: Likewise ror if CPU_HAS_ROR.
(validate_mips_insn, mips_ip): Handle '[', ']', 'e' and '%'.
(OPTION_FIX_VR4122, OPTION_NO_FIX_VR4122): New options.
(md_longopts): Add -mfix-vr4122-bugs and -no-mfix-vr4122-bugs.
(OPTION_ELF_BASE): Bump.
(md_parse_option): Handle the new options.
(mips_cpu_info_table): Add entries for vr4120, vr4130, vr4181,
vr5400 and vr5500.
[gas/testsuite/]
* gas/mips/mips4100.[sd]: Move dmadd16 and madd16 checks to...
* gas/mips/vr4111.[sd]: ...this new test.
* gas/mips/vr4120.[sd],
* gas/mips/vr4122.[sd],
* gas/mips/vr5400.[sd],
* gas/mips/vr5500.[sd]: New tests.
* mips.exp: Run them.
2002-09-30 14:04:54 +02:00
|
|
|
|
2005-03-09 10:53:50 +01:00
|
|
|
@item -mfix-vr4130
|
2009-10-25 03:11:13 +01:00
|
|
|
@itemx -mno-fix-vr4130
|
2005-03-09 10:53:50 +01:00
|
|
|
Insert nops to work around the VR4130 @samp{mflo}/@samp{mfhi} errata.
|
|
|
|
|
2009-04-09 17:55:59 +02:00
|
|
|
@item -mfix-24k
|
|
|
|
@itemx -no-mfix-24k
|
|
|
|
Insert nops to work around the 24K @samp{eret}/@samp{deret} errata.
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
@item -m4010
|
|
|
|
@itemx -no-m4010
|
|
|
|
Generate code for the LSI @sc{r4010} chip. This tells the assembler to
|
|
|
|
accept the @sc{r4010} specific instructions (@samp{addciu}, @samp{ffc},
|
|
|
|
etc.), and to not schedule @samp{nop} instructions around accesses to
|
|
|
|
the @samp{HI} and @samp{LO} registers. @samp{-no-m4010} turns off this
|
|
|
|
option.
|
|
|
|
|
|
|
|
@item -m4650
|
|
|
|
@itemx -no-m4650
|
|
|
|
Generate code for the MIPS @sc{r4650} chip. This tells the assembler to accept
|
|
|
|
the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop}
|
|
|
|
instructions around accesses to the @samp{HI} and @samp{LO} registers.
|
|
|
|
@samp{-no-m4650} turns off this option.
|
|
|
|
|
|
|
|
@itemx -m3900
|
|
|
|
@itemx -no-m3900
|
|
|
|
@itemx -m4100
|
|
|
|
@itemx -no-m4100
|
|
|
|
For each option @samp{-m@var{nnnn}}, generate code for the MIPS
|
|
|
|
@sc{r@var{nnnn}} chip. This tells the assembler to accept instructions
|
|
|
|
specific to that chip, and to schedule for that chip's hazards.
|
|
|
|
|
2001-06-29 23:27:43 +02:00
|
|
|
@item -march=@var{cpu}
|
1999-05-03 09:29:11 +02:00
|
|
|
Generate code for a particular MIPS cpu. It is exactly equivalent to
|
|
|
|
@samp{-m@var{cpu}}, except that there are more value of @var{cpu}
|
|
|
|
understood. Valid @var{cpu} value are:
|
|
|
|
|
|
|
|
@quotation
|
|
|
|
2000,
|
|
|
|
3000,
|
|
|
|
3900,
|
|
|
|
4000,
|
|
|
|
4010,
|
|
|
|
4100,
|
|
|
|
4111,
|
[gas/]
* doc/c-mips.texi: Add entries for -march=vr4120,vr4130,vr4181,
vr5400 and vr5500. Add entry for -mfix-vr4122-bugs.
* config/tc-mips.c (CPU_HAS_DROR, CPU_HAS_ROR): New macros.
(hilo_interlocks): True for CPU_VR5500.
(gpr_interlocks, cop_interlocks): True for CPU_VR5400 and CPU_VR5500.
(mips_fix_vr4122_bugs): New.
(append_insn): Work around 4122 errors if mips_fix_vr4122_bugs.
(mips_emit_delays): Likewise.
(macro2) [M_DROLI]: Use dror or dror32 if CPU_HAS_DROR.
[M_ROLI]: Likewise ror if CPU_HAS_ROR.
(validate_mips_insn, mips_ip): Handle '[', ']', 'e' and '%'.
(OPTION_FIX_VR4122, OPTION_NO_FIX_VR4122): New options.
(md_longopts): Add -mfix-vr4122-bugs and -no-mfix-vr4122-bugs.
(OPTION_ELF_BASE): Bump.
(md_parse_option): Handle the new options.
(mips_cpu_info_table): Add entries for vr4120, vr4130, vr4181,
vr5400 and vr5500.
[gas/testsuite/]
* gas/mips/mips4100.[sd]: Move dmadd16 and madd16 checks to...
* gas/mips/vr4111.[sd]: ...this new test.
* gas/mips/vr4120.[sd],
* gas/mips/vr4122.[sd],
* gas/mips/vr5400.[sd],
* gas/mips/vr5500.[sd]: New tests.
* mips.exp: Run them.
2002-09-30 14:04:54 +02:00
|
|
|
vr4120,
|
|
|
|
vr4130,
|
|
|
|
vr4181,
|
1999-05-03 09:29:11 +02:00
|
|
|
4300,
|
|
|
|
4400,
|
|
|
|
4600,
|
|
|
|
4650,
|
|
|
|
5000,
|
2000-06-16 21:11:27 +02:00
|
|
|
rm5200,
|
|
|
|
rm5230,
|
|
|
|
rm5231,
|
|
|
|
rm5261,
|
|
|
|
rm5721,
|
[gas/]
* doc/c-mips.texi: Add entries for -march=vr4120,vr4130,vr4181,
vr5400 and vr5500. Add entry for -mfix-vr4122-bugs.
* config/tc-mips.c (CPU_HAS_DROR, CPU_HAS_ROR): New macros.
(hilo_interlocks): True for CPU_VR5500.
(gpr_interlocks, cop_interlocks): True for CPU_VR5400 and CPU_VR5500.
(mips_fix_vr4122_bugs): New.
(append_insn): Work around 4122 errors if mips_fix_vr4122_bugs.
(mips_emit_delays): Likewise.
(macro2) [M_DROLI]: Use dror or dror32 if CPU_HAS_DROR.
[M_ROLI]: Likewise ror if CPU_HAS_ROR.
(validate_mips_insn, mips_ip): Handle '[', ']', 'e' and '%'.
(OPTION_FIX_VR4122, OPTION_NO_FIX_VR4122): New options.
(md_longopts): Add -mfix-vr4122-bugs and -no-mfix-vr4122-bugs.
(OPTION_ELF_BASE): Bump.
(md_parse_option): Handle the new options.
(mips_cpu_info_table): Add entries for vr4120, vr4130, vr4181,
vr5400 and vr5500.
[gas/testsuite/]
* gas/mips/mips4100.[sd]: Move dmadd16 and madd16 checks to...
* gas/mips/vr4111.[sd]: ...this new test.
* gas/mips/vr4120.[sd],
* gas/mips/vr4122.[sd],
* gas/mips/vr5400.[sd],
* gas/mips/vr5500.[sd]: New tests.
* mips.exp: Run them.
2002-09-30 14:04:54 +02:00
|
|
|
vr5400,
|
|
|
|
vr5500,
|
1999-05-03 09:29:11 +02:00
|
|
|
6000,
|
2000-06-16 21:11:27 +02:00
|
|
|
rm7000,
|
1999-05-03 09:29:11 +02:00
|
|
|
8000,
|
2003-07-15 11:02:59 +02:00
|
|
|
rm9000,
|
2000-12-01 22:35:38 +01:00
|
|
|
10000,
|
2001-07-04 14:32:07 +02:00
|
|
|
12000,
|
* aoutx.h (NAME): Add case statements for bfd_mach_mips14000,
bfd_mach_mips16000.
* archures.c (bfd_architecture): Add .#defines for bfd_mach_mips14000,
bfd_mach_mips16000.
* bfd-in2.h: Regenerate.
* cpu-mips.c: Add enums I_mips14000, I_mips16000.
(arch_info_struct): Add refs to R14000, R16000.
* elfxx-mips.c (mips_set_isa_flags): Handle bfd_mach_mips14000,
bfd_mach_mips16000.
(mips_mach_extensions): Map R14000, R16000 to R10000.
* config/tc-mips.c (hilo_interlocks): Handle CPU_R14000, CPU_R16000.
(mips_cpu_info_table): Add r14000, r16000.
* doc/c-mips.texi: Add entries for 14000, 16000.
* mips-dis.c (mips_arch_choices): Add r14000, r16000.
* mips.h: Define CPU_R14000, CPU_R16000.
(OPCODE_IS_MEMBER): Include R14000, R16000 in test.
2008-11-28 19:02:17 +01:00
|
|
|
14000,
|
|
|
|
16000,
|
[ gas/ChangeLog ]
* config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS): Rename.
(ISA_SUPPORTS_DSP_ASE, ISA_SUPPORTS_MT_ASE, ISA_HAS_64BIT_FPRS,
ISA_HAS_MXHC1): New macros.
(HAVE_32BIT_FPRS): Use ISA_HAS_64BIT_FPRS instead of
ISA_HAS_64BIT_REGS. Formatting fixes. Improved comments.
(mips_cpu_info): Change to use combined ASE/IS_ISA flag.
(MIPS_CPU_IS_ISA, MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP,
MIPS_CPU_ASE_MT, MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX): New defines.
(mips_after_parse_args): Change default handling of float register
size to account for 32bit code with 64bit FP. Better sanity checking
of ISA/ASE/ABI option combinations.
(s_mipsset): Support switching of GPR and FPR sizes via
.set {g,f}p={32,64,default}. Better sanity checking for .set ASE
options.
(mips_elf_final_processing): We should record the use of 64bit FP
registers in 32bit code but we don't, because ELF header flags are
a scarce ressource.
(mips_cpu_info_table): Add ASE flags for CPUs with mandatory ASE
extensions. Add 4ksc, 4kec, 4kem, 4kep, 4ksd, m4kp, 24kec, 24kef,
24kex, 34kc, 34kf, 34kx, 25kf CPU definitions.
(mips_cpu_info_from_isa): Use MIPS_CPU_IS_ISA.
* doc/c-mips.texi: Document .set {g,f}p={32,64,default}. Document
missing -march options. Document .set arch=CPU. Move .set smartmips
to ASE page. Use @code for .set FOO examples.
[ gas/testsuite/Changelog ]
* gas/mips/mips-gp32-fp64-pic.d, mips/mips-gp32-fp64.d,
gas/mips/mips-gp64-fp32-pic.d, gas/mips/mips-gp64-fp32.l,
gas/mips/mips-gp64-fp64.d: Adjust test cases to the changes assembler
output.
* gas/mips/mips-gp32-fp64.l, gas/mips/mips-gp64-fp32-pic.l: New files,
catch assembler warnings.
2006-05-23 17:37:20 +02:00
|
|
|
4kc,
|
|
|
|
4km,
|
|
|
|
4kp,
|
|
|
|
4ksc,
|
|
|
|
4kec,
|
|
|
|
4kem,
|
|
|
|
4kep,
|
|
|
|
4ksd,
|
|
|
|
m4k,
|
|
|
|
m4kp,
|
|
|
|
24kc,
|
2007-07-04 21:55:18 +02:00
|
|
|
24kf2_1,
|
[ gas/ChangeLog ]
* config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS): Rename.
(ISA_SUPPORTS_DSP_ASE, ISA_SUPPORTS_MT_ASE, ISA_HAS_64BIT_FPRS,
ISA_HAS_MXHC1): New macros.
(HAVE_32BIT_FPRS): Use ISA_HAS_64BIT_FPRS instead of
ISA_HAS_64BIT_REGS. Formatting fixes. Improved comments.
(mips_cpu_info): Change to use combined ASE/IS_ISA flag.
(MIPS_CPU_IS_ISA, MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP,
MIPS_CPU_ASE_MT, MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX): New defines.
(mips_after_parse_args): Change default handling of float register
size to account for 32bit code with 64bit FP. Better sanity checking
of ISA/ASE/ABI option combinations.
(s_mipsset): Support switching of GPR and FPR sizes via
.set {g,f}p={32,64,default}. Better sanity checking for .set ASE
options.
(mips_elf_final_processing): We should record the use of 64bit FP
registers in 32bit code but we don't, because ELF header flags are
a scarce ressource.
(mips_cpu_info_table): Add ASE flags for CPUs with mandatory ASE
extensions. Add 4ksc, 4kec, 4kem, 4kep, 4ksd, m4kp, 24kec, 24kef,
24kex, 34kc, 34kf, 34kx, 25kf CPU definitions.
(mips_cpu_info_from_isa): Use MIPS_CPU_IS_ISA.
* doc/c-mips.texi: Document .set {g,f}p={32,64,default}. Document
missing -march options. Document .set arch=CPU. Move .set smartmips
to ASE page. Use @code for .set FOO examples.
[ gas/testsuite/Changelog ]
* gas/mips/mips-gp32-fp64-pic.d, mips/mips-gp32-fp64.d,
gas/mips/mips-gp64-fp32-pic.d, gas/mips/mips-gp64-fp32.l,
gas/mips/mips-gp64-fp64.d: Adjust test cases to the changes assembler
output.
* gas/mips/mips-gp32-fp64.l, gas/mips/mips-gp64-fp32-pic.l: New files,
catch assembler warnings.
2006-05-23 17:37:20 +02:00
|
|
|
24kf,
|
2007-07-04 21:55:18 +02:00
|
|
|
24kf1_1,
|
[ gas/ChangeLog ]
* config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS): Rename.
(ISA_SUPPORTS_DSP_ASE, ISA_SUPPORTS_MT_ASE, ISA_HAS_64BIT_FPRS,
ISA_HAS_MXHC1): New macros.
(HAVE_32BIT_FPRS): Use ISA_HAS_64BIT_FPRS instead of
ISA_HAS_64BIT_REGS. Formatting fixes. Improved comments.
(mips_cpu_info): Change to use combined ASE/IS_ISA flag.
(MIPS_CPU_IS_ISA, MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP,
MIPS_CPU_ASE_MT, MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX): New defines.
(mips_after_parse_args): Change default handling of float register
size to account for 32bit code with 64bit FP. Better sanity checking
of ISA/ASE/ABI option combinations.
(s_mipsset): Support switching of GPR and FPR sizes via
.set {g,f}p={32,64,default}. Better sanity checking for .set ASE
options.
(mips_elf_final_processing): We should record the use of 64bit FP
registers in 32bit code but we don't, because ELF header flags are
a scarce ressource.
(mips_cpu_info_table): Add ASE flags for CPUs with mandatory ASE
extensions. Add 4ksc, 4kec, 4kem, 4kep, 4ksd, m4kp, 24kec, 24kef,
24kex, 34kc, 34kf, 34kx, 25kf CPU definitions.
(mips_cpu_info_from_isa): Use MIPS_CPU_IS_ISA.
* doc/c-mips.texi: Document .set {g,f}p={32,64,default}. Document
missing -march options. Document .set arch=CPU. Move .set smartmips
to ASE page. Use @code for .set FOO examples.
[ gas/testsuite/Changelog ]
* gas/mips/mips-gp32-fp64-pic.d, mips/mips-gp32-fp64.d,
gas/mips/mips-gp64-fp32-pic.d, gas/mips/mips-gp64-fp32.l,
gas/mips/mips-gp64-fp64.d: Adjust test cases to the changes assembler
output.
* gas/mips/mips-gp32-fp64.l, gas/mips/mips-gp64-fp32-pic.l: New files,
catch assembler warnings.
2006-05-23 17:37:20 +02:00
|
|
|
24kec,
|
2007-07-04 21:55:18 +02:00
|
|
|
24kef2_1,
|
[ gas/ChangeLog ]
* config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS): Rename.
(ISA_SUPPORTS_DSP_ASE, ISA_SUPPORTS_MT_ASE, ISA_HAS_64BIT_FPRS,
ISA_HAS_MXHC1): New macros.
(HAVE_32BIT_FPRS): Use ISA_HAS_64BIT_FPRS instead of
ISA_HAS_64BIT_REGS. Formatting fixes. Improved comments.
(mips_cpu_info): Change to use combined ASE/IS_ISA flag.
(MIPS_CPU_IS_ISA, MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP,
MIPS_CPU_ASE_MT, MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX): New defines.
(mips_after_parse_args): Change default handling of float register
size to account for 32bit code with 64bit FP. Better sanity checking
of ISA/ASE/ABI option combinations.
(s_mipsset): Support switching of GPR and FPR sizes via
.set {g,f}p={32,64,default}. Better sanity checking for .set ASE
options.
(mips_elf_final_processing): We should record the use of 64bit FP
registers in 32bit code but we don't, because ELF header flags are
a scarce ressource.
(mips_cpu_info_table): Add ASE flags for CPUs with mandatory ASE
extensions. Add 4ksc, 4kec, 4kem, 4kep, 4ksd, m4kp, 24kec, 24kef,
24kex, 34kc, 34kf, 34kx, 25kf CPU definitions.
(mips_cpu_info_from_isa): Use MIPS_CPU_IS_ISA.
* doc/c-mips.texi: Document .set {g,f}p={32,64,default}. Document
missing -march options. Document .set arch=CPU. Move .set smartmips
to ASE page. Use @code for .set FOO examples.
[ gas/testsuite/Changelog ]
* gas/mips/mips-gp32-fp64-pic.d, mips/mips-gp32-fp64.d,
gas/mips/mips-gp64-fp32-pic.d, gas/mips/mips-gp64-fp32.l,
gas/mips/mips-gp64-fp64.d: Adjust test cases to the changes assembler
output.
* gas/mips/mips-gp32-fp64.l, gas/mips/mips-gp64-fp32-pic.l: New files,
catch assembler warnings.
2006-05-23 17:37:20 +02:00
|
|
|
24kef,
|
2007-07-04 21:55:18 +02:00
|
|
|
24kef1_1,
|
[ gas/ChangeLog ]
* config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS): Rename.
(ISA_SUPPORTS_DSP_ASE, ISA_SUPPORTS_MT_ASE, ISA_HAS_64BIT_FPRS,
ISA_HAS_MXHC1): New macros.
(HAVE_32BIT_FPRS): Use ISA_HAS_64BIT_FPRS instead of
ISA_HAS_64BIT_REGS. Formatting fixes. Improved comments.
(mips_cpu_info): Change to use combined ASE/IS_ISA flag.
(MIPS_CPU_IS_ISA, MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP,
MIPS_CPU_ASE_MT, MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX): New defines.
(mips_after_parse_args): Change default handling of float register
size to account for 32bit code with 64bit FP. Better sanity checking
of ISA/ASE/ABI option combinations.
(s_mipsset): Support switching of GPR and FPR sizes via
.set {g,f}p={32,64,default}. Better sanity checking for .set ASE
options.
(mips_elf_final_processing): We should record the use of 64bit FP
registers in 32bit code but we don't, because ELF header flags are
a scarce ressource.
(mips_cpu_info_table): Add ASE flags for CPUs with mandatory ASE
extensions. Add 4ksc, 4kec, 4kem, 4kep, 4ksd, m4kp, 24kec, 24kef,
24kex, 34kc, 34kf, 34kx, 25kf CPU definitions.
(mips_cpu_info_from_isa): Use MIPS_CPU_IS_ISA.
* doc/c-mips.texi: Document .set {g,f}p={32,64,default}. Document
missing -march options. Document .set arch=CPU. Move .set smartmips
to ASE page. Use @code for .set FOO examples.
[ gas/testsuite/Changelog ]
* gas/mips/mips-gp32-fp64-pic.d, mips/mips-gp32-fp64.d,
gas/mips/mips-gp64-fp32-pic.d, gas/mips/mips-gp64-fp32.l,
gas/mips/mips-gp64-fp64.d: Adjust test cases to the changes assembler
output.
* gas/mips/mips-gp32-fp64.l, gas/mips/mips-gp64-fp32-pic.l: New files,
catch assembler warnings.
2006-05-23 17:37:20 +02:00
|
|
|
34kc,
|
2007-07-04 21:55:18 +02:00
|
|
|
34kf2_1,
|
[ gas/ChangeLog ]
* config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS): Rename.
(ISA_SUPPORTS_DSP_ASE, ISA_SUPPORTS_MT_ASE, ISA_HAS_64BIT_FPRS,
ISA_HAS_MXHC1): New macros.
(HAVE_32BIT_FPRS): Use ISA_HAS_64BIT_FPRS instead of
ISA_HAS_64BIT_REGS. Formatting fixes. Improved comments.
(mips_cpu_info): Change to use combined ASE/IS_ISA flag.
(MIPS_CPU_IS_ISA, MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP,
MIPS_CPU_ASE_MT, MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX): New defines.
(mips_after_parse_args): Change default handling of float register
size to account for 32bit code with 64bit FP. Better sanity checking
of ISA/ASE/ABI option combinations.
(s_mipsset): Support switching of GPR and FPR sizes via
.set {g,f}p={32,64,default}. Better sanity checking for .set ASE
options.
(mips_elf_final_processing): We should record the use of 64bit FP
registers in 32bit code but we don't, because ELF header flags are
a scarce ressource.
(mips_cpu_info_table): Add ASE flags for CPUs with mandatory ASE
extensions. Add 4ksc, 4kec, 4kem, 4kep, 4ksd, m4kp, 24kec, 24kef,
24kex, 34kc, 34kf, 34kx, 25kf CPU definitions.
(mips_cpu_info_from_isa): Use MIPS_CPU_IS_ISA.
* doc/c-mips.texi: Document .set {g,f}p={32,64,default}. Document
missing -march options. Document .set arch=CPU. Move .set smartmips
to ASE page. Use @code for .set FOO examples.
[ gas/testsuite/Changelog ]
* gas/mips/mips-gp32-fp64-pic.d, mips/mips-gp32-fp64.d,
gas/mips/mips-gp64-fp32-pic.d, gas/mips/mips-gp64-fp32.l,
gas/mips/mips-gp64-fp64.d: Adjust test cases to the changes assembler
output.
* gas/mips/mips-gp32-fp64.l, gas/mips/mips-gp64-fp32-pic.l: New files,
catch assembler warnings.
2006-05-23 17:37:20 +02:00
|
|
|
34kf,
|
2007-07-04 21:55:18 +02:00
|
|
|
34kf1_1,
|
2007-02-20 16:03:45 +01:00
|
|
|
74kc,
|
2007-07-04 21:55:18 +02:00
|
|
|
74kf2_1,
|
2007-02-20 16:03:45 +01:00
|
|
|
74kf,
|
2007-07-04 21:55:18 +02:00
|
|
|
74kf1_1,
|
|
|
|
74kf3_2,
|
2009-08-05 02:44:01 +02:00
|
|
|
1004kc,
|
|
|
|
1004kf2_1,
|
|
|
|
1004kf,
|
|
|
|
1004kf1_1,
|
[ gas/ChangeLog ]
* config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS): Rename.
(ISA_SUPPORTS_DSP_ASE, ISA_SUPPORTS_MT_ASE, ISA_HAS_64BIT_FPRS,
ISA_HAS_MXHC1): New macros.
(HAVE_32BIT_FPRS): Use ISA_HAS_64BIT_FPRS instead of
ISA_HAS_64BIT_REGS. Formatting fixes. Improved comments.
(mips_cpu_info): Change to use combined ASE/IS_ISA flag.
(MIPS_CPU_IS_ISA, MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP,
MIPS_CPU_ASE_MT, MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX): New defines.
(mips_after_parse_args): Change default handling of float register
size to account for 32bit code with 64bit FP. Better sanity checking
of ISA/ASE/ABI option combinations.
(s_mipsset): Support switching of GPR and FPR sizes via
.set {g,f}p={32,64,default}. Better sanity checking for .set ASE
options.
(mips_elf_final_processing): We should record the use of 64bit FP
registers in 32bit code but we don't, because ELF header flags are
a scarce ressource.
(mips_cpu_info_table): Add ASE flags for CPUs with mandatory ASE
extensions. Add 4ksc, 4kec, 4kem, 4kep, 4ksd, m4kp, 24kec, 24kef,
24kex, 34kc, 34kf, 34kx, 25kf CPU definitions.
(mips_cpu_info_from_isa): Use MIPS_CPU_IS_ISA.
* doc/c-mips.texi: Document .set {g,f}p={32,64,default}. Document
missing -march options. Document .set arch=CPU. Move .set smartmips
to ASE page. Use @code for .set FOO examples.
[ gas/testsuite/Changelog ]
* gas/mips/mips-gp32-fp64-pic.d, mips/mips-gp32-fp64.d,
gas/mips/mips-gp64-fp32-pic.d, gas/mips/mips-gp64-fp32.l,
gas/mips/mips-gp64-fp64.d: Adjust test cases to the changes assembler
output.
* gas/mips/mips-gp32-fp64.l, gas/mips/mips-gp64-fp32-pic.l: New files,
catch assembler warnings.
2006-05-23 17:37:20 +02:00
|
|
|
5kc,
|
|
|
|
5kf,
|
|
|
|
20kc,
|
|
|
|
25kf,
|
2006-11-06 16:05:40 +01:00
|
|
|
sb1,
|
2007-11-29 13:23:44 +01:00
|
|
|
sb1a,
|
|
|
|
loongson2e,
|
* config/tc-mips.c (file_mips_soft_float, file_mips_single_float):
New statics.
(OPTION_ELF_BASE): Make room for new option macros.
(OPTION_SOFT_FLOAT, OPTION_HARD_FLOAT, OPTION_SINGLE_FLOAT,
OPTION_DOUBLE_FLOAT): New option macros.
(md_longopts): Add msoft-float, mhard-float, msingle-float and
mdouble-float.
(md_parse_option): Handle OPTION_SINGLE_FLOAT,
OPTION_DOUBLE_FLOAT, OPTION_SOFT_FLOAT and OPTION_HARD_FLOAT.
(md_show_usage): Add -msoft-float, -mhard-float, -msingle-float
and -mdouble-float.
(struct mips_set_options): New fields soft_float and single_float.
(mips_opts): Initialized them. Add comment for each field
initializer.
(mips_after_parse_args): Set them based on file_mips_soft_float
and file_mips_single_float.
(s_mipsset): Add support for `.set softfloat', `.set hardfloat',
`.set singlefloat' and `.set doublefloat'.
(is_opcode_valid): New function to invoke OPCODE_IS_MEMBER.
Handle single-float and soft-float instructions here.
(macro_build, mips_ip): Use it instead of OPCODE_IS_MEMBER.
(is_opcode_valid_16): New function.
(mips16_ip): Use it instead of OPCODE_IS_MEMBER.
(macro) <M_LDC1_AB, M_SDC1_AB, M_L_DOB, M_L_DAB, M_S_DAB,
M_S_DOB>: Remove special-casing of r4650.
* doc/c-mips.texi (-march=): Add Octeon.
(MIPS Opts): Document -msoft-float and -mhard-float. Document
-msingle-float and -mdouble-float.
(MIPS floating-point): New section. Document `.set softfloat' and
`.set hardfloat'. Document `.set singlefloat' and `.set
doublefloat'.
2008-04-28 19:06:28 +02:00
|
|
|
loongson2f,
|
bfd:
2009-02-03 Sandip Matte <sandip@rmicorp.com>
* aoutx.h (NAME (aout, machine_type)): Handle bfd_mach_mips_xlr.
* archures.c (bfd_mach_mips_xlr): Define.
* bfd-in2.h: Regenerate.
* cpu-mips.c (I_xlr): Define.
(arch_info_struct): Add XLR entry.
* elfxx-mips.c (_bfd_elf_mips_mach): Handle E_MIPS_MACH_XLR.
(mips_set_isa_flags): Handle bfd_mach_mips_xlr
(mips_mach_extensions): Add XLR entry.
binutils:
2009-02-03 Sandip Matte <sandip@rmicorp.com>
* readelf.c (get_machine_flags): Handle E_MIPS_MACH_XLR.
gas:
2009-02-03 Sandip Matte <sandip@rmicorp.com>
* config/tc-mips.c (macro): Handle M_MSGSND, M_MSGLD, M_MSGLD_T,
M_MSGWAIT and M_MSGWAIT_T.
(mips_cpu_info_table): Add XLR entry.
* doc/c-mips.texi (-march): Document xlr.
gas/testsuite:
2009-02-03 Sandip Matte <sandip@rmicorp.com>
* gas/mips/mips.exp (xlr): New architecture.
(xlr-ext): Run test.
* gas/mips/xlr-ext.d, gas/mips/xlr-ext.s: New.
include/elf:
2009-02-03 Sandip Matte <sandip@rmicorp.com>
* mips.h (E_MIPS_MACH_XLR): Define.
include/opcode:
2009-02-03 Sandip Matte <sandip@rmicorp.com>
* mips.h (INSN_XLR): Define.
(INSN_CHIP_MASK): Update.
(CPU_XLR): Define.
(OPCODE_IS_MEMBER): Update.
(M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
opcodes:
2009-02-03 Sandip Matte <sandip@rmicorp.com>
* mips-dis.c (mips_cp0_names_xlr, mips_cp0sel_names_xlr): Define.
(mips_arch_choices): Add XLR entry.
* mips-opc.c (XLR): Define.
(mips_builtin_opcodes): Add XLR instructions.
2009-02-03 19:16:04 +01:00
|
|
|
octeon,
|
|
|
|
xlr
|
1999-05-03 09:29:11 +02:00
|
|
|
@end quotation
|
|
|
|
|
2007-07-04 21:55:18 +02:00
|
|
|
For compatibility reasons, @samp{@var{n}x} and @samp{@var{b}fx} are
|
|
|
|
accepted as synonyms for @samp{@var{n}f1_1}. These values are
|
|
|
|
deprecated.
|
|
|
|
|
2001-06-29 23:27:43 +02:00
|
|
|
@item -mtune=@var{cpu}
|
|
|
|
Schedule and tune for a particular MIPS cpu. Valid @var{cpu} values are
|
|
|
|
identical to @samp{-march=@var{cpu}}.
|
|
|
|
|
[gas/]
* doc/c-mips.texi: Remove -mcpu. Document -mabi.
* configure.in (MIPS_CPU_STRING_DEFAULT): New configuration macro.
(USE_E_MIPS_ABI_O32, MIPS_DEFAULT_64BIT): New configuration macros.
* configure, config.in: Regenerate.
* config/tc-mips.c (file_mips_abi): Rename to mips_abi.
(mips_set_options): Remove "abi" field.
(mips_opts): Update accordingly. Replace all uses of mips_opts.abi
with mips_abi.
(mips_cpu): Remove.
(mips_arch_string, mips_arch_info): New vars.
(mips_tune_string, mips_tune_info): New vars.
(ABI_NEEDS_32BIT_REGS, ABI_NEEDS_64BIT_REGS): New macros.
(HAVE_32BIT_GPRS, HAVE_32BIT_FPRS): Don't check the ABI.
(mips_isa_to_str, mips_cpu_to_str): Remove.
(mips_ip): If the selected architecture is a generic ISA rather
than a processor, only mention the ISA level in error messages.
(OPTION_MCPU): Remove.
(OPTION_FP64): New.
(md_longopts): Add -mfp64, remove -mcpu.
(mips_set_option_string): New fn.
(md_parse_option): Make -mipsN update file_mips_isa rather than
mips_opts.isa. Use mips_set_option_string to set -march or -mtune.
Don't let -mgp32 and -mfp32 change the ABI.
(show): Move to end of file. Constify string argument.
(md_show_usage): Move to the end of the file. Read available
architectures from mips_cpu_info_table.
(mips_set_architecture): New fn.
(mips_after_parse_args): Rework. Remove -mcpu handling. -mipsN
is an alias for -march=mipsN. Don't change the ABI based on other
flags. Infer the register size from the ABI as well as the
architecture. Complain about more conflicting arguments.
Unify logic with GCC.
(s_mipsset): Don't change the ABI.
(mips_elf_final_processing): Check USE_E_MIPS_ABI_O32.
(mips_cpu_info_table): Remove Generic-MIPS* entries, keeping just
"mipsN"-type entries. Remove entries that vary only in the
manufacturer's prefix, or that have "000" replaced by "k".
Remove TARGET_CPU entries. Make r2000 entry use CPU_R3000.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p): New fns.
(mips_parse_cpu): New fn.
(mips_cpu_info_from_name, mips_cpu_info_from_cpu): Remove.
(mips_cpu_info_from_isa): Minor formatting tweak.
[gas/testsuite]
* gas/mips/mips-gp32-fp64.d,
* gas/mips/mips-gp32-fp64-pic.d: Add -mfp64.
2002-07-25 11:48:07 +02:00
|
|
|
@item -mabi=@var{abi}
|
|
|
|
Record which ABI the source code uses. The recognized arguments
|
|
|
|
are: @samp{32}, @samp{n32}, @samp{o64}, @samp{64} and @samp{eabi}.
|
1999-05-03 09:29:11 +02:00
|
|
|
|
2005-03-04 10:51:11 +01:00
|
|
|
@item -msym32
|
|
|
|
@itemx -mno-sym32
|
|
|
|
@cindex -msym32
|
|
|
|
@cindex -mno-sym32
|
|
|
|
Equivalent to adding @code{.set sym32} or @code{.set nosym32} to
|
|
|
|
the beginning of the assembler input. @xref{MIPS symbol sizes}.
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
@cindex @code{-nocpp} ignored (MIPS)
|
|
|
|
@item -nocpp
|
|
|
|
This option is ignored. It is accepted for command-line compatibility with
|
|
|
|
other assemblers, which use it to turn off C style preprocessing. With
|
|
|
|
@sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the
|
|
|
|
@sc{gnu} assembler itself never runs the C preprocessor.
|
|
|
|
|
* config/tc-mips.c (file_mips_soft_float, file_mips_single_float):
New statics.
(OPTION_ELF_BASE): Make room for new option macros.
(OPTION_SOFT_FLOAT, OPTION_HARD_FLOAT, OPTION_SINGLE_FLOAT,
OPTION_DOUBLE_FLOAT): New option macros.
(md_longopts): Add msoft-float, mhard-float, msingle-float and
mdouble-float.
(md_parse_option): Handle OPTION_SINGLE_FLOAT,
OPTION_DOUBLE_FLOAT, OPTION_SOFT_FLOAT and OPTION_HARD_FLOAT.
(md_show_usage): Add -msoft-float, -mhard-float, -msingle-float
and -mdouble-float.
(struct mips_set_options): New fields soft_float and single_float.
(mips_opts): Initialized them. Add comment for each field
initializer.
(mips_after_parse_args): Set them based on file_mips_soft_float
and file_mips_single_float.
(s_mipsset): Add support for `.set softfloat', `.set hardfloat',
`.set singlefloat' and `.set doublefloat'.
(is_opcode_valid): New function to invoke OPCODE_IS_MEMBER.
Handle single-float and soft-float instructions here.
(macro_build, mips_ip): Use it instead of OPCODE_IS_MEMBER.
(is_opcode_valid_16): New function.
(mips16_ip): Use it instead of OPCODE_IS_MEMBER.
(macro) <M_LDC1_AB, M_SDC1_AB, M_L_DOB, M_L_DAB, M_S_DAB,
M_S_DOB>: Remove special-casing of r4650.
* doc/c-mips.texi (-march=): Add Octeon.
(MIPS Opts): Document -msoft-float and -mhard-float. Document
-msingle-float and -mdouble-float.
(MIPS floating-point): New section. Document `.set softfloat' and
`.set hardfloat'. Document `.set singlefloat' and `.set
doublefloat'.
2008-04-28 19:06:28 +02:00
|
|
|
@item -msoft-float
|
|
|
|
@itemx -mhard-float
|
|
|
|
Disable or enable floating-point instructions. Note that by default
|
|
|
|
floating-point instructions are always allowed even with CPU targets
|
|
|
|
that don't have support for these instructions.
|
|
|
|
|
|
|
|
@item -msingle-float
|
|
|
|
@itemx -mdouble-float
|
|
|
|
Disable or enable double-precision floating-point operations. Note
|
|
|
|
that by default double-precision floating-point operations are always
|
|
|
|
allowed even with CPU targets that don't have support for these
|
|
|
|
operations.
|
|
|
|
|
2000-07-15 00:23:33 +02:00
|
|
|
@item --construct-floats
|
|
|
|
@itemx --no-construct-floats
|
|
|
|
The @code{--no-construct-floats} option disables the construction of
|
|
|
|
double width floating point constants by loading the two halves of the
|
|
|
|
value into the two single width floating point registers that make up
|
|
|
|
the double width register. This feature is useful if the processor
|
|
|
|
support the FR bit in its status register, and this bit is known (by
|
|
|
|
the programmer) to be set. This bit prevents the aliasing of the double
|
|
|
|
width register by the single width registers.
|
|
|
|
|
2000-07-15 17:09:13 +02:00
|
|
|
By default @code{--construct-floats} is selected, allowing construction
|
2000-07-15 00:23:33 +02:00
|
|
|
of these floating point constants.
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
@item --trap
|
|
|
|
@itemx --no-break
|
|
|
|
@c FIXME! (1) reflect these options (next item too) in option summaries;
|
|
|
|
@c (2) stop teasing, say _which_ instructions expanded _how_.
|
|
|
|
@code{@value{AS}} automatically macro expands certain division and
|
|
|
|
multiplication instructions to check for overflow and division by zero. This
|
|
|
|
option causes @code{@value{AS}} to generate code to take a trap exception
|
|
|
|
rather than a break exception when an error is detected. The trap instructions
|
|
|
|
are only supported at Instruction Set Architecture level 2 and higher.
|
|
|
|
|
|
|
|
@item --break
|
|
|
|
@itemx --no-trap
|
|
|
|
Generate code to take a break exception rather than a trap exception when an
|
|
|
|
error is detected. This is the default.
|
2001-06-11 22:40:36 +02:00
|
|
|
|
2003-07-28 22:06:27 +02:00
|
|
|
@item -mpdr
|
|
|
|
@itemx -mno-pdr
|
|
|
|
Control generation of @code{.pdr} sections. Off by default on IRIX, on
|
|
|
|
elsewhere.
|
2004-12-10 20:48:21 +01:00
|
|
|
|
|
|
|
@item -mshared
|
|
|
|
@itemx -mno-shared
|
|
|
|
When generating code using the Unix calling conventions (selected by
|
|
|
|
@samp{-KPIC} or @samp{-mcall_shared}), gas will normally generate code
|
|
|
|
which can go into a shared library. The @samp{-mno-shared} option
|
|
|
|
tells gas to generate code which uses the calling convention, but can
|
|
|
|
not go into a shared library. The resulting code is slightly more
|
|
|
|
efficient. This option only affects the handling of the
|
|
|
|
@samp{.cpload} and @samp{.cpsetup} pseudo-ops.
|
1999-05-03 09:29:11 +02:00
|
|
|
@end table
|
|
|
|
|
|
|
|
@node MIPS Object
|
|
|
|
@section MIPS ECOFF object code
|
|
|
|
|
|
|
|
@cindex ECOFF sections
|
|
|
|
@cindex MIPS ECOFF sections
|
|
|
|
Assembling for a @sc{mips} @sc{ecoff} target supports some additional sections
|
|
|
|
besides the usual @code{.text}, @code{.data} and @code{.bss}. The
|
|
|
|
additional sections are @code{.rdata}, used for read-only data,
|
|
|
|
@code{.sdata}, used for small data, and @code{.sbss}, used for small
|
|
|
|
common objects.
|
|
|
|
|
|
|
|
@cindex small objects, MIPS ECOFF
|
|
|
|
@cindex @code{gp} register, MIPS
|
|
|
|
When assembling for @sc{ecoff}, the assembler uses the @code{$gp} (@code{$28})
|
|
|
|
register to form the address of a ``small object''. Any object in the
|
|
|
|
@code{.sdata} or @code{.sbss} sections is considered ``small'' in this sense.
|
|
|
|
For external objects, or for objects in the @code{.bss} section, you can use
|
|
|
|
the @code{@value{GCC}} @samp{-G} option to control the size of objects addressed via
|
|
|
|
@code{$gp}; the default value is 8, meaning that a reference to any object
|
|
|
|
eight bytes or smaller uses @code{$gp}. Passing @samp{-G 0} to
|
|
|
|
@code{@value{AS}} prevents it from using the @code{$gp} register on the basis
|
|
|
|
of object size (but the assembler uses @code{$gp} for objects in @code{.sdata}
|
|
|
|
or @code{sbss} in any case). The size of an object in the @code{.bss} section
|
|
|
|
is set by the @code{.comm} or @code{.lcomm} directive that defines it. The
|
|
|
|
size of an external object may be set with the @code{.extern} directive. For
|
|
|
|
example, @samp{.extern sym,4} declares that the object at @code{sym} is 4 bytes
|
|
|
|
in length, whie leaving @code{sym} otherwise undefined.
|
|
|
|
|
|
|
|
Using small @sc{ecoff} objects requires linker support, and assumes that the
|
|
|
|
@code{$gp} register is correctly initialized (normally done automatically by
|
|
|
|
the startup code). @sc{mips} @sc{ecoff} assembly code must not modify the
|
|
|
|
@code{$gp} register.
|
|
|
|
|
|
|
|
@node MIPS Stabs
|
|
|
|
@section Directives for debugging information
|
|
|
|
|
|
|
|
@cindex MIPS debugging directives
|
|
|
|
@sc{mips} @sc{ecoff} @code{@value{AS}} supports several directives used for
|
|
|
|
generating debugging information which are not support by traditional @sc{mips}
|
|
|
|
assemblers. These are @code{.def}, @code{.endef}, @code{.dim}, @code{.file},
|
|
|
|
@code{.scl}, @code{.size}, @code{.tag}, @code{.type}, @code{.val},
|
|
|
|
@code{.stabd}, @code{.stabn}, and @code{.stabs}. The debugging information
|
|
|
|
generated by the three @code{.stab} directives can only be read by @sc{gdb},
|
|
|
|
not by traditional @sc{mips} debuggers (this enhancement is required to fully
|
|
|
|
support C++ debugging). These directives are primarily used by compilers, not
|
|
|
|
assembly language programmers!
|
|
|
|
|
2005-03-04 10:51:11 +01:00
|
|
|
@node MIPS symbol sizes
|
|
|
|
@section Directives to override the size of symbols
|
|
|
|
|
|
|
|
@cindex @code{.set sym32}
|
|
|
|
@cindex @code{.set nosym32}
|
|
|
|
The n64 ABI allows symbols to have any 64-bit value. Although this
|
|
|
|
provides a great deal of flexibility, it means that some macros have
|
|
|
|
much longer expansions than their 32-bit counterparts. For example,
|
|
|
|
the non-PIC expansion of @samp{dla $4,sym} is usually:
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
lui $4,%highest(sym)
|
|
|
|
lui $1,%hi(sym)
|
|
|
|
daddiu $4,$4,%higher(sym)
|
|
|
|
daddiu $1,$1,%lo(sym)
|
|
|
|
dsll32 $4,$4,0
|
|
|
|
daddu $4,$4,$1
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
whereas the 32-bit expansion is simply:
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
lui $4,%hi(sym)
|
|
|
|
daddiu $4,$4,%lo(sym)
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
n64 code is sometimes constructed in such a way that all symbolic
|
|
|
|
constants are known to have 32-bit values, and in such cases, it's
|
|
|
|
preferable to use the 32-bit expansion instead of the 64-bit
|
|
|
|
expansion.
|
|
|
|
|
|
|
|
You can use the @code{.set sym32} directive to tell the assembler
|
|
|
|
that, from this point on, all expressions of the form
|
|
|
|
@samp{@var{symbol}} or @samp{@var{symbol} + @var{offset}}
|
|
|
|
have 32-bit values. For example:
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
.set sym32
|
|
|
|
dla $4,sym
|
|
|
|
lw $4,sym+16
|
|
|
|
sw $4,sym+0x8000($4)
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
will cause the assembler to treat @samp{sym}, @code{sym+16} and
|
|
|
|
@code{sym+0x8000} as 32-bit values. The handling of non-symbolic
|
|
|
|
addresses is not affected.
|
|
|
|
|
|
|
|
The directive @code{.set nosym32} ends a @code{.set sym32} block and
|
|
|
|
reverts to the normal behavior. It is also possible to change the
|
|
|
|
symbol size using the command-line options @option{-msym32} and
|
|
|
|
@option{-mno-sym32}.
|
|
|
|
|
|
|
|
These options and directives are always accepted, but at present,
|
|
|
|
they have no effect for anything other than n64.
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
@node MIPS ISA
|
|
|
|
@section Directives to override the ISA level
|
|
|
|
|
|
|
|
@cindex MIPS ISA override
|
|
|
|
@kindex @code{.set mips@var{n}}
|
|
|
|
@sc{gnu} @code{@value{AS}} supports an additional directive to change
|
|
|
|
the @sc{mips} Instruction Set Architecture level on the fly: @code{.set
|
[ bfd/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* archures.c (bfd_mach_mipsisa64r2): New define.
* bfd-in2.h: Regenerate.
* aoutx.h (NAME(aout,machine_type)): Handle bfd_mach_mipsisa64r2.
* cpu-mips.c (I_mipsisa64r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa64r2.
* elfxx-mips.c (_bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_64R2.
(mips_set_isa_flags): Add bfd_mach_mipsisa64r2 case.
(mips_mach_extensions): Add entry for bfd_mach_mipsisa64r2.
[ binutils/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* readelf.c (get_machine_flags): Handle E_MIPS_ARCH_64R2.
[ gas/Changelog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa64r2, mipsisa64r2el, mipsisa64r2*): New CPUs.
* configure: Regenerate.
* config/tc-mips.c (imm2_expr): New variable.
(md_assemble, mips16_ip): Initialize imm2_expr.
(ISA_HAS_64BIT_REGS, ISA_HAS_DROR, ISA_HAS_ROR): Add ISA_MIPS64R2.
(macro_build): Handle +A, +B, +C, +E, +F, +G, and +H format operands.
(macro): Handle M_DEXT and M_DINS.
(validate_mips_insn): Handle +E, +F, +G, +H, and +I format operands.
(mips_ip): Likewise.
(OPTION_MIPS64R2): New define.
(md_longopts): New entry for -mips64r2 (OPTION_MIPS64R2).
OPTION_ASE_BASE): Increase to compensate for OPTION_MIPS64R2.
(md_parse_option): Handle OPTION_MIPS64R2.
(s_mipsset): Handle setting "mips64r2" ISA.
(mips_cpu_info_table): Add mips64r2.
(md_show_usage): Document -mips64r2 option.
* doc/as.texinfo: Docuemnt -mips64r2 option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips64r2.d: New file.
* gas/mips/cp0sel-names-mips64r2.d: New file.
* gas/mips/elf_arch_mips64r2.d: New file.
* gas/mips/hwr-names-mips64r2.d: New file.
* gas/mips/mips32r2-ill-fp64.l: New file.
* gas/mips/mips32r2-ill-fp64.s: New file.
* gas/mips/mips64r2-ill.l: New file.
* gas/mips/mips64r2-ill.s: New file.
* gas/mips/mips64r2.d: New file.
* gas/mips/mips64r2.s: New file.
* gas/mips/mips.exp: Define "mips64r2" arch, and run new tests.
[ include/elf/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_64R2): New define.
[ include/opcode/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document +E, +F, +G, +H, and +I operand types.
Update documentation of I, +B and +C operand types.
(INSN_ISA64R2, ISA_MIPS64R2, CPU_MIPS64R2): New defines.
(M_DEXT, M_DINS): New enum values.
[ ld/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ldmain.c (get_emulation): Ignore "-mips64r2".
[ ld/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ld-mips-elf/mips-elf-flags.exp: Add tests for combinations
with MIPS64r2.
[ opcodes/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_arch_choices): Add entry for "mips64r2"
(print_insn_args): Add handing for +E, +F, +G, and +H.
* mips-opc.c (I65): New define for MIPS64r2.
(mips_builtin_opcodes): Add "dext", "dextm", "dextu", "dins",
"dinsm", "dinsu", "drotl", "drotr", "drotr32", "drotrv", "dsbh",
and "dshd" for MIPS64r2. Adjust "dror", "dror32", and "drorv" to
be supported on MIPS64r2.
2003-09-30 18:17:15 +02:00
|
|
|
mips@var{n}}. @var{n} should be a number from 0 to 5, or 32, 32r2, 64
|
|
|
|
or 64r2.
|
2003-01-02 21:03:09 +01:00
|
|
|
The values other than 0 make the assembler accept instructions
|
2000-12-12 20:36:32 +01:00
|
|
|
for the corresponding @sc{isa} level, from that point on in the
|
|
|
|
assembly. @code{.set mips@var{n}} affects not only which instructions
|
|
|
|
are permitted, but also how certain macros are expanded. @code{.set
|
|
|
|
mips0} restores the @sc{isa} level to its original level: either the
|
|
|
|
level you selected with command line options, or the default for your
|
[ gas/ChangeLog ]
* config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS): Rename.
(ISA_SUPPORTS_DSP_ASE, ISA_SUPPORTS_MT_ASE, ISA_HAS_64BIT_FPRS,
ISA_HAS_MXHC1): New macros.
(HAVE_32BIT_FPRS): Use ISA_HAS_64BIT_FPRS instead of
ISA_HAS_64BIT_REGS. Formatting fixes. Improved comments.
(mips_cpu_info): Change to use combined ASE/IS_ISA flag.
(MIPS_CPU_IS_ISA, MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP,
MIPS_CPU_ASE_MT, MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX): New defines.
(mips_after_parse_args): Change default handling of float register
size to account for 32bit code with 64bit FP. Better sanity checking
of ISA/ASE/ABI option combinations.
(s_mipsset): Support switching of GPR and FPR sizes via
.set {g,f}p={32,64,default}. Better sanity checking for .set ASE
options.
(mips_elf_final_processing): We should record the use of 64bit FP
registers in 32bit code but we don't, because ELF header flags are
a scarce ressource.
(mips_cpu_info_table): Add ASE flags for CPUs with mandatory ASE
extensions. Add 4ksc, 4kec, 4kem, 4kep, 4ksd, m4kp, 24kec, 24kef,
24kex, 34kc, 34kf, 34kx, 25kf CPU definitions.
(mips_cpu_info_from_isa): Use MIPS_CPU_IS_ISA.
* doc/c-mips.texi: Document .set {g,f}p={32,64,default}. Document
missing -march options. Document .set arch=CPU. Move .set smartmips
to ASE page. Use @code for .set FOO examples.
[ gas/testsuite/Changelog ]
* gas/mips/mips-gp32-fp64-pic.d, mips/mips-gp32-fp64.d,
gas/mips/mips-gp64-fp32-pic.d, gas/mips/mips-gp64-fp32.l,
gas/mips/mips-gp64-fp64.d: Adjust test cases to the changes assembler
output.
* gas/mips/mips-gp32-fp64.l, gas/mips/mips-gp64-fp32-pic.l: New files,
catch assembler warnings.
2006-05-23 17:37:20 +02:00
|
|
|
configuration. You can use this feature to permit specific @sc{mips3}
|
2000-12-12 20:36:32 +01:00
|
|
|
instructions while assembling in 32 bit mode. Use this directive with
|
2001-06-29 23:27:43 +02:00
|
|
|
care!
|
1999-05-03 09:29:11 +02:00
|
|
|
|
[ gas/ChangeLog ]
* config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS): Rename.
(ISA_SUPPORTS_DSP_ASE, ISA_SUPPORTS_MT_ASE, ISA_HAS_64BIT_FPRS,
ISA_HAS_MXHC1): New macros.
(HAVE_32BIT_FPRS): Use ISA_HAS_64BIT_FPRS instead of
ISA_HAS_64BIT_REGS. Formatting fixes. Improved comments.
(mips_cpu_info): Change to use combined ASE/IS_ISA flag.
(MIPS_CPU_IS_ISA, MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP,
MIPS_CPU_ASE_MT, MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX): New defines.
(mips_after_parse_args): Change default handling of float register
size to account for 32bit code with 64bit FP. Better sanity checking
of ISA/ASE/ABI option combinations.
(s_mipsset): Support switching of GPR and FPR sizes via
.set {g,f}p={32,64,default}. Better sanity checking for .set ASE
options.
(mips_elf_final_processing): We should record the use of 64bit FP
registers in 32bit code but we don't, because ELF header flags are
a scarce ressource.
(mips_cpu_info_table): Add ASE flags for CPUs with mandatory ASE
extensions. Add 4ksc, 4kec, 4kem, 4kep, 4ksd, m4kp, 24kec, 24kef,
24kex, 34kc, 34kf, 34kx, 25kf CPU definitions.
(mips_cpu_info_from_isa): Use MIPS_CPU_IS_ISA.
* doc/c-mips.texi: Document .set {g,f}p={32,64,default}. Document
missing -march options. Document .set arch=CPU. Move .set smartmips
to ASE page. Use @code for .set FOO examples.
[ gas/testsuite/Changelog ]
* gas/mips/mips-gp32-fp64-pic.d, mips/mips-gp32-fp64.d,
gas/mips/mips-gp64-fp32-pic.d, gas/mips/mips-gp64-fp32.l,
gas/mips/mips-gp64-fp64.d: Adjust test cases to the changes assembler
output.
* gas/mips/mips-gp32-fp64.l, gas/mips/mips-gp64-fp32-pic.l: New files,
catch assembler warnings.
2006-05-23 17:37:20 +02:00
|
|
|
@cindex MIPS CPU override
|
|
|
|
@kindex @code{.set arch=@var{cpu}}
|
|
|
|
The @code{.set arch=@var{cpu}} directive provides even finer control.
|
|
|
|
It changes the effective CPU target and allows the assembler to use
|
|
|
|
instructions specific to a particular CPU. All CPUs supported by the
|
|
|
|
@samp{-march} command line option are also selectable by this directive.
|
|
|
|
The original value is restored by @code{.set arch=default}.
|
1999-05-03 09:29:11 +02:00
|
|
|
|
[ gas/ChangeLog ]
* config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS): Rename.
(ISA_SUPPORTS_DSP_ASE, ISA_SUPPORTS_MT_ASE, ISA_HAS_64BIT_FPRS,
ISA_HAS_MXHC1): New macros.
(HAVE_32BIT_FPRS): Use ISA_HAS_64BIT_FPRS instead of
ISA_HAS_64BIT_REGS. Formatting fixes. Improved comments.
(mips_cpu_info): Change to use combined ASE/IS_ISA flag.
(MIPS_CPU_IS_ISA, MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP,
MIPS_CPU_ASE_MT, MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX): New defines.
(mips_after_parse_args): Change default handling of float register
size to account for 32bit code with 64bit FP. Better sanity checking
of ISA/ASE/ABI option combinations.
(s_mipsset): Support switching of GPR and FPR sizes via
.set {g,f}p={32,64,default}. Better sanity checking for .set ASE
options.
(mips_elf_final_processing): We should record the use of 64bit FP
registers in 32bit code but we don't, because ELF header flags are
a scarce ressource.
(mips_cpu_info_table): Add ASE flags for CPUs with mandatory ASE
extensions. Add 4ksc, 4kec, 4kem, 4kep, 4ksd, m4kp, 24kec, 24kef,
24kex, 34kc, 34kf, 34kx, 25kf CPU definitions.
(mips_cpu_info_from_isa): Use MIPS_CPU_IS_ISA.
* doc/c-mips.texi: Document .set {g,f}p={32,64,default}. Document
missing -march options. Document .set arch=CPU. Move .set smartmips
to ASE page. Use @code for .set FOO examples.
[ gas/testsuite/Changelog ]
* gas/mips/mips-gp32-fp64-pic.d, mips/mips-gp32-fp64.d,
gas/mips/mips-gp64-fp32-pic.d, gas/mips/mips-gp64-fp32.l,
gas/mips/mips-gp64-fp64.d: Adjust test cases to the changes assembler
output.
* gas/mips/mips-gp32-fp64.l, gas/mips/mips-gp64-fp32-pic.l: New files,
catch assembler warnings.
2006-05-23 17:37:20 +02:00
|
|
|
The directive @code{.set mips16} puts the assembler into MIPS 16 mode,
|
|
|
|
in which it will assemble instructions for the MIPS 16 processor. Use
|
|
|
|
@code{.set nomips16} to return to normal 32 bit mode.
|
2006-05-08 17:57:05 +02:00
|
|
|
|
2001-06-29 23:27:43 +02:00
|
|
|
Traditional @sc{mips} assemblers do not support this directive.
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
@node MIPS autoextend
|
|
|
|
@section Directives for extending MIPS 16 bit instructions
|
|
|
|
|
|
|
|
@kindex @code{.set autoextend}
|
|
|
|
@kindex @code{.set noautoextend}
|
|
|
|
By default, MIPS 16 instructions are automatically extended to 32 bits
|
[ gas/ChangeLog ]
* config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS): Rename.
(ISA_SUPPORTS_DSP_ASE, ISA_SUPPORTS_MT_ASE, ISA_HAS_64BIT_FPRS,
ISA_HAS_MXHC1): New macros.
(HAVE_32BIT_FPRS): Use ISA_HAS_64BIT_FPRS instead of
ISA_HAS_64BIT_REGS. Formatting fixes. Improved comments.
(mips_cpu_info): Change to use combined ASE/IS_ISA flag.
(MIPS_CPU_IS_ISA, MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP,
MIPS_CPU_ASE_MT, MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX): New defines.
(mips_after_parse_args): Change default handling of float register
size to account for 32bit code with 64bit FP. Better sanity checking
of ISA/ASE/ABI option combinations.
(s_mipsset): Support switching of GPR and FPR sizes via
.set {g,f}p={32,64,default}. Better sanity checking for .set ASE
options.
(mips_elf_final_processing): We should record the use of 64bit FP
registers in 32bit code but we don't, because ELF header flags are
a scarce ressource.
(mips_cpu_info_table): Add ASE flags for CPUs with mandatory ASE
extensions. Add 4ksc, 4kec, 4kem, 4kep, 4ksd, m4kp, 24kec, 24kef,
24kex, 34kc, 34kf, 34kx, 25kf CPU definitions.
(mips_cpu_info_from_isa): Use MIPS_CPU_IS_ISA.
* doc/c-mips.texi: Document .set {g,f}p={32,64,default}. Document
missing -march options. Document .set arch=CPU. Move .set smartmips
to ASE page. Use @code for .set FOO examples.
[ gas/testsuite/Changelog ]
* gas/mips/mips-gp32-fp64-pic.d, mips/mips-gp32-fp64.d,
gas/mips/mips-gp64-fp32-pic.d, gas/mips/mips-gp64-fp32.l,
gas/mips/mips-gp64-fp64.d: Adjust test cases to the changes assembler
output.
* gas/mips/mips-gp32-fp64.l, gas/mips/mips-gp64-fp32-pic.l: New files,
catch assembler warnings.
2006-05-23 17:37:20 +02:00
|
|
|
when necessary. The directive @code{.set noautoextend} will turn this
|
|
|
|
off. When @code{.set noautoextend} is in effect, any 32 bit instruction
|
|
|
|
must be explicitly extended with the @code{.e} modifier (e.g.,
|
|
|
|
@code{li.e $4,1000}). The directive @code{.set autoextend} may be used
|
1999-05-03 09:29:11 +02:00
|
|
|
to once again automatically extend instructions when necessary.
|
|
|
|
|
|
|
|
This directive is only meaningful when in MIPS 16 mode. Traditional
|
|
|
|
@sc{mips} assemblers do not support this directive.
|
|
|
|
|
|
|
|
@node MIPS insn
|
|
|
|
@section Directive to mark data as an instruction
|
|
|
|
|
|
|
|
@kindex @code{.insn}
|
|
|
|
The @code{.insn} directive tells @code{@value{AS}} that the following
|
|
|
|
data is actually instructions. This makes a difference in MIPS 16 mode:
|
|
|
|
when loading the address of a label which precedes instructions,
|
|
|
|
@code{@value{AS}} automatically adds 1 to the value, so that jumping to
|
|
|
|
the loaded address will do the right thing.
|
|
|
|
|
2009-07-23 12:19:20 +02:00
|
|
|
@kindex @code{.global}
|
|
|
|
The @code{.global} and @code{.globl} directives supported by
|
|
|
|
@code{@value{AS}} will by default mark the symbol as pointing to a
|
|
|
|
region of data not code. This means that, for example, any
|
|
|
|
instructions following such a symbol will not be disassembled by
|
2009-07-30 10:45:41 +02:00
|
|
|
@code{objdump} as it will regard them as data. To change this
|
2009-07-23 12:19:20 +02:00
|
|
|
behaviour an optional section name can be placed after the symbol name
|
|
|
|
in the @code{.global} directive. If this section exists and is known
|
|
|
|
to be a code section, then the symbol will be marked as poiting at
|
|
|
|
code not data. Ie the syntax for the directive is:
|
|
|
|
|
|
|
|
@code{.global @var{symbol}[ @var{section}][, @var{symbol}[ @var{section}]] ...},
|
|
|
|
|
|
|
|
Here is a short example:
|
|
|
|
|
|
|
|
@example
|
|
|
|
.global foo .text, bar, baz .data
|
|
|
|
foo:
|
|
|
|
nop
|
|
|
|
bar:
|
|
|
|
.word 0x0
|
|
|
|
baz:
|
|
|
|
.word 0x1
|
|
|
|
|
|
|
|
@end example
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
@node MIPS option stack
|
|
|
|
@section Directives to save and restore options
|
|
|
|
|
|
|
|
@cindex MIPS option stack
|
|
|
|
@kindex @code{.set push}
|
|
|
|
@kindex @code{.set pop}
|
|
|
|
The directives @code{.set push} and @code{.set pop} may be used to save
|
|
|
|
and restore the current settings for all the options which are
|
|
|
|
controlled by @code{.set}. The @code{.set push} directive saves the
|
|
|
|
current settings on a stack. The @code{.set pop} directive pops the
|
|
|
|
stack and restores the settings.
|
|
|
|
|
|
|
|
These directives can be useful inside an macro which must change an
|
|
|
|
option such as the ISA level or instruction reordering but does not want
|
|
|
|
to change the state of the code which invoked the macro.
|
|
|
|
|
|
|
|
Traditional @sc{mips} assemblers do not support these directives.
|
2002-03-16 04:09:19 +01:00
|
|
|
|
|
|
|
@node MIPS ASE instruction generation overrides
|
|
|
|
@section Directives to control generation of MIPS ASE instructions
|
|
|
|
|
|
|
|
@cindex MIPS MIPS-3D instruction generation override
|
|
|
|
@kindex @code{.set mips3d}
|
|
|
|
@kindex @code{.set nomips3d}
|
|
|
|
The directive @code{.set mips3d} makes the assembler accept instructions
|
|
|
|
from the MIPS-3D Application Specific Extension from that point on
|
|
|
|
in the assembly. The @code{.set nomips3d} directive prevents MIPS-3D
|
|
|
|
instructions from being accepted.
|
|
|
|
|
[ gas/ChangeLog ]
* config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS): Rename.
(ISA_SUPPORTS_DSP_ASE, ISA_SUPPORTS_MT_ASE, ISA_HAS_64BIT_FPRS,
ISA_HAS_MXHC1): New macros.
(HAVE_32BIT_FPRS): Use ISA_HAS_64BIT_FPRS instead of
ISA_HAS_64BIT_REGS. Formatting fixes. Improved comments.
(mips_cpu_info): Change to use combined ASE/IS_ISA flag.
(MIPS_CPU_IS_ISA, MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP,
MIPS_CPU_ASE_MT, MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX): New defines.
(mips_after_parse_args): Change default handling of float register
size to account for 32bit code with 64bit FP. Better sanity checking
of ISA/ASE/ABI option combinations.
(s_mipsset): Support switching of GPR and FPR sizes via
.set {g,f}p={32,64,default}. Better sanity checking for .set ASE
options.
(mips_elf_final_processing): We should record the use of 64bit FP
registers in 32bit code but we don't, because ELF header flags are
a scarce ressource.
(mips_cpu_info_table): Add ASE flags for CPUs with mandatory ASE
extensions. Add 4ksc, 4kec, 4kem, 4kep, 4ksd, m4kp, 24kec, 24kef,
24kex, 34kc, 34kf, 34kx, 25kf CPU definitions.
(mips_cpu_info_from_isa): Use MIPS_CPU_IS_ISA.
* doc/c-mips.texi: Document .set {g,f}p={32,64,default}. Document
missing -march options. Document .set arch=CPU. Move .set smartmips
to ASE page. Use @code for .set FOO examples.
[ gas/testsuite/Changelog ]
* gas/mips/mips-gp32-fp64-pic.d, mips/mips-gp32-fp64.d,
gas/mips/mips-gp64-fp32-pic.d, gas/mips/mips-gp64-fp32.l,
gas/mips/mips-gp64-fp64.d: Adjust test cases to the changes assembler
output.
* gas/mips/mips-gp32-fp64.l, gas/mips/mips-gp64-fp32-pic.l: New files,
catch assembler warnings.
2006-05-23 17:37:20 +02:00
|
|
|
@cindex SmartMIPS instruction generation override
|
|
|
|
@kindex @code{.set smartmips}
|
|
|
|
@kindex @code{.set nosmartmips}
|
|
|
|
The directive @code{.set smartmips} makes the assembler accept
|
|
|
|
instructions from the SmartMIPS Application Specific Extension to the
|
|
|
|
MIPS32 @sc{isa} from that point on in the assembly. The
|
|
|
|
@code{.set nosmartmips} directive prevents SmartMIPS instructions from
|
|
|
|
being accepted.
|
|
|
|
|
[ gas/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* config/tc-mips.c (mips_set_options): New "ase_mdmx" member.
(mips_opts): Initialize "ase_mdmx" member.
(file_ase_mdmx): New variable.
(CPU_HAS_MDMX): New macro.
(md_begin): Initialize mips_opts.ase_mdmx and file_ase_mdmx
based on command line options and configuration defaults.
(macro_build): Note in comment that use of MDMX in macros is
not currently allowed.
(validate_mips_insn): Add support for the "O", "Q", "X", "Y", and
"Z" MDMX operand types.
(mips_ip): Accept MDMX instructions if mips_opts.ase_mdmx is set,
and add support for the "O", "Q", "X", "Y", and "Z" MDMX operand
types.
(OPTION_MDMX, OPTION_NO_MDMX, md_longopts, md_parse_option):
Add support for "-mdmx" and "-no-mdmx" options.
(OPTION_ELF_BASE): Move to accomodate new options.
(s_mipsset): Support ".set mdmx" and ".set nomdmx".
(mips_elf_final_processing): Set MDMX ASE ELF header flag if
file_ase_mdmx was set.
* doc/as.texinfo: Document -mdmx and -no-mdmx options.
* doc/c-mips.texi: Likewise, and document ".set mdmx" and ".set
nomdmx" directives.
[ gas/testsuite/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
* gas/mips/mips64-mdmx.s: New file.
* gas/mips/mips64-mdmx.d: Likewise.
* gas/mips/mips.exp: Run new "mips64-mdmx" test.
[ include/opcode/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
* mips.h (OP_SH_ALN, OP_MASK_ALN, OP_SH_VSEL, OP_MASK_VSEL)
(MDMX_FMTSEL_IMM_QH, MDMX_FMTSEL_IMM_OB, MDMX_FMTSEL_VEC_QH)
(MDMX_FMTSEL_VEC_OB, INSN_READ_MDMX_ACC, INSN_WRITE_MDMX_ACC)
(INSN_MDMX): New constants, for MDMX support.
(opcode character list): Add "O", "Q", "X", "Y", and "Z" for MDMX.
[ opcodes/ChangeLog ]
2002-05-30 Chris G. Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* mips-dis.c (print_insn_arg): Add support for 'O', 'Q', 'X', 'Y',
and 'Z' formats, for MDMX.
(mips_isa_type): Add MDMX instructions to the ISA
bit mask for bfd_mach_mipsisa64.
* mips-opc.c: Add support for MDMX instructions.
(MX): New definition.
* mips-dis.c: Update copyright years to include 2002.
2002-05-31 03:17:18 +02:00
|
|
|
@cindex MIPS MDMX instruction generation override
|
|
|
|
@kindex @code{.set mdmx}
|
|
|
|
@kindex @code{.set nomdmx}
|
|
|
|
The directive @code{.set mdmx} makes the assembler accept instructions
|
|
|
|
from the MDMX Application Specific Extension from that point on
|
|
|
|
in the assembly. The @code{.set nomdmx} directive prevents MDMX
|
|
|
|
instructions from being accepted.
|
|
|
|
|
[ gas/ChangeLog ]
* config/tc-mips.c (mips_set_options, mips_opts, file_ase_dspr2,
ISA_SUPPORTS_DSPR2_ASE, MIPS_CPU_ASE_DSPR2): Add DSP R2 ASE support.
(macro_build): Add case '2'.
(macro): Expand M_BALIGN to nop, packrl.ph or balign.
(validate_mips_insn): Add support for balign instruction.
(mips_ip): Handle DSP R2 instructions. Support balign instruction.
(OPTION_DSPR2, OPTION_NO_DSPR2, OPTION_COMPAT_ARCH_BASE,
md_parse_option, mips_after_parse_args): Add -mdspr2 and -mno-dspr2
command line options.
(s_mipsset): Add support for .set dspr2 and .set nodspr2 directives.
(md_show_usage): Add -mdspr2 and -mno-dspr2 help output.
* doc/c-mips.texi, doc/as.texinfo: Document -mdspr2, -mno-dspr2,
.set dspr2, .set nodspr2.
[ gas/testsuite/ChangeLog ]
* gas/mips/mips32-dspr2.s, gas/mips/mips32-dspr2.d: New test for
DSP R2.
* gas/mips/mips.exp: Run new test.
[ include/opcode/Changelog ]
* mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
(INSN_DSPR2): Add flag for DSP R2 instructions.
(M_BALIGN): New macro.
[ opcodes/ChangeLog ]
* mips-dis.c (mips_arch_choices): Add DSP R2 support.
(print_insn_args): Add support for balign instruction.
* mips-opc.c (D33): New shortcut for DSP R2 instructions.
(mips_builtin_opcodes): Add DSP R2 instructions.
[ sim/mips/ChangeLog ]
* Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
* configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
Add dsp2 to sim_igen_machine.
* configure: Regenerate.
* dsp.igen (do_ph_op): Add MUL support when op = 2.
(do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
(mulq_rs.ph): Use do_ph_mulq.
(MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
* mips.igen: Add dsp2 model and include dsp2.igen.
(MFHI, MFLO, MTHI, MTLO): Extend these instructions for
for *mips32r2, *mips64r2, *dsp.
(MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
for *mips32r2, *mips64r2, *dsp2.
* dsp2.igen: New file for MIPS DSP REV 2 ASE.
[ sim/testsuite/sim/mips/ChangeLog ]
* basic.exp: Run the dsp2 test.
* utils-dsp.inc (dspckacc_astio, dspck_tsimm): New macro.
* mips32-dsp2.s: New test.
2007-02-20 14:28:56 +01:00
|
|
|
@cindex MIPS DSP Release 1 instruction generation override
|
2005-09-08 20:05:15 +02:00
|
|
|
@kindex @code{.set dsp}
|
|
|
|
@kindex @code{.set nodsp}
|
|
|
|
The directive @code{.set dsp} makes the assembler accept instructions
|
[ gas/ChangeLog ]
* config/tc-mips.c (mips_set_options, mips_opts, file_ase_dspr2,
ISA_SUPPORTS_DSPR2_ASE, MIPS_CPU_ASE_DSPR2): Add DSP R2 ASE support.
(macro_build): Add case '2'.
(macro): Expand M_BALIGN to nop, packrl.ph or balign.
(validate_mips_insn): Add support for balign instruction.
(mips_ip): Handle DSP R2 instructions. Support balign instruction.
(OPTION_DSPR2, OPTION_NO_DSPR2, OPTION_COMPAT_ARCH_BASE,
md_parse_option, mips_after_parse_args): Add -mdspr2 and -mno-dspr2
command line options.
(s_mipsset): Add support for .set dspr2 and .set nodspr2 directives.
(md_show_usage): Add -mdspr2 and -mno-dspr2 help output.
* doc/c-mips.texi, doc/as.texinfo: Document -mdspr2, -mno-dspr2,
.set dspr2, .set nodspr2.
[ gas/testsuite/ChangeLog ]
* gas/mips/mips32-dspr2.s, gas/mips/mips32-dspr2.d: New test for
DSP R2.
* gas/mips/mips.exp: Run new test.
[ include/opcode/Changelog ]
* mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
(INSN_DSPR2): Add flag for DSP R2 instructions.
(M_BALIGN): New macro.
[ opcodes/ChangeLog ]
* mips-dis.c (mips_arch_choices): Add DSP R2 support.
(print_insn_args): Add support for balign instruction.
* mips-opc.c (D33): New shortcut for DSP R2 instructions.
(mips_builtin_opcodes): Add DSP R2 instructions.
[ sim/mips/ChangeLog ]
* Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
* configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
Add dsp2 to sim_igen_machine.
* configure: Regenerate.
* dsp.igen (do_ph_op): Add MUL support when op = 2.
(do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
(mulq_rs.ph): Use do_ph_mulq.
(MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
* mips.igen: Add dsp2 model and include dsp2.igen.
(MFHI, MFLO, MTHI, MTLO): Extend these instructions for
for *mips32r2, *mips64r2, *dsp.
(MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
for *mips32r2, *mips64r2, *dsp2.
* dsp2.igen: New file for MIPS DSP REV 2 ASE.
[ sim/testsuite/sim/mips/ChangeLog ]
* basic.exp: Run the dsp2 test.
* utils-dsp.inc (dspckacc_astio, dspck_tsimm): New macro.
* mips32-dsp2.s: New test.
2007-02-20 14:28:56 +01:00
|
|
|
from the DSP Release 1 Application Specific Extension from that point
|
|
|
|
on in the assembly. The @code{.set nodsp} directive prevents DSP
|
|
|
|
Release 1 instructions from being accepted.
|
|
|
|
|
|
|
|
@cindex MIPS DSP Release 2 instruction generation override
|
|
|
|
@kindex @code{.set dspr2}
|
|
|
|
@kindex @code{.set nodspr2}
|
|
|
|
The directive @code{.set dspr2} makes the assembler accept instructions
|
|
|
|
from the DSP Release 2 Application Specific Extension from that point
|
|
|
|
on in the assembly. This dirctive implies @code{.set dsp}. The
|
|
|
|
@code{.set nodspr2} directive prevents DSP Release 2 instructions from
|
|
|
|
being accepted.
|
2005-09-08 20:05:15 +02:00
|
|
|
|
* config/tc-mips.c (mips_set_options): Add ase_mt for MT instructions.
(mips_opts): Add -1 to initialize ase_mt.
(file_ase_mt): New variable for -mmt.
(CPU_HAS_MT): New define.
(validate_mips_insn): Add supports for +t, +T, !, $, *, &, g operand
formats.
(mips_ip): Check ase_mt to enable MT instructions.
Handle !, $, *, &, +T, +t, g operand formats.
For "mftc1", "mfthc1", "cftc1", "mttc1", "mtthc1", "cttc1", we allow
odd float registers.
(OPTION_MT, OPTION_NO_MT): New define.
(OPTION_COMPAT_ARCH_BASE): Change because of inserting MT define.
(md_parse_option): Parse OPTION_MT and OPTION_NO_MT.
(mips_after_parse_args): Set ase_mt based on CPU.
(s_mipsset): Handle ".set mt" and ".set nomt".
(mips_elf_final_processing): Remind of adding new flag for MT ASE.
(md_show_usage): Show usage of -mmt and -mno-mt.
* doc/as.texinfo: Document -mmt and -mno-mt options.
* doc/c-mips.texi: Likewise, and document ".set mt" and ".set nomt"
directives.
2005-09-06 20:53:03 +02:00
|
|
|
@cindex MIPS MT instruction generation override
|
|
|
|
@kindex @code{.set mt}
|
|
|
|
@kindex @code{.set nomt}
|
|
|
|
The directive @code{.set mt} makes the assembler accept instructions
|
|
|
|
from the MT Application Specific Extension from that point on
|
|
|
|
in the assembly. The @code{.set nomt} directive prevents MT
|
|
|
|
instructions from being accepted.
|
|
|
|
|
2002-03-16 04:09:19 +01:00
|
|
|
Traditional @sc{mips} assemblers do not support these directives.
|
* config/tc-mips.c (file_mips_soft_float, file_mips_single_float):
New statics.
(OPTION_ELF_BASE): Make room for new option macros.
(OPTION_SOFT_FLOAT, OPTION_HARD_FLOAT, OPTION_SINGLE_FLOAT,
OPTION_DOUBLE_FLOAT): New option macros.
(md_longopts): Add msoft-float, mhard-float, msingle-float and
mdouble-float.
(md_parse_option): Handle OPTION_SINGLE_FLOAT,
OPTION_DOUBLE_FLOAT, OPTION_SOFT_FLOAT and OPTION_HARD_FLOAT.
(md_show_usage): Add -msoft-float, -mhard-float, -msingle-float
and -mdouble-float.
(struct mips_set_options): New fields soft_float and single_float.
(mips_opts): Initialized them. Add comment for each field
initializer.
(mips_after_parse_args): Set them based on file_mips_soft_float
and file_mips_single_float.
(s_mipsset): Add support for `.set softfloat', `.set hardfloat',
`.set singlefloat' and `.set doublefloat'.
(is_opcode_valid): New function to invoke OPCODE_IS_MEMBER.
Handle single-float and soft-float instructions here.
(macro_build, mips_ip): Use it instead of OPCODE_IS_MEMBER.
(is_opcode_valid_16): New function.
(mips16_ip): Use it instead of OPCODE_IS_MEMBER.
(macro) <M_LDC1_AB, M_SDC1_AB, M_L_DOB, M_L_DAB, M_S_DAB,
M_S_DOB>: Remove special-casing of r4650.
* doc/c-mips.texi (-march=): Add Octeon.
(MIPS Opts): Document -msoft-float and -mhard-float. Document
-msingle-float and -mdouble-float.
(MIPS floating-point): New section. Document `.set softfloat' and
`.set hardfloat'. Document `.set singlefloat' and `.set
doublefloat'.
2008-04-28 19:06:28 +02:00
|
|
|
|
|
|
|
@node MIPS floating-point
|
|
|
|
@section Directives to override floating-point options
|
|
|
|
|
|
|
|
@cindex Disable floating-point instructions
|
|
|
|
@kindex @code{.set softfloat}
|
|
|
|
@kindex @code{.set hardfloat}
|
|
|
|
The directives @code{.set softfloat} and @code{.set hardfloat} provide
|
|
|
|
finer control of disabling and enabling float-point instructions.
|
|
|
|
These directives always override the default (that hard-float
|
|
|
|
instructions are accepted) or the command-line options
|
|
|
|
(@samp{-msoft-float} and @samp{-mhard-float}).
|
|
|
|
|
|
|
|
@cindex Disable single-precision floating-point operations
|
2009-09-25 20:58:58 +02:00
|
|
|
@kindex @code{.set singlefloat}
|
|
|
|
@kindex @code{.set doublefloat}
|
* config/tc-mips.c (file_mips_soft_float, file_mips_single_float):
New statics.
(OPTION_ELF_BASE): Make room for new option macros.
(OPTION_SOFT_FLOAT, OPTION_HARD_FLOAT, OPTION_SINGLE_FLOAT,
OPTION_DOUBLE_FLOAT): New option macros.
(md_longopts): Add msoft-float, mhard-float, msingle-float and
mdouble-float.
(md_parse_option): Handle OPTION_SINGLE_FLOAT,
OPTION_DOUBLE_FLOAT, OPTION_SOFT_FLOAT and OPTION_HARD_FLOAT.
(md_show_usage): Add -msoft-float, -mhard-float, -msingle-float
and -mdouble-float.
(struct mips_set_options): New fields soft_float and single_float.
(mips_opts): Initialized them. Add comment for each field
initializer.
(mips_after_parse_args): Set them based on file_mips_soft_float
and file_mips_single_float.
(s_mipsset): Add support for `.set softfloat', `.set hardfloat',
`.set singlefloat' and `.set doublefloat'.
(is_opcode_valid): New function to invoke OPCODE_IS_MEMBER.
Handle single-float and soft-float instructions here.
(macro_build, mips_ip): Use it instead of OPCODE_IS_MEMBER.
(is_opcode_valid_16): New function.
(mips16_ip): Use it instead of OPCODE_IS_MEMBER.
(macro) <M_LDC1_AB, M_SDC1_AB, M_L_DOB, M_L_DAB, M_S_DAB,
M_S_DOB>: Remove special-casing of r4650.
* doc/c-mips.texi (-march=): Add Octeon.
(MIPS Opts): Document -msoft-float and -mhard-float. Document
-msingle-float and -mdouble-float.
(MIPS floating-point): New section. Document `.set softfloat' and
`.set hardfloat'. Document `.set singlefloat' and `.set
doublefloat'.
2008-04-28 19:06:28 +02:00
|
|
|
The directives @code{.set singlefloat} and @code{.set doublefloat}
|
|
|
|
provide finer control of disabling and enabling double-precision
|
|
|
|
float-point operations. These directives always override the default
|
|
|
|
(that double-precision operations are accepted) or the command-line
|
|
|
|
options (@samp{-msingle-float} and @samp{-mdouble-float}).
|
|
|
|
|
|
|
|
Traditional @sc{mips} assemblers do not support these directives.
|