binutils-gdb/opcodes/d30v-dis.c

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/* Disassemble D30V instructions.
Copyright (C) 1997-2020 Free Software Foundation, Inc.
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This file is part of the GNU opcodes library.
This library is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
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You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
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#include "sysdep.h"
PR 14072 * configure.in: Add check that sysdep.h has been included before any system header files. * configure: Regenerate. * config.in: Regenerate. * sysdep.h: Generate an error if included before config.h. * alpha-opc.c: Include sysdep.h before any other header file. * alpha-dis.c: Likewise. * avr-dis.c: Likewise. * cgen-opc.c: Likewise. * cr16-dis.c: Likewise. * cris-dis.c: Likewise. * crx-dis.c: Likewise. * d10v-dis.c: Likewise. * d10v-opc.c: Likewise. * d30v-dis.c: Likewise. * d30v-opc.c: Likewise. * h8500-dis.c: Likewise. * i370-dis.c: Likewise. * i370-opc.c: Likewise. * m10200-dis.c: Likewise. * m10300-dis.c: Likewise. * micromips-opc.c: Likewise. * mips-opc.c: Likewise. * mips61-opc.c: Likewise. * moxie-dis.c: Likewise. * or32-opc.c: Likewise. * pj-dis.c: Likewise. * ppc-dis.c: Likewise. * ppc-opc.c: Likewise. * s390-dis.c: Likewise. * sh-dis.c: Likewise. * sh64-dis.c: Likewise. * sparc-dis.c: Likewise. * sparc-opc.c: Likewise. * spu-dis.c: Likewise. * tic30-dis.c: Likewise. * tic54x-dis.c: Likewise. * tic80-dis.c: Likewise. * tic80-opc.c: Likewise. * tilegx-dis.c: Likewise. * tilepro-dis.c: Likewise. * v850-dis.c: Likewise. * v850-opc.c: Likewise. * vax-dis.c: Likewise. * w65-dis.c: Likewise. * xgate-dis.c: Likewise. * xtensa-dis.c: Likewise. * rl78-decode.opc: Likewise. * rl78-decode.c: Regenerate. * rx-decode.opc: Likewise. * rx-decode.c: Regenerate. * configure.in: Add check that sysdep.h has been included before any system header files. * configure: Regenerate. * config.in: Regenerate. * sysdep.h: Generate an error if included before config.h. * configure.in: Add check that sysdep.h has been included before any system header files. * configure: Regenerate. * config.in: Regenerate. * aclocal.m4: Regenerate. * bfd-in.h: Generate an error if included before config.h. * sysdep.h: Likewise. * bfd-in2.h: Regenerate. * compress.c: Remove #include "config.h". * plugin.c: Likewise. * elf32-m68hc1x.c: Include sysdep.h before alloca-conf.h. * elf64-hppa.c: Likewise. * som.c: Likewise. * xsymc.c: Likewise. * configure.in: Add check that sysdep.h has been included before any system header files. * configure: Regenerate. * config.in: Regenerate. * configure.in: Add check that sysdep.h has been included before any system header files. * configure: Regenerate. * config.in: Regenerate. * aclocal.m4: Regenerate. * Makefile.am: Use wrappers around C files generated by flex. * Makefile.in: Regenerate. * doc/Makefile.in: Regenerate. * itbl-lex-wrapper.c: New file. * config/bfin-lex-wrapper.c: New file. * cgen.c: Include as.h before setjmp.h. * config/tc-dlx.c: Include as.h before any other header. * config/tc-h8300.c: Likewise. * config/tc-lm32.c: Likewise. * config/tc-mep.c: Likewise. * config/tc-microblaze.c: Likewise. * config/tc-mmix.c: Likewise. * config/tc-msp430.c: Likewise. * config/tc-or32.c: Likewise. * config/tc-tic4x.c: Likewise. * config/tc-tic54x.c: Likewise. * config/tc-xtensa.c: Likewise. * configure.in: Add check that sysdep.h has been included before any system header files. * configure: Regenerate. * config.in: Regenerate. * unwind-ia64.h: Include config.h.
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#include <stdio.h>
#include "opcode/d30v.h"
Move print_insn_XXX to an opcodes internal header With the changes done in previous patches, print_insn_XXX functions don't have to be external visible out of opcodes, because both gdb and objdump select disassemblers through a single interface. This patch moves these print_insn_XXX declarations from include/dis-asm.h to opcodes/disassemble.h, which is a new header added by this patch. include: 2017-05-24 Yao Qi <yao.qi@linaro.org> * dis-asm.h: Move some function declarations to opcodes/disassemble.h. opcodes: 2017-05-24 Yao Qi <yao.qi@linaro.org> * alpha-dis.c: Include disassemble.h, don't include dis-asm.h. * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise. * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise. * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise. * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise. * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise. * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise. * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise. * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise. * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise. * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise. * moxie-dis.c, msp430-dis.c, mt-dis.c: * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise. * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise. * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise. * rl78-dis.c, s390-dis.c, score-dis.c: Likewise. * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise. * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise. * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise. * v850-dis.c, vax-dis.c, visium-dis.c: Likewise. * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise. * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise. * z80-dis.c, z8k-dis.c: Likewise. * disassemble.h: New file.
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#include "disassemble.h"
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#include "opintl.h"
#include "libiberty.h"
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#define PC_MASK 0xFFFFFFFF
/* Return 0 if lookup fails,
1 if found and only one form,
2 if found and there are short and long forms. */
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static int
lookup_opcode (struct d30v_insn *insn, long num, int is_long)
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{
int i = 0, op_index;
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struct d30v_format *f;
struct d30v_opcode *op = (struct d30v_opcode *) d30v_opcode_table;
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int op1 = (num >> 25) & 0x7;
int op2 = (num >> 20) & 0x1f;
int mod = (num >> 18) & 0x3;
/* Find the opcode. */
do
{
if ((op->op1 == op1) && (op->op2 == op2))
break;
op++;
}
while (op->name);
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if (!op || !op->name)
return 0;
while (op->op1 == op1 && op->op2 == op2)
{
/* Scan through all the formats for the opcode. */
op_index = op->format[i++];
do
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{
f = (struct d30v_format *) &d30v_format_table[op_index];
while (f->form == op_index)
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{
if ((!is_long || f->form >= LONG) && (f->modifier == mod))
{
insn->form = f;
break;
}
f++;
}
if (insn->form)
break;
}
while ((op_index = op->format[i++]) != 0);
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if (insn->form)
break;
op++;
i = 0;
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}
if (insn->form == NULL)
return 0;
insn->op = op;
insn->ecc = (num >> 28) & 0x7;
if (op->format[1])
return 2;
else
return 1;
}
static int
extract_value (uint64_t num, const struct d30v_operand *oper, int is_long)
{
unsigned int val;
int shift = 12 - oper->position;
unsigned int mask = (0xFFFFFFFF >> (32 - oper->bits));
if (is_long)
{
if (oper->bits == 32)
/* Piece together 32-bit constant. */
val = ((num & 0x3FFFF)
| ((num & 0xFF00000) >> 2)
| ((num & 0x3F00000000LL) >> 6));
else
val = (num >> (32 + shift)) & mask;
}
else
val = (num >> shift) & mask;
if (oper->flags & OPERAND_SHIFT)
val <<= 3;
return val;
}
static void
print_insn (struct disassemble_info *info,
bfd_vma memaddr,
uint64_t num,
struct d30v_insn *insn,
int is_long,
int show_ext)
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{
int val, opnum, need_comma = 0;
const struct d30v_operand *oper;
int i, match, need_paren = 0, found_control = 0;
unsigned int opind = 0;
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(*info->fprintf_func) (info->stream, "%s", insn->op->name);
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/* Check for CMP or CMPU. */
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if (d30v_operand_table[insn->form->operands[0]].flags & OPERAND_NAME)
{
opind++;
val =
extract_value (num,
&d30v_operand_table[insn->form->operands[0]],
is_long);
(*info->fprintf_func) (info->stream, "%s", d30v_cc_names[val]);
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}
/* Add in ".s" or ".l". */
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if (show_ext == 2)
{
if (is_long)
(*info->fprintf_func) (info->stream, ".l");
else
(*info->fprintf_func) (info->stream, ".s");
}
if (insn->ecc)
(*info->fprintf_func) (info->stream, "/%s", d30v_ecc_names[insn->ecc]);
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(*info->fprintf_func) (info->stream, "\t");
while (opind < ARRAY_SIZE (insn->form->operands)
&& (opnum = insn->form->operands[opind++]) != 0)
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{
int bits;
oper = &d30v_operand_table[opnum];
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bits = oper->bits;
if (oper->flags & OPERAND_SHIFT)
bits += 3;
if (need_comma
&& oper->flags != OPERAND_PLUS
&& oper->flags != OPERAND_MINUS)
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{
need_comma = 0;
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(*info->fprintf_func) (info->stream, ", ");
}
if (oper->flags == OPERAND_ATMINUS)
{
(*info->fprintf_func) (info->stream, "@-");
continue;
}
if (oper->flags == OPERAND_MINUS)
{
(*info->fprintf_func) (info->stream, "-");
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continue;
}
if (oper->flags == OPERAND_PLUS)
{
(*info->fprintf_func) (info->stream, "+");
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continue;
}
if (oper->flags == OPERAND_ATSIGN)
{
(*info->fprintf_func) (info->stream, "@");
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continue;
}
if (oper->flags == OPERAND_ATPAR)
{
(*info->fprintf_func) (info->stream, "@(");
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need_paren = 1;
continue;
}
if (oper->flags == OPERAND_SPECIAL)
continue;
val = extract_value (num, oper, is_long);
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if (oper->flags & OPERAND_REG)
{
match = 0;
if (oper->flags & OPERAND_CONTROL)
{
const struct d30v_operand *oper3
= &d30v_operand_table[insn->form->operands[2]];
int id = extract_value (num, oper3, is_long);
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found_control = 1;
switch (id)
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{
case 0:
val |= OPERAND_CONTROL;
break;
case 1:
case 2:
val = OPERAND_CONTROL + MAX_CONTROL_REG + id;
break;
case 3:
val |= OPERAND_FLAG;
break;
default:
opcodes error messages Another patch aimed at making binutils comply with the GNU coding standard. The generated files require https://sourceware.org/ml/cgen/2018-q1/msg00004.html cpu/ * frv.opc: Include opintl.h. (add_next_to_vliw): Use opcodes_error_handler to print error. Standardize error message. (fr500_check_insn_major_constraints, frv_vliw_add_insn): Likewise. opcodes/ * sysdep.h (opcodes_error_handler): Define. (_bfd_error_handler): Declare. * Makefile.am: Remove stray #. * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT EDIT" comment. * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c, * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c, * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use opcodes_error_handler to print errors. Standardize error messages. * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise, and include opintl.h. * nds32-asm.c: Likewise, and include sysdep.h and opintl.h. * i386-gen.c: Standardize error messages. * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate. * Makefile.in: Regenerate. * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c, * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c, * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c, * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c, * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c, * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c, * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c, * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c, * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c, * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c, * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c, * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c, * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
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/* xgettext: c-format */
opcodes_error_handler (_("illegal id (%d)"), id);
abort ();
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}
}
else if (oper->flags & OPERAND_ACC)
val |= OPERAND_ACC;
else if (oper->flags & OPERAND_FLAG)
val |= OPERAND_FLAG;
for (i = 0; i < reg_name_cnt (); i++)
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{
if (val == pre_defined_registers[i].value)
{
if (pre_defined_registers[i].pname)
(*info->fprintf_func)
(info->stream, "%s", pre_defined_registers[i].pname);
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else
(*info->fprintf_func)
(info->stream, "%s", pre_defined_registers[i].name);
match = 1;
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break;
}
}
if (match == 0)
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{
/* This would only get executed if a register was not in
the register table. */
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(*info->fprintf_func)
(info->stream, _("<unknown register %d>"), val & 0x3F);
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}
}
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/* repeati has a relocation, but its first argument is a plain
immediate. OTOH instructions like djsri have a pc-relative
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delay target, but an absolute jump target. Therefore, a test
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of insn->op->reloc_flag is not specific enough; we must test
if the actual operand we are handling now is pc-relative. */
else if (oper->flags & OPERAND_PCREL)
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{
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int neg = 0;
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/* IMM6S3 is unsigned. */
if (oper->flags & OPERAND_SIGNED || bits == 32)
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{
unsigned int sign = 1u << (bits - 1);
if (val & sign)
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{
val = -val & (sign + sign - 1);
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neg = 1;
}
}
if (neg)
{
(*info->fprintf_func) (info->stream, "-%x\t(", val);
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(*info->print_address_func) ((memaddr - val) & PC_MASK, info);
(*info->fprintf_func) (info->stream, ")");
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}
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else
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{
(*info->fprintf_func) (info->stream, "%x\t(", val);
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(*info->print_address_func) ((memaddr + val) & PC_MASK, info);
(*info->fprintf_func) (info->stream, ")");
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}
}
else if (insn->op->reloc_flag == RELOC_ABS)
{
(*info->print_address_func) (val, info);
}
else
{
if (oper->flags & OPERAND_SIGNED)
{
unsigned int sign = 1u << (bits - 1);
if (val & sign)
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{
val = -val & (sign + sign - 1);
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(*info->fprintf_func) (info->stream, "-");
}
}
(*info->fprintf_func) (info->stream, "0x%x", val);
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}
/* If there is another operand, then write a comma and space. */
if (opind < ARRAY_SIZE (insn->form->operands)
&& insn->form->operands[opind]
&& !(found_control && opind == 2))
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need_comma = 1;
}
if (need_paren)
(*info->fprintf_func) (info->stream, ")");
}
int
print_insn_d30v (bfd_vma memaddr, struct disassemble_info *info)
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{
int status, result;
bfd_byte buffer[12];
uint32_t in1, in2;
struct d30v_insn insn;
uint64_t num;
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insn.form = NULL;
info->bytes_per_line = 8;
info->bytes_per_chunk = 4;
info->display_endian = BFD_ENDIAN_BIG;
status = (*info->read_memory_func) (memaddr, buffer, 4, info);
if (status != 0)
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{
(*info->memory_error_func) (status, memaddr, info);
return -1;
}
in1 = bfd_getb32 (buffer);
status = (*info->read_memory_func) (memaddr + 4, buffer, 4, info);
if (status != 0)
{
info->bytes_per_line = 8;
if (!(result = lookup_opcode (&insn, in1, 0)))
(*info->fprintf_func) (info->stream, ".long\t0x%x", in1);
else
print_insn (info, memaddr, (uint64_t) in1, &insn, 0, result);
return 4;
}
in2 = bfd_getb32 (buffer);
if (in1 & in2 & FM01)
{
/* LONG instruction. */
if (!(result = lookup_opcode (&insn, in1, 1)))
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{
(*info->fprintf_func) (info->stream, ".long\t0x%x,0x%x", in1, in2);
return 8;
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}
num = (uint64_t) in1 << 32 | in2;
print_insn (info, memaddr, num, &insn, 1, result);
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}
else
{
num = in1;
if (!(result = lookup_opcode (&insn, in1, 0)))
(*info->fprintf_func) (info->stream, ".long\t0x%x", in1);
else
print_insn (info, memaddr, num, &insn, 0, result);
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switch (((in1 >> 31) << 1) | (in2 >> 31))
{
case 0:
(*info->fprintf_func) (info->stream, "\t||\t");
break;
case 1:
(*info->fprintf_func) (info->stream, "\t->\t");
break;
case 2:
(*info->fprintf_func) (info->stream, "\t<-\t");
default:
break;
}
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insn.form = NULL;
num = in2;
if (!(result = lookup_opcode (&insn, in2, 0)))
(*info->fprintf_func) (info->stream, ".long\t0x%x", in2);
else
print_insn (info, memaddr, num, &insn, 0, result);
}
return 8;
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}