Commit Graph

186 Commits

Author SHA1 Message Date
Andre Vieira 4ab90a7a90 Fixes for unpredictable nops and 26-bit versions of teq,tst,cmn,cmp.
opcodes * arm-dis.c (print_insn_arm): Disassembling for all targets V6
	and higher with ARM instruction set will now mark the 26-bit
	versions of teq,tst,cmn and cmp as UNPREDICTABLE.
	(arm_opcodes): Fix for unpredictable nop being recognized as a teq.

test    * gas/arm/nops.d: New.
	* gas/arm/nops.s: New.
	* gas/arm/inst.d: Changed expectation file for 26-bit  teq,
	tst, cmn and cmp.
2015-08-13 11:39:08 +01:00
H.J. Lu 43e65147c0 Remove trailing spaces in opcodes 2015-08-12 04:45:07 -07:00
Alessandro Marzocchi 6f1c214259 Updates the ARM disassembler's output of floating point constants to include the actual floating point value.
opcodes	* arm-dis.c (print_insn_coprocessor): Added support for quarter
	float bitfield format.
	(coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
	quarter float bitfield format.

tests	* gas/arm/vfpv3-const-conv.d: Update expected result due to change
	of comment for vmov reg,immediate with VFP coprocessor.
2015-07-16 16:43:16 +01:00
Szabolcs Nagy 24b4cf66a6 Fixes a compile time warnng about left shifting a negative value.
* arm-dis.c (print_insn_coprocessor): Avoid negative shift.
2015-06-16 13:35:33 +01:00
Matthew Wahab d6b4b13ed2 [ARM] Support for ARMv8.1 Adv.SIMD extension 2015-06-02 12:37:33 +01:00
Matthew Wahab ddfded2f7b [ARM] Add support for ARMv8.1 PAN extension 2015-06-02 12:30:38 +01:00
Matthew Wahab 1af1dd51db [ARM] Rework CPU feature selection in the disassembler
include/opcode/
	* arm.h (ARM_FEATURE_ALL): New.

opcodes/
	* arm-dis.c (select_arm_features): Rework to avoid used of
	redefined macros.
2015-06-02 12:24:24 +01:00
Renlin Li f0fba320ab [ARM] Disassembles SSAT and SSAT16 instructions incorrectly for Thumb-2
2015-04-15  Renlin Li  <renlin.li@arm.com>
opcodes/:
    * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
    use it for ssat and ssat16.
    (print_insn_thumb32): Add handle case for 'D' control code.

gas/testsuite/:
    * gas/arm/arch7em.d: Adjust required ssat and ssat16 immediate field.
    * gas/arm/thumb32.d: Likewise.
2015-04-15 17:44:03 +01:00
Terry Guo 823d25713d Extend arm_feature_set struct to provide more bits
gas/ChangeLog:
2015-03-24  Terry Guo  <terry.guo@arm.com>

	* config/tc-arm.c (no_cpu_selected): Use new macro to compare
	features.
	(parse_psr): Likewise.
	(do_t_mrs): Likewise.
	(do_t_msr): Likewise.
	(static const arm_feature_set arm_ext_*): Defined with new
	macros.
	(static const arm_feature_set arm_cext_*): Likewise.
	(static const arm_feature_set fpu_fpa_ext_*): Likewise.
	(static const arm_feature_set fpu_vfp_ext_*): Likewise.
	(deprecated_coproc_regs): Likewise.
	(UL_BARRIER): Likewise.
	(barrier_opt_names): Likewise.
	(arm_cpus): Likewise.
	(arm_extensions): Likewise.

include/opcode/ChangeLog:
2015-03-24  Terry Guo  <terry.guo@arm.com>

	* arm.h (arm_feature_set): Extended to provide more available
	* bits.
	(ARM_ANY): Updated to follow above new definition.
	(ARM_CPU_HAS_FEATURE): Likewise.
	(ARM_CPU_IS_ANY): Likewise.
	(ARM_MERGE_FEATURE_SETS): Likewise.
	(ARM_CLEAR_FEATURE): Likewise.
	(ARM_FEATURE): Likewise.
	(ARM_FEATURE_COPY): New macro.
	(ARM_FEATURE_EQUAL): Likewise.
	(ARM_FEATURE_ZERO): Likewise.
	(ARM_FEATURE_CORE_EQUAL): Likewise.
	(ARM_FEATURE_LOW): Likewise.
	(ARM_FEATURE_CORE_LOW): Likewise.
	(ARM_FEATURE_CORE_COPROC): Likewise.

opcodes/ChangeLog:
2015-03-24  Terry Guo  <terry.guo@arm.com>

	* arm-dis.c (opcode32): Updated to use new arm feature struct.
	(opcode16): Likewise.
	(coprocessor_opcodes): Replace bit with feature struct.
	(neon_opcodes): Likewise.
	(arm_opcodes): Likewise.
	(thumb_opcodes): Likewise.
	(thumb32_opcodes): Likewise.
	(print_insn_coprocessor): Likewise.
	(print_insn_arm): Likewise.
	(select_arm_features): Follow new feature struct.
2015-03-24 14:08:08 +08:00
Jiong Wang d8282f0eb1 [ARM] Skip private symbol when doing objdump
2015-03-03  Jiong Wang  <jiong.wang@arm.com>

  opcode/
    * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.

  binutils/testsuite/
    * binutils-all/arm/rvct_symbol.s: New testcase.
    * binutils-all/arm/objdump.exp: Run it.
2015-03-03 15:00:59 +00:00
Alan Modra b90efa5b79 ChangeLog rotatation and copyright year update 2015-01-02 00:53:45 +10:30
Maciej W. Rozycki 84919466a8 ARM/opcodes: Fix negative hexadecimal offset disassembly
2014-08-21  Nathan Sidwell  <nathan@codesourcery.com>
            Maciej W. Rozycki  <macro@codesourcery.com>

	opcodes/
	* arm-dis.c (print_arm_address): Negate the GPR-relative offset
	returned if the U bit is set.

2014-08-21  Paul Brook  <paul@codesourcery.com>

	gas/testsuite/
	* gas/arm/arch7a-mp.d: Adjust according to `print_arm_address'
	offset fix.
	* gas/arm/arch7r-mp.d: Likewise.
2014-08-22 16:42:12 +01:00
Alan Modra 4b95cf5c0c Update copyright years 2014-03-05 22:16:15 +10:30
Ramana Radhakrishnan 8518117318 Fix neon vshll disassembly.
opcodes/
2013-10-15  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

	* arm-dis.c (neon_opcodes): Adjust print string for vshll.

gas/testsuite/
2013-10-15  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

	* gas/arm/neon-cov.d: Adjust output.
2013-10-15 13:30:40 +00:00
Nick Clifton 74db7efbe3 PR gas/15914
* config/tc-arm.c (T16_32_TAB): Add _udf.
	(do_t_udf): New function.
	(insns): Add "udf".

	* gas/arm/udf-bad.s: New file.
	* gas/arm/udf-bad.d: New file.
	* gas/arm/udf-bad.l: New file.
	* gas/arm/udf.s: New file.
	* gas/arm/udf.d: New file.
	* gas/arm/udf.l: New file.

	* arm-dis.c (arm_opcodes): Add udf.
	(thumb_opcodes): Use "udf" mnemonic rather than UNDEFINED_INSTRUCTION.
	(thumb32_opcodes): Add udf.w.
	(print_insn_thumb32): Handle %H as the thumb32_opcodes comment says.
2013-09-04 07:59:33 +00:00
Kyrylo Tkachov dd5181d57f Add support for AArch32 CRC instruction in ARMv8.
gas/ChangeLog
2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* config/tc-arm.c (crc_ext_armv8): New feature set.
	(UNPRED_REG): New macro.
	(do_crc32_1): New function.
	(do_crc32b, do_crc32h, do_crc32w, do_crc32cb,
	do_crc32ch, do_crc32cw): Likewise.
	(TUEc): New macro.
	(insns): Add entries for crc32 mnemonics.
	(arm_extensions): Add entry for crc.

include/opcode/ChangeLog
2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* arm.h (CRC_EXT_ARMV8): New constant.
	(ARCH_CRC_ARMV8): New macro.

opcodes/ChangeLog
2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* arm-dis.c (arm_opcodes): Add entries for CRC instructions.
	(thumb32_opcodes): Likewise.
	(print_insn_thumb32): Handle 'S' control char.

gas/testsuite/ChangeLog
2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* gas/arm/crc32-bad.d: New file.
	* gas/arm/crc32-bad.l: Likewise.
	* gas/arm/crc32-bad.s: Likewise.
	* gas/arm/crc32.d: Likewise.
	* gas/arm/crc32.s: Likewise.
2013-03-11 11:09:33 +00:00
Richard Earnshaw 6fe6ded97b 2013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* arm-dis.c: Update strht pattern.

	* gas/arm/archv6t2.s: Add strht and ldrht tests.
	* gas/arm/archv6t2.d: Add disassembly patterns for the above.
2013-02-11 10:15:52 +00:00
Richard Earnshaw f8ece37fb1 2012-10-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* arm-dis.c: Use preferred form of vrint instruction variants
	for disassembly.

2012-10-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* gas/arm/armv8-a+fp.d: Use preferred form of vrint instruction
	variants for disassembly.
	* gas/arm/armv8-a+fp.s: Likewise.
	* gas/arm/armv8-a+simd.d: Likewise.
	* gas/arm/armv8-a+simd.s: Likewise.
2012-10-11 15:33:08 +00:00
Richard Earnshaw 4b8c8c02e9 2012-09-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
opcodes:
	* arm-dis.c: Changed ldra and strl-form mnemonics
	to lda and stl-form.
gas:
	* config/tc-arm.c: Changed ldra and strl-form mnemonics
	to lda and stl-form for armv8.
gas/testsuite:
	* gas/arm/armv8-a-bad.l: Updated for changed mnemonics.
	* gas/arm/armv8-a-bad.s: Likewise.
	* gas/arm/armv8-a.d: Likewise.
	* gas/arm/armv8-a.s: Likewise.
	* gas/arm/inst.s: Added test for ldrt encoding compatibly with ldralt.
	* gas/arm/inst.d: Updated.
2012-09-18 14:52:43 +00:00
Matthew Gretton-Dann 3c9017d250 * gas/config/tc-arm.c (ARM_ENC_TAB): Add sha1h and sha2op entries.
(do_sha1h): New function.
	(do_sha1su1): Likewise.
	(do_sha256su0): Likewise.
	(insns): Add 2 operand SHA instructions.
	* gas/testsuite/gas/arm/armv8-a+crypto.s: Update testcase.
	* gas/testsuite/gas/arm/armv8-a+crypto.d: Likewise.
	* opcodes/arm-dis.c (neon_opcodes): Add 2 operand sha instructions.
2012-08-24 08:14:40 +00:00
Matthew Gretton-Dann 48adcd8ed5 * gas/config/tc-arm.c (NEON_ENC_TAB): Add sha3op entry.
(do_crypto_3op_1): New function.
	(do_sha1c): Likewise.
	(do_sha1p): Likewise.
	(do_sha1m): Likewise.
	(do_sha1su0): Likewise.
	(do_sha256h): Likewise.
	(do_sha256h2): Likewise.
	(do_sha256su1): Likewise.
	(insns): Add SHA 3 operand instructions.
	* gas/testsuite/gas/arm/armv8-a+crypto.d: Update testcase.
	* gas/testsuite/gas/arm/armv8-a+crypto.s: Likewise.
	* opcodes/arm-dis.c (neon_opcodes): Add SHA 3-operand instructions.
2012-08-24 08:14:04 +00:00
Matthew Gretton-Dann 4f51b4bdbb * gas/config/tc-arm.c (neon_type_mask): Add P64 type.
(type_chk_of_el_type): Handle P64 type.
	(el_type_of_type_chk): Likewise.
	(do_neon_vmull): Handle VMULL.P64.
	* gas/testsuite/gas/arm/armv8-a+crypto.d: Update testcase.
	* gas/testsuite/gas/arm/armv8-a+crypto.s: Likewise.
	* opcodes/arm-dis.c (neon_opcodes): Handle VMULL.P64.
2012-08-24 08:13:24 +00:00
Matthew Gretton-Dann 91ff78946d * gas/config/tc-arm.c (NEON_ENC_TAB): Add aes entry.
(neon_type_mask): Add N_UNT.
	(neon_check_type): Don't always decay typed to untyped sizes.
	(do_crypto_2op_1): New function.
	(do_aese): Likewise.
	(do_aesd): Likewise.
	(do_aesmc.8): Likewise.
	(do_aesimc.8): Likewise.
	(insns): Add AES instructions.
	* gas/testsuite/gas/arm/armv8-a+crypto.d: New testcase.
	* gas/testsuite/gas/arm/armv8-a+crypto.s: Likewise.
	* opcodes/arm-dis.c (neon_opcodes): Add support for AES instructions.
2012-08-24 08:12:45 +00:00
Matthew Gretton-Dann c70a898785 * gas/config/tc-arm.c (el_type_type_check): Add handling for 16-bit
floating point types.
	(do_neon_cvttb_2): New function.
	(do_neon_cvttb_1): Likewise.
	(do_neon_cvtb): Refactor to use do_neon_cvttb_1.
	(do_neon_cvtt): Likewise.
	* gas/testsuite/gas/arm/armv8-a+fp.d: Update testcase.
	* gas/testsuite/gas/arm/armv8-a+fp.s: Likewise.
	* gas/testsuite/gas/arm/half-prec-vfpv3.s: Likewise.
	* opcodes/arm-dis.c (coprocessor_opcodes): Add support for HP/DP
	conversions.
2012-08-24 08:11:44 +00:00
Matthew Gretton-Dann 30bdf75259 * gas/config/tc-arm.c (NEON_ENC_TAB): Add vrint entries.
(neon_cvt_mode): Add neon_cvt_mode_r.
	(do_vrint_1): New function.
	(do_vrint_x): Likewise.
	(do_vrint_z): Likewise.
	(do_vrint_r): Likewise.
	(do_vrint_a): Likewise.
	(do_vrint_n): Likewise.
	(do_vrint_p): Likewise.
	(do_vrint_m): Likewise.
	(insns): Add VRINT instructions.
	* gas/testsuite/gas/arm/armv8-a+fpv5.d: Update testcase.
	* gas/testsuite/gas/arm/armv8-a+fpv5.s: Likewise.
	* gas/testsuite/gas/arm/armv8-a+simdv3.d: Likewise.
	* gas/testsuite/gas/arm/armv8-a+simdv3.s: Likewise.
	* opcodes/arm-dis.c (coprocessor_opcodes): Add VRINT.
	(neon_opcodes): Likewise.
2012-08-24 08:11:13 +00:00
Matthew Gretton-Dann 7e8e678496 * gas/config/tc-arm.c (NEON_ENC_TAB): Add vcvta entry.
(neon_cvt_mode): New enumeration.
	(do_vfp_nsyn_cvt_fpv8): New function.
	(do_neon_cvt_1): Add support for new conversions.
	(do_neon_cvtr): Use neon_cvt_mode enumerator.
	(do_neon_cvt): Likewise.
	(do_neon_cvta): New function.
	(do_neon_cvtn): Likewise.
	(do_neon_cvtp): Likewise.
	(do_neon_cvtm): Likewise.
	(insns): Add new VCVT instructions.
	* gas/testsuite/gas/arm/armv8-a+fp.d: Update testcase.
	* gas/testsuite/gas/arm/armv8-a+fp.s: Likewise.
	* gas/testsuite/gas/arm/armv8-a+simd.d: Likewise.
	* gas/testsuite/gas/arm/armv8-a+simd.s: Likewise.
	* opcodes/arm-dis.c (coprocessor_opcodes): Add support for new VCVT
	variants.
	(neon_opcodes): Likewise.
2012-08-24 08:09:50 +00:00
Matthew Gretton-Dann 73924fbcf8 * gas/config/tc-arm.c (NEON_ENC_TAB): Add vmaxnm, vminnm entries.
(vfp_or_neon_is_neon_bits): Add NEON_CHECK_ARCH8 enumerator.
	(vfp_or_neon_is_neon): Add check for SIMD for ARMv8.
	(do_maxnm): New function.
	(insns): Add vmaxnm, vminnm entries.
	* gas/testsuite/gas/testsuite/gas/armv8-a+fp.d: Update testcase.
	* gas/testsuite/gas/testsuite/gas/armv8-a+fp.s: Likewise.
	* gas/testsuite/gas/testsuite/gas/armv8-a+simd.d: New testcase.
	* gas/testsuite/gas/testsuite/gas/armv8-a+simd.s: Likewise.
	* opcodes/arm-dis.c (coprocessor_opcodes): Add VMAXNM/VMINNM.
	(neon_opcodes): Likewise.
2012-08-24 08:07:36 +00:00
Matthew Gretton-Dann 33399f071c * gas/config/tc-arm.c (NEON_ENC_TAB): Add entries for VSEL.
(NEON_ENC_FPV8_): New define.
	(do_vfp_nsyn_fpv8): New function.
	(do_vsel): Likewise.
	(insns): Add VSEL instructions.
	* gas/testsuite/gas/arm/armv8-a+fp.d: New testcase.
	* gas/testsuite/gas/arm/armv8-a+fp.s: Likewise.
	* opcodes/arm-dis.c (coprocessor_opcodes): Add VSEL.
	(print_insn_coprocessor): Add new %<>c bitfield format
	specifier.
2012-08-24 08:06:36 +00:00
Matthew Gretton-Dann 9eb6c0f132 * gas/config/tc-arm.c (do_rm_rn): New function.
(do_strlex): Likewise.
	(do_t_strlex): Likewise.
	(insns): Add support for LDRA/STRL instructions.
	* gas/testsuite/gas/arm/armv8-a-bad.l: Update testcase.
	* gas/testsuite/gas/arm/armv8-a-bad.s: Likewise.
	* gas/testsuite/gas/arm/armv8-a.d: Likewise.
	* gas/testsuite/gas/arm/armv8-a.s: Likewise.
	* opcodes/arm-dis.c (arm_opcodes): Add LDRA/STRL instructions.
	(thumb32_opcodes): Likewise.
	(print_arm_insn): Add support for %<>T formatter.
2012-08-24 08:03:39 +00:00
Matthew Gretton-Dann 8884b7208b * gas/config/tc-arm.c (do_t_bkpt_hlt1): New function.
(do_t_hlt): New function.
	(do_t_bkpt): Use do_t_bkpt_hlt1.
	(insns): Add HLT.
	* gas/testsuite/gas/arm/armv8-a-bad.l: Update for HLT.
	* gas/testsuite/gas/arm/armv8-a-bad.s: Likewise.
	* gas/testsuite/gas/arm/armv8-a.d: Likewise.
	* gas/testsuite/gas/arm/armv8-a.s: Likewise.
	* opcodes/arm-dis.c (arm_opcodes): Add HLT.
	(thumb_opcodes): Likewise.
2012-08-24 08:02:51 +00:00
Matthew Gretton-Dann b79f7053dd * gas/config/tc-arm.c (insns): Add DCPS instruction.
* gas/testsuite/gas/arm/armv8-a.d: Update.
	* gas/testsuite/gas/arm/armv8-a.s: Likewise.
	* opcodes/arm-dis.c (thumb32_opcodes): Add DCPS instruction.
2012-08-24 08:02:09 +00:00
Matthew Gretton-Dann 53c4b28b4f * gas/config/tc-arm.c (T16_32_TAB): Add _sevl.
(insns): Add SEVL.
	* gas/testsuite/gas/arm/armv8-a.s: New testcase.
	* gas/testsuite/gas/arm/armv8-a.d: Likewise.
	* opcodes/arm-dis.c (arm_opcodes): Add SEVL.
	(thumb_opcodes): Likewise.
	(thumb32_opcodes): Likewise.
2012-08-24 08:01:18 +00:00
Matthew Gretton-Dann e797f7e0b2 * gas/config/tc-arm.c (asm_barrier_opt): Add arch field.
(mark_feature_used): New function.
	(parse_barrier): Check specified option is valid for the
	specified architecture.
	(UL_BARRIER): New macro.
	(barrier_opt_names): Update for new barrier options.
	* gas/testsuite/gas/arm/armv8-a-barrier.s: New testcase.
	* gas/testsuite/gas/arm/armv8-a-barrier-arm.d: Likewise.
	* gas/testsuite/gas/arm/armv8-a-barrier-thumb.d: Likewise.
	* opcodes/arm-dis.c (data_barrier_option): New function.
	(print_insn_arm): Use data_barrier_option.
	(print_insn_thumb32): Use data_barrier_option.
2012-08-24 08:00:20 +00:00
Matthew Gretton-Dann e2efe87d8a * opcodes/arm-dis.c (COND_UNCOND): New constant.
(print_insn_coprocessor): Add support for %u format specifier.
	(print_insn_neon): Likewise.
2012-08-24 07:59:05 +00:00
Nick Clifton d908c8af5a PR binutils/13135
* arm-dis.c: Add necessary casts for printing integer values.
	Use %s when printing string values.
	* hppa-dis.c: Likewise.
	* m68k-dis.c: Likewise.
	* microblaze-dis.c: Likewise.
	* mips-dis.c: Likewise.
	* ppc-dis.c: Likewise.
	* sparc-dis.c: Likewise.

	* dis-asm.h (fprintf_ftype): Add ATTRIBUTE_FPTR_PRINTF_2.
2012-07-24 12:56:47 +00:00
Nick Clifton 101af531fe * arm-dis.c (arm_opcodes): Don't disassemble STMFD/LDMIA sp!, {reg}
to PUSH/POP {reg}.

	* binutils-all/arm/objdump.exp:
	STMFD/LDMIA sp!, {reg} don't disassemble to PUSH/POP {reg} any longer.

	* gas/arm/stm-ldm.d: STMFD/LDMIA sp!, {reg} don't disassemble to
	PUSH/POP {reg} any longer.  Some new test cases have been added as well.
	* gas/arm/stm-ldm.s: Likewise.
2012-05-16 10:53:49 +00:00
Nick Clifton 6750a3a775 PR binutils/14006
* arm-dis.c (print_insn): Fix detection of instruction mode in
	files containing multiple executable sections.
2012-05-11 09:41:21 +00:00
Julian Brown a415b1cd63 Jie Zhang <jie@codesourcery.com>
Julian Brown  <julian@codesourcery.com>

    gas/
    * config/tc-arm.c (parse_shifter_operand): Fix handling
    of explicit rotation.
    (encode_arm_shifter_operand): Likewise.

    gas/testsuite/
    * gas/arm/adrl.d: Adjust.
    * gas/arm/immed2.d: New test.
    * gas/arm/immed2.s: New test.

    ld/testsuite/
    * ld-arm/cortex-a8-fix-b-plt.d: Adjust.
    * ld-arm/cortex-a8-fix-bcc-plt.d: Adjust.
    * ld-arm/cortex-a8-fix-bl-plt.d: Adjust.
    * ld-arm/cortex-a8-fix-bl-rel-plt.d: Adjust.
    * ld-arm/cortex-a8-fix-blx-plt.d: Adjust.
    * ld-arm/ifunc-1.dd: Adjust.
    * ld-arm/ifunc-2.dd: Adjust.
    * ld-arm/ifunc-3.dd: Adjust.
    * ld-arm/ifunc-4.dd: Adjust.
    * ld-arm/ifunc-5.dd: Adjust.
    * ld-arm/ifunc-6.dd: Adjust.
    * ld-arm/ifunc-7.dd: Adjust.
    * ld-arm/ifunc-8.dd: Adjust.
    * ld-arm/ifunc-9.dd: Adjust.
    * ld-arm/ifunc-10.dd: Adjust.
    * ld-arm/ifunc-14.dd: Adjust.
    * ld-arm/ifunc-15.dd: Adjust.
    * ld-arm/ifunc-16.dd: Adjust.

    opcodes/
    * arm-dis.c (print_insn_arm): Explicitly specify rotation
    if needed.
2011-10-18 14:41:55 +00:00
Nick Clifton 1b93226d63 * arm-dis.c (print_insn_arm): Revert previous, undocumented,
accidental change.
2011-07-12 08:45:45 +00:00
Nick Clifton 5d73b1f18f PR binutils/12329
* avr-dis.c (avr_operand): Fix disassembly of ELPM, LPM and SPM
	insns using post-increment addressing.

	* avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
2011-07-01 16:11:27 +00:00
Nick Clifton f8b960bc80 PR binutils/12752
* arm-dis.c (print_insn_coprocessor): Use bfd_vma type for
	computing address offsets.
	(print_arm_address): Likewise.
	(print_insn_arm): Likewise.
	(print_insn_thumb16): Likewise.
	(print_insn_thumb32): Likewise.
2011-06-03 10:04:03 +00:00
Nathan Sidwell 26d97720ed gas/
* config/tc-arm.c (parse_address_main): Handle -0 offsets.
	(encode_arm_addr_mode_2): Set default sign of zero here ...
	(encode_arm_addr_mode_3): ... and here.
	(encode_arm_cp_address): ... and here.
	(md_apply_fix): Use default sign of zero here.

	gas/testsuite/
	* gas/arm/inst.d: Adjust for signed zero offsets.
	* gas/arm/ldst-offset0.d: New test.
	* gas/arm/ldst-offset0.s: New test.
	* gas/arm/offset-1.d: New test.
	* gas/arm/offset-1.s: New test.

	ld/testsuite/
	Adjust tests for zero offset formatting.
	* ld-arm/cortex-a8-fix-bcc-plt.d: Adjust.
	* ld-arm/farcall-arm-arm-pic-veneer.d: Adjust.
	* ld-arm/farcall-arm-thumb.d: Adjust.
	* ld-arm/farcall-group-size2.d: Adjust.
	* ld-arm/farcall-group.d: Adjust.
	* ld-arm/farcall-mix.d: Adjust.
	* ld-arm/farcall-mix2.d: Adjust.
	* ld-arm/farcall-mixed-lib-v4t.d: Adjust.
	* ld-arm/farcall-mixed-lib.d: Adjust.
	* ld-arm/farcall-thumb-arm-blx-pic-veneer.d: Adjust.
	* ld-arm/farcall-thumb-arm-pic-veneer.d: Adjust.
	* ld-arm/farcall-thumb-thumb.d: Adjust.
	* ld-arm/ifunc-10.dd: Adjust.
	* ld-arm/ifunc-3.dd: Adjust.
	* ld-arm/ifunc-4.dd: Adjust.
	* ld-arm/ifunc-5.dd: Adjust.
	* ld-arm/ifunc-6.dd: Adjust.
	* ld-arm/ifunc-7.dd: Adjust.
	* ld-arm/ifunc-8.dd: Adjust.
	* ld-arm/jump-reloc-veneers-long.d: Adjust.
	* ld-arm/tls-longplt-lib.d: Adjust.
	* ld-arm/tls-thumb1.d: Adjust.

	opcodes/
	* arm-dis.c (print_insn_coprocessor): Explicitly print #-0
	as address offset.
	(print_arm_address): Likewise. Elide positive #0 appropriately.
	(print_insn_arm): Likewise.
2011-06-02 15:32:10 +00:00
Nick Clifton cc643b88f1 Fix spelling mistakes. 2011-06-02 13:43:24 +00:00
Nick Clifton 00bbc0bdc6 * config/tc-arm.c (v7m_psrs): Revert previous delta.
* gas/arm/mrs-msr-thumb-v7e-m.s: Restore name of basepri_max
	register.
	* gas/arm/mrs-msr-thumb-v7e-m.d: Likewise.
	* gas/arm/arch7.d: Likewise.
	* gas/arm/arch7.s: Likewise.

	* arm-dis.c: Revert previous reversion.
2011-04-19 07:44:12 +00:00
Nick Clifton ac7f631be1 * gas/arm/arch7.s: Fix typo basepri_max should be basepri_mask.
* gas/arm/mrs-msr-thumb-v7e-m.s: Likewise.
	* gas/arm/arch7.d: Update expected disassembly.
	* gas/arm/attr-march-armv7.d: Remove Microcontroller tag.
	* gas/arm/blx-bad.d: Only run for ELF based targets.
	* gas/arm/mrs-msr-thumb-v6t2.d: Likewise.
	* gas/arm/vldm-arm.d: Likewise.
	* gas/arm/mrs-msr-thumb-v7-m.d: Likewise.
	Remove qualifiers from PSR and IAPSR regsiter names.
	* gas/arm/mrs-msr-thumb-v7e-m.d: Likewise.
	* gas/arm/thumb2_bcond.d: Update expected disassembly to allow for
	relaxing of branch insns.
	* gas/arm/thumb32.d: Fix whitespace problems in disassembly.

	* config/tc-arm.c (parse_psr): Use selected_cpu not cpu_variant to
	detect M-profile targets.
	(do_t_swi): Exclude v7 and higher variants from arm_ext_os test.
	(v7m_psrs): Fix typo: basepri_max should be basepri_mask.

	* arm-dis.c (psr_name): Revert previous delta.

	* arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
2011-04-19 07:27:32 +00:00
Nick Clifton 32a946987b PR binutils/12534
* arm-dis.c (thumb32_opcodes): Add %L suffix to LDRD and STRD insn
	patterns.
	(print_insn_thumb32): Handle %L.

	* gas/arm/thumb32.s: Add PC relative LDRD and STRD insns.
	* gas/arm/thumb32.l: Update expected output.
	* gas/arm/thumb32.d: Update expected disassembly.
2011-04-12 16:01:48 +00:00
Julian Brown d2cd120565 gas/
* config/tc-arm.c (parse_psr): Add LHS argument. Improve support
    for *APSR bitmasks.
    (operand_parse_code): Replace OP_PSR with OP_wPSR and OP_rPSR.
    Remove OP_RVC_PSR.
    (parse_operands): Likewise.
    (do_mrs): Tweak error message for constraint.
    (do_t_mrs): Update constraints for changes to APSR support.
    (do_t_msr): Likewise. Don't set PSR_f flag here.
    (psrs): Remove "g", "nzcvq", "nzcvqg".
    (insns): Tweak entries for msr and mrs instructions.

    opcodes/
    * arm-dis.c (psr_name): Fix typo for BASEPRI_MAX.
    (print_insn_thumb32): Add APSR bitmask support.

    gas/testsuite/
    * gas/arm/mrs-msr-thumb-v7-m.s: New.
    * gas/arm/mrs-msr-thumb-v7-m.d: New.
    * gas/arm/mrs-msr-thumb-v7-m-bad.d: New.
    * gas/arm/mrs-msr-thumb-v7-m-bad.l: New.
    * gas/arm/mrs-msr-thumb-v7-m-bad.s: New.
    * gas/arm/mrs-msr-thumb-v7e-m.d: New.
    * gas/arm/mrs-msr-thumb-v7e-m.s: New.
    * gas/arm/mrs-msr-arm-v7-a-bad.d: New.
    * gas/arm/mrs-msr-arm-v7-a-bad.l: New.
    * gas/arm/mrs-msr-arm-v7-a-bad.s: New.
    * gas/arm/mrs-msr-arm-v7-a.d: New.
    * gas/arm/mrs-msr-arm-v7-a.s: New.
    * gas/arm/mrs-msr-arm-v6.d: New.
    * gas/arm/mrs-msr-arm-v6.s: New.
    * gas/arm/mrs-msr-thumb-v6t2.d: New.
    * gas/arm/mrs-msr-thumb-v6t2.s: New.
    * gas/arm/arch7.d: Fix typo in disassembly for BASEPRI_MAX,
    bitmasks for IAPSR etc.
    * gas/arm/arch7.s: Specify bitmask for APSR writes.
    * gas/arm/archv6m.s: Likewise.
    * msr-imm-bad.l: Tweak expected disassembly in error message.
    * msr-reg-bad.l: Likewise.
    * msr-imm.d: Tweak expected disassembly.
    * msr-reg.d: Likewise.
    * msr-reg-thumb.d: Likewise.
    * msr-imm.s: Specify bitmask on APSR writes.
    * msr-reg.s: Add comment about deprecated usage.
2011-04-11 18:49:06 +00:00
Paul Brook 1fbaefec00 2011-04-07 Paul Carroll<pcarroll@codesourcery.com>
opcodes/
	* arm-dis.c (print_insn): init vars moved into private_data structure.

	binutils/testsuite/
	* binutils-all/arm/simple.s: Demo issue with objdump with
	multiple input files
	* binutils-all/arm/objdump.exp: added new ARM test case code
2011-04-08 11:42:19 +00:00
Richard Sandiford 34e77a920a include/elf/
* arm.h (R_ARM_IRELATIVE): New relocation.

bfd/
	* reloc.c (BFD_RELOC_ARM_IRELATIVE): New relocation.
	* bfd-in2.h: Regenerate.
	* elf32-arm.c (elf32_arm_howto_table_2): Rename existing definition
	to elf32_arm_howto_table_3 and replace with a single R_ARM_IRELATIVE
	entry.
	(elf32_arm_howto_from_type): Update accordingly.
	(elf32_arm_reloc_map): Map BFD_RELOC_ARM_IRELATIVE to R_ARM_IRELATIVE.
	(elf32_arm_reloc_name_lookup): Handle elf32_arm_howto_table_3.
	(arm_plt_info): New structure, split out from elf32_arm_link_hash_entry
	with an extra noncall_refcount field.
	(arm_local_iplt_info): New structure.
	(elf_arm_obj_tdata): Add local_iplt.
	(elf32_arm_local_iplt): New accessor macro.
	(elf32_arm_link_hash_entry): Replace plt_thumb_refcount,
	plt_maybe_thumb_refcount and plt_got_offset with an arm_plt_info.
	Change tls_type to a bitfield and add is_iplt.
	(elf32_arm_link_hash_newfunc): Update accordingly.
	(elf32_arm_allocate_local_sym_info): New function.
	(elf32_arm_create_local_iplt): Likewise.
	(elf32_arm_get_plt_info): Likewise.
	(elf32_arm_plt_needs_thumb_stub_p): Likewise.
	(elf32_arm_get_local_dynreloc_list): Likewise.
	(create_ifunc_sections): Likewise.
	(elf32_arm_copy_indirect_symbol): Update after the changes to
	elf32_arm_link_hash_entry.  Assert the is_iplt has not yet been set.
	(arm_type_of_stub): Add an st_type argument.  Use elf32_arm_get_plt_info
	to get PLT information.  Assert that all STT_GNU_IFUNC references
	are turned into PLT references.
	(arm_build_one_stub): Pass the symbol type to
	elf32_arm_final_link_relocate.
	(elf32_arm_size_stubs): Pass the symbol type to arm_type_of_stub.
	(elf32_arm_allocate_irelocs): New function.
	(elf32_arm_add_dynreloc): In static objects, use .rel.iplt for
	all R_ARM_IRELATIVE.
	(elf32_arm_allocate_plt_entry): New function.
	(elf32_arm_populate_plt_entry): Likewise.
	(elf32_arm_final_link_relocate): Add an st_type parameter.
	Set srelgot to null for static objects.  Use separate variables
	to record which st_value and st_type should be used when generating
	a dynamic relocation.  Use elf32_arm_get_plt_info to find the
	symbol's PLT information, setting has_iplt_entry, splt,
	plt_offset and gotplt_offset accordingly.  Check whether
	STT_GNU_IFUNC symbols should resolve to an .iplt entry, and change
	the relocation target accordingly.  Broaden assert to include
	.iplts.  Don't set sreloc for static relocations.  Assert that
	we only generate dynamic R_ARM_RELATIVE relocations for R_ARM_ABS32
	and R_ARM_ABS32_NOI.  Generate R_ARM_IRELATIVE relocations instead
	of R_ARM_RELATIVE relocations if the target is an STT_GNU_IFUNC
	symbol.  Pass the symbol type to arm_type_of_stub.  Conditionally
	resolve GOT references to the .igot.plt entry.
	(elf32_arm_relocate_section): Update the call to
	elf32_arm_final_link_relocate.
	(elf32_arm_gc_sweep_hook): Use elf32_arm_get_plt_info to get PLT
	information.  Treat R_ARM_REL32 and R_ARM_REL32_NOI as call
	relocations in shared libraries and relocatable executables.
	Count non-call PLT references.  Use elf32_arm_get_local_dynreloc_list
	to get the list of dynamic relocations for a local symbol.
	(elf32_arm_check_relocs): Always create ifunc sections.  Set isym
	at the same time as setting h.  Use elf32_arm_allocate_local_sym_info
	to allocate local symbol information.  Treat R_ARM_REL32 and
	R_ARM_REL32_NOI as call relocations in shared libraries and
	relocatable executables.  Record PLT information for local
	STT_GNU_IFUNC functions as well as global functions.   Count
	non-call PLT references.  Use elf32_arm_get_local_dynreloc_list
	to get the list of dynamic relocations for a local symbol.
	(elf32_arm_adjust_dynamic_symbol): Handle STT_GNU_IFUNC symbols.
	Don't remove STT_GNU_IFUNC PLTs unless all references have been
	removed.  Update after the changes to elf32_arm_link_hash_entry.
	(allocate_dynrelocs_for_symbol): Decide whether STT_GNU_IFUNC PLT
	entries should live in .plt or .iplt.  Check whether the .igot.plt
	and .got entries can be combined.  Use elf32_arm_allocate_plt_entry
	to allocate .plt and .(i)got.plt entries.  Detect which .got
	entries will need R_ARM_IRELATIVE relocations and use
	elf32_arm_allocate_irelocs to allocate them.  Likewise other
	non-.got dynamic relocations.
	(elf32_arm_size_dynamic_sections): Allocate .iplt, .igot.plt
	and dynamic relocations for local STT_GNU_IFUNC symbols.
	Check whether the .igot.plt and .got entries can be combined.
	Detect which .got entries will need R_ARM_IRELATIVE relocations
	and use elf32_arm_allocate_irelocs to allocate them.  Use stashed
	section pointers intead of strcmp checks.  Handle iplt and igotplt.
	(elf32_arm_finish_dynamic_symbol): Use elf32_arm_populate_plt_entry
	to fill in .plt, .got.plt and .rel(a).plt entries.  Point
	STT_GNU_IFUNC symbols at an .iplt entry if non-call relocations
	resolve to it.
	(elf32_arm_output_plt_map_1): New function, split out from
	elf32_arm_output_plt_map.  Handle .iplt entries.  Use
	elf32_arm_plt_needs_thumb_stub_p.
	(elf32_arm_output_plt_map): Call it.
	(elf32_arm_output_arch_local_syms): Add mapping symbols for
	local .iplt entries.
	(elf32_arm_swap_symbol_in): Handle Thumb STT_GNU_IFUNC symbols.
	(elf32_arm_swap_symbol_out): Likewise.
	(elf32_arm_add_symbol_hook): New function.
	(elf_backend_add_symbol_hook): Define for all targets.

opcodes/
	* arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.

gas/
	* config/tc-arm.c (md_pcrel_from_section): Use S_FORCE_RELOC to
	determine whether a relocation is needed.
	(md_apply_fix, arm_apply_sym_value): Likewise.

ld/testsuite/
	* ld-arm/ifunc-1.s, ld-arm/ifunc-1.dd, ld-arm/ifunc-1.gd,
	ld-arm/ifunc-1.rd, ld-arm/ifunc-2.s, ld-arm/ifunc-2.dd,
	ld-arm/ifunc-2.gd, ld-arm/ifunc-2.rd, ld-arm/ifunc-3.s,
	ld-arm/ifunc-3.dd, ld-arm/ifunc-3.gd, ld-arm/ifunc-3.rd,
	ld-arm/ifunc-4.s, ld-arm/ifunc-4.dd, ld-arm/ifunc-4.gd,
	ld-arm/ifunc-4.rd, ld-arm/ifunc-5.s, ld-arm/ifunc-5.dd,
	ld-arm/ifunc-5.gd, ld-arm/ifunc-5.rd, ld-arm/ifunc-6.s,
	ld-arm/ifunc-6.dd, ld-arm/ifunc-6.gd, ld-arm/ifunc-6.rd,
	ld-arm/ifunc-7.s, ld-arm/ifunc-7.dd, ld-arm/ifunc-7.gd,
	ld-arm/ifunc-7.rd, ld-arm/ifunc-8.s, ld-arm/ifunc-8.dd,
	ld-arm/ifunc-8.gd, ld-arm/ifunc-8.rd, ld-arm/ifunc-9.s,
	ld-arm/ifunc-9.dd, ld-arm/ifunc-9.gd, ld-arm/ifunc-9.rd,
	ld-arm/ifunc-10.s, ld-arm/ifunc-10.dd, ld-arm/ifunc-10.gd,
	ld-arm/ifunc-10.rd, ld-arm/ifunc-11.s, ld-arm/ifunc-11.dd,
	ld-arm/ifunc-11.gd, ld-arm/ifunc-11.rd, ld-arm/ifunc-12.s,
	ld-arm/ifunc-12.dd, ld-arm/ifunc-12.gd, ld-arm/ifunc-12.rd,
	ld-arm/ifunc-13.s, ld-arm/ifunc-13.dd, ld-arm/ifunc-13.gd,
	ld-arm/ifunc-13.rd, ld-arm/ifunc-14.s, ld-arm/ifunc-14.dd,
	ld-arm/ifunc-14.gd, ld-arm/ifunc-14.rd, ld-arm/ifunc-15.s,
	ld-arm/ifunc-15.dd, ld-arm/ifunc-15.gd, ld-arm/ifunc-15.rd,
	ld-arm/ifunc-16.s, ld-arm/ifunc-16.dd, ld-arm/ifunc-16.gd,
	ld-arm/ifunc-16.rd, ld-arm/ifunc-dynamic.ld,
	ld-arm/ifunc-static.ld: New tests.
	* ld-arm/farcall-group.d, ld-arm/farcall-group-size2.d,
	ld-arm/farcall-mixed-lib-v4t.d, ld-arm/farcall-mixed-lib.d: Update
	for new stub hashes.
	* ld-arm/arm-elf.exp: Run them.
2011-03-14 16:04:16 +00:00
Richard Sandiford 35fc36a8d6 include/elf/
* internal.h (elf_internal_sym): Add st_target_internal.
	* arm.h (arm_st_branch_type): New enum.
	(ARM_SYM_BRANCH_TYPE): New macro.

bfd/
	* elf-bfd.h (elf_link_hash_entry): Add target_internal.
	* elf.c (swap_out_syms): Set st_target_internal for each
	Elf_Internal_Sym.
	* elfcode.h (elf_swap_symbol_in): Likewise.
	* elf32-i370.c (i370_elf_finish_dynamic_sections): Likewise.
	* elf32-sh-symbian.c (sh_symbian_relocate_section): Likewise.
	* elf64-sparc.c (elf64_sparc_output_arch_syms): Likewise.
	* elfxx-sparc.c (_bfd_sparc_elf_size_dynamic_sections): Likewise.
	* elflink.c (elf_link_output_extsym): Likewise.
	(bfd_elf_final_link): Likewise.
	(elf_link_add_object_symbols): Copy st_target_internal
	to the hash table if we see a definition.
	(_bfd_elf_copy_link_hash_symbol_type): Copy target_internal.
	* elf32-arm.c (elf32_arm_stub_hash_entry): Replace st_type with
	a branch_type field.
	(a8_erratum_fix, a8_erratum_reloc): Likewise.
	(arm_type_of_stub): Replace actual_st_type with an
	actual_branch_type parameter.
	(arm_build_one_stub): Use branch types rather than st_types to
	determine the type of branch.
	(cortex_a8_erratum_scan): Likewise.
	(elf32_arm_size_stubs): Likewise.
	(bfd_elf32_arm_process_before_allocation): Likewise.
	(allocate_dynrelocs_for_symbol): Likewise.
	(elf32_arm_finish_dynamic_sections): Likewise.
	(elf32_arm_final_link_relocate): Replace sym_flags parameter with
	a branch_type parameter.
	(elf32_arm_relocate_section): Update call accordingly.
	(elf32_arm_adjust_dynamic_symbol): Don't check STT_ARM_TFUNC.
	(elf32_arm_output_map_sym): Initialize st_target_internal.
	(elf32_arm_output_stub_sym): Likewise.
	(elf32_arm_symbol_processing): Delete.
	(elf32_arm_swap_symbol_in): Convert STT_ARM_TFUNCs into STT_FUNCs.
	Use st_target_internal to record the branch type.
	(elf32_arm_swap_symbol_out): Use st_target_internal to test for
	Thumb functions.
	(elf32_arm_is_function_type): Delete.
	(elf_backend_symbol_processing): Likewise.
	(elf_backend_is_function_type): Likewise.

gas/
	* config/tc-arm.c (arm_adjust_symtab): Set the branch type
	for Thumb symbols.

ld/
	* emultempl/armelf.em (gld${EMULATION_NAME}_finish): Check
	eh->target_internal.

opcodes/
	* arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC.
	Use branch types instead.
	(print_insn): Likewise.
2011-03-14 15:55:04 +00:00