Commit Graph

2138 Commits

Author SHA1 Message Date
Yufeng Zhang 87b8eed7fb gas/testsuite/
* gas/aarch64/msr.s: Add tests.
	* gas/aarch64/msr.d: Update.

include/opcode

	* aarch64.h (aarch64_pstatefields): Change element type to
	aarch64_sys_reg.

opcodes/

	* aarch64-opc.c (aarch64_pstatefields): Update.
2013-11-20 11:22:53 +00:00
Catherine Moore 8f8c3854e0 2013-11-19 Catherine Moore <clm@codesourcery.com>
* micromips-opc.c (LM): Define.
	(micromips_opcodes): Add LM to load instructions.
	* mips-opc.c (prefe): Add LM attribute.
2013-11-19 05:25:32 -08:00
Yufeng Zhang a203d9b72f Revert "Add support for AArch64 trace unit registers."
This reverts commit 75468c93c1.
2013-11-18 11:42:41 +00:00
Yufeng Zhang 75468c93c1 gas/
* config/tc-aarch64.c (set_other_error): New function.
	(parse_sys_reg): Add new parameter 'sys_reg' and if non-NULL set
	the variable to which it points with 'o'.
	(parse_operands): Update; check for write to read-only system
	registers or read from write-only ones.

gas/testsuite/

	* gas/aarch64/diagnostic.s: Add tests.
	* gas/aarch64/diagnostic.l: Update.
	* gas/aarch64/tracereg-illegal.d: New file.
	* gas/aarch64/tracereg-illegal.l: Ditto.
	* gas/aarch64/tracereg-illegal.s: Ditto.
	* gas/aarch64/tracereg.d: Ditto.
	* gas/aarch64/tracereg.s: Ditto.

include/opcode

	* aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
	(aarch64_sys_reg_writeonly_p): Ditto.

opcodes/

	* aarch64-opc.c (CPENT): New define.
	(F_READONLY, F_WRITEONLY): Likewise.
	(aarch64_sys_regs): Add trace unit registers.
	(aarch64_sys_reg_readonly_p): New function.
	(aarch64_sys_reg_writeonly_p): Ditto.
2013-11-15 23:40:34 +00:00
Maciej W. Rozycki caeba11c83 MIPS/opcodes: Add MFCR and MTCR data dependencies
* mips-opc.c (mips_builtin_opcodes): Add RD_2 to "mfcr" and
	"mtcr".
2013-11-15 21:57:11 +00:00
Catherine Moore b83a9376e9 Fix ChangeLog entries from earlier commit. 2013-11-11 15:34:48 -08:00
Catherine Moore 67dc82bc51 2013-11-11 Catherine Moore <clm@codesourcery.com>
gas/
	* config/mips/tc-mips.c (convert_reg_type): Use
	INSN_LOAD_MEMORY instead of INSN_LOAD_MEMORY_DELAY.
	(reg_needs_delay): Likewise.
	(insns_between): Likewise.

	include/
	* opcode/mips.h (INSN_LOAD_MEMORY_DELAY): Rename to...
	(INSN_LOAD_MEMORY): ...this.

	opcodes/
	* mips-dis.c (print_insn_mips): Use
	INSN_LOAD_MEMORY instead of INSN_LOAD_MEMORY_DELAY.
	(print_insn_micromips): Likewise.
	* mips-opc.c (LDD): Remove.
	(CLD): Include INSN_LOAD_MEMORY.
	(LM): New.
	(mips_builtin_opcodes): Use LM instead of LDD.
        Add LM to load instructions.
2013-11-11 08:03:47 -08:00
H.J. Lu d56da83e58 Remove CpuNop from CPU_K6_2_FLAGS
PR gas/16140
	* i386-gen.c (cpu_flag_init): Remove CpuNop from CPU_K6_2_FLAGS.
	* i386-init.h: Regenerated.
2013-11-08 09:42:08 -08:00
Yufeng Zhang 49eec19300 gas/
* config/tc-aarch64.c (parse_sys_reg): Update to use aarch64_sys_reg;
	call aarch64_sys_reg_deprecated_p and warn about the deprecated
	system registers.

gas/testsuite/

	* gas/aarch64/deprecated.d: New file.
	* gas/aarch64/deprecated.l: New file.
	* gas/aarch64/deprecated.s: New file.
	* gas/aarch64/sysreg-1.s: Add tests.
	* gas/aarch64/sysreg-1.d: Add tests.

include/opcode/

	* aarch64.h (aarch64_sys_reg): New typedef.
	(aarch64_sys_regs): Change to define with the new type.
	(aarch64_sys_reg_deprecated_p): Declare.

opcodes/

	* aarch64-opc.c (F_DEPRECATED): New macro.
	(aarch64_sys_regs): Update; flag "spsr_svc" and "spsr_hyp" with
	F_DEPRECATED.
	(aarch64_print_operand): Call aarch64_sys_reg_deprecated_p on
	AARCH64_OPND_SYSREG.
2013-11-05 20:54:22 +00:00
Yufeng Zhang 68a6428382 gas/
* config/tc-aarch64.c (parse_operands): Handle AARCH64_OPND_COND1.

gas/testsuite/

	* gas/aarch64/alias.s: Add tests.
	* gas/aarch64/alias.d: Update.
	* gas/aarch64/no-aliases.d: Update.
	* gas/aarch64/diagnostic.s: Add tests.
	* gas/aarch64/diagnostic.l: Update.
	* gas/aarch64/illegal.s: Add tests.
	* gas/aarch64/illegal.l: Update.

include/opcode/

	* aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
	(enum aarch64_opnd): Add AARCH64_OPND_COND1.

opcodes/

	* aarch64-dis.c (convert_ubfm_to_lsl): Check for cond != '111x'.
	(convert_from_csel): Likewise.
	* aarch64-opc.c (operand_general_constraint_met_p): Handle
	AARCH64_OPND_CLASS_COND and AARCH64_OPND_COND1.
	(aarch64_print_operand): Handle AARCH64_OPND_COND1.
	* aarch64-tbl.h (aarch64_opcode_table): Use COND1 instead of
	COND for cinc, cset, cinv, csetm and cneg.
	(AARCH64_OPERANDS): Add entry for AARCH64_OPND_COND1.
	* aarch64-asm-2.c: Re-generated.
	* aarch64-dis-2.c: Ditto.
	* aarch64-opc-2.c: Ditto.
2013-11-05 20:50:18 +00:00
Yufeng Zhang 4e50d5f863 opcodes/
* aarch64-opc.c (set_syntax_error): New function.
	(operand_general_constraint_met_p): Replace set_other_error
	with set_syntax_error.

gas/testsuite/

	* gas/aarch64/diagnostic.s: Add tests of ldp/stp.
	* gas/aarch64/diagnostic.l: Update.
2013-11-05 20:46:24 +00:00
Andreas Arnez 7d4a7d107a S/390: Disassemble 31-bit binaries with "zarch" opcode set by default
Currently the disassembler for s390 (by default) assumes that a 31-bit
binary was compiled in "ESA" mode -- and then only disassembles a
limited opcode set.  The change upgrades the default to the full "zarch"
opcode set even for 31-bit binaries.

opcodes/
	* s390-dis.c (init_disasm): Default to full 'zarch' opcode
	availability even for 31-bit programs.
2013-10-30 18:04:32 +01:00
Ramana Radhakrishnan 8518117318 Fix neon vshll disassembly.
opcodes/
2013-10-15  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

	* arm-dis.c (neon_opcodes): Adjust print string for vshll.

gas/testsuite/
2013-10-15  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

	* gas/arm/neon-cov.d: Adjust output.
2013-10-15 13:30:40 +00:00
Chao-ying Fu 4edbb8e35a 2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
* micromips-opc.c (decode_micromips_operand): Add +T, +U, +V, +W,
	+d, +e, +h, +k, +l, +n, +o, +u, +v, +w, +x,
	+~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
	(MSA): New define.
	(MSA64): New define.
	(micromips_opcodes): Add MSA instructions.
	* mips-dis.c (msa_control_names): New array.
	(mips_abi_choice): Add ASE_MSA to mips32r2.
	Remove ASE_MDMX from mips64r2.
	Add ASE_MSA and ASE_MSA64 to mips64r2.
	(parse_mips_dis_option): Handle -Mmsa.
	(print_reg): Handle cases for OP_REG_MSA and OP_REG_MSA_CTRL.
	(print_insn_arg): Handle cases for OP_IMM_INDEX and OP_REG_INDEX.
	(print_mips_disassembler_options): Print -Mmsa.
	* mips-opc.c (decode_mips_operand): Add +T, +U, +V, +W, +d, +e, +h, +k,
	+l, +n, +o, +u, +v, +w, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
	(MSA): New define.
	(MSA64): New define.
	(mips_builtin_op): Add MSA instructions.
2013-10-14 18:58:15 +00:00
Sandra Loosemore ae335a4e26 2013-10-13 Sandra Loosemore <sandra@codesourcery.com>
opcodes/
	* nios2-opc.c (nios2_builtin_reg): Use "sstatus" rather than "ba"
	as the primary name of r30.

	gas/
	* config/tc-nios2.c (nios2_consume_arg): Make the "ba" warning
	also test/refer to "sstatus".  Reformat the warning message.

	gas/testsuite/
	* gas/nios2/warn_nobreak.l: Update text of warning messages.
	* gas/nios2/registers.s: Use "sstatus" rather than "ba"
	as the primary name of r30.
	* gas/nios2/registers.d: Likewise.
2013-10-14 00:42:28 +00:00
H.J. Lu 6c75cc62a3 Only allow 32-bit/64-bit registers for bndcl/bndcu/bndcn
gas/testsuite/

	* gas/i386/mpx.s: Remove bndcl/bndcu/bndcn tests with AX.
	* gas/i386/x86-64-mpx.s: Likwise.

	* gas/i386/mpx.d: Updated.
	* gas/i386/x86-64-mpx.d: Likewise.

opcodes/

	* i386-dis.c (intel_operand_size): Move v_bnd_mode alongside the
	default case.
	(OP_E_register): Move v_bnd_mode alongside m_mode.
	* i386-opc.tbl (bndcl, bndcu, bndcn): Split 32- and 64-bit variants.
	Drop Reg16 and Disp16. Add NoRex64.
	(bndmk, bndmov, bndldx, bndstx): Drop Disp16.
	* i386-tbl.h: Re-generate.
2013-10-12 15:57:07 +00:00
Sean Keys 0e1c243401 * Removed short_hand field from opcode table and
refactored assembler/disassember accordingly.
     Testsuite checkout OK.
2013-10-11 04:55:42 +00:00
Roland McGrath 9ce09ba2d7 opcodes/
* i386-dis.c (oappend_maybe_intel): New function.
	(OP_ST, OP_STi, append_seg, OP_I, OP_I64, OP_sI, OP_ESreg): Use it.
	(OP_C, OP_T, CMP_Fixup, OP_EX_VexImmW): Likewise.
	(VCMP_Fixup, VPCMP_Fixup, PCLMUL_Fixup): Likewise.
2013-10-11 00:58:29 +00:00
Roland McGrath 2b4e983c39 opcodes/
* cr16-opc.c (REG): Cast NAME to 'reg' enum type to suppress
	possible compiler warnings when the union's initializer is
	actually meant for the 'preg' enum typed member.
	* crx-opc.c (REG): Likewise.
2013-10-10 17:43:37 +00:00
Roland McGrath 7903e53098 opcodes/
* v850-dis.c (v850_cacheop_codes, v850_prefop_codes):
	Remove duplicate const qualifier.
2013-10-10 17:19:49 +00:00
Jan Beulich 79e0e31dc9 opcodes/
2013-10-08  Jan Beulich <jbeulich@suse.com>

	* i386-opc.tbl (invlpg): Use Anysize instead of Unspecified.
	(clflush): Use Anysize instead of Byte|Unspecified.
	(prefetch*): Likewise.
	* i386-tbl.h: Re-generate.
2013-10-08 15:12:59 +00:00
Chao-ying Fu 45099dfad2 2013-10-07 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
* micromips-opc.c (micromips_opcodes): Fix dmfgc0 and dmtgc0.
2013-10-07 18:02:47 +00:00
H.J. Lu 916fae9135 Add Size64 to movq/vmovq with Reg64 operand
* i386-opc.tbl: Add Size64 to movq/vmovq with Reg64 operand.
	* i386-init.h: Regenerated.
2013-09-30 17:48:11 +00:00
Saravanan Ekanathan c7b0bd56ce Add AMD bdver4 support.
gas/
	* config/tc-i386.c (cpu_arch): Add CPU_BDVER4_FLAGS.
	* doc/c-i386.texi: Add -march=bdver4 option.

gas/testsuite/
	* gas/i386/i386.exp: Run bdver4 test cases.
	* gas/i386/nops-1-bdver4.d: New.
	* gas/i386/arch-10-bdver4.d: New.
	* gas/i386/x86-64-nops-1-bdver4.d: New.
	* gas/i386/x86-64-arch-2-bdver4.d: New.

opcodes/
	* i386-gen.c (cpu_flag_init): Add CPU_BDVER4_FLAGS.
	* i386-init.h: Regenerated.
2013-09-30 17:02:07 +00:00
Alan Modra cc9afea3e4 * libtool.m4 (_LT_ENABLE_LOCK <ld -m flags>): Remove non-canonical
ppc host match.  Support little-endian powerpc linux hosts.
Regenerate binutils configure files.
2013-09-20 09:51:25 +00:00
Richard Sandiford e3f9e85275 opcodes/
* s390-opc.txt (clih): Make the immediate unsigned.

gas/testsuite/
	* gas/s390/zarch-z196.s, gas/s390/zarch-z196.d: Test CLIH with
	4000000000.
2013-09-17 09:02:37 +00:00
Nick Clifton 74db7efbe3 PR gas/15914
* config/tc-arm.c (T16_32_TAB): Add _udf.
	(do_t_udf): New function.
	(insns): Add "udf".

	* gas/arm/udf-bad.s: New file.
	* gas/arm/udf-bad.d: New file.
	* gas/arm/udf-bad.l: New file.
	* gas/arm/udf.s: New file.
	* gas/arm/udf.d: New file.
	* gas/arm/udf.l: New file.

	* arm-dis.c (arm_opcodes): Add udf.
	(thumb_opcodes): Use "udf" mnemonic rather than UNDEFINED_INSTRUCTION.
	(thumb32_opcodes): Add udf.w.
	(print_insn_thumb32): Handle %H as the thumb32_opcodes comment says.
2013-09-04 07:59:33 +00:00
Andreas Krebbel c8094e012c 2013-09-02 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* s390-opc.txt: Fix description for fiebra, fidbra, and fixbra.
	For the load fp integer instructions only the suppression flag was
	new with z196 version.
2013-09-02 11:42:38 +00:00
Nick Clifton 7e10503172 * aarch64-opc.c (aarch64_logical_immediate_p): Return FALSE if the
immediate is not suitable for the 32-bit ABI.

	* gas/aarch64/illegal.s: Add illegal constant for logical
	operation.
	* gas/aarch64/illegal.l: Add expected error message.
2013-08-28 10:25:36 +00:00
Maciej W. Rozycki fb6f389526 opcodes/
* micromips-opc.c (micromips_opcodes): Use RD_4 for "alnv.ps",
	replacing NODS.

	gas/testsuite/
	* gas/testsuite/gas/mips/micromips-insn32.d: Adjust for delay
	slot scheduling of ALNV.PS.
	* gas/testsuite/gas/mips/micromips-noinsn32.d: Likewise.
	* gas/testsuite/gas/mips/micromips-trap.d: Likewise.
	* gas/testsuite/gas/mips/micromips.d: Likewise.
	* gas/testsuite/gas/mips/micromips@alnv_ps-swap.d: Likewise.
2013-08-23 14:12:59 +00:00
Nick Clifton 9aff4b7ac1 PR binutils/15834
Fix typos:
---
 bfd/bfdio.c                                  |  2 +-
 bfd/elf32-spu.c                              |  2 +-
 bfd/elfnn-aarch64.c                          |  2 +-
 binutils/od-xcoff.c                          |  2 +-
 config/tcl.m4                                |  2 +-
 gas/config/tc-ia64.c                         |  2 +-
 gas/config/tc-sparc.c                        |  2 +-
 gas/config/tc-z80.c                          | 12 ++++++------
 gas/doc/c-i386.texi                          |  6 +++---
 gas/doc/c-m32r.texi                          |  2 +-
 gas/testsuite/gas/d10v/instruction_packing.d |  2 +-
 gas/testsuite/gas/z80/atend.d                |  2 +-
 gold/object.h                                |  2 +-
 include/gdb/remote-sim.h                     |  2 +-
 include/opcode/ChangeLog                     |  2 +-
 include/opcode/i960.h                        |  2 +-
 ld/testsuite/ld-mips-elf/mips16-pic-1.inc    |  2 +-
 opcodes/aarch64-asm.c                        |  2 +-
 opcodes/aarch64-dis.c                        |  2 +-
 opcodes/msp430-dis.c                         |  2 +-
2013-08-23 07:54:19 +00:00
Richard Sandiford 5e0dc5bae9 include/opcode/
* mips.h (M_DEXT, M_DINS): Delete.

opcodes/
	* micromips-opc.c (micromips_opcodes): Replace "dext" and "dins"
	macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases.
	Use +H rather than +C for the real "dext".
	* mips-opc.c (mips_builtin_opcodes): Likewise.

gas/
	* config/tc-mips.c (report_bad_range, report_bad_field): Delete.
	(macro): Remove M_DEXT and M_DINS handling.

gas/testsuite/
	* gas/mips/ext-ill.l, gas/mips/mips64r2-ill.l: Expect DEXT and DINS
	error messages to have the same form as the EXT and INS ones.
	* gas/mips/micromips-insn32.d, gas/mips/micromips-noinsn32.d,
	gas/mips/micromips-trap.d, gas/mips/micromips.d,
	gas/mips/micromips@mips64r2.d, gas/mips/mips64r2.d: Expect
	"dext" and "dins" instead of "dextm", "dextu", "dinsm" and "dinsu".
2013-08-19 19:54:41 +00:00
Richard Sandiford 0f35dbc4d9 include/opcode/
* mips.h (OP_OPTIONAL_REG): New mips_operand_type.
	(mips_optional_operand_p): New function.

opcodes/
	* mips-formats.h (OPTIONAL_REG, OPTIONAL_MAPPED_REG): New macros.
	* micromips-opc.c (decode_micromips_operand): Use OPTIONAL_REG
	and OPTIONAL_MAPPED_REG.
	* mips-opc.c (decode_mips_operand): Likewise.
	* mips16-opc.c (decode_mips16_operand): Likewise.
	* mips-dis.c (print_insn_arg): Handle OP_OPTIONAL_REG.

gas/
	* config/tc-mips.c (operand_reg_mask, match_operand): Handle
	OP_OPTIONAL_REG.
	(mips_ip, mips16_ip): Use mips_optional_operand_p to check
	for optional operands.
2013-08-19 18:57:00 +00:00
H.J. Lu 79ceb7cb73 Remove PREFIX_EVEX_0F3A3E and PREFIX_EVEX_0F3A3F
* i386-dis.c (PREFIX_EVEX_0F3A3E): Removed.
	(PREFIX_EVEX_0F3A3F): Likewise.
	* i386-dis-evex.h (evex_table): Updated.
2013-08-19 15:58:52 +00:00
Richard Sandiford ee5734f078 opcodes/
2013-08-06  Jürgen Urban  <JuergenUrban@gmx.de>

	* mips-opc.c (mips_builtin_opcodes): Add a suffixless version of
	VCLIPW.

gas/
2013-08-06  Jürgen Urban  <JuergenUrban@gmx.de>

	* config/tc-mips.c (match_vu0_suffix_operand): Allow single-channel
	suffixes to be elided too.
	(mips_lookup_insn): Don't reject INSN2_VU0_CHANNEL_SUFFIX here.
	(mips_ip): Assume .xyzw if no VU0 suffix is specified.  Allow +N
	to be omitted too.

gas/testsuite/
2013-08-06  Jürgen Urban  <JuergenUrban@gmx.de>

	* gas/mips/r5900-error-vu0.s, gas/mips/r5900-error-vu0.l,
	gas/mips/r5900-full-vu0.s, gas/mips/r5900-full-vu0.d: Allow
	single-channel suffixes to be elided.
2013-08-06 19:27:07 +00:00
Eric Botcazou fb49eea0b5 * sparc-opc.c (v9andleon): Fix thinko. 2013-08-05 17:04:08 +00:00
Eric Botcazou d6787ef95c gas/
* config/tc-sparc.c (sparc_arch_types): Add leon.
	(sparc_arch): Move sparc4 around and add leon.
	(sparc_target_format): Document -Aleon.
	* doc/c-sparc.texi: Likewise.
include/
	* opcode/sparc.h (sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_LEON.
opcodes/
	* sparc-dis.c (compute_arch_mask): Set SPARC_OPCODE_ARCH_LEON bit for
	bfd_mach_sparc.
	* sparc-opc.c (MASK_LEON): Define.
	(v6, v6notlet, v7, v8, v6notv9): Add MASK_LEON.
	(letandleon): New macro.
	(v9andleon): Likewise.
	(sparc_opc): Add leon.
	(umac): Enable for letandleon.
	(smac): Likewise.
	(casa): Enable for v9andleon.
	(cas): Likewise.
	(casl): Likewise.
2013-08-05 16:11:07 +00:00
Richard Sandiford 14daeee3ae include/opcode/
2013-08-04  Jürgen Urban  <JuergenUrban@gmx.de>
	    Richard Sandiford  <rdsandiford@googlemail.com>

	* mips.h: Document new VU0 operand characters.
	(OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
	(OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
	(OP_REG_R5900_ACC): New mips_reg_operand_types.
	(INSN2_VU0_CHANNEL_SUFFIX): New macro.
	(mips_vu0_channel_mask): Declare.

opcodes/
2013-08-04  Jürgen Urban  <JuergenUrban@gmx.de>
	    Richard Sandiford  <rdsandiford@googlemail.com>

	* mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
	OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
	(print_vu0_channel): New function.
	(print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
	(print_insn_args): Handle '#'.
	(print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX.
	* mips-opc.c (mips_vu0_channel_mask): New constant.
	(decode_mips_operand): Handle new VU0 operand types.
	(VU0, VU0CH): New macros.
	(mips_builtin_opcodes): Add VU0 opcodes.  Use "+7" rather than "E"
	for LQC2 and SQC2.  Use "+9" rather than "G" for EE CFC2 and CTC2.
	Use "+6" rather than "G" for QMFC2 and QMTC2.

gas/
2013-08-04  Jürgen Urban  <JuergenUrban@gmx.de>
	    Richard Sandiford  <rdsandiford@googlemail.com>

	* config/tc-mips.c (MAX_OPERANDS): Bump to 6.
	(RWARN): Bump to 0x8000000.
	(RTYPE_VI, RTYPE_VF, RTYPE_R5900_I, RTYPE_R5900_Q, RTYPE_R5900_R)
	(RTYPE_R5900_ACC): New register types.
	(RTYPE_MASK): Include them.
	(R5900_I_NAMES, R5900_Q_NAMES, R5900_R_NAMES, R5900_ACC_NAMES): New
	macros.
	(reg_names): Include them.
	(mips_parse_register_1): New function, split out from...
	(mips_parse_register): ...here.  Add a channels_ptr parameter.
	Look for VU0 channel suffixes when nonnull.
	(reg_lookup): Update the call to mips_parse_register.
	(mips_parse_vu0_channels): New function.
	(OT_CHANNELS, OT_DOUBLE_CHAR): New mips_operand_token_types.
	(mips_operand_token): Add a "channels" field to the union.
	Extend the comment above "ch" to OT_DOUBLE_CHAR.
	(mips_parse_base_start): Match -- and ++.  Handle channel suffixes.
	(mips_parse_argument_token): Handle channel suffixes here too.
	(validate_mips_insn): Handle INSN2_VU0_CHANNEL_SUFFIX.
	Ignore OP_VU0_MATCH_SUFFIX when calculating the used bits.
	Handle '#' formats.
	(md_begin): Register $vfN and $vfI registers.
	(operand_reg_mask): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
	(convert_reg_type): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
	OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
	(match_vu0_suffix_operand): New function.
	(match_operand): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
	(macro): Use "+7" rather than "E" for LDQ2 and STQ2.
	(mips_lookup_insn): New function.
	(mips_ip): Use it.  Allow "+K" operands to be elided at the end
	of an instruction.  Handle '#' sequences.

gas/testsuite/
2013-08-04  Jürgen Urban  <JuergenUrban@gmx.de>

	* gas/mips/r5900-vu0.d: Expect $vfN and $viN instead of numeric
	coprocessor registers.
	* gas/mips/r5900-all-vu0.s, gas/mips/r5900-all-vu0.d,
	gas/mips/r5900-full-vu0.s, gas/mips/r5900-full-vu0.d,
	gas/mips/r5900-error-vu0.s, gas/mips/r5900-error-vu0.l: New tests.
	* gas/mips/mips.exp: Run them.
2013-08-04 07:31:39 +00:00
Richard Sandiford 3ccad066ac include/opcode/
* mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
	(mips_int_operand_min, mips_int_operand_max): New functions.
	(mips_decode_pcrel_operand): Use mips_decode_int_operand.

opcodes/
	* mips-formats.h (PCREL): Reorder parameters and update the definition
	to match new mips_pcrel_operand layout.
	(JUMP, JALX, BRANCH): Update accordingly.
	* mips16-opc.c (decode_mips16_operand): Likewise.

gas/
	* config/tc-mips.c (match_int_operand): Use mips_int_operand_min
	and mips_int_operand_max.
	(mips16_immed_operand, mips16_immed_operands, MIPS16_NUM_IMMED):
	Delete.
	(mips16_immed_operand, mips16_immed_in_range_p): New functions.
	(mips16_immed, mips16_extended_frag): Use them.  Use mips_int_operand
	instead of mips16_immed_operand.
2013-08-03 10:49:48 +00:00
Richard Sandiford df34fbcce8 opcodes/
* micromips-opc.c (WR_s): Delete.
2013-08-01 22:33:24 +00:00
Richard Sandiford fc76e73056 include/opcode/
* mips.h (mips_decode_reg_operand): New function.
	(INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
	(INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
	(INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
	New macros.
	(INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
	(INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
	(INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
	(INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
	(INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
	(INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
	(INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
	(INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
	(INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
	(INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete.  Renumber other
	macros to cover the gaps.
	(INSN2_MOD_SP): Replace with...
	(INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
	(MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
	(MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
	(MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
	(MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
	Delete.

opcodes/
	* mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI):
	New macros.
	(WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R)
	(WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete.
	(mips_builtin_opcodes): Use the new position-based read-write flags
	instead of field-based ones.  Use UDI for "udi..." instructions.
	* mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
	New macros.
	(WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete.
	(RD_T, WR_T, WR_31): Redefine using generic INSN_* flags.
	(WR_SP, RD_16): New macros.
	(RD_SP): Redefine as an INSN2_* flag.
	(MOD_SP): Redefine in terms of RD_SP and WR_SP.
	(mips16_opcodes): Use the new position-based read-write flags
	instead of field-based ones.  Use RD_16 for "nop".  Move RD_SP to
	pinfo2 field.
	* micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
	New macros.
	(WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj)
	(WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D)
	(WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete.
	(RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP.
	(micromips_opcodes): Use the new position-based read-write flags
	instead of field-based ones.
	* mips-dis.c (print_insn_arg): Use mips_decode_reg_operand.
	(print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead
	of field-based flags.

gas/
	* config/tc-mips.c (MAX_OPERANDS): New macro.
	(mips_operand_array): New structure.
	(mips_operands, mips16_operands, micromips_operands): New arrays.
	(micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
	(micromips_to_32_reg_e_map, micromips_to_32_reg_f_map)
	(micromips_to_32_reg_g_map, micromips_to_32_reg_l_map)
	(micromips_to_32_reg_q_map): Delete.
	(insn_operands, insn_opno, insn_extract_operand): New functions.
	(validate_mips_insn): Take a mips_operand_array as argument and
	use it to build up a list of operands.  Extend to handle INSN_MACRO
	and MIPS16.
	(validate_mips16_insn): New function.
	(validate_micromips_insn): Take a mips_operand_array as argument.
	Handle INSN_MACRO.
	(md_begin): Initialize mips_operands, mips16_operands and
	micromips_operands.  Call validate_mips_insn and
	validate_micromips_insn for macro instructions too.
	Call validate_mips16_insn for MIPS16 instructions.
	(insn_read_mask, insn_write_mask, operand_reg_mask, insn_reg_mask):
	New functions.
	(gpr_read_mask, gpr_write_mask, fpr_read_mask, fpr_write_mask): Use
	them.  Handle INSN_UDI.
	(get_append_method): Use gpr_read_mask.
2013-08-01 20:55:25 +00:00
Richard Sandiford 265459441c include/opcode/
* mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
	(MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
	(MIPS16_INSN_COND_BRANCH): Delete.

opcodes/
	* mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags.
	(WR_SP): Replace with...
	(MOD_SP): ...this.
	(mips16_opcodes): Update accordingly.
	* mips-dis.c (print_insn_mips16): Likewise.

gas/
	* config/tc-mips.c (compact_branch_p, uncond_branch_p): Use the same
	flags for MIPS16 and non-MIPS16 instructions.
	(gpr_mod_mask): Move the INSN2_MOD_SP case outside the micromips block.
	(gpr_read_mask): Use INSN2_READ_GPR_31 for MIPS16 instructions too.
	(gpr_write_mask): Remove MIPS16_INSN_WRITE_SP handling.
	(can_swap_branch_p, get_append_method): Use the same flags for MIPS16
	and non-MIPS16 instructions.  Fix formatting.
2013-08-01 20:40:24 +00:00
Richard Sandiford a8d92fc6c3 opcodes/
* mips16-opc.c (mips16_opcodes): Reformat.
2013-08-01 20:35:11 +00:00
Richard Sandiford 6a819047ab opcodes/
* mips-opc.c (mips_builtin_opcodes): Remove WR_* and RD_* flags
	for operands that are hard-coded to $0.
	* micromips-opc.c (micromips_opcodes): Likewise.
2013-08-01 20:30:02 +00:00
Richard Sandiford 344c74a665 opcodes/
* mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d
	for the single-operand forms of JALR and JALR.HB.
	* micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB
	and JALRS.HB.
2013-08-01 20:25:30 +00:00
Richard Sandiford 41989114b8 opcodes/
* mips-opc.c (mips_builtin_opcodes): Add FP_D to VR5400 vector
	instructions.  Fix them to use WR_MACC instead of WR_CC and
	add missing RD_MACCs.
2013-08-01 20:20:49 +00:00
Richard Sandiford 6d075bce12 opcodes/
* mips-dis.c (print_mips16_insn_arg): Include ISA bit in base address.
2013-08-01 07:13:21 +00:00
Peter Bergner 4f6ffcd38d opcodes/
* ppc-dis.c (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect.
2013-07-30 02:26:09 +00:00
H.J. Lu 43234a1e14 Add Intel AVX-512 support
binutils/

2013-07-26  Sergey Guriev  <sergey.s.guriev@intel.com>
	    Alexander Ivchenko  <alexander.ivchenko@intel.com>
	    Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
	    Sergey Lega  <sergey.s.lega@intel.com>
	    Anna Tikhonova  <anna.tikhonova@intel.com>
	    Ilya Tocar  <ilya.tocar@intel.com>
	    Andrey Turetskiy  <andrey.turetskiy@intel.com>
	    Ilya Verbin  <ilya.verbin@intel.com>
	    Kirill Yukhin  <kirill.yukhin@intel.com>
	    Michael Zolotukhin  <michael.v.zolotukhin@intel.com>

	* dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and
	numeration in comments.
	(dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to
	dwarf table.

gas/

2013-07-26  Sergey Guriev  <sergey.s.guriev@intel.com>
	    Alexander Ivchenko  <alexander.ivchenko@intel.com>
	    Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
	    Sergey Lega  <sergey.s.lega@intel.com>
	    Anna Tikhonova  <anna.tikhonova@intel.com>
	    Ilya Tocar  <ilya.tocar@intel.com>
	    Andrey Turetskiy  <andrey.turetskiy@intel.com>
	    Ilya Verbin  <ilya.verbin@intel.com>
	    Kirill Yukhin  <kirill.yukhin@intel.com>
	    Michael Zolotukhin  <michael.v.zolotukhin@intel.com>

	* config/tc-i386-intel.c (O_zmmword_ptr): New.
	(i386_types): Add zmmword.
	(i386_intel_simplify_register): Allow regzmm.
	(i386_intel_simplify): Handle zmmwords.
	(i386_intel_operand): Handle RC/SAE, vector operations and
	zmmwords.
	* config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New.
	(struct RC_Operation): New.
	(struct Mask_Operation): New.
	(struct Broadcast_Operation): New.
	(vex_prefix): Size of bytes increased to 4 to support EVEX
	encoding.
	(enum i386_error): Add new error codes: unsupported_broadcast,
	broadcast_not_on_src_operand, broadcast_needed,
	unsupported_masking, mask_not_on_destination, no_default_mask,
	unsupported_rc_sae, rc_sae_operand_not_last_imm,
	invalid_register_operand, try_vector_disp8.
	(struct _i386_insn): Add new fields vrex, need_vrex, mask,
	rounding, broadcast, memshift.
	(struct RC_name): New.
	(RC_NamesTable): New.
	(evexlig): New.
	(evexwig): New.
	(extra_symbol_chars): Add '{'.
	(cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF.
	(i386_operand_type): Add regzmm, regmask and vec_disp8.
	(match_mem_size): Handle zmmwords.
	(operand_type_match): Handle zmm-registers.
	(mode_from_disp_size): Handle vec_disp8.
	(fits_in_vec_disp8): New.
	(md_begin): Handle {} properly.
	(type_names): Add "rZMM", "Mask reg" and "Vector d8".
	(build_vex_prefix): Handle vrex.
	(build_evex_prefix): New.
	(process_immext): Adjust to properly handle EVEX.
	(md_assemble): Add EVEX encoding support.
	(swap_2_operands): Correctly handle operands with masking,
	broadcasting or RC/SAE.
	(check_VecOperands): Support EVEX features.
	(VEX_check_operands): Properly handle 16 upper [xyz]mm registers.
	(match_template): Support regzmm and handle new error codes.
	(process_suffix): Handle zmmwords and zmm-registers.
	(check_byte_reg): Extend to zmm-registers.
	(process_operands): Extend to zmm-registers.
	(build_modrm_byte): Handle EVEX.
	(output_insn): Adjust to properly handle EVEX case.
	(disp_size): Handle vec_disp8.
	(output_disp): Support compressed disp8*N evex feature.
	(output_imm): Handle RC/SAE immediates properly.
	(check_VecOperations): New.
	(i386_immediate): Handle EVEX features.
	(i386_index_check): Handle zmmwords and zmm-registers.
	(RC_SAE_immediate): New.
	(i386_att_operand): Handle EVEX features.
	(parse_real_register): Add a check for ZMM/Mask registers.
	(OPTION_MEVEXLIG): New.
	(OPTION_MEVEXWIG): New.
	(md_longopts): Add mevexlig and mevexwig.
	(md_parse_option): Handle mevexlig and mevexwig options.
	(md_show_usage): Add description for mevexlig and mevexwig.
	* doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd,
	avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig.

gas/testsuite/

2013-07-26  Sergey Guriev  <sergey.s.guriev@intel.com>
	    Alexander Ivchenko  <alexander.ivchenko@intel.com>
	    Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
	    Sergey Lega  <sergey.s.lega@intel.com>
	    Anna Tikhonova  <anna.tikhonova@intel.com>
	    Ilya Tocar  <ilya.tocar@intel.com>
	    Andrey Turetskiy  <andrey.turetskiy@intel.com>
	    Ilya Verbin  <ilya.verbin@intel.com>
	    Kirill Yukhin  <kirill.yukhin@intel.com>
	    Michael Zolotukhin  <michael.v.zolotukhin@intel.com>

	* gas/cfi/cfi-i386.s: Add tests for k0-k7.
	* gas/cfi/cfi-i386.d: Change to reflect above mentioned changes.
	* gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7.
	* gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes.
	* gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto.
	* gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers.
	* gas/i386/intel-regs.d: Change correspondingly.
	* gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1.
	* gas/i386/prefetch.d: Ditto.
	* gas/i386/x86-64-prefetch-intel.d: Ditto.
	* gas/i386/x86-64-prefetch.d: Ditto.
	* gas/i386/avx512f-intel.d: New.
	* gas/i386/avx512f-nondef.d: New.
	* gas/i386/avx512f-nondef.s: New.
	* gas/i386/avx512f-opts-intel.d: New.
	* gas/i386/avx512f-opts.d: New.
	* gas/i386/avx512f-opts.s: New.
	* gas/i386/avx512f.d: New.
	* gas/i386/avx512f.s: New.
	* gas/i386/avx512cd-intel.d: New.
	* gas/i386/avx512cd.d: New.
	* gas/i386/avx512cd.s: New.
	* gas/i386/avx512er-intel.d: New.
	* gas/i386/avx512er.d: New.
	* gas/i386/avx512er.s: New.
	* gas/i386/avx512pf-intel.d: New.
	* gas/i386/avx512pf.d: New.
	* gas/i386/avx512pf.s: New.
	* gas/i386/evex-lig.s: New.
	* gas/i386/evex-lig256-intel.d: New.
	* gas/i386/evex-lig256.d: New.
	* gas/i386/evex-lig512-intel.d: New.
	* gas/i386/evex-lig512.d: New.
	* gas/i386/evex-wig.s: New.
	* gas/i386/evex-wig1-intel.d: New.
	* gas/i386/evex-wig1.d: New.
	* gas/i386/inval-avx512f.l: New.
	* gas/i386/inval-avx512f.s: New.
	* gas/i386/x86-64-avx512f-intel.d: New.
	* gas/i386/x86-64-avx512f-nondef.d: New.
	* gas/i386/x86-64-avx512f-nondef.s: New.
	* gas/i386/x86-64-avx512f-opts-intel.d: New.
	* gas/i386/x86-64-avx512f-opts.d: New.
	* gas/i386/x86-64-avx512f-opts.s: New.
	* gas/i386/x86-64-avx512f.d: New.
	* gas/i386/x86-64-avx512f.s: New.
	* gas/i386/x86-64-avx512cd-intel.d: New.
	* gas/i386/x86-64-avx512cd.d: New.
	* gas/i386/x86-64-avx512cd.s: New.
	* gas/i386/x86-64-avx512er-intel.d: New.
	* gas/i386/x86-64-avx512er.d: New.
	* gas/i386/x86-64-avx512er.s: New.
	* gas/i386/x86-64-avx512pf-intel.d: New.
	* gas/i386/x86-64-avx512pf.d: New.
	* gas/i386/x86-64-avx512pf.s: New.
	* gas/i386/x86-64-evex-lig.s: New.
	* gas/i386/x86-64-evex-lig256-intel.d: New.
	* gas/i386/x86-64-evex-lig256.d: New.
	* gas/i386/x86-64-evex-lig512-intel.d: New.
	* gas/i386/x86-64-evex-lig512.d: New.
	* gas/i386/x86-64-evex-wig.s: New.
	* gas/i386/x86-64-evex-wig1-intel.d: New.
	* gas/i386/x86-64-evex-wig1.d: New.
	* gas/i386/x86-64-inval-avx512f.l: New.
	* gas/i386/x86-64-inval-avx512f.s: New.
	* gas/i386/i386.exp: Run new AVX-512 tests.

opcodes/

2013-07-26  Sergey Guriev  <sergey.s.guriev@intel.com>
	    Alexander Ivchenko  <alexander.ivchenko@intel.com>
	    Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
	    Sergey Lega  <sergey.s.lega@intel.com>
	    Anna Tikhonova  <anna.tikhonova@intel.com>
	    Ilya Tocar  <ilya.tocar@intel.com>
	    Andrey Turetskiy  <andrey.turetskiy@intel.com>
	    Ilya Verbin  <ilya.verbin@intel.com>
	    Kirill Yukhin  <kirill.yukhin@intel.com>
	    Michael Zolotukhin  <michael.v.zolotukhin@intel.com>

	* i386-dis-evex.h: New.
	* i386-dis.c (OP_Rounding): New.
	(VPCMP_Fixup): New.
	(OP_Mask): New.
	(Rdq): New.
	(XMxmmq): New.
	(EXdScalarS): New.
	(EXymm): New.
	(EXEvexHalfBcstXmmq): New.
	(EXxmm_mdq): New.
	(EXEvexXGscat): New.
	(EXEvexXNoBcst): New.
	(VPCMP): New.
	(EXxEVexR): New.
	(EXxEVexS): New.
	(XMask): New.
	(MaskG): New.
	(MaskE): New.
	(MaskR): New.
	(MaskVex): New.
	(modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
	evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
	evex_rounding_mode, evex_sae_mode, mask_mode.
	(USE_EVEX_TABLE): New.
	(EVEX_TABLE): New.
	(EVEX enum): New.
	(REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
	REG_EVEX_0F38C7.
	(MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
	MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
	MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
	MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
	MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,  MOD_EVEX_0F38C7_REG_5,
	MOD_EVEX_0F38C7_REG_6.
	(PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
	PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
	PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
	PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
	PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
	PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
	PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
	PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
	PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
	PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
	PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
	PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
	PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
	PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
	PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
	PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
	PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
	PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
	PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
	PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
	PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
	PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
	PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
	PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
	PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
	PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
	PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
	PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
	PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
	PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
	PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
	PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
	PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
	PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
	PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
	PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
	PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
	PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
	PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
	PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
	PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
	PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
	PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
	PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
	PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
	PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
	PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
	PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
	PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
	PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
	PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
	PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
	PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
	PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
	PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
	PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
	PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
	PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
	PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
	PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
	PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
	PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
	PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
	PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
	PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
	PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
	PREFIX_EVEX_0F3A00,  PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
	PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
	PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
	PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
	PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
	PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
	PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
	PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
	PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
	PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
	PREFIX_EVEX_0F3A55.
	(VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
	VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
	VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
	VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
	VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
	VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
	VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
	VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
	VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
	VEX_W_0F3A32_P_2_LEN_0.
	(VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
	EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
	EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
	EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
	EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
	EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
	EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
	EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
	EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
	EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
	EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
	EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
	EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
	EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
	EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
	EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
	EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
	EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
	EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
	EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
	EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
	EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
	EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
	EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
	EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
	EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
	EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
	EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
	EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
	EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
	EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
	EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
	EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
	EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
	EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
	EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
	EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
	EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
	EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
	EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
	EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
	EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
	EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
	EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
	EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
	EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
	EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
	EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
	EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
	EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
	EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
	EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
	EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
	EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
	(struct vex): Add fields evex, r, v, mask_register_specifier,
	zeroing, ll, b.
	(intel_names_xmm): Add upper 16 registers.
	(att_names_xmm): Ditto.
	(intel_names_ymm): Ditto.
	(att_names_ymm): Ditto.
	(names_zmm): New.
	(intel_names_zmm): Ditto.
	(att_names_zmm): Ditto.
	(names_mask): Ditto.
	(intel_names_mask): Ditto.
	(att_names_mask): Ditto.
	(names_rounding): Ditto.
	(names_broadcast): Ditto.
	(x86_64_table): Add escape to evex-table.
	(reg_table): Include reg_table evex-entries from
	i386-dis-evex.h.  Fix prefetchwt1 instruction.
	(prefix_table): Add entries for new instructions.
	(vex_table): Ditto.
	(vex_len_table): Ditto.
	(vex_w_table): Ditto.
	(mod_table): Ditto.
	(get_valid_dis386): Properly handle new instructions.
	(print_insn): Handle zmm and mask registers, print mask operand.
	(intel_operand_size): Support EVEX, new modes and sizes.
	(OP_E_register): Handle new modes.
	(OP_E_memory): Ditto.
	(OP_G): Ditto.
	(OP_XMM): Ditto.
	(OP_EX): Ditto.
	(OP_VEX): Ditto.
	* i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
	CPU_ANY_AVX_FLAGS.  Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
	CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
	(cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
	CpuAVX512PF and CpuVREX.
	(operand_type_init): Add OPERAND_TYPE_REGZMM,
	OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
	(opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
	StaticRounding, SAE, Disp8MemShift, NoDefMask.
	(operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
	* i386-init.h: Regenerate.
	* i386-opc.h (CpuAVX512F): New.
	(CpuAVX512CD): New.
	(CpuAVX512ER): New.
	(CpuAVX512PF): New.
	(CpuVREX): New.
	(i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
	cpuavx512pf and cpuvrex fields.
	(VecSIB): Add VecSIB512.
	(EVex): New.
	(Masking): New.
	(VecESize): New.
	(Broadcast): New.
	(StaticRounding): New.
	(SAE): New.
	(Disp8MemShift): New.
	(NoDefMask): New.
	(i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
	staticrounding, sae, disp8memshift and nodefmask.
	(RegZMM): New.
	(Zmmword): Ditto.
	(Vec_Disp8): Ditto.
	(i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
	fields.
	(RegVRex): New.
	* i386-opc.tbl: Add AVX512 instructions.
	* i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
	registers, mask registers.
	* i386-tbl.h: Regenerate.
2013-07-26 17:20:25 +00:00
Richard Sandiford 1d2db237d8 opcodes/
2013-07-25  Aaro Koskinen  <aaro.koskinen@iki.fi>

	PR gas/15220
	* mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
	Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.

gas/testsuite/
	* gas/mips/loongson-2f.d: Fix expected output for madd.ps,
	msub.ps, nmadd.ps and nmsub.ps.
2013-07-25 19:11:39 +00:00