Commit Graph

9324 Commits

Author SHA1 Message Date
Nick Clifton
bfeaed386d Updated Swedish translation for the gas sub-directory 2020-05-06 14:17:36 +01:00
Nick Clifton
6ef719c016 Section "3.1 Preprocessing" of the online GAS manual has a wrong reference to "Using GNU CC". This fixes that link.
PR 25927
	* doc/as.texi (Preprocessing): Replace cross reference to not
	existant document with a URL to the equivalent page in the GCC
	manual.
2020-05-06 13:21:02 +01:00
Nick Clifton
546cb2d85e Restore readelf's warnings that describe real problems with the file being examined. Fix bug displaying empty file name tables.
binutils* dwarf.c (do_checks): New global variable.
	(display_formatted_table): Warn about an unexpected number of
	columns in the table, if checks are enabled.  Do not complain
	about the lack of data following the number of entries in the
	table if the table is empty.
	(display_debug_lines_decoded): Only warn about an unexpected
	number of columns in a table if checks are enabled.
	* dwarf.h (do_checks): Add a prototype.
	* elfcomm.c (error): Remove weak attribute.
	(warn): Likewise.
	* readelf.c (do_checks): Delete.
	(warn): Delete.
	(process_section_headers): Only warn about empty sections if
	checks are enabled.

gas	* dwarf2dbg.c (out_dir_and_file_list): Add comments describing the
	construction of a DWARF-5 directory name table.
	* testsuite/gas/elf/pr25917.d: Update expected output.
2020-05-05 16:16:03 +01:00
Gunther Nikl
7d0bd48744 [GAS] change of ELF flags initial value in rx-linux
* config/tc-rx.c (elf_flags): Initialize for non-linux targets.
	(md_parse_option): Remove initialization of elf_flags.
2020-05-05 10:19:41 +01:00
Nick Clifton
070b775f03 GAS: Do not create an entry for the default directory if the directory table is empty. Improve readelf's decoding of empty directory and file name tables.
PR 25917
	* dwarf.c (display_debug_lines_decoded): Warn if encountering a
	supicious number of entries for DWARF-5 format directory and file
	name tables.  Do not display file name table header if the table
	is empty.  Do not allocate space for empty tables.
2020-05-04 13:50:05 +01:00
Andre Simoes Dias Vieira
fe05f369f0 gas: PR 25863: Fix scalar vmul inside it block when assembling for MVE
This fixes PR 25863 by fixing the condition in the parsing of vmul in
do_mve_vmull.  It also simplifies the code in there fixing latent issues that
would lead to NEON code being accepted when it shouldn't.

gas/ChangeLog:
2020-05-04  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	PR gas/25863
	* config/tc-arm.c (do_mve_vmull): Fix scalar and NEON parsing of vmul.
	* testsuite/gas/arm/mve-scalar-vmult-it.d: New test.
	* testsuite/gas/arm/mve-scalar-vmult-it.s: New test.
2020-05-04 13:07:45 +01:00
Nick Clifton
4706679dac Fix an illegal memory access in the assembler when generating a DWARF5 file/directory table with no entries.
PR 25917
	* dwarf2dbg.c (out_dir_and_file_list): Check for the directory
	table's existence before looking at its entries.
	* testsuite/gas/elf/pr25917.s: New test source file.
	* testsuite/gas/elf/pr25917.d: New test driver.
	* testsuite/gas/elf/elf.exp (run_elf_list_test): Run the new test.
2020-05-04 10:19:38 +01:00
Alex Coplan
09c1e68a16 AArch64: add GAS support for UDF instruction
binutils * testsuite/binutils-all/aarch64/in-order-all.d: Update to use new
          disassembly.
        * testsuite/binutils-all/aarch64/out-of-order-all.d: Likewise.

ld/     * testsuite/ld-aarch64/erratum843419_tls_ie.d: Use udf in disassembly.
        * testsuite/ld-aarch64/farcall-b-section.d: Likewise.
        * testsuite/ld-aarch64/farcall-back.d: Likewise.
        * testsuite/ld-aarch64/farcall-bl-section.d: Likewise.

gas/   * config/tc-aarch64.c (fix_insn): Implement for AARCH64_OPND_UNDEFINED.
          (parse_operands): Implement for AARCH64_OPND_UNDEFINED.
        * testsuite/gas/aarch64/udf.s: New.
        * testsuite/gas/aarch64/udf.d: New.
        * testsuite/gas/aarch64/udf-invalid.s: New.
        * testsuite/gas/aarch64/udf-invalid.l: New.
        * testsuite/gas/aarch64/udf-invalid.d: New.

include * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_UNDEFINED.

opcodes * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
        * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
          (operand_general_constraint_met_p): validate AARCH64_OPND_UNDEFINED.
        * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry for
          FLD_imm16_2.
        * aarch64-asm-2.c: Regenerated.
        * aarch64-dis-2.c: Regenerated.
        * aarch64-opc-2.c: Regenerated.
2020-04-30 15:47:30 +01:00
Yoshinori Sato
c578f16ef1 ld: Add rx-linux emulation. gas: Change ELF flags initial value in rx-linux
ld	* emulparams/elf32rx_linux.sh: New rx-linux emulation.
	* emultempl/rxlinux.em: New.
	* configure.tgt: Add rx-linux.
	* Makefile.am: Add eelf32rx_linux.c
	* Makefile.in: Regenerate.

gas	* config/tc-rx.c (elf_flags): Reset default value.
	(md_parse_option): For rx-elf Initialize elf_flags with RX_ABI.
2020-04-30 13:35:37 +01:00
Max Filippov
935f1f4ba3 xtensa: gas: support optional immediate simcall parameter
Starting with RH.0 release Xtensa ISA adds immediate parameter to
simcall opcode. For assembly source compatibility treat "simcall"
instruction without parameter as "simcall 0" when parameter is required.

2020-04-29  Max Filippov  <jcmvbkbc@gmail.com>
gas/
	* config/tc-xtensa.c (XTENSA_MARCH_EARLIEST): Define macro as 0
	if it's not defined.
	(microarch_earliest): New static variable.
	(xg_translate_idioms): Translate "simcall" to "simcall 0" when
	simcall opcode has mandatory parameter.
	(xg_init_global_config): Initialize microarch_earliest.
2020-04-29 18:31:32 -07:00
Nick Clifton
241e541d00 Update expected disassembly after recent update.
PR 22699
	* testsuite/gas/sh/sh4al-dsp.d: Update expected disassembly.
2020-04-29 17:18:56 +01:00
Nick Clifton
5c936ef50f Fix the disassmbly of SH instructions which have an unsigned 8-bit immediate operand.
PR 22699
opcodes	* sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
	IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
	* sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
	IMM0_8U case.

gas	* config/tc-sh.c (build_Mytes): Change operand type IMM0_8 to
	IMM0_8S and add support for IMM0_8U.
	* testsuite/gas/sh/sh4a.s: Add test of a logical insn using an
	unsigned 8-bit immediate.
	* testsuite/gas/sh/sh4a.d: Extended expected disassembly.
2020-04-29 13:13:55 +01:00
Tamar Christina
251dae9107 x86: Add i386 PE big-object support
The 64-bit version of binutils got support for the PE COFF BIG OBJ format a
couple of years ago.   The BIG OBJ format is a slightly different COFF format
which extends the size of the number of section field in the header from a
uint16_t to a uint32_t and so greatly increases the number of sections allowed.

However the 32-bit version of bfd never got support for this.  The GHC Haskell
compiler generates a great deal of symbols due to it's use of
-ffunction-sections and -fdata-sections.

This meant that we could not build the 32-bit version of the GHC Compiler for
many releases now as binutils didn't have this support.

This patch adds the support to the 32-bit port of binutils as well and also does
come cleanup in the code.

bfd/ChangeLog:

	* coff-i386.c (COFF_WITH_PE_BIGOBJ): New.
	* coff-x86_64.c (COFF_WITH_PE_BIGOBJ): New.
	* config.bfd (targ_selvecs): Rename x86_64_pe_be_vec
	to x86_64_pe_big_vec as it not a big-endian format.
	(vec i386_pe_big_vec): New.
	* configure.ac: Likewise.
	* targets.c: Likewise.
	* configure: Regenerate.
	* pe-i386.c (TARGET_SYM_BIG, TARGET_NAME_BIG,
	COFF_WITH_PE_BIGOBJ): New.
	* pe-x86_64.c (TARGET_SYM_BIG, TARGET_NAME_BIG):
	New.
	(x86_64_pe_be_vec): Moved.

gas/ChangeLog:

	* NEWS: Add news entry for big-obj.
	* config/tc-i386.c (i386_target_format): Support new format.
	* doc/c-i386.texi: Add i386 support.
	* testsuite/gas/pe/big-obj.d: Rename test to not be x64 specific.
	* testsuite/gas/pe/pe.exp (big-obj): Make test run on i386 as well.

ld/ChangeLog:

	* pe-dll.c (pe_detail_list):  Add pe-bigobj-i386.
2020-04-27 17:41:39 +01:00
Nick Clifton
714e6c969f GAS: Allow automatically assigned entries in the file table to be reassigned if the source file specifically requests to use the assigned slot.
PR 25878
	* dwarf2dbg.c (struct file_entry): Add auto_assigned field.
	(assign_file_to_slot): New function.  Fills in an entry in the
	files table.
	(allocate_filenum): Use new function.
	(allocate_filename_to_slot): Use new function.  If the specified
	slot entry is already in use, but was chosen automatically then
	reassign the automatic entry.
2020-04-27 11:35:25 +01:00
liuhongt
a09f656b26 Improve -mlfence-after-load
1.Implict load for POP/POPF/POPA/XLATB, no load for Anysize insns
  2. Add -mlfence-before-ret=shl/yes, adjust operand size of
  or/not/shl according to ret's.
  3. Issue warning for REP CMPS/SCAS since they would affect control
  flow behavior.
  4. Adjust testcases and documents.

gas/Changelog:
	* config/tc-i386.c (lfence_before_ret_shl): New member.
	(load_insn_p): implict load for POP/POPA/POPF/XLATB, no load
	for Anysize insns.
	(insert_after_load): Issue warning for REP CMPS/SCAS.
	(insert_before_before): Handle iret, Handle
	-mlfence-before-ret=shl, Adjust operand size of or/not/shl to ret's,
	(md_parse_option): Change -mlfence-before-ret=[none|not|or] to
	-mlfence-before-ret=[none/not/or/shl/yes].
	Enable -mlfence-before-ret=shl when
	-mlfence-beofre-indirect-branch=all and no explict -mlfence-before-ret option.
	(md_show_usage): Ditto.
	* doc/c-i386.texi: Ditto.
	* testsuite/gas/i386/i386.exp: Add new testcases.
	* testsuite/gas/i386/lfence-load-b.d: New.
	* testsuite/gas/i386/lfence-load-b.e: New.
	* testsuite/gas/i386/lfence-load.d: Modified.
	* testsuite/gas/i386/lfence-load.e: New.
	* testsuite/gas/i386/lfence-load.s: Modified.
	* testsuite/gas/i386/lfence-ret-a.d: Modified.
	* testsuite/gas/i386/lfence-ret-b.d: Modified.
	* testsuite/gas/i386/lfence-ret-c.d: New.
	* testsuite/gas/i386/lfence-ret-d.d: New.
	* testsuite/gas/i386/lfence-ret.s: Modified.
	* testsuite/gas/i386/x86-64-lfence-load-b.d: New.
	* testsuite/gas/i386/x86-64-lfence-load.d: Modified.
	* testsuite/gas/i386/x86-64-lfence-load.s: Modified.
	* testsuite/gas/i386/x86-64-lfence-ret-a.d: Modified.
	* testsuite/gas/i386/x86-64-lfence-ret-b.d: Modified.
	* testsuite/gas/i386/x86-64-lfence-ret-c.d: New.
	* testsuite/gas/i386/x86-64-lfence-ret-d.d: New
	* testsuite/gas/i386/x86-64-lfence-ret-e.d: New.
	* testsuite/gas/i386/x86-64-lfence-ret.e: New.
	* testsuite/gas/i386/x86-64-lfence-ret.s: New.
2020-04-26 14:26:24 +08:00
Max Filippov
30ce8e47fa xtensa: fix PR ld/25861
Introduce new relaxations XTENSA_PDIFF{8,16,32} for positive differences
(subtracted symbol precedes diminished symbol) and XTENSA_NDIFF{8,16,32}
for negative differences (subtracted symbol follows diminished symbol).
Don't generate XTENSA_DIFF relocations in the assembler, generate
XTENSA_PDIFF or XTENSA_NDIFF based on relative symbol position.

Handle XTENSA_DIFF in BFD for compatibility with old object files.
Handle XTENSA_PDIFF and XTENSA_NDIFF in BFD, treating difference value
as unsigned.

2020-04-22  Max Filippov  <jcmvbkbc@gmail.com>
bfd/
	* bfd-in2.h: Regenerated.
	* elf32-xtensa.c (elf_howto_table): New entries for
	R_XTENSA_PDIFF{8,16,32} and R_XTENSA_NDIFF{8,16,32}.
	(elf_xtensa_reloc_type_lookup, elf_xtensa_do_reloc)
	(relax_section): Add cases for R_XTENSA_PDIFF{8,16,32} and
	R_XTENSA_NDIFF{8,16,32}.
	* libbfd.h (bfd_reloc_code_real_names): Add names for
	BFD_RELOC_XTENSA_PDIFF{8,16,32} and
	BFD_RELOC_XTENSA_NDIFF{8,16,32}.
	* reloc.c: Add documentation for BFD_RELOC_XTENSA_PDIFF{8,16,32}
	and BFD_RELOC_XTENSA_NDIFF{8,16,32}.

binutils/
	* readelf.c (is_none_reloc): Recognize
	BFD_RELOC_XTENSA_PDIFF{8,16,32} and
	BFD_RELOC_XTENSA_NDIFF{8,16,32}.

gas/
	* config/tc-xtensa.c (md_apply_fix): Replace
	BFD_RELOC_XTENSA_DIFF{8,16,32} generation with
	BFD_RELOC_XTENSA_PDIFF{8,16,32} and
	BFD_RELOC_XTENSA_NDIFF{8,16,32} generation.
	* testsuite/gas/xtensa/loc.d: Replace BFD_RELOC_XTENSA_DIFF16
	with BFD_RELOC_XTENSA_PDIFF16 in the expected output.

include/
	* elf/xtensa.h (elf_xtensa_reloc_type): New entries for
	R_XTENSA_PDIFF{8,16,32} and R_XTENSA_NDIFF{8,16,32}.

ld/
	* testsuite/ld-xtensa/relax-loc.d: New test definition.
	* testsuite/ld-xtensa/relax-loc.s: New test source.
	* testsuite/ld-xtensa/xtensa.exp (relax-loc): New test.
2020-04-22 18:46:45 -07:00
Alan Modra
31c89d6038 .symver fixes
* config/obj-elf.c (elf_frob_symbol): Unconditionally remove
	symbol for ".symver .. remove".
	* doc/as.texi (.symver): Update.
	* testsuite/gas/symver/symver11.s: Make foo weak.
	* testsuite/gas/symver/symver11.d: Expect an error.
	* testsuite/gas/symver/symver7.d: Allow other random symbols.
2020-04-22 22:24:03 +09:30
H.J. Lu
1d3eb55695 symver11.s: Add ".balign 8"
Add ".balign 8" to avoid

symver11.s:9: Error: misaligned data

for sh targets.

	* testsuite/gas/symver/symver11.s: Add ".balign 8".
2020-04-21 18:21:56 -07:00
Andreas Schwab
bb2a145347 Disallow PC relative for CMPI on MC68000/10
The MC68000/10 decodes the second operand of CMPI strictly as destination
operand, which disallows PC relative addressing, even though the insn
doesn't write to the operand.  This restriction has only been lifted for
the MC68020+ and CPU32.

opcodes:
	PR 25848
	* m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
	cmpi only on m68020up and cpu32.

gas:
	PR 25848
	* testsuite/gas/m68k/operands.s: Add tests for cmpi.
	* testsuite/gas/m68k/operands.d: Update.
	* testsuite/gas/m68k/op68000.d: Update for new error messages.
2020-04-21 16:53:36 +02:00
Tamar Christina
c36876fe5b BFD: Exclude sections with no content from compress check.
The check in bfd_get_full_section_contents is trying to check that we don't
allocate more space for a section than the size of the section is on disk.

Previously we excluded linker created sections since they didn't have a size on
disk.  However we also need to exclude sections with no content as well such as
the BSS section.  Space for these would not have been allocated by the assembler
and so the check would incorrectly fail.

bfd/ChangeLog:

	PR binutils/24753
	* compress.c (bfd_get_full_section_contents): Exclude sections with no
	content.

gas/ChangeLog:

	PR binutils/24753
	* testsuite/gas/arm/pr24753.d: New test.
	* testsuite/gas/arm/pr24753.s: New test.
2020-04-21 15:17:18 +01:00
H.J. Lu
6914be53bd gas: Extend .symver directive
Extend .symver directive to update visibility of the original symbol and
assign one original symbol to different versioned symbols:

  .symver foo, foo@VERS_1, local    # Change foo to a local symbol.
  .symver foo, foo@VERS_2, hidden   # Change foo to a hidden symbol.
  .symver foo, foo@@VERS_3, remove  # Remove foo from symbol table.
  .symver foo, bar@V1               # Assign foo to bar@V1 and baz@V2.
  .symver foo, baz@V2

	PR gas/23840
	PR gas/25295
	* NEWS: Mention .symver extension.
	* config/obj-elf.c (obj_elf_find_and_add_versioned_name): New
	function.
	(obj_elf_symver): Call obj_elf_find_and_add_versioned_name to
	add a version name.  Add local, hidden and remove visibility
	support.
	(elf_frob_symbol): Handle the list of version names.  Update the
	original symbol to local, hidden or remove it from the symbol
	table.
	(elf_frob_file_before_adjust): Handle the list of version names.
	* config/obj-elf.h (elf_visibility): New.
	(elf_versioned_name_list): Likewise.
	(elf_obj_sy): Change local to bitfield. Add rename, bad_version
	and visibility.  Change versioned_name pointer to struct
	elf_versioned_name_list.
	* doc/as.texi: Update .symver directive.
	* testsuite/gas/symver/symver.exp: Run all *.d tests.  Add more
	error checking tests.
	* testsuite/gas/symver/symver6.d: New file.
	* testsuite/gas/symver/symver7.d: Likewise.
	* testsuite/gas/symver/symver7.s: Likewise.
	* testsuite/gas/symver/symver8.d: Likewise.
	* testsuite/gas/symver/symver8.s: Likewise.
	* testsuite/gas/symver/symver9.s: Likewise.
	* testsuite/gas/symver/symver9a.d: Likewise.
	* testsuite/gas/symver/symver9b.d: Likewise.
	* testsuite/gas/symver/symver10.s: Likewise.
	* testsuite/gas/symver/symver10a.d: Likewise.
	* testsuite/gas/symver/symver10b.d: Likewise.
	* testsuite/gas/symver/symver11.d: Likewise.
	* testsuite/gas/symver/symver11.s: Likewise.
	* testsuite/gas/symver/symver12.d: Likewise.
	* testsuite/gas/symver/symver12.s: Likewise.
	* testsuite/gas/symver/symver13.d: Likewise.
	* testsuite/gas/symver/symver13.s: Likewise.
	* testsuite/gas/symver/symver14.d: Likewise.
	* testsuite/gas/symver/symver14.l: Likewise.
	* testsuite/gas/symver/symver15.d: Likewise.
	* testsuite/gas/symver/symver15.l: Likewise.
	* testsuite/gas/symver/symver6.l: Removed.
	* testsuite/gas/symver/symver6.s: Updated.
2020-04-21 05:33:17 -07:00
Sudakshina Das
c2e5c986b3 [AArch64, Binutils] Add missing TSB instruction
This patch implements the TSB instructions:
https://developer.arm.com/docs/ddi0596/f/base-instructions-alphabetic-order/
tsb-csync-trace-synchronization-barrier
Since TSB and PSB both use the same (and only) argument "CSYNC", this patch
reuses it for TSB. However, the same argument would imply different value
for CRm:Op2 which are anyway fixed values, so I have diverted the
inserter/extracter function to dummy versions instead of the "hint" version.
The operand checker part still uses the existing infratructure for
AARCH64_OPND_BARRIER_PSB to make sure the operand is parsed correctly.

gas/ChangeLog:

2020-04-20  Sudakshina Das  <sudi.das@arm.com>

	* config/tc-aarch64.c (parse_barrier_psb): Update error messages
	to include TSB.
	* testsuite/gas/aarch64/system-2.d: Update -march and new tsb tests.
	* testsuite/gas/aarch64/system-2.s: Add new tsb tests.
	* testsuite/gas/aarch64/system.d: Update.

opcodes/ChangeLog:

2020-04-20  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-asm.c (aarch64_ins_none): New.
	* aarch64-asm.h (ins_none): New declaration.
	* aarch64-dis.c (aarch64_ext_none): New.
	* aarch64-dis.h (ext_none): New declaration.
	* aarch64-opc.c (aarch64_print_operand): Update case for
	AARCH64_OPND_BARRIER_PSB.
	* aarch64-tbl.h (aarch64_opcode_table): Add tsb.
	(AARCH64_OPERANDS): Update inserter/extracter for
	AARCH64_OPND_BARRIER_PSB to use new dummy functions.
	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.
2020-04-20 10:58:16 +01:00
Sudakshina Das
8a6e1d1d7f [AArch64, Binutils] Make hint space instructions valid for Armv8-a
There are a few instruction in AArch64 that are in the HINT space. Any of
these instructions should be accepted by the assembler/disassembler at any
architecture version. This patch fixes the existing instructions that are
not behaving accordingly.
I have used all of the instructions mentioned in the following to make the
changes:
https://developer.arm.com/docs/ddi0596/f/base-instructions-alphabetic-order/
hint-hint-instruction

gas/ChangeLog:

2020-04-20  Sudakshina Das  <sudi.das@arm.com>

	* testsuite/gas/aarch64/bti.d: Update -march option.
	* testsuite/gas/aarch64/illegal-bti.d: Remove.
	* testsuite/gas/aarch64/illegal-bti.l: Remove.
	* testsuite/gas/aarch64/illegal-ras-1.l: Remove esb.
	* testsuite/gas/aarch64/illegal-ras-1.s: Remove esb.

opcodes/ChangeLog:

2020-04-20  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
	(aarch64_feature_ras, RAS): Likewise.
	(aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
	(aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
	autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
	autiaz, autiasp, autibz, autibsp to be CORE_INSN.
	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.
2020-04-20 10:50:52 +01:00
Alan Modra
49af2f5c83 bfin: allow ".=.+delta"
BFIN has lots of instructions that contain "=", so "sym = expression"
is disabled for that target.  This makes an exception for assignment
to dot, fixing the recent regression of ld-scripts/pr18963.

	* config/tc-bfin.h (TC_EQUAL_IN_INSN): Allow assignment to dot.
2020-04-17 12:45:23 +09:30
Nick Clifton
8e4979ac1e Stop the MIPS assembler from accepting ifunc symbols.
PR 25803
gas	* config/obj-elf.c (obj_elf_type): Reject ifunc symbols on MIPS
	targets.
	* testsuite/gas/elf/elf.exp: Add MIPS targets to the list to skip
	for the type-2 test.
	* testsuite/gas/elf/type-noifunc.e: Update to allow for MIPS
	targets running this test.

bfd	* elfxx-mips.c (_bfd_mips_elf_adjust_dynamic_symbol): Replace an
	abort with a more helpful error message.
2020-04-16 18:02:10 +01:00
David Faust
c54a9b5669 cpu,gas,opcodes: support for eBPF JMP32 instruction class
Add support for the JMP32 class of eBPF instructions.

cpu/ChangeLog

	* bpf.cpu (define-cond-jump-insn): Renamed from djci.
	(dcji) New version with support for JMP32

gas/ChangeLog

	* testsuite/gas/bpf/bpf.exp: Run jump32 tests.
	* testsuite/gas/bpf/jump32.s: New file.
	* testsuite/gas/bpf/jump32.d: Likewise.

opcodes/ChangeLog

	* bpf-desc.c: Regenerate.
	* bpf-desc.h: Likewise.
	* bpf-opc.c: Regenerate.
	* bpf-opc.h: Likewise.
2020-04-16 09:52:57 +02:00
H.J. Lu
3071b197da x86: Correct -mlfence-before-indirect-branch= documentation
Replace "after indirect near branch" with "before indirect near branch".

	* doc/c-i386.texi: Correct -mlfence-before-indirect-branch=
	documentation.
2020-04-08 19:31:45 -07:00
Gunther Nikl
4c09b8c4e7 [PATCH 1/4]: microblaze: remove duplicate prototypes
The microblaze target header duplicates prototypes already provided by tc.h.

	* config/tc-microblaze.h (md_begin, md_assemble, md_undefined_symbol,
	md_show_usage, md_convert_frag, md_operand, md_number_to_chars,
	md_estimate_size_before_relax, md_section_align, tc_gen_reloc,
	md_apply_fix3): Delete prototypes.
2020-04-08 12:33:16 +01:00
Gunther Nikl
9ad4cfa8c3 [PATCH 4/4]: Add generic prototype for md_pcrel_from_section
This patch removes the need for target headers to provide a custom prototype
for md_pcrel_from_section.

	* tc.h (md_pcrel_from_section): Add prototype.
	* config/tc-aarch64.h (md_pcrel_from_section): Remove prototype.
	* config/tc-arc.h (md_pcrel_from_section): Likewise.
	* config/tc-arm.h (md_pcrel_from_section): Likewise.
	* config/tc-avr.h (md_pcrel_from_section): Likewise.
	* config/tc-bfin.h (md_pcrel_from_section): Likewise.
	* config/tc-bpf.h (md_pcrel_from_section): Likewise.
	* config/tc-csky.h (md_pcrel_from_section): Likewise.
	* config/tc-d10v.h (md_pcrel_from_section): Likewise.
	* config/tc-d30v.h (md_pcrel_from_section): Likewise.
	* config/tc-epiphany.h (md_pcrel_from_section): Likewise.
	* config/tc-fr30.h (md_pcrel_from_section): Likewise.
	* config/tc-frv.h (md_pcrel_from_section): Likewise.
	* config/tc-iq2000.h (md_pcrel_from_section): Likewise.
	* config/tc-lm32.h (md_pcrel_from_section): Likewise.
	* config/tc-m32c.h (md_pcrel_from_section): Likewise.
	* config/tc-m32r.h (md_pcrel_from_section): Likewise.
	* config/tc-mcore.h (md_pcrel_from_section): Likewise.
	* config/tc-mep.h (md_pcrel_from_section): Likewise.
	* config/tc-metag.h (md_pcrel_from_section): Likewise.
	* config/tc-microblaze.h (md_pcrel_from_section): Likewise.
	* config/tc-mmix.h (md_pcrel_from_section): Likewise.
	* config/tc-moxie.h (md_pcrel_from_section): Likewise.
	* config/tc-msp430.h (md_pcrel_from_section): Likewise.
	* config/tc-mt.h (md_pcrel_from_section): Likewise.
	* config/tc-or1k.h (md_pcrel_from_section): Likewise.
	* config/tc-ppc.h (md_pcrel_from_section): Likewise.
	* config/tc-rl78.h (md_pcrel_from_section): Likewise.
	* config/tc-rx.h (md_pcrel_from_section): Likewise.
	* config/tc-s390.h (md_pcrel_from_section): Likewise.
	* config/tc-sh.h (md_pcrel_from_section): Likewise.
	* config/tc-xc16x.h (md_pcrel_from_section): Likewise.
	* config/tc-xstormy16.h (md_pcrel_from_section): Likewise.
2020-04-08 12:28:10 +01:00
Gunther Nikl
d9f1988553 [PATCH 3/4]: m32c: remove duplicate define and prototype
The m32c target header has a duplicate entry for MD_PCREL_FROM_SECTION.
The duplication was present since the initial commit of the port.

	* config/tc-m32c.h (MD_PCREL_FROM_SECTION): Delete duplicate define.
	(md_pcrel_from_section): Remove duplicate prototype.
2020-04-08 11:15:28 +01:00
Gunther Nikl
6a3ab9239a [PATCH 2/4]: moxie: use generic pcrel support
The moxie target header uses md_pcrel_from, thus the local prototype and
the macro definition for MD_PCREL_FROM_SECTION are not needed.

	* config/tc-moxie.h (MD_PCREL_FROM_SECTION): Delete define.
	(md_pcrel_from): Remove prototytpe.
2020-04-08 11:13:04 +01:00
H.J. Lu
6e0e8b4502 gas: Mention support for Intel SERIALIZE and TSXLDTRK
* NEWS: Mention support for Intel SERIALIZE and TSXLDTRK
	instructions.
2020-04-07 04:43:49 -07:00
H.J. Lu
266803a291 gas/doc/c-z80.texi: Fix @xref warnings
Fix

gas/doc/c-z80.texi:244: warning: `.' or `,' must follow @xref, not )
gas/doc/c-z80.texi:278: warning: `.' or `,' must follow @xref, not )
gas/doc/c-z80.texi:284: warning: `.' or `,' must follow @xref, not )
gas/doc/c-z80.texi:291: warning: `.' or `,' must follow @xref, not )
gas/doc/c-z80.texi:295: warning: `.' or `,' must follow @xref, not )

	* doc/c-z80.texi: Fix @xref warnings.
2020-04-07 04:21:41 -07:00
Cui,Lili
bb651e8b7f Add support for intel TSXLDTRK instructions$
gas/

	* config/tc-i386.c (cpu_arch): Add .TSXLDTRK.
	(cpu_noarch): Likewise.
	* doc/c-i386.texi: Document TSXLDTRK.
	* testsuite/gas/i386/i386.exp: Run TSXLDTRK tests.
	* testsuite/gas/i386/tsxldtrk.d: Likewise.
	* testsuite/gas/i386/tsxldtrk.s: Likewise.
	* testsuite/gas/i386/x86-64-tsxldtrk.d: Likewise.

opcodes/

	* i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
	(prefix_table): New instructions (see prefixes above).
	(rm_table): Likewise.
	* i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
	CPU_ANY_TSXLDTRK_FLAGS.
	(cpu_flags): Add CpuTSXLDTRK.
	* i386-opc.h (enum): Add CpuTSXLDTRK.
	(i386_cpu_flags): Add cputsxldtrk.
	* i386-opc.tbl: Add XSUSPLDTRK insns.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Likewise.
2020-04-07 13:59:50 +08:00
LiliCui
4b27d27c07 Add support for intel SERIALIZE instruction
gas/

	* config/tc-i386.c (cpu_arch): Add .serialize.
	(cpu_noarch): Likewise.
	* doc/c-i386.texi: Document serialize.
	* testsuite/gas/i386/i386.exp: Run serialize tests
	* testsuite/gas/i386/serialize.d: Likewise.
	* testsuite/gas/i386/x86-64-serialize.d: Likewise.
	* testsuite/gas/i386/serialize.s: Likewise.

opcodes/

	* i386-dis.c (prefix_table): New instructions serialize.
	* i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
	CPU_ANY_SERIALIZE_FLAGS.
	(cpu_flags): Add CpuSERIALIZE.
	* i386-opc.h (enum): Add CpuSERIALIZE.
	(i386_cpu_flags): Add cpuserialize.
	* i386-opc.tbl: Add SERIALIZE insns.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Likewise.
2020-04-02 05:48:36 -07:00
Rainer Orth
bb89747721 ld: Disable ifunc tests on Solaris
A couple of ld ifunc tests currently FAIL on 64-bit Solaris/x86:

FAIL: ld-ifunc/ifunc-10-x86-64
FAIL: ld-ifunc/ifunc-11-x86-64
FAIL: ld-ifunc/ifunc-12-x86-64
FAIL: ld-ifunc/ifunc-13-x86-64
FAIL: ld-ifunc/ifunc-14a-x86-64
FAIL: ld-ifunc/ifunc-14b-x86-64
FAIL: ld-ifunc/ifunc-14c-x86-64
FAIL: ld-ifunc/ifunc-14d-x86-64
FAIL: ld-ifunc/ifunc-14e-x86-64
FAIL: ld-ifunc/ifunc-14f-x86-64
FAIL: ld-ifunc/ifunc-15-x86-64
FAIL: ld-ifunc/ifunc-17a-x86-64
FAIL: ld-ifunc/ifunc-17b-x86-64
FAIL: ld-ifunc/ifunc-2-local-x86-64-now
FAIL: ld-ifunc/ifunc-2-local-x86-64
FAIL: ld-ifunc/ifunc-2-x86-64-now
FAIL: ld-ifunc/ifunc-2-x86-64
FAIL: ld-ifunc/ifunc-20-x86-64
FAIL: ld-ifunc/pr17154-x86-64-now
FAIL: ld-ifunc/pr17154-x86-64

For one, the actual error is weird:

./ld-new: target elf64-x86-64 not found
failed with: <./ld-new: target elf64-x86-64 not found>, no expected output
FAIL: ld-ifunc/ifunc-10-x86-64

although ld -V does report the elf_x86_64 emulation as supported:

$ ./ld/ld-new -V
GNU ld (GNU Binutils) 2.34.50.20200328
  Supported emulations:
   elf_x86_64_sol2
   elf_x86_64
[...]

When using ld -m elf_x86_64_sol2 instead, one of the testcases links
successfully.

However, there's no point in pursuing this: Solaris does not support
ifunc, as can be seen in <sys/elf.h>:

/*
 * GNU/Linux specific symbol type not used by Solaris
 */
#define STT_GNU_IFUNC   10

and never will, given that it has symbol capabilities as solution to
effectively the same problem:

http://www.linker-aliens.org/blogs/rie/entry/symbol_capabilitie/

Therefore this patch disables ifunc testing on Solaris completely by
removing Solaris from binutils/testsuite/lib/binutils-common.exp
(supports_gnu_osabi).  The ifunc part is justified above.  SHF_GNU_MBIND is
in the OS-specific range and conflicts with

#define SHF_SUNW_REALLOC        0x01000000      /* internal: krtld realloc */

While the comment suggests this might be relocatable without too much
problems, the description of mbind (no formal spec AFAICS, just the
comment in the binutils patch submission) strongly suggests that this
isn't relevant to Solaris at all.

Indirectly, clearing supports_gnu_osabi on Solaris disables
supports_gnu_unique.  Again, Solaris <sys/elf.h> has

/*
 * GNU/Linux specific binding not used by Solaris
 */
#define STB_GNU_UNIQUE  10

so this seems the right thing to do.

Afterwards, one can remove the explicit mentions of *-*-solaris2* in
quite a number of (but not all) the ld-ifunc dump file notarget lists.

There's one fallout, though: two gas tests now XPASS because they are
xfail'ed for !supports_gnu_osabi:

XPASS: mbind sections 12
XPASS: mbind section contents 16
XPASS: mbind sections 16
XPASS: mbind section contents 16

To fix that, I've changed

#xfail: ![supports_gnu_osabi]

to notarget.

Tested on x86_64-pc-solaris2.11, i386-pc-solaris2.11,
x86_64-pc-linux-gnu, and i686-pc-linux-gnu.

	ld:
	* testsuite/ld-ifunc/ifunc-10-i386.d: Remove *-*-solaris2* from
	notarget.
	* ifunc-11-i386.d: Likewise.
	* ifunc-12-i386.d: Likewise.
	* ifunc-13-i386.d: Likewise.
	* ifunc-14a-i386.d: Likewise.
	* ifunc-14b-i386.d: Likewise.
	* ifunc-14c-i386.d: Likewise.
	* ifunc-14d-i386.d: Likewise.
	* ifunc-14e-i386.d: Likewise.
	* ifunc-14f-i386.d: Likewise.
	* ifunc-15-i386.d: Likewise.
	* ifunc-16-i386-now.d: Likewise.
	* ifunc-16-i386.d: Likewise.
	* ifunc-17a-i386.d: Likewise.
	* ifunc-17b-i386.d: Likewise.
	* ifunc-18a-i386.d: Likewise.
	* ifunc-18b-i386.d: Likewise.
	* ifunc-19a-i386.d: Likewise.
	* ifunc-19b-i386.d: Likewise.
	* ifunc-2-i386-now.d: Likewise.
	* ifunc-2-i386.d: Likewise.
	* ifunc-2-local-i386-now.d: Likewise.
	* ifunc-2-local-i386.d: Likewise.
	* ifunc-20-i386.d: Likewise.
	* ifunc-21-i386.d: Likewise.
	* ifunc-22-i386.d: Likewise.
	* ifunc-5a-i386.d: Likewise.
	* ifunc-5a-local-i386.d: Likewise.
	* ifunc-5b-i386.d: Likewise.
	* ifunc-5b-local-i386.d: Likewise.
	* ifunc-5r-local-i386.d: Likewise.
	* ifunc-6a-i386.d: Likewise.
	* ifunc-6b-i386.d: Likewise.
	* ifunc-7a-i386.d: Likewise.
	* ifunc-7b-i386.d: Likewise.
	* ifunc-8-i386.d: Likewise.
	* ifunc-9-i386.d: Likewise.
	* pr17154-i386-now.d: Likewise.
	* pr17154-i386.d: Likewise.

	* ifunc-23a-x86.d: Remove notarget.
	* ifunc-24a-x86.d: Likewise.
	* ifunc-25a-x86.d: Likewise.

	gas:
	* testsuite/gas/elf/section12a.d: Use notarget instead of xfail.
	* testsuite/gas/elf/section12b.d: Likewise.
	* testsuite/gas/elf/section16a.d: Likewise.
	* testsuite/gas/elf/section16b.d: Likewise.

	binutils:
	* testsuite/lib/binutils-common.exp (supports_gnu_osabi): Don't
	enable on *-*-solaris*.
2020-04-02 10:52:57 +02:00
Gunther Nikl
59e28a9767 [PATCH gas/m68k] Fix a register range check
* config/tc-m68k.c (m68k_ip): Fix range check for index register
       with a suppressed address register.
2020-04-02 08:57:45 +01:00
H.J. Lu
efc3a95039 x86: Force relocation against local absolute symbol
Define TC_FORCE_RELOCATION_ABS to force relocation against local
absolute symbol.

	PR gas/25756
	* config/tc-i386.h (TC_FORCE_RELOCATION_ABS): New.
	* testsuite/gas/i386/localpic.s: Add a test for relocation
	against local absolute symbol.
	* testsuite/gas/i386/x86-64-localpic.s: Likewise.
	* testsuite/gas/i386/localpic.d: Updated.
	* testsuite/gas/i386/x86-64-localpic.d: Likewise.
	* testsuite/gas/i386/ilp32/x86-64-localpic.d: Likewise.
2020-04-01 05:41:06 -07:00
Rainer Orth
15d47c3a70 gas: Fix some x86_64 testcases for Solaris not using R_X86_64_PLT32 [PR25732]
As reported in PR gas/25732, some testcases currently FAIL on
Solaris/x86:

FAIL: x86-64 branch 2
FAIL: x86-64 branch 3
FAIL: x86-64 MPX branch
FAIL: x86-64 branch with BND prefix
FAIL: x86-64 jump

Since https://sourceware.org/ml/binutils/2019-03/msg00163.html, gas
doesn't emit R_X86_64_PLT32 as branch marker on Solaris.  Since the
testsuite lacks a way to preprocess dump files, adjusted copies of the
affected dumps are now used on Solaris.  Unfortunately, those dumps
weren't adapted when the original testcases were changed or other
testcases started to differ between non-Solaris and Solaris targets.

The following patch fixes that, re-syncing the affected dump files or
creating new Solaris-specific ones.

Tested on i386-pc-solaris2.11, x86_64-pc-solaris2.11,
x86_64-pc-linux-gnu, and i686-pc-linux-gnu.

	PR gas/25732
	* testsuite/gas/i386/solaris/x86-64-branch-2.d: New file.
	* testsuite/gas/i386/solaris/x86-64-branch-3.d: New file.
	* testsuite/gas/i386/solaris/x86-64-jump.d: Incorporate changes to
	testsuite/gas/i386/x86-64-jump.d.
	* gas/testsuite/gas/i386/solaris/x86-64-mpx-branch-1.d:
	Incorporate changes to
	gas/testsuite/gas/i386/x86-64-mpx-branch-1.d.
	* testsuite/gas/i386/solaris/x86-64-mpx-branch-2.d : Incorporate
	changes to testsuite/gas/i386/x86-64-mpx-branch-2.d.
	* testsuite/gas/i386/x86-64-branch-2.d: Skip on *-*-solaris*.
	* testsuite/gas/i386/x86-64-branch-3.d: Likewise.
2020-04-01 14:10:34 +02:00
Maciej W. Rozycki
876678f05e PR 25611, PR 25614: GAS: Remove a double inclusion of "bignum.h"
Correct an issue with commit 5496f3c635 ("Add support for generating
DWARF-5 format directory and file name tables from the assembler.") and
remove a duplicate direct inclusion of "bignum.h" from dwarf2dbg.c that
causes a GAS compilation error:

In file included from .../gas/dwarf2dbg.c:33:
.../gas/bignum.h:42: error: redefinition of typedef 'LITTLENUM_TYPE'
.../gas/bignum.h:42: error: previous declaration of 'LITTLENUM_TYPE' was here
make[4]: *** [dwarf2dbg.o] Error 1

with some GCC versions, as this header has been already included via
"as.h" and then "flonum.h".

	gas/
	PR 25611
	PR 25614
	* dwarf2dbg.c: Do not include "bignum.h".
2020-03-31 23:01:36 +01:00
Nelson Chu
d1a89da5de RISC-V: Update CSR to privileged spec 1.11.
gas/
	* testsuite/gas/riscv/alias-csr.d: Move this to priv-reg-pseudo.
	* testsuite/gas/riscv/alias-csr.s: Likewise.
	* testsuite/gas/riscv/no-aliases-csr.d: Move this
	to priv-reg-pseudo-noalias.
	* testsuite/gas/riscv/bad-csr.d: Rename to priv-reg-fail-nonexistent.
	* testsuite/gas/riscv/bad-csr.l: Likewise.
	* testsuite/gas/riscv/bad-csr.s: Likewise.
	* testsuite/gas/riscv/satp.d: Removed.  Already included in priv-reg.
	* testsuite/gas/riscv/satp.s: Likewise.
	* testsuite/gas/riscv/priv-reg-pseudo.d: New testcase for all pseudo
	csr instruction, including alias-csr testcase.
	* testsuite/gas/riscv/priv-reg-pseudo.s: Likewise.
	* testsuite/gas/riscv/priv-reg-pseudo-noalias.d: New testcase for all
	pseudo instruction with objdump -Mno-aliases.
	* testsuite/gas/riscv/priv-reg-fail-nonexistent.d: New testcase.
	* testsuite/gas/riscv/priv-reg-fail-nonexistent.l: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-nonexistent.s: Likewise.
	* testsuite/gas/riscv/priv-reg.d: Update CSR to 1.11.
	* testsuite/gas/riscv/priv-reg.s: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
	* testsuite/gas/riscv/csr-dw-regnums.d: Likewise.
	* testsuite/gas/riscv/csr-dw-regnums.s: Likewise.

	include/
	* opcode/riscv-opc.h: Update CSR to 1.11.

	gdb/
	* features/riscv/32bit-csr.xml: Regenerated.
	* features/riscv/64bit-csr.xml: Regenerated.
2020-03-30 12:24:53 -07:00
J.W. Jagersma
b778095777 The "b" flag for COFF sections only unsets the LOAD attribute. It should also clear the CONTENTS attribute so that named bss sections don't take up space in an object file. This can be achieved by setting the 'bss' flag in seg_info.
* config/obj-coff.c (obj_coff_section): Set the bss flag on
	sections with the "b" attribute.
2020-03-25 11:53:12 +00:00
Alan Modra
d1023b5d1e s12z disassembler tidy
Don't ignore buffer memory read failure, or malloc failure.  Lots of
functions get a return status to pass these failures up the chain in
this patch.

opcodes/
	* s12z-dis.c (abstract_read_memory): Don't print error on EOI.
	* s12z-opc.c: Formatting.
	(operands_f): Return an int.
	(opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
	(opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
	(shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
	(exg_sex_discrim): Likewise.
	(create_immediate_operand, create_bitfield_operand),
	(create_register_operand_with_size, create_register_all_operand),
	(create_register_all16_operand, create_simple_memory_operand),
	(create_memory_operand, create_memory_auto_operand): Don't
	segfault on malloc failure.
	(z_ext24_decode): Return an int status, negative on fail, zero
	on success.
	(x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
	(imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
	(z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
	(decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
	(ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
	(mov_imm_opr, ld_18bit_decode, exg_sex_decode),
	(loop_primitive_decode, shift_decode, psh_pul_decode),
	(bit_field_decode): Similarly.
	(z_decode_signed_value, decode_signed_value): Similarly.  Add arg
	to return value, update callers.
	(x_opr_decode_with_size): Check all reads, returning NULL on fail.
	Don't segfault on NULL operand.
	(decode_operation): Return OP_INVALID on first fail.
	(decode_s12z): Check all reads, returning -1 on fail.
gas/
	* testsuite/gas/s12z/truncated.d: Update expected output.
2020-03-22 23:20:15 +10:30
Sergey Belyashov
0d832e7f5e Add support for the xdef and xref pseudo-ops to the Z80 assembler.
PR 25690
	* config/tc-z80.c (md_pseudo_table): Add xdef anf xref pseudo ops.
	* doc/c-z80.texi: Update documentation.
2020-03-20 13:53:02 +00:00
Nick Clifton
327ef784ba Replace a couple of assertions in the BFD library that can be triggered by attempts to parse corrupt input files.
PR 25633
	* elf.c (_bfd_elf_copy_special_section_fields): Replace assertions
	with error messages.
2020-03-17 17:02:15 +00:00
Sergey Belyashov
68e52bc7ec Fix a small set of Z80 problems.
PR 25641
	PR 25668
	PR 25633
gas	Fix disassembling ED+A4/AC/B4/BC opcodes.
	Fix assembling lines containing colonless label and instruction
	with first operand inside parentheses.
	Fix registration of unsupported by target CPU registers.
	* config/tc-z80.c: See above.
	* config/tc-z80.h: See above.
	* testsuite/gas/z80/colonless.d: Update test.
	* testsuite/gas/z80/colonless.s: Likewise.
	* testsuite/gas/z80/ez80_adl_all.d: Likewise.
	* testsuite/gas/z80/ez80_unsup_regs.d: Likewise.
	* testsuite/gas/z80/ez80_z80_all.d: Likewise.
	* testsuite/gas/z80/gbz80_unsup_regs.d: Likewise.
	* testsuite/gas/z80/r800_unsup_regs.d: Likewise.
	* testsuite/gas/z80/unsup_regs.s: Likewise.
	* testsuite/gas/z80/z180_unsup_regs.d: Likewise.
	* testsuite/gas/z80/z80.exp: Likewise.
	* testsuite/gas/z80/z80_strict_unsup_regs.d: Likewise.
	* testsuite/gas/z80/z80_unsup_regs.d: Likewise.
	* testsuite/gas/z80/z80n_unsup_regs.d: Likewise.

opcodes	* z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
2020-03-17 16:55:32 +00:00
Andre Vieira
66d1f7cc12 gas, arm: PR25660L Fix vadd/vsub with lt and le condition codes for MVE
As explained in the PR, the addition of MVE makes the parser strip 't' and 'e'
as suffixes when MVE is enabled.  This leads to vadd and vsub in it blocks with
lt and le conditions to be initially parsed as vaddl and vsubl.  This means the
operand parsing for these must allow for the same operands as the scalar vadd
and vsub.  I had forgotten to do this and this patch remedies that oversight.

gas/ChangeLog:
2020-03-13  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	PR 25660
	*  config/tc-arm.c (operand_parse_code): Add OP_RNSDMQR and OP_oRNSDMQ.
	(parse_operands): Handle new operand codes.
	(do_neon_dyadic_long): Make shape check accept the scalar variants.
	(asm_opcode_insns): Fix operand codes for vaddl and vsubl.
	* testsuite/gas/arm/mve-vaddsub-it.s: New test.
	* testsuite/gas/arm/mve-vaddsub-it.d: New test.
	* testsuite/gas/arm/mve-vaddsub-it-bad.s: New test.
	* testsuite/gas/arm/mve-vaddsub-it-bad.l: New test.
	* testsuite/gas/arm/mve-vaddsub-it-bad.d: New test.
	* testsuite/gas/arm/nomve-vaddsub-it.d: New test.
2020-03-13 13:35:04 +00:00
H.J. Lu
9e8f1c9000 NEWS: Mention x86 assembler options for CVE-2020-0551
* NEWS: Mention x86 assembler options for CVE-2020-0551.
2020-03-11 09:57:35 -07:00
H.J. Lu
97b4a8f744 i386: Add tests for lfence with load/indirect branch/ret
Add tests for -mlfence-after-load=, -mlfence-before-indirect-branch=
and -mlfence-before-ret=.

	* testsuite/gas/i386/i386.exp: Run new tests.
	* testsuite/gas/i386/lfence-byte.d: New file.
	* testsuite/gas/i386/lfence-byte.e: Likewise.
	* testsuite/gas/i386/lfence-byte.s: Likewise.
	* testsuite/gas/i386/lfence-indbr-a.d: Likewise.
	* testsuite/gas/i386/lfence-indbr-b.d: Likewise.
	* testsuite/gas/i386/lfence-indbr-c.d: Likewise.
	* testsuite/gas/i386/lfence-indbr.e: Likewise.
	* testsuite/gas/i386/lfence-indbr.s: Likewise.
	* testsuite/gas/i386/lfence-load.d: Likewise.
	* testsuite/gas/i386/lfence-load.s: Likewise.
	* testsuite/gas/i386/lfence-ret-a.d: Likewise.
	* testsuite/gas/i386/lfence-ret-b.d: Likewise.
	* testsuite/gas/i386/lfence-ret.s: Likewise.
	* testsuite/gas/i386/x86-64-lfence-byte.d: Likewise.
	* testsuite/gas/i386/x86-64-lfence-byte.e: Likewise.
	* testsuite/gas/i386/x86-64-lfence-byte.s: Likewise.
	* testsuite/gas/i386/x86-64-lfence-indbr-a.d: Likewise.
	* testsuite/gas/i386/x86-64-lfence-indbr-b.d: Likewise.
	* testsuite/gas/i386/x86-64-lfence-indbr-c.d: Likewise.
	* testsuite/gas/i386/x86-64-lfence-indbr.e: Likewise.
	* testsuite/gas/i386/x86-64-lfence-indbr.s: Likewise.
	* testsuite/gas/i386/x86-64-lfence-load.d: Likewise.
	* testsuite/gas/i386/x86-64-lfence-load.s: Likewise.
	* testsuite/gas/i386/x86-64-lfence-ret-a.d: Likewise.
	* testsuite/gas/i386/x86-64-lfence-ret-b.d: Likewise.
2020-03-11 09:49:13 -07:00
H.J. Lu
ae531041c7 i386: Generate lfence with load/indirect branch/ret [CVE-2020-0551]
Add 3 command-line options to generate lfence for load, indirect near
branch and ret to help mitigate:

https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00334.html
http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2020-0551

1. -mlfence-after-load=[no|yes]:
  -mlfence-after-load=yes generates lfence after load instructions.
2. -mlfence-before-indirect-branch=[none|all|memory|register]:
  a. -mlfence-before-indirect-branch=all generates lfence before indirect
  near branches via register and a warning before indirect near branches
  via memory.
  b. -mlfence-before-indirect-branch=memory issue a warning before
  indirect near branches via memory.
  c. -mlfence-before-indirect-branch=register generates lfence before
  indirect near branches via register.
Note that lfence won't be generated before indirect near branches via
register with -mlfence-after-load=yes since lfence will be generated
after loading branch target register.
3. -mlfence-before-ret=[none|or|not]
  a. -mlfence-before-ret=or generates or with lfence before ret.
  b. -mlfence-before-ret=not generates not with lfence before ret.

A warning will be issued and lfence won't be generated before indirect
near branch and ret if the previous item is a prefix or a constant
directive, which may be used to hardcode an instruction, since there
is no clear instruction boundary.

	* config/tc-i386.c (lfence_after_load): New.
	(lfence_before_indirect_branch_kind): New.
	(lfence_before_indirect_branch): New.
	(lfence_before_ret_kind): New.
	(lfence_before_ret): New.
	(last_insn): New.
	(load_insn_p): New.
	(insert_lfence_after): New.
	(insert_lfence_before): New.
	(md_assemble): Call insert_lfence_before and insert_lfence_after.
	Set last_insn.
	(OPTION_MLFENCE_AFTER_LOAD): New.
	(OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH): New.
	(OPTION_MLFENCE_BEFORE_RET): New.
	(md_longopts): Add -mlfence-after-load=,
	-mlfence-before-indirect-branch= and -mlfence-before-ret=.
	(md_parse_option): Handle -mlfence-after-load=,
	-mlfence-before-indirect-branch= and -mlfence-before-ret=.
	(md_show_usage): Display -mlfence-after-load=,
	-mlfence-before-indirect-branch= and -mlfence-before-ret=.
	(i386_cons_align): New.
	* config/tc-i386.h (i386_cons_align): New.
	(md_cons_align): New.
	* doc/c-i386.texi: Document -mlfence-after-load=,
	-mlfence-before-indirect-branch= and -mlfence-before-ret=.
2020-03-11 09:46:19 -07:00