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1792 Commits

Author SHA1 Message Date
Maciej W. Rozycki 0067d8fc73 opcodes/ 
* mips-opc.c (mips_builtin_opcodes): Correct register use
	annotation of "alnv.ps".

	gas/testsuite/
	* gas/mips/alnv_ps-swap.d: New test for ALNV.PS instruction
	branch swapping.
	* gas/mips/alnv_ps-swap.s: Source for the new test.
	* gas/mips/mips.exp: Run the new test.
 2011-02-28 16:34:39 +00:00
Maciej W. Rozycki 3eebd5eb03 gas/ 
* config/tc-mips.c (macro): Handle M_PREF_AB.

	include/opcode/
	* mips.h (M_PREF_AB): New enum value.

	opcodes/
	* mips-opc.c (mips_builtin_opcodes): Add "pref" macro.
 2011-02-28 16:06:51 +00:00
Maciej W. Rozycki 89c0d58cff Swap ChangeLog entries. 2011-02-28 16:03:38 +00:00
Mike Frysinger 500cccad3b opcodes: blackfin: drop null/nul checks in OUTS 
Parts of the disassembler rely on the disasm info never being NULL (such
as being able to read memory to disassemble in the first place).  So drop
useless null checks in the OUTS helper.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
 2011-02-22 20:52:31 +00:00
Mike Frysinger f5caf9f434 opcodes: blackfin: use OUTS helper 
We have an OUTS helper to handle outf fprintf_func logic, so conver the
few places not using it over.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
 2011-02-22 20:51:42 +00:00
Mike Frysinger e5bc42655d opcodes: blackfin: clean up saved_state 
Mark the state static, punt unused members, unify indexable register
lookups, and abort when there is a register lookup failure.  Otherwise
we return NULL and the calling code assumes a valid pointer is returned.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
 2011-02-20 01:26:14 +00:00
Mike Frysinger 602427c4af opcodes: blackfin: fix style 
Non-functional thrashing to the GNU style.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
 2011-02-14 17:12:05 +00:00
Mike Frysinger 298c1ec2a0 opcodes: blackfin: catch invalid loopsetup insns 
The LoopSetup insn is only valid when the reg field is 0-7, so
don't go decoding it incorrectly when reg is 8-15.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
 2011-02-14 05:21:04 +00:00
Ralf Wildenhues 822ce8ee21 Remove freebsd1 from libtool.m4 macros and config.rpath. 
/:
	Import from Libtool and gnulib:

	2011-01-27  Gerald Pfeifer  <gerald@pfeifer.com>

	Prepare for supporting FreeBSD 10.
	* config.rpath: Remove handling of freebsd1* which soon would
	match FreeBSD 10.0.

	2011-01-20  Gerald Pfeifer  <gerald@pfeifer.com>  (tiny change)

	Remove support for FreeBSD 1.x.
	* libtool.m4 (_LT_LINKER_SHLIBS)
	(_LT_SYS_DYNAMIC_LINKER): Remove handling of freebsd1* which
	soon would incorrectly match FreeBSD 10.0.

bfd/:
	* configure: Regenerate.

gas/:
	* configure: Regenerate.

ld/:
	* configure: Regenerate.

opcodes/:
	* configure: Regenerate.

binutils/:
	* configure: Regenerate.

gprof/:
	* configure: Regenerate.
 2011-02-13 21:00:14 +00:00
Mike Frysinger 13c02f06ff opcodes: blackfin: fix decoding of ABS 
The single cycle dual mac ABS insn was incorrectly decoding the mac1
part of the insn.

Once we fix the decode, update the gas tests to have the correct output.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
 2011-02-13 18:55:22 +00:00
Mike Frysinger 4db6639409 opcodes: blackfin: fix decoding of dsp mult insns 
When assigning to a register half, the mac0 part of the mult insn
was not decoding properly.  It would always show a full dreg instead
of the dreg low half.

Once we fix the disassembler, we have to update a few of the gas
tests as their previous expected output was incorrect.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
 2011-02-13 18:54:49 +00:00
Mike Frysinger 36f446111a gas/opcodes: blackfin: punt BYTEOP2M insn support 
The BYTEOP2M insn was part of the initial Blackfin designs, but never made
it into any actual silicon.  So punt support for it.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
 2011-02-13 18:53:16 +00:00
Mike Frysinger 9805c0a5b6 opcodes: blackfin: add missing space after PRNT insn 
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
 2011-02-12 19:38:11 +00:00
Mike Frysinger 43a6aa65fe opcodes: blackfin: drop "GP" register 
There never was a "GP" register, so punt it from the decode map.  It's
a hold over from a very old processor definition and never made it into
actual silicon.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
 2011-02-12 19:37:32 +00:00
Mike Frysinger 26bb3ddd50 gas/opcodes: blackfin: move dsp mac func defines to common header 
The mmod field is decoded in a few places (gas/opcodes/sim), so move it to
a common place to avoid duplication.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
 2011-02-12 19:36:31 +00:00
Mike Frysinger 69b8ea4abd opcodes: blackfin: constify register names 
Constify the array itself since it need not be writable.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
 2011-02-11 19:03:27 +00:00
Michael Snyder 42d5f9c6ef 2011-02-09 Michael Snyder <msnyder@vmware.com> 
* i386-dis.c (OP_J): Parenthesize expression to prevent
	truncated addresses.
	(print_insn): Fix indentation off-by-one.
 2011-02-09 18:43:41 +00:00
Nick Clifton 4be0c94123 Updated Danish translation. 2011-02-01 13:14:40 +00:00
Alan Modra 6b069ee70d * ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS. 2011-01-21 00:53:11 +00:00
H.J. Lu e3949f17f3 Properly sign-extend byte. 
gas/testsuite/

2011-01-18  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/intel.d: Updated.
	* gas/i386/opcode-intel.d: Likewise.
	* gas/i386/opcode-suffix.d: Likewise.
	* gas/i386/opcode.d: Likewise.

opcodes/

2011-01-18  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (sIbT): New.
	(b_T_mode): Likewise.
	(dis386): Replace sIb with sIbT on "pushT".
	(x86_64_table): Replace sIb with Ib on "aam" and "aad".
	(OP_sI): Handle b_T_mode.  Properly sign-extend byte.
 2011-01-18 17:08:13 +00:00
Jan Kratochvil 752573b292 opcodes/ 
* i386-init.h: Regenerated.
	* i386-tbl.h: Regenerated.
 2011-01-18 14:14:46 +00:00
Quentin Neill 2a2a0f38e7 Add support for TBM instructions. 
gas/

2011-01-17  Quentin Neill  <quentin.neill@amd.com>

	* config/tc-i386.c (cpu_arch): Add CPU_TBM_FLAGS.

	* doc/c-i386.texi (i386-TBM): New section.

opcodes/

2011-01-17  Quentin Neill  <quentin.neill@amd.com>

	* i386-dis.c (REG_XOP_TBM_01): New.
	(REG_XOP_TBM_02): New.
	(reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
	(xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
	entries, and add bextr instruction.

	* i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
	(cpu_flags): Add CpuTBM.

	* i386-opc.h (CpuTBM) New.
	(i386_cpu_flags): Add bit cputbm.

	* i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk,
	blcs, blsfill, blsic, t1mskc, and tzmsk.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Regenerated

gas/testsuite

2011-01-17  Quentin Neill  <quentin.neill@amd.com>

	* gas/i386/tbm.s: New.
	* gas/i386/tbm.d: New.
	* gas/i386/tbm-intel.d: New.
	* gas/i386/x86-64-tbm.s: New.
	* gas/i386/x86-64-tbm.d: New.
	* gas/i386/x86-64-tbm-intel.d: New.
	* gas/i386/arch-10.d: Add tbm flag and TBM instruction pattern.
	* gas/i386/arch-10.s: Add a TBM instruction.
	* gas/i386/arch-10-1.l: Add TBM instruction pattern.
	* gas/i386/arch-10-2.l: Likewise.
	* gas/i386/arch-10-3.l: Likewise.
	* gas/i386/arch-10-4.l: Likewise.
	* gas/i386/x86-64-arch-2.s: Likewise.
	* gas/i386/x86-64-arch-2.d: Likewise.
 2011-01-17 18:40:36 +00:00
DJ Delorie 90d6ff629e * rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg. 2011-01-12 07:06:29 +00:00
Mingjie Xing c95354ed13 Take unadjusted offset for loongson3a specific instructions. 2011-01-11 07:22:09 +00:00
Nick Clifton f74656046a * po/da.po: Updated Danish translation. 2011-01-10 13:51:10 +00:00
Nathan Sidwell 639e30d297 gas/testsuite/ 
* gas/arm/blx-bad.s: New.
	* gas/arm/blx-bad.d: New.

	opcodes/
	* arm-dis.c (thumb32_opcodes): BLX must have bit zero clear.
 2011-01-06 14:30:43 +00:00
H.J. Lu f12dc42220 Implement BMI instructions. 2011-01-05 00:16:57 +00:00
H.J. Lu cb21baef77 Add VexGdq. 
2011-01-04  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (VexGdq): New.
	(OP_VEX): Handle dq_mode.
 2011-01-04 20:53:32 +00:00
H.J. Lu 4fb3aee212 Update copyright in comments to 2011. 2011-01-01 21:42:17 +00:00
H.J. Lu 0db46eb403 Update copyright to 2011. 
binutils/

2011-01-01  H.J. Lu  <hongjiu.lu@intel.com>

	* version.c (print_version): Update copyright to 2011.

gas/

2011-01-01  H.J. Lu  <hongjiu.lu@intel.com>

	* gas.c (parse_args): Update copyright to 2011.

gold/

2011-01-01  H.J. Lu  <hongjiu.lu@intel.com>

	* version.cc (print_version): Update copyright to 2011.

ld/

2011-01-01  H.J. Lu  <hongjiu.lu@intel.com>

	* ldver.c (ldversion): Update copyright to 2011.

opcodes/

2011-01-01  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (process_copyright): Update copyright to 2011.
 2011-01-01 20:55:48 +00:00
H.J. Lu 9e9e082043 Rotate binutils ChangeLogs. 2011-01-01 16:43:53 +00:00
Dave Anglin 3c853d9313 PR gas/11395 
* config/tc-hppa.c (pa_ip): Revert last change.  Add variable need_cond
	to determine whether a 64-bit condition is needed for 'A' and 'S'
	conditions.  Default to 32-bit never condition for logical and unit
	instructions.  Add error message for missing branch on bit condition.

	* hppa.h (pa_opcodes): Revert last change.  Exchange 32 and 64-bit
	"bb" entries.

	* hppa-dis.c (compare_cond_64_names): Change never condition to ",*".
	(add_cond_64_names): Likewise.
	(logical_cond_64_names): Likewise.
	(unit_cond_64_names): Likewise.
 2010-12-31 16:43:46 +00:00
H.J. Lu 351f65ca26 Add x86-64 ILP32 support. 
bfd/

2010-12-30  H.J. Lu  <hongjiu.lu@intel.com>

	* archures.c (bfd_mach_x64_32): New.
	(bfd_mach_x64_32_intel_syntax): Likewise.
	* bfd-in2.h: Regenerated.

	* config.bfd (targ64_selvecs): Add bfd_elf32_x86_64_vec for
	i[3-7]86-*-linux-*.
	(targ_selvecs): Add bfd_elf32_x86_64_vec for x86_64-*-linux-*.

	* configure.in: Support bfd_elf32_x86_64_vec.
	* configure: Regenerated.

	* cpu-i386.c (bfd_x64_32_arch_intel_syntax): New.
	(bfd_x64_32_arch): Likewise.

	* elf-bfd.h (elf_append_rela): New prototype.
	(elf_append_rel): Likewise.
	(elf64_r_info): Likewise.
	(elf32_r_info): Likewise.
	(elf64_r_sym): Likewise.
	(elf32_r_sym): Likewise.

	* elf64-x86-64.c (ABI_64_P): New.
	(elf_x86_64_info_to_howto): Replace ELF64_R_TYPE with
	ELF32_R_TYPE.  Replace ELF64_ST_TYPE with ELF_ST_TYPE.
	(elf_x86_64_check_tls_transition):Likewise.
	(elf_x86_64_check_relocs): Likewise.
	(elf_x86_64_gc_mark_hook):Likewise.
	(elf_x86_64_gc_sweep_hook): Likewise.
	(elf_x86_64_relocate_section): Likewise.
	(elf_x86_64_reloc_type_class): Likewise.
	(ELF_DYNAMIC_INTERPRETER): Renamed to ...
	(ELF64_DYNAMIC_INTERPRETER): This.
	(ELF32_DYNAMIC_INTERPRETER): New.
	(elf_x86_64_link_hash_table): Add r_info, r_sym, swap_reloca_out,
	dynamic_interpreter and dynamic_interpreter_size.
	(elf_x86_64_get_local_sym_hash): Replace ELF64_R_SYM with
	htab->r_sym.  Replace ELF64_R_INFO with htab->r_info.
	(elf_x86_64_get_local_sym_hash): Likewise.
	(elf_x86_64_check_tls_transition):Likewise.
	(elf_x86_64_check_relocs): Likewise.
	(elf_x86_64_gc_mark_hook):Likewise.
	(elf_x86_64_gc_sweep_hook): Likewise.
	(elf_x86_64_relocate_section): Likewise.
	(elf_x86_64_finish_dynamic_symbol): Likewise.
	(elf_x86_64_finish_local_dynamic_symbol): Likewise.
	(elf_x86_64_link_hash_table_create): Initialize r_info, r_sym,
	swap_reloca_out, dynamic_interpreter and dynamic_interpreter_size.
	(elf_x86_64_check_relocs): Check ABI_64_P when requesting for
	PIC.
	(elf_x86_64_relocate_section): Likewise.
	(elf64_x86_64_adjust_dynamic_symbol): Replace sizeof
	(Elf64_External_Rela) with bed->s->sizeof_rela.
	(elf64_x86_64_allocate_dynrelocs): Likewise.
	(elf64_x86_64_size_dynamic_sections): Likewise.
	(elf64_x86_64_finish_dynamic_symbol): Likewise.
	(elf64_x86_64_append_rela): Removed.
	(elf32_x86_64_elf_object_p): New.
	Add bfd_elf32_x86_64_vec.

	* elf64-x86-64.c (elf64_x86_64_xxx): Renamed to ...
	(elf_x86_64_xxx): This.

	* elflink.c (bfd_elf_final_link): Check ELF file class on error.
	(elf_append_rela): New.
	(elf_append_rel): Likewise.
	(elf64_r_info): Likewise.
	(elf32_r_info): Likewise.
	(elf64_r_sym): Likewise.
	(elf32_r_sym): Likewise.

	* targets.c (bfd_elf32_x86_64_vec): New.
	(_bfd_target_vector): Add bfd_elf32_x86_64_vec.

gas/

2010-12-30  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (x86_elf_abi): New.
	(i386_mach): Return bfd_mach_x64_32 for ILP32.
	(OPTION_N32): Likewise.
	(md_longopts): Add "n32" for ELF.
	(md_parse_option): Handle OPTION_N32.
	(md_show_usage): Add --n32.
	(i386_target_format): Update and check x86_elf_abi.

	* config/tc-i386.h (ELF_TARGET_FORMAT32): New.

	* doc/as.texinfo: Document --n32.
	* doc/c-i386.texi: Likewise.

gas/testsuite/

2010-12-30  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/ilp32/lns/ilp32.exp: New.
	* gas/i386/ilp32/lns/lns-common-1.d: Likewise.
	* gas/i386/ilp32/lns/lns-duplicate.d: Likewise.

	* gas/i386/ilp32/cfi/cfi-common-1.d: New.
	* gas/i386/ilp32/cfi/cfi-common-2.d: Likewise.
	* gas/i386/ilp32/cfi/cfi-common-3.d: Likewise.
	* gas/i386/ilp32/cfi/cfi-common-4.d: Likewise.
	* gas/i386/ilp32/cfi/cfi-common-5.d: Likewise.
	* gas/i386/ilp32/cfi/cfi-common-6.d: Likewise.
	* gas/i386/ilp32/cfi/cfi-common-7.d: Likewise.
	* gas/i386/ilp32/cfi/cfi-x86_64.d: Likewise.
	* gas/i386/ilp32/cfi/ilp32.exp: Likewise.
	* gas/i386/ilp32/elf/ehopt0.d: Likewise.
	* gas/i386/ilp32/elf/equ-reloc.d: Likewise.
	* gas/i386/ilp32/elf/file.d: Likewise.
	* gas/i386/ilp32/elf/group0a.d: Likewise.
	* gas/i386/ilp32/elf/group0b.d: Likewise.
	* gas/i386/ilp32/elf/group1a.d: Likewise.
	* gas/i386/ilp32/elf/group1b.d: Likewise.
	* gas/i386/ilp32/elf/ifunc-1.d: Likewise.
	* gas/i386/ilp32/elf/ilp32.exp: Likewise.
	* gas/i386/ilp32/elf/redef.d: Likewise.
	* gas/i386/ilp32/elf/section0.d: Likewise.
	* gas/i386/ilp32/elf/section1.d: Likewise.
	* gas/i386/ilp32/elf/section3.d: Likewise.
	* gas/i386/ilp32/elf/section4.d: Likewise.
	* gas/i386/ilp32/elf/section6.d: Likewise.
	* gas/i386/ilp32/elf/section7.d: Likewise.
	* gas/i386/ilp32/elf/struct.d: Likewise.
	* gas/i386/ilp32/elf/symtab.d: Likewise.
	* gas/i386/ilp32/elf/symver.d: Likewise.

	* gas/i386/ilp32/ilp32.exp: New.
	* gas/i386/ilp32/immed64.d: Likewise.
	* gas/i386/ilp32/mixed-mode-reloc64.d: Likewise.
	* gas/i386/ilp32/reloc64.d: Likewise.
	* gas/i386/ilp32/rex.d: Likewise.
	* gas/i386/ilp32/rexw.d: Likewise.
	* gas/i386/ilp32/svme64.d: Likewise.
	* gas/i386/ilp32/x86-64-addr32.d: Likewise.
	* gas/i386/ilp32/x86-64-addr32-intel.d: Likewise.
	* gas/i386/ilp32/x86-64-aes.d: Likewise.
	* gas/i386/ilp32/x86-64-aes-intel.d: Likewise.
	* gas/i386/ilp32/x86-64-amdfam10.d: Likewise.
	* gas/i386/ilp32/x86-64-arch-1.d: Likewise.
	* gas/i386/ilp32/x86-64-arch-2.d: Likewise.
	* gas/i386/ilp32/x86-64-avx.d: Likewise.
	* gas/i386/ilp32/x86-64-avx-intel.d: Likewise.
	* gas/i386/ilp32/x86-64-avx-swap.d: Likewise.
	* gas/i386/ilp32/x86-64-avx-swap-intel.d: Likewise.
	* gas/i386/ilp32/x86-64-branch.d: Likewise.
	* gas/i386/ilp32/x86-64-cbw.d: Likewise.
	* gas/i386/ilp32/x86-64-cbw-intel.d: Likewise.
	* gas/i386/ilp32/x86-64-clmul.d: Likewise.
	* gas/i386/ilp32/x86-64-clmul-intel.d: Likewise.
	* gas/i386/ilp32/x86-64-crc32.d: Likewise.
	* gas/i386/ilp32/x86-64-crc32-intel.d: Likewise.
	* gas/i386/ilp32/x86-64-crx.d: Likewise.
	* gas/i386/ilp32/x86-64-crx-suffix.d: Likewise.
	* gas/i386/ilp32/x86-64.d: Likewise.
	* gas/i386/ilp32/x86-64-disp.d: Likewise.
	* gas/i386/ilp32/x86-64-disp-intel.d: Likewise.
	* gas/i386/ilp32/x86-64-drx.d: Likewise.
	* gas/i386/ilp32/x86-64-drx-suffix.d: Likewise.
	* gas/i386/ilp32/x86-64-ept.d: Likewise.
	* gas/i386/ilp32/x86-64-ept-intel.d: Likewise.
	* gas/i386/ilp32/x86-64-fma4.d: Likewise.
	* gas/i386/ilp32/x86-64-fma.d: Likewise.
	* gas/i386/ilp32/x86-64-fma-intel.d: Likewise.
	* gas/i386/ilp32/x86-64-gidt.d: Likewise.
	* gas/i386/ilp32/x86-64-ifunc.d: Likewise.
	* gas/i386/ilp32/x86-64-intel64.d: Likewise.
	* gas/i386/ilp32/x86-64-io.d: Likewise.
	* gas/i386/ilp32/x86-64-io-intel.d: Likewise.
	* gas/i386/ilp32/x86-64-io-suffix.d: Likewise.
	* gas/i386/ilp32/x86-64-localpic.d: Likewise.
	* gas/i386/ilp32/x86-64-mem.d: Likewise.
	* gas/i386/ilp32/x86-64-mem-intel.d: Likewise.
	* gas/i386/ilp32/x86-64-movbe.d: Likewise.
	* gas/i386/ilp32/x86-64-movbe-intel.d: Likewise.
	* gas/i386/ilp32/x86-64-nops-1-core2.d: Likewise.
	* gas/i386/ilp32/x86-64-nops-1.d: Likewise.
	* gas/i386/ilp32/x86-64-nops-1-k8.d: Likewise.
	* gas/i386/ilp32/x86-64-nops-1-nocona.d: Likewise.
	* gas/i386/ilp32/x86-64-nops-1-pentium.d: Likewise.
	* gas/i386/ilp32/x86-64-nops-2.d: Likewise.
	* gas/i386/ilp32/x86-64-nops-3.d: Likewise.
	* gas/i386/ilp32/x86-64-nops-4-core2.d: Likewise.
	* gas/i386/ilp32/x86-64-nops-4.d: Likewise.
	* gas/i386/ilp32/x86-64-nops-4-k8.d: Likewise.
	* gas/i386/ilp32/x86-64-nops-5.d: Likewise.
	* gas/i386/ilp32/x86-64-nops-5-k8.d: Likewise.
	* gas/i386/ilp32/x86-64-nops.d: Likewise.
	* gas/i386/ilp32/x86-64-opcode.d: Likewise.
	* gas/i386/ilp32/x86-64-opcode-inval.d: Likewise.
	* gas/i386/ilp32/x86-64-opcode-inval-intel.d: Likewise.
	* gas/i386/ilp32/x86-64-opts.d: Likewise.
	* gas/i386/ilp32/x86-64-opts-intel.d: Likewise.
	* gas/i386/ilp32/x86-64-pcrel.d: Likewise.
	* gas/i386/ilp32/x86-64-reg.d: Likewise.
	* gas/i386/ilp32/x86-64-reg-intel.d: Likewise.
	* gas/i386/ilp32/x86-64-rep.d: Likewise.
	* gas/i386/ilp32/x86-64-rep-suffix.d: Likewise.
	* gas/i386/ilp32/x86-64-rip.d: Likewise.
	* gas/i386/ilp32/x86-64-rip-intel.d: Likewise.
	* gas/i386/ilp32/x86-64-sib.d: Likewise.
	* gas/i386/ilp32/x86-64-sib-intel.d: Likewise.
	* gas/i386/ilp32/x86-64-simd.d: Likewise.
	* gas/i386/ilp32/x86-64-simd-intel.d: Likewise.
	* gas/i386/ilp32/x86-64-simd-suffix.d: Likewise.
	* gas/i386/ilp32/x86-64-sse2avx.d: Likewise.
	* gas/i386/ilp32/x86-64-sse2avx-opts.d: Likewise.
	* gas/i386/ilp32/x86-64-sse2avx-opts-intel.d: Likewise.
	* gas/i386/ilp32/x86-64-sse3.d: Likewise.
	* gas/i386/ilp32/x86-64-sse4_1.d: Likewise.
	* gas/i386/ilp32/x86-64-sse4_1-intel.d: Likewise.
	* gas/i386/ilp32/x86-64-sse4_2.d: Likewise.
	* gas/i386/ilp32/x86-64-sse4_2-intel.d: Likewise.
	* gas/i386/ilp32/x86-64-sse-check.d: Likewise.
	* gas/i386/ilp32/x86-64-sse-check-none.d: Likewise.
	* gas/i386/ilp32/x86-64-sse-check-warn.d: Likewise.
	* gas/i386/ilp32/x86-64-sse-noavx.d: Likewise.
	* gas/i386/ilp32/x86-64-ssse3.d: Likewise.
	* gas/i386/ilp32/x86-64-stack.d: Likewise.
	* gas/i386/ilp32/x86-64-stack-intel.d: Likewise.
	* gas/i386/ilp32/x86-64-stack-suffix.d: Likewise.
	* gas/i386/ilp32/x86-64-unwind.d: Likewise.
	* gas/i386/ilp32/x86-64-vmx.d: Likewise.
	* gas/i386/ilp32/x86-64-xsave.d: Likewise.
	* gas/i386/ilp32/x86-64-xsave-intel.d: Likewise.

ld/

2010-12-30  H.J. Lu  <hongjiu.lu@intel.com>

	* emulparams/elf32_x86_64.sh: New.

	* configure.tgt (targ64_extra_emuls): Add elf32_x86_64 for
	i[3-7]86-*-linux-*.
	(targ_extra_libpath): Likewise.
	(targ_extra_emuls): Add elf32_x86_64 for x86_64-*-linux-*.
	(targ_extra_libpath): Likewise.

	* Makefile.am (ALL_64_EMULATION_SOURCES): Add eelf32_x86_64.c.
	(eelf32_x86_64.c): New.
	* Makefile.in: Regenerated.

opcodes/

2010-12-30  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (print_insn): Support bfd_mach_x64_32 and
	bfd_mach_x64_32_intel_syntax.
 2010-12-31 00:33:36 +00:00
Richard Sandiford 9867540240 include/opcode/ 
2010-12-14  Mingjie Xing  <mingjie.xing@gmail.com>

	* mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
	(OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
	(INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.

opcodes/
2010-12-14  Mingjie Xing  <mingjie.xing@gmail.com>

	* mips-opc.c (WR_z, WR_Z, RD_z, RD_Z, RD_d): Define.
	(mips_builtin_opcodes): Add loongson3a specific instructions.
	* mips-dis.c (print_insn_args): Handle the new arguments +a|b|c|z|Z.

gas/
2010-12-14  Mingjie Xing  <mingjie.xing@gmail.com>

	* config/tc-mips.c (insn_uses_reg): Handle the new flags
	INSN2_READ_FPR_Z, INSN2_READ_GPR_D and INSN2_READ_GPR_Z.
	(append_insn): Handle delay-slot filling for the new flags.
	(validate_mips_insn): Handle the new arguments +a|b|c|z|Z.
	(mips_ip): Handle the new arguments +a|b|c|z|Z.

gas/testsuite/
2010-12-14  Mingjie Xing  <mingjie.xing@gmail.com>

	* gas/mips/loongson-3a-2.s, gas/mips/loongson-3a-2.d,
	gas/mips/loongson-3a-3.s, gas/mips/loongson-3a-3.d: New tests.
	* gas/mips/mips.exp: Run them.
 2010-12-18 11:14:14 +00:00
Richard Sandiford a471ec3a5c opcodes/ 
2010-12-03 Mingming Sun <mingm.sun@gmail.com>

	* mips-opc.c: (mips_builtin_opcodes): Add loongson3a mul/div and
	fixed point instructions.

gas/testsuite/
2010-12-03 Mingming Sun <mingm.sun@gmail.com>

	* gas/mips/loongson-3a.s, gas/mips/loongson-3a.d: New test.
	* gas/mips/mips.exp: Run it.
 2010-12-11 10:48:55 +00:00
Mike Frysinger 8b9a522f57 bfd/binutils/gas/gprof/ld/libiberty/opcodes: add .gitignore 
This seems to cover a few random targets as well as --enable-targets=all.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
 2010-12-09 09:03:18 +00:00
Alan Modra 1de34e0afe Update translations 2010-11-25 06:08:52 +00:00
Nick Clifton fd50354116 bfd/ 
* archures.c (bfd_mach_mips_loongson_3a): Defined.
	* bfd-in2.h (bfd_mach_mips_loongson_3a): Defined.
	* cpu-mips.c (I_loongson_3a): New add.
	(arch_info_struct): Add loongson_3a.
	* elfxx-mips.c (_bfd_elf_mips_mach): Add loongson_3a.
	(mips_set_isa_flags): Add loongson_3a.
	(mips_mach_extensions): Add loongson_3a in MIPS64 extensions.

	binutils/
	* readelf.c (get_machine_flags): Add loongson-3a.

	gas/
	* config/tc-mips.c (mips_cpu_info_table): Add loongson3a in MIPS 64.
	* doc/c-mips.texi (MIPS cpu): Add loongson3a.

	include/
	* elf/mips.h (E_MIPS_MACH_LS3A): Defined.
	* opcode/mips.h (INSN_LOONGSON_3A): Defined.
	(CPU_LOONGSON_3A): Defined.
	(OPCODE_IS_MEMBER): Add LOONGSON_3A.

	opcodes/
	* mips-dis.c (mips_arch_choices): Add loongson3a.
	* mips-opc.c (IL3A): Defined as INSN_LOONGSON_3A.
	(mips_builtin_opcodes): Modify some instructions' membership from
	IL2F to IL2F|IL3A, since these instructions are supported by Loongson_3A.
 2010-11-11 10:23:39 +00:00
Nick Clifton 8e295ce05a Updated translations. 2010-11-10 14:39:10 +00:00
Tristan Gingold 2ee0aedfb8 bfd/ 
2010-11-05  Tristan Gingold  <gingold@adacore.com>

	* po/bfd.pot: Regenerate

binutils/
2010-11-05  Tristan Gingold  <gingold@adacore.com>

	* po/binutils.pot: Regenerate

gas/
2010-11-05  Tristan Gingold  <gingold@adacore.com>

	* po/gas.pot: Regenerate
	* po/POTFILES.in: Regenerate

gprof/
2010-11-05  Tristan Gingold  <gingold@adacore.com>

	* po/gprof.pot: Regenerate

ld/
2010-11-05  Tristan Gingold  <gingold@adacore.com>

	* po/ld.pot: Regenerate
	* po/POTFILES.in: Regenerate

opcodes/
2010-11-05  Tristan Gingold  <gingold@adacore.com>

	* po/opcodes.pot: Regenerate
 2010-11-05 10:25:11 +00:00
Maciej W. Rozycki af47889861 * mips-opc.c (mips_builtin_opcodes): Fix formatting of "ld". 2010-10-28 13:49:51 +00:00
Andreas Krebbel be7a250d1a 2010-10-28 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> 
* config/tc-s390.c (md_begin): Only add to hash table if cpu and
	mode mask fit.

2010-10-28  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>

	* s390-opc.txt: cfxr, cfdr and cfer z900 -> g5.
 2010-10-28 07:37:45 +00:00
Chao-ying Fu d958d1a369 2010-10-25 Chao-ying Fu <fu@mips.com> 
* mips-opc.c (madd, maddu, msub, msubu, mult, multu): Change D33 to D32.
 2010-10-25 18:09:10 +00:00
Nathan Sidwell c0621d88b0 bfd/ 
* elf32-tic6x.c: Add attribution.

	gas/
	* config/tc-tic6x.c: Add attribution.

	opcodes/
	* tic6x-dis.c: Add attribution.
 2010-10-25 15:33:54 +00:00
Alan Modra a43817dfc9 * Makefile.am (CLEANFILES): Add stamp-lm32. Sort. 
* Makefile.in: Regenerate.
 2010-10-21 23:50:57 +00:00
Maciej W. Rozycki 704897fbef opcodes/ 
* mips-opc.c (mips_builtin_opcodes): Move M_LD_OB and M_SD_OB
	macros before their corresponding MIPS III hardware instructions.

	gas/
	* config/tc-mips.c (macro)[M_LD_OB, M_SD_OB]: Handle 64-bit ABIs.

	gas/testsuite/
	* gas/mips/lineno.s: Convert to o32.
	* gas/mips/lineno.d: Adjust patterns accordingly.  Force the o32
	ABI.
 2010-10-18 00:15:35 +00:00
H.J. Lu da98bb4c74 Add CpuNop to CPU_GENERIC64_FLAGS. 
gas/testsuite/

2010-10-16  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/i386.exp: Run x86-64-nops-1-g64.

	* gas/i386/x86-64-nops-1.d: Remove -mtune=generic64.

	* gas/i386/x86-64-nops-1-g64.d: New.

opcodes/

2010-10-16  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Add CpuNop to CPU_GENERIC64_FLAGS.

	* i386-init.h: Regenerated.
 2010-10-16 21:53:16 +00:00
Mike Frysinger e1791cb8b5 gas: blackfin: fix encoding of BYTEOP2M insn 
The BYTEOP2M parser incorrectly calls BYTEOP2P to generate the opcode.
Once we've fixed that, it's easy to see that the disassembler also likes
to decode this insn incorrectly.  So fix that and then add some tests.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
 2010-10-15 20:44:46 +00:00
H.J. Lu 553d0a7447 Remove CheckRegSize from movq. 
2010-10-14  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Remove CheckRegSize from movq.
	* i386-tbl.h: Regenerated.
 2010-10-14 23:16:19 +00:00
H.J. Lu cfc08d490e Remove CheckRegSize from instructions with 0, 1 or fixed operands. 
2010-10-14  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Remove CheckRegSize from instructions with
	0, 1 or fixed operands.
	* i386-tbl.h: Regenerated.
 2010-10-14 21:37:30 +00:00