OpenE2K
/
binutils-gdb
12
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity
17,802 Commits 4 Branches 0 Tags 364 MiB
Commit Graph

468 Commits

Author SHA1 Message Date
Jeff Law ba8ed10c7e * mn10300-opc.c (FMT*): Remove definitions. 
Moved into opcode/mn10300.h
 1996-10-10 20:31:06 +00:00
Jeff Law 1e5ddd3be4 * mn10300-opc.c (mn10300_opcodes): Fix destination register 
for shift-by-register opcodes.
Bug found by testsuite.
 1996-10-10 19:08:46 +00:00
Jeff Law 36b34aa4a9 * mn10300-opc.c (mn10300_operands): Break DN, DM, AN, AM 
into [AD][MN][01] for encoding the position of the register
        in the opcode.
Matsushita.
 1996-10-10 16:28:14 +00:00
Jeff Law 344d6417bb * mn10300-opc.c (mn10300_opcodes): Add "extended" instructions, 
"putx", "getx", "mulq", "mulqu", "sat16", "sat24", "bsch".
Matsushita.
 1996-10-09 17:20:59 +00:00
Jeff Law db22905430 * mn10300-opc.c (mn10300_operands): Remove "REGS" operand. 
Fix various typos.  Add "PAREN" operand.
        (MEM, MEM2): Define.
        (mn10300_opcodes): Surround all memory addresses with "PAREN"
        operands.  Fix several typos.
Should parse all opcodes in the instruction specification, except the
"user extension instructions".
 1996-10-08 21:09:57 +00:00
Jeff Law 06b796584d * mn10300-opc.c (mn10300_opcodes): Fix typos in yesterday's 
changes.
Matsushita.
 1996-10-08 17:56:40 +00:00
Jeff Law 5ab7bce62d * mn10300-opc.c (FMT_XX): Renumber starting at one. 
(mn10300_operands): Rough cut.  Enough to parse "mov" instructions
        at this time.
        (mn10300_opcodes): Break opcode format out into its own field.
        Update many operand fields to deal with signed vs unsigned
        issues.  Fix one or two typos in the "mov" instruction
        opcode, mask and/or operand fields.
Checkpointing today's work.  Matsushita.
 1996-10-07 22:52:18 +00:00
Ian Lance Taylor 6ba7ecd4eb Mon Oct 7 11:39:49 1996 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> 
* m68k-opc.c (plusha): Prefer encoding for m68040up, in case
	m68851 wasn't reset.
 1996-10-07 15:41:56 +00:00
Jeff Law 99777c0bfb * mn10300-opc.c (mn10300_opcodes): Add opcode & masks for 
all opcodes.  Very rough cut at operands for all opcodes.
Matsushita.
 1996-10-04 22:02:43 +00:00
Jeff Law cd8a9026b9 * mn10300-opc.c (mn10300_opcodes): Start fleshing out the 
opcode table.
Checkpointint 10300 work.
 1996-10-04 19:20:19 +00:00
Ian Lance Taylor 6c9370db2a * Makefile.in (ALL_MACHINES): Add mn10200-dis.o, mn10200-opc.o, 
mn10300-dis.o, and mn10300-opc.o.
Also add d10v and v850 files, with appropriate sanitization.
 1996-10-03 21:17:46 +00:00
Jeff Law ae1b99e42d Grrr. The mn10200 and mn10300 are _not_ similar enough to easily support 
with a single generic configuration.  So break them up into two different
configurations.  See the individual ChangeLogs for additional detail.
 1996-10-03 16:42:22 +00:00
Jason Molenda 42b4add910 * Makefile.in (MOSTLYCLEAN): Move config.log to distclean. 1996-10-03 06:58:15 +00:00
Jeff Law e7c50ceffd * mn10x00-opc.c, mn10x00-dis.c: New files for Matsushita 
MN10x00 processors.
        * disassemble (ARCH_mn10x00): Define.
        (disassembler): Handle bfd_arch_mn10x00.
        * configure.in: Recognize bfd_mn10x00_arch.
        * configure: Rebuilt.
Continue stubbing out for Matsushita work.
 1996-10-03 05:31:01 +00:00
Jeff Law 072b27ea5e Add missing copyright. 1996-10-03 04:48:16 +00:00
Ian Lance Taylor a5cb84dd6f * i386-dis.c (op_rtn): Change to be a pointer. Adjust uses 
accordingly.  Don't declare functions using op_rtn.
Remove ANSI C constructs.
 1996-10-01 14:50:19 +00:00
Ian Lance Taylor 800bda836e * mips-opc.c: Add a case for "div" and "divu" with two registers 
and a destination of $0.
PR 10654.
 1996-09-17 16:07:41 +00:00
Fred Fish d7deed257c * mips-dis.c (print_insn_arg): Add prototype. 
(_print_insn_mips): Ditto.
 1996-09-11 04:26:58 +00:00
Ian Lance Taylor 30b1724cc8 * mips-dis.c (print_insn_arg): Print condition code registers as 
$fccN.
 1996-09-09 18:27:10 +00:00
Jeff Law eb5c28e173 * v850-dis.c (disassemble): Make static. Provide prototype. 1996-09-03 18:05:25 +00:00
Ian Lance Taylor 44789bee66 whoops--typo 1996-09-02 16:41:29 +00:00
Ian Lance Taylor 01d34e4be3 file was really removed a long time ago 1996-09-02 16:41:28 +00:00
Jeff Law 09478dc331 * v850-dis.c (disassemble): Handle insertion of ',', '[' and 
']' characters into the output stream.
        * v850-opc.c (v850_opcodes: Remove size field from all opcodes.
        Add "memop" field to all opcodes (for the disassembler).
        Reorder opcodes so that "nop" comes before "mov" and "jr"
        comes before "jarl".
Should give us a functional disassembler.
 1996-08-31 22:00:45 +00:00
Jeff Law e05cae190b * v850-dis.c (print_insn_v850): Properly handle disassembling 
a two byte insn at the end of a memory region when the memory
        region's size is only two byte aligned.
 1996-08-31 21:21:27 +00:00
Jeff Law a5f2a4e50e * v850-dis.c (v850_cc_names): Fix stupid thinkos. 1996-08-31 21:10:43 +00:00
Jeff Law 502535cff7 * v850-dis.c (v850_reg_names): Define. 
(v850_sreg_names, v850_cc_names): Likewise.
        (disassemble): Very rough cut at printing operands (unformatted).
One step at a time.

        * v850-opc.c (BOP_MASK): Fix.
        (v850_opcodes): Fix mask for jarl and jr.
Bugs exposed by disassembler testing.
 1996-08-31 20:56:05 +00:00
Jeff Law 529418ddc4 * v850-dis.c: New file. Skeleton for disassembler support. 
* Makefile.in Remove v850 references, they're not needed here
        and they weren't being sanitized away.
        * configure.in: Add v850-dis.o when building v850 toolchains.
        * configure: Rebuilt.
        * disassemble.c (disassembler): Call v850 disassembler.
 1996-08-31 19:22:11 +00:00
Jeff Law ba39d3dde1 * v850-dis.c: New file. Skeleton for disassembler support. 
* Makefile.in Remove v850 references, they're not needed here
        and they weren't being sanitized away.
        * configure.in: Add v850-dis.o when building v850 toolchains.
        * configure: Rebuilt.
        * disassemble.c (disassembler): Call v850 disassembler.
Skeleton support for V850 disassembler.
 1996-08-31 19:20:28 +00:00
Jeff Law b219416478 * v850-opc.c (insert_d8_7, extract_d8_7): New functions. 
(insert_d8_6, extract_d8_6): New functions.
        (v850_operands): Rename D7S to D7; operand for D7 is unsigned.
        Rename D8 to D8_7, use {insert,extract}_d8_7 routines.
        Add D8_6.
        (IF4A, IF4B): Use "D7" instead of "D7S".
        (IF4C, IF4D): Use "D8_7" instead of "D8".
        (IF4E, IF4F): New.  Use "D8_6".
        (v850_opcodes): Use IF4A/IF4B for sld.b/sst.b.  Use IF4C/IF4D for
        sld.h/sst.h.  Use IF4E/IF4F for sld.w/sst.w.
So we can assemble sst/sld instructions correctly.
 1996-08-31 18:23:02 +00:00
Jeff Law c6b9c13532 * v850-opc.c (insert_d16_15, extract_d16_15): New functions. 
(v850_operands): Change D16 to D16_15, use special insert/extract
        routines.  New new D16 that uses the generic insert/extract code.
        (IF7A, IF7B): Use D16_15.
        (IF7C, IF7D): New.  Use D16.
        (v850_opcodes): Use IF7C and IF7D for ld.b and st.b.
 1996-08-31 17:43:28 +00:00
Jeff Law fb8c25a3e4 * v850-opc.c (insert_d9, insert_d22): Slightly improve error 
message.  Issue an error if the branch offset is odd.
 1996-08-31 17:23:49 +00:00
Jeff Law 69ae4b82dc * v850-opc.c: Add notes about needing special insert/extract 
for all the load/store insns, except "ld.b" and "st.b".
So we don't forget!
 1996-08-31 07:32:01 +00:00
Jeff Law 574b9cb3d3 * v850-opc.c (insert_d22, extract_d22): New functions. 
(v850_operands): Use insert_d22 and extract_d22 for
        D22 operands.
        (insert_d9): Fix range check.
 1996-08-31 07:28:22 +00:00
J.T. Conklin d44b697b78 * v850-opc.c (v850_operands): Add V850_OPERAND_SIGNED flag 
and set bits field to D9 and D22 operands.
 1996-08-31 01:04:39 +00:00
Jeff Law e9ebb36451 * v850-opc.c (v850_operands): Define SR2 operand. 
(v850_opcodes): "ldsr" uses R1,SR2.
ldsr is kinda weird.
 1996-08-30 19:44:42 +00:00
Jeff Law e7f3e5fbbf * v850-opc.c (v850_opcodes): Fix opcode specs for 
sld.w, sst.b, sst.h, sst.w, and nop.
 1996-08-29 17:11:13 +00:00
Jeff Law e7dd77751d * v850-opc.c (v850_opcodes): Add null opcode to mark the 
end of the opcode table.
For the simulator
 1996-08-28 21:56:03 +00:00
J.T. Conklin c6d5c52650 Remove v850-opc.c from things-to-keep 1996-08-26 17:36:45 +00:00
Jeff Law d3edb57f12 * v850-opc.c (v850_operands): Define EP operand. 
(IF4A, IF4B, IF4C, IF4D): Use EP.
 1996-08-23 20:55:15 +00:00
Jeff Law 18c97701b4 * v850-opc.c (v850_opcodes): Fix opcode numbers for "mov" 
with immediate operand, "movhi".  Tweak "ldsr".
More fixes.
 1996-08-23 20:27:25 +00:00
Jeff Law fb6da8680e * v850-opc.c (v850_opcodes): Get ld.[bhw] and st.[bhw] 
correct.  Get sld.[bhw] and sst.[bhw] closer.
 1996-08-23 19:32:41 +00:00
Jeff Law 38c7a4504d * v850-opc.c (v850_operands): "not" is a two byte insn. 1996-08-23 19:12:05 +00:00
Jeff Law 6c1fc4d3fa * v850-opc.c (v850_opcodes): Correct bit pattern for setf. 1996-08-23 18:58:57 +00:00
Jeff Law 9ab069eadc * v850-opc.c (v850_operands): D16 inserts at offset 16! 1996-08-23 18:27:43 +00:00
Jeff Law b1e897a97d * v850-opc.c (two): Get order of words correct. 1996-08-23 18:17:31 +00:00
Jeff Law 9ad8ddf1bd * v850-opc.c (v850_operands): I16 inserts at offset 16! 
Should get immediate 16bit operands into the right place
 1996-08-23 17:52:00 +00:00
Jeff Law e41c99bd11 * v850-opc.c (v850_operands): Add "SR1" and "SR2" for system 
register source and destination operands.
        (v850_opcodes): Use SR1 and SR2 for "ldsr" and "stsr".
More parsing fixes.
 1996-08-23 17:35:11 +00:00
Jeff Law c262d7d8f4 * v850-opc.c (v850_opcodes): Fix thinko in "jmp" opcode. Fix 
same thinko in "trap" opcode.
 1996-08-23 17:09:28 +00:00
Jeff Law 85b5201342 * v850-opc.c (v850_opcodes): Fix thinko in "jmp" opcode. 1996-08-23 17:07:21 +00:00
Jeff Law 280d40df39 * v850-opc.c (v850_opcodes): Add initializer for size field 
on all opcodes.
 1996-08-23 16:40:15 +00:00
Jeff Law 4be84c4951 * v850-opc.c (v850_operands): D6 -> DS7. References changed. 
Add D8 for 8-bit unsigned field in short load/store insns.
        (IF4A, IF4D): These both need two registers.
        (IF4C, IF4D): Define.  Use 8-bit unsigned field.
        (v850_opcodes): For "sld.h", "sld.w", "sst.h", "sst.w", use
        IF4C & IF4D.  For "trap" use I5U, not I5.  Add IF1 operand
        for "ldsr" and "stsr".
        * v850-opc.c (v850_operands): 3-bit immediate for bit insns
        is unsigned.
Fixing up the parser again.
 1996-08-23 15:41:30 +00:00
Jeff Law 3c72ab7035 * v850-opc.c (v850_operansd): 3-bit immediate for bit insns 
is unsigned.
 1996-08-23 06:56:44 +00:00
J.T. Conklin dbc6a8f6b3 Add V850_OPERAND_SIGNED flag as appropriate, create new unsigned IMM5 operand 1996-08-23 06:29:55 +00:00
Jeff Law cc6e50b5b2 * v850-opc.c (v850_opcodes): Correct short store half (sst.h) and 
short store word (sst.w).
 1996-08-23 06:27:37 +00:00
J.T. Conklin 4f23511029 start writing functions for extracting and inserting unusual operands 1996-08-23 02:35:16 +00:00
J.T. Conklin 69463cbb2b * v850-opc.c (v850_operands): Added insert and extract fields, 
pointers to functions that handle unusual operand encodings.
 1996-08-23 00:00:18 +00:00
Jeff Law 9c201b1fab * v850-opc.c (v850_opcodes): Enable "trap". 1996-08-22 23:08:03 +00:00
Jeff Law 0bdf3144c6 * v850-opc.c (v850_opcodes): Fix order of displacement 
and register for "set1", "clr1", "not1", and "tst1".
 1996-08-22 07:06:13 +00:00
J.T. Conklin 088d5b7309 minimal setf support 1996-08-22 06:33:27 +00:00
J.T. Conklin e89a42c117 Stub in load and store insns. Fix order of jarl operands 1996-08-22 05:29:14 +00:00
Jeff Law fa6761106f Arggh. B3. shift counts are from the start of each half-word apparently. 1996-08-22 02:20:08 +00:00
Jeff Law 4cd595fcdd Fix thinko in B3. 1996-08-22 02:18:07 +00:00
Jeff Law 7c8157dd48 * v850-opc.c (v850_operands): Add "B3" support. 
(v850_opcodes): Fix and enable "set1", "clr1", "not1"
        and "tst1".
 1996-08-22 02:08:02 +00:00
Jeff Law fed1d21fc0 * v850-ope.c ("jmp"): R1 is only operand. 1996-08-22 01:39:22 +00:00
Jeff Law b10e29f4b8 * v850-opc.c: Close unterminated comment. 
Something -Wall caught.
 1996-08-22 00:46:47 +00:00
J.T. Conklin 6bc33c7fa5 * v850-opc.c: Add flags field to struct v850_operands, add move 
opcodes to opcode table.
 1996-08-22 00:35:28 +00:00
J.T. Conklin 6d1e1ee875 * Makefile.in (ALL_MACHINES): Add v850-opc.o. 
* configure: (bfd_v850v_arch) Add new case.
* configure.in: (bfd_v850_arch) Add new case.
* v850-opc.c: New file.
 1996-08-20 21:45:02 +00:00
David Edelsohn 5751b0d72d * sparc-dis.c (print_insn_sparc): Handle little endian sparcs. 1996-08-19 22:22:11 +00:00
Stan Shebs a952ea1cb8 * mpw-make.sed: Update editing of include pathnames to be 
more general.
 1996-08-15 20:13:38 +00:00
Jackie Smith Cashion 5247a22a88 Thu Aug 15 16:28:41 1996 James G. Smith <jsmith@cygnus.co.uk> 
* arm-opc.h: Added "bx" instruction definition.
 1996-08-15 15:29:41 +00:00
Ian Lance Taylor 375d76efcc Wed Aug 14 17:00:04 1996 Richard Henderson <rth@tamu.edu> 
* alpha-opc.c (EV4EXTHWINDEX): Field width should be 8 not 5.
 1996-08-15 00:01:21 +00:00
Martin Hunt ed36b6cd33 Mon Aug 12 14:30:37 1996 Martin M. Hunt <hunt@pizza.cygnus.com> 
* d10v-opc.c (d10v_opcodes): Minor fixes to addi and bl.l.
 1996-08-12 21:32:03 +00:00
Martin Hunt cff827d7df Fri Aug 9 13:21:59 1996 Martin M. Hunt <hunt@pizza.cygnus.com> 
* d10v-opc.c (d10v_opcodes): Correct 'mv' unit entry to EITHER.
 1996-08-09 20:25:12 +00:00
Ian Lance Taylor 0f38eaa09f Thu Aug 8 12:43:52 1996 Klaus Kaempf <kkaempf@progis.de> 
* makefile.vms: Update for alpha-opc changes.
 1996-08-08 16:45:05 +00:00
Ian Lance Taylor 484c464505 * i386-dis.c (print_insn_i386): Actually return the correct value. 
(ONE, OP_ONE): #ifdef out; not used.
 1996-08-07 15:56:13 +00:00
Martin Hunt c5e1996f55 Fri Aug 2 17:47:03 1996 Martin M. Hunt <hunt@pizza.cygnus.com> 
* d10v-opc.c (d10v_operands): Added 2 accumulator sub instructions.
	Changed subi operand type to treat 0 as 16.
 1996-08-03 00:49:00 +00:00
Ian Lance Taylor 82e8213e4e * m68k-opc.c: Add cpushl for the mcf5200. From Ken Rose 
<rose@netcom.com>.
 1996-07-31 20:22:50 +00:00
Jackie Smith Cashion 50569deeb5 Wed Jul 31 14:39:27 1996 James G. Smith <jsmith@cygnus.co.uk> 
* arm-opc.h: (arm_opcodes): Added halfword and sign-extension
 	memory transfer instructions. Add new format string entries %h and %s.
	* arm-dis.c: (print_insn_arm): Provide decoding of the new
	formats %h and %s.
 1996-07-31 13:43:51 +00:00
Martin Hunt 3dd5a8d337 Fri Jul 26 11:45:04 1996 Martin M. Hunt <hunt@pizza.cygnus.com> 
* d10v-opc.c (d10v_operands): Added UNUM4S; a 4-bit accumulator shift.
 	(d10v_opcodes): Modified accumulator shift instructions to use UNUM4S.
 1996-07-26 18:59:21 +00:00
Ian Lance Taylor 239ce44d9c * alpha-dis.c (print_insn_alpha_osf): Remove. 
(print_insn_alpha_vms): Remove.
	(print_insn_alpha): Make globally visible.  Chose the register
	names based on info->flavour.
	* disassemble.c: Always return print_insn_alpha for the alpha.
 1996-07-26 18:06:35 +00:00
Martin Hunt ab0a229408 Thu Jul 25 15:24:17 1996 Martin M. Hunt <hunt@pizza.cygnus.com> 
* d10v-dis.c (dis_long): Handle unknown opcodes.
 1996-07-25 22:28:10 +00:00
Martin Hunt 0be715623f Thu Jul 25 12:08:09 1996 Martin M. Hunt <hunt@pizza.cygnus.com> 
* d10v-opc.c: Changes to support signed and unsigned numbers.
	All instructions with the same name that have long and short forms
	now end in ".l" or ".s".  Divs added.
	* d10v-dis.c: Changes to support signed and unsigned numbers.
 1996-07-25 19:16:34 +00:00
Martin Hunt 687c3cc863 start-sanitize-d10v 
Tue Jul 23 11:02:53 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>

	* d10v-dis.c: Change all functions to use info->print_address_func.

end-sanitize-d10v
 1996-07-23 18:11:55 +00:00
Ian Lance Taylor 354447a435 Mon Jul 22 15:38:53 1996 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> 
* m68k-opc.c (m68k_opcodes): Make opcode masks for the ColdFire
 	move ccr/sr insns more strict so that the disassembler only
 	selects them when the addressing mode is data register.
 1996-07-22 19:49:24 +00:00
Martin Hunt 95e3e73328 start-sanitize-d10v 
Mon Jul 22 11:25:24 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
        * d10v-opc.c (pre_defined_registers):  Declare.
        * d10v-dis.c (print_operand): Now uses pre_defined_registers
        to pick a better name for the registers.

end-sanitize-d10v
 1996-07-22 18:57:20 +00:00
Ian Lance Taylor d82a4ac0aa fix last patch 1996-07-22 18:38:50 +00:00
Ian Lance Taylor e4024966b2 * sparc-opc.c: Fix opcode values for fpack16, and fpackfix. Fix 
operands for fexpand and fpmerge.  From Christian Kuehnke
	<Christian.Kuehnke@arbi.informatik.uni-oldenburg.de>.
 1996-07-22 17:58:19 +00:00
Ian Lance Taylor e7bc7bc3fc Mon Jul 22 13:17:06 1996 Richard Henderson <rth@tamu.edu> 
* alpha-dis.c (print_insn_alpha): No longer the user-visible
	print routine.  Take new regnames and cpumask arguments.
	Kill the environment variable nonsense.
	(print_insn_alpha_osf): New function.  Do OSF/1 style regnames.
	(print_insn_alpha_vms): New function.  Do VMS style regnames.
	* disassemble.c (disassembler): Test bfd flavour to pick
	between OSF and VMS routines.  Default to OSF.
 1996-07-22 17:19:09 +00:00
Ian Lance Taylor 8ec904659e * configure.in: Call AC_SUBST (INSTALL_SHLIB). 
* configure: Rebuild.
	* Makefile.in (install): Use @INSTALL_SHLIB@.
 1996-07-18 21:20:15 +00:00
Martin Hunt e3659cbf49 start-sanitize-d10v 
Wed Jul 17 14:39:05 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
        * configure: (bfd_d10v_arch) Add new case.
        * configure.in: (bfd_d10v_arch) Add new case.
        * d10v-dis.c: New file.
        * d10v-opc.c: New file.
        * disassemble.c (disassembler) Add entry for d10v.
end-sanitize-d10v
 1996-07-18 00:49:26 +00:00
J.T. Conklin dec678d6ca Wed Jul 17 10:12:05 1996 J.T. Conklin <jtc@rtl.cygnus.com> 
* m68k-opc.c (m68k_opcodes): Fix bugs in coldfire insns relating
        to bcc, trapfl, subxl, and wddata discovered by Andreas Schwab.
 1996-07-17 17:18:13 +00:00
Stu Grossman 9498be1a05 oops! 1996-07-16 00:03:38 +00:00
Stu Grossman d9ad578c49 * i386-dis.c (print_insn_i8086): New routine to disassemble using 
the 8086 instruction set.
	* i386-dis.c:  General cleanups.  Make most things static.  Add
	prototypes.  Get rid of static variables aflags and dflags.  Pass
	them as args (to almost everything).
 1996-07-16 00:01:50 +00:00
Stu Grossman be0c8b0508 * i386-dis.c (print_insn_i8086): New routine to disassemble using 
the 8086 instruction set.
	* i386-dis.c:  General cleanups.  Make most things static.  Add
	prototypes.  Get rid of static variables aflags and dflags.  Pass
	them as args (to almost everything).
 1996-07-12 17:15:38 +00:00
Jeff Law 3b2a7894d8 * h8300-dis.c (bfd_h8_disassemble): Handle macregs in ldmac insns. 
More HMSE.
 1996-07-11 19:06:21 +00:00
Jeff Law 8e9c1f74c9 * h8300-dis.c (bfd_h8_disassemble): Handle "ldm.l" and "stm.l". 
More disassembler fixes.  HMSE.
 1996-07-11 18:59:57 +00:00
Jeff Law 52aa53362e * h8300-dis.c (bfd_h8_disassemble): "abs" is implicitly two 
if the next arg is marked with SRC_IN_DST.  Gross.
Gross hack so that shift-by-two insns are disassembled correctly.
 1996-07-11 18:46:41 +00:00
Jeff Law b3ef936e6b * h8300-dis.c (bfd_h8_disassemble): Print "exr" when 
we're looking for and find EXR.
So we disassemble andc/orc/xorc with exr correctly.
 1996-07-11 18:30:02 +00:00
Jeff Law 81fc72a71a * h8300-dis.c (bfd_h8_disassemble): We don't have a match 
if we're looking for KBIT and we don't find it.
So we don't disassemble "inc" instructions as "adds" instructions.
 1996-07-11 18:24:59 +00:00
Jeff Law bf0b880f39 * h8300-dis.c (bfd_h8_disassemble): Mask off unwanted bits 
for L_3 and L_2.
So we only get values in the right range for L_3 (0..7) and L_2 (0..3).
 1996-07-11 18:07:31 +00:00