I meant for this script to be +x, but missed when doing the initial CVS
commit. It wasn't possible to fix w/CVS, but it is w/git, so do it.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-12-03 Mike Frysinger <vapier@gentoo.org>
* run-tests.sh: Add +x file mode.
Since the sim has a few fake debug insns that the hardware does not, we
need to check for those before attempting to run them. Otherwise we'll
randomly trigger the sim debug asserts/aborts/halts insns. On the
hardware, these are proper invalid insns, and the table catches that.
The main body of the "all insn" test is executed once per tested insn, and
we test millions of insns here. Any shrinkage we can do in this loop will
speed things up nicely (since it's multiplied per tested insn).
To that end, simplify the end-of-table test into one less insn, and omit
the SSYNC when we build for the sim. When we build to run on the hardware,
this insn matters, but the sim doesn't have write store buffers in the chip
that might get in the way (memory writes are atomic).
Since these insns run in usermode, there should be no need to setup
RET[ENI] to safe values. They won't be dereferenced, and any insn
that returns via them are valid only in supervisor mode. Since this
is in the main exception code path, saving any insn at all is good
as it gets multiplied quickly (as in O(n^2) times).
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
From: Jayant R. Sonar <Jayant.Sonar@kpitcummins.com>
This patch adds simulator support for handling the armv7 instructions
'movw (immediate)' and 'movt'.
Compiler frequently use these instructions to load the 32bit addresses of
global variables, string pointers etc. into the general registers.
In absence of support of these instructions:
1. GDB run simulator fails to print even simple "hello world" string
on console.
2. Loading of global variable addresses into the registers fail causing
arithmetic operation failures.
Patch has been regression tested for arm-none-eabi (-march=armv7-a).
Two modifications:
1. The addition of 2013 to the copyright year range for every file;
2. The use of a single year range, instead of potentially multiple
year ranges, as approved by the FSF.
These are randomly generated tests to track down issues in ASTAT
handling with shift insns.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Now that we check for valid sub-insns in parallel insns, we can
enable the tests that explicitly validate those code paths.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Now that we have the se_all helpers together and working, we can see
what pieces are duplicated in each test and unify them in the common
header file.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Similar to logic in the cris exp, attempt a simple compile and if it fails
(presumably due to the compiler being broken), skip all the related tests.
Fortunately, most tests (~600 out of ~800) are pure assembly, so people should
still get pretty good coverage.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The current se_all*opcodes tests are very similar in how they work.
In preparation for adding more tests along these lines, unify the
common bits into a framework that others can include and build off
of easily.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The 32bit allopcodes test had quite a bit of optimization added to it
so that it ran in a reasonable amount of time out of uncached memory.
Port those changes over to the 16bit test so the two share common code.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The VIT_MAX insns can be used in parallel, so we need to use the store
buffer so we don't clobber the output register before we get a chance
to do a memory store with it.
Reported-by: Kai Iskratsch <kai@stella.at>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Now that the common sim testsuite code supports .S and .c files, we
can import the Blackfin testsuite. There are about ~800 tests here,
so I'm only attaching a compressed patch of them. Other than adding
files to sim/testsuite/sim/bfin/, the sim/configure.tgt file was
updated to mark Blackfin as having a testsuite, and sim/configure
regenerated.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Rather than requiring all sim tests to be preprocessed .s files, add
support for .S and .c files so we can easily write code using a higher
level language like C.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The testsuite subdir has a note about unifying the target->subdir logic,
so do just that. The end goal here is to have `make check` work out of
the box without having to delve into dejagnu internals.
The target-specific logic is split out of the top level configure.ac file
and into a dedicated configure.tgt similar to other subprojects (gdb and
ld and etc...) with the difference that this file has to be included at
the m4 level instead of the shell level. This is necessary only because
autoconf requires AC_CONFIG_SUBDIRS be given a string literal and not a
variable value.
Then the toplevel and the testsuite configure files pull this in, the sim
subdir gets expanded into testsuite/site.exp, and the default sim run code
uses this info to set the sim path to the local compiled run file if it
hasn't already been specified.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
sim/cris/c/badldso2.c, sim/cris/c/badldso3.c,
sim/cris/c/helloaout.c, sim/cris/c/hellodyn.c,
sim/cris/c/hellodyn2.c, sim/cris/c/writev1.c,
sim/cris/c/writev2.c: New tests.
* sim/cris/c/c.exp: If compiler links libc.so when attempting to
link dynamically, create symlink named "lib" to the directory
where it is found. Handle new test-case option "dynamic".
* config/tc-mips.c (mips_set_options, mips_opts, file_ase_dspr2,
ISA_SUPPORTS_DSPR2_ASE, MIPS_CPU_ASE_DSPR2): Add DSP R2 ASE support.
(macro_build): Add case '2'.
(macro): Expand M_BALIGN to nop, packrl.ph or balign.
(validate_mips_insn): Add support for balign instruction.
(mips_ip): Handle DSP R2 instructions. Support balign instruction.
(OPTION_DSPR2, OPTION_NO_DSPR2, OPTION_COMPAT_ARCH_BASE,
md_parse_option, mips_after_parse_args): Add -mdspr2 and -mno-dspr2
command line options.
(s_mipsset): Add support for .set dspr2 and .set nodspr2 directives.
(md_show_usage): Add -mdspr2 and -mno-dspr2 help output.
* doc/c-mips.texi, doc/as.texinfo: Document -mdspr2, -mno-dspr2,
.set dspr2, .set nodspr2.
[ gas/testsuite/ChangeLog ]
* gas/mips/mips32-dspr2.s, gas/mips/mips32-dspr2.d: New test for
DSP R2.
* gas/mips/mips.exp: Run new test.
[ include/opcode/Changelog ]
* mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
(INSN_DSPR2): Add flag for DSP R2 instructions.
(M_BALIGN): New macro.
[ opcodes/ChangeLog ]
* mips-dis.c (mips_arch_choices): Add DSP R2 support.
(print_insn_args): Add support for balign instruction.
* mips-opc.c (D33): New shortcut for DSP R2 instructions.
(mips_builtin_opcodes): Add DSP R2 instructions.
[ sim/mips/ChangeLog ]
* Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
* configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
Add dsp2 to sim_igen_machine.
* configure: Regenerate.
* dsp.igen (do_ph_op): Add MUL support when op = 2.
(do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
(mulq_rs.ph): Use do_ph_mulq.
(MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
* mips.igen: Add dsp2 model and include dsp2.igen.
(MFHI, MFLO, MTHI, MTLO): Extend these instructions for
for *mips32r2, *mips64r2, *dsp.
(MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
for *mips32r2, *mips64r2, *dsp2.
* dsp2.igen: New file for MIPS DSP REV 2 ASE.
[ sim/testsuite/sim/mips/ChangeLog ]
* basic.exp: Run the dsp2 test.
* utils-dsp.inc (dspckacc_astio, dspck_tsimm): New macro.
* mips32-dsp2.s: New test.
(process): Don't write as much to the pipe as to trig the
inordinate-amount test in the sim pipe machinery. Correct test of
write return-value; check only that pipemax bytes were
successfully written. For error-case, emit strerror as well.
(main): Add a second read.
Mike Frysinger
James Bowman
Joel Brobecker
Alan Modra
Joel Brobecker
H.J. Lu
Steve Ellcey
Nick Clifton
Hans-Peter Nilsson
Joseph Myers
Ralf Wildenhues
M R Swami Reddy
DJ Delorie
Daniel Jacobowitz
Thiemo Seufer
Chao-ying Fu