H.J. Lu
dd455cf51d
gas: Add .enqcmd and noenqcmd directives
...
2019-06-06 Lili Cui <lili.cui@intel.com>
* config/tc-i386.c (cpu_arch): Add .enqcmd.
(cpu_noarch): Add noenqcmd.
* doc/c-i386.texi: Document noenqcmd.
2019-06-06 07:57:52 -07:00
H.J. Lu
9186c494a3
Enable Intel AVX512_VP2INTERSECT insn
...
This patch enables support for VP2INTERSECT in binutils. Please refer to
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
for VP2INTERSECT details.
Make check-gas is ok.
gas/
2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
Lili Cui <lili.cui@intel.com>
* config/tc-i386.c (cpu_arch): Add .avx512_vp2intersect.
(cpu_noarch): Likewise.
* doc/c-i386.texi: Document avx512_vp2intersect.
* testsuite/gas/i386/i386.exp: Run vp2intersect tests.
* testsuite/gas/i386/vp2intersect-intel.d: New test.
* testsuite/gas/i386/vp2intersect.d: Likewise.
* testsuite/gas/i386/vp2intersect.s: Likewise.
* testsuite/gas/i386/vp2intersect-inval-bcast.l: Likewise.
* testsuite/gas/i386/vp2intersect-inval-bcast.s: Likewise.
* testsuite/gas/i386/x86-64-vp2intersect-intel.d: Likewise.
* testsuite/gas/i386/x86-64-vp2intersect.d: Likewise.
* testsuite/gas/i386/x86-64-vp2intersect.s: Likewise.
* testsuite/gas/i386/x86-64-vp2intersect-inval-bcast.l: Likewise.
* testsuite/gas/i386/x86-64-vp2intersect-inval-bcast.s: Likewise.
opcodes/
2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
Lili Cui <lili.cui@intel.com>
* i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
* i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
instructions.
* i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
(cpu_flags): Add CpuAVX512_VP2INTERSECT.
* i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
(i386_cpu_flags): Add cpuavx512_vp2intersect.
* i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2019-06-04 08:58:31 -07:00
H.J. Lu
5d79adc4b2
Add support for Intel ENQCMD[S] instructions
...
This patch enables support for ENQCMD[S] in binutils. Please refer to
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
for ENQCMD[S] details.
Make check-gas is ok.
gas/ChangeLog:
2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
Lili Cui <lili.cui@intel.com>
* doc/c-i386.texi: Document enqcmd.
* testsuite/gas/i386/enqcmd-intel.d: New file.
* testsuite/gas/i386/enqcmd-inval.l: Likewise.
* testsuite/gas/i386/enqcmd-inval.s: Likewise.
* testsuite/gas/i386/enqcmd.d: Likewise.
* testsuite/gas/i386/enqcmd.s: Likewise.
* testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
* testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
* testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
* testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
* testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
* testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
and x86-64-enqcmd.
opcodes/ChangeLog:
2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
Lili Cui <lili.cui@intel.com>
* i386-dis.c (enum): Add MOD_0F38F8_PREFIX_1 and
MOD_0F38F8_PREFIX_3.
(prefix_table): New instructions (see prefix above).
(mod_table): New instructions (see prefix above).
* i386-gen.c (cpu_flag_init): Add entries for enqcmd.
(cpu_flags): Add a bitfield for enqmcd.
* i386-init.h: Regenerated.
* i386-opc.h (enum): Add CpuENQCMD.
(i386_cpu_flags): Add a bitfield for cpuenqcmd.
* i386-opc.tbl: Add enqcmd and enqcmds instructions.
* i386-init.h: Regenerated.
* i386-tbl.h: Regenerated.
2019-06-04 08:50:46 -07:00
Xuepeng Guo
d6aab7a11b
x86: Support Intel AVX512 BF16
...
Add assembler and disassembler support Intel AVX512 BF16:
https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference
gas/
2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
* config/tc-i386.c (cpu_arch): Add .avx512_bf16.
(cpu_noarch): Add noavx512_bf16.
* doc/c-i386.texi: Document avx512_bf16.
* testsuite/gas/i386/avx512_bf16.d: New file.
* testsuite/gas/i386/avx512_bf16.s: Likewise.
* testsuite/gas/i386/avx512_bf16_vl-inval.l: Likewise.
* testsuite/gas/i386/avx512_bf16_vl-inval.s: Likewise.
* testsuite/gas/i386/avx512_bf16_vl.d: Likewise.
* testsuite/gas/i386/avx512_bf16_vl.s: Likewise.
* testsuite/gas/i386/x86-64-avx512_bf16.d: Likewise.
* testsuite/gas/i386/x86-64-avx512_bf16.s: Likewise.
* testsuite/gas/i386/x86-64-avx512_bf16_vl-inval.l: Likesie.
* testsuite/gas/i386/x86-64-avx512_bf16_vl-inval.s: Likewise.
* testsuite/gas/i386/x86-64-avx512_bf16_vl.d: Likewise.
* testsuite/gas/i386/x86-64-avx512_bf16_vl.s: Likewise.
* testsuite/gas/i386/i386.exp: Add BF16 related tests.
opcodes/
2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
* i386-dis-evex.h (evex_table): Updated to support BF16
instructions.
* i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
and EVEX_W_0F3872_P_3.
* i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
(cpu_flags): Add bitfield for CpuAVX512_BF16.
* i386-opc.h (enum): Add CpuAVX512_BF16.
(i386_cpu_flags): Add bitfield for cpuavx512_bf16.
* i386-opc.tbl: Add AVX512 BF16 instructions.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2019-04-05 11:03:13 -07:00
H.J. Lu
97ed31ae00
x86: Optimize EVEX vector load/store instructions
...
When there is no write mask, we can encode lower 16 128-bit/256-bit
EVEX vector register load and store instructions as VEX vector register
load and store instructions with -O1.
gas/
PR gas/24348
* config/tc-i386.c (optimize_encoding): Encode 128-bit and
256-bit EVEX vector register load/store instructions as VEX
vector register load/store instructions for -O1.
* doc/c-i386.texi: Update -O1 documentation.
* testsuite/gas/i386/i386.exp: Run PR gas/24348 tests.
* testsuite/gas/i386/optimize-1.s: Add tests for EVEX vector
load/store instructions.
* testsuite/gas/i386/optimize-2.s: Likewise.
* testsuite/gas/i386/optimize-3.s: Likewise.
* testsuite/gas/i386/optimize-5.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-2.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-3.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-4.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-5.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-6.s: Likewise.
* testsuite/gas/i386/optimize-1.d: Updated.
* testsuite/gas/i386/optimize-2.d: Likewise.
* testsuite/gas/i386/optimize-3.d: Likewise.
* testsuite/gas/i386/optimize-4.d: Likewise.
* testsuite/gas/i386/optimize-5.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-2.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-3.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-4.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-5.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-6.d: Likewise.
* testsuite/gas/i386/optimize-7.d: New file.
* testsuite/gas/i386/optimize-7.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-8.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-8.s: Likewise.
opcodes/
PR gas/24348
* i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
vmovdqu16, vmovdqu32 and vmovdqu64.
* i386-tbl.h: Regenerated.
2019-03-18 08:58:19 +08:00
H.J. Lu
99112332cd
x86: Encode 256-bit/512-bit VEX/EVEX insns with 128-bit VEX
...
Since all AVX512 processors support AVX, we can encode 256-bit/512-bit
VEX/EVEX vector register clearing instructions with 128-bit VEX vector
register clearing instructions at -O1.
* config/tc-i386.c (optimize_encoding): Encode 256-bit/512-bit
VEX/EVEX vector register clearing instructions with 128-bit VEX
vector register clearing instructions at -O1.
* doc/c-i386.texi: Update -O1 and -O2 documentation.
* testsuite/gas/i386/i386.exp: Run optimize-1a and
x86-64-optimize-2a.
* testsuite/gas/i386/optimize-1a.d: New file.
* testsuite/gas/i386/x86-64-optimize-2a.d: Likewise.
2019-03-18 03:51:50 +08:00
Alan Modra
827041555a
Update year range in copyright notice of binutils files
2019-01-01 22:06:53 +10:30
H.J. Lu
0375113302
x86: Add -mvexwig=[0|1] option to assembler
...
Add -mvexwig=[0|1] option to x86 assembler to control how the assembler
should encode the VEX.W bit in WIG VEX instructions.
* gas/NEWS: Mention -mvexwig=[0|1] option.
* config/tc-i386.c (vexwig): New.
(build_vex_prefix): Set the VEX.W bit for -mvexwig=1 for WIG
VEX instructions.
(OPTION_MVEXWIG): New.
(md_longopts): Add -mvexwig=.
(md_parse_option): Handle OPTION_MVEXWIG.
(md_show_usage): Show -mvexwig=[0|1].
* doc/c-i386.texi: Document -mvexwig=[0|1].
* testsuite/gas/i386/avx-wig.d: New file.
* testsuite/gas/i386/avx-wig.s: Likewise.
* testsuite/gas/i386/avx2-wig.d: Likewise.
* testsuite/gas/i386/avx2-wig.s: Likewise.
* testsuite/gas/i386/x86-64-avx-wig.d: Likewise.
* testsuite/gas/i386/x86-64-avx-wig.s: Likewise.
* testsuite/gas/i386/x86-64-avx2-wig.d: Likewise.
* testsuite/gas/i386/x86-64-avx2-wig.s: Likewise.
* testsuite/gas/i386/i386.exp: Run avx-wig, avx2-wig,
x86-64-avx-wig and x86-64-avx2-wig.
2018-09-17 09:26:29 -07:00
H.J. Lu
b4a3a7b44c
x86: Extend assembler to generate GNU property notes
...
Add -mx86-used-note=[yes|no] option to generate (or not) GNU property
notes with GNU_PROPERTY_X86_FEATURE_2_USED and GNU_PROPERTY_X86_ISA_1_USED
properties. If the assembly input contains no instructions, set the
GNU_PROPERTY_X86_UINT32_VALID bit in GNU_PROPERTY_X86_FEATURE_2_USED
property. Add a --enable-x86-used-note configure time option to set the
default behavior. Set the default if the configure option is not used
to "no".
* NEWS: Mention -mx86-used-note=[no|yes].
* configure.ac: Add --enable-x86-used-note. Define
DEFAULT_X86_USED_NOTE.
* config.in: Regenerated.
* configure: Likewise.
* config/tc-i386.c (x86_isa_1_used): New.
(x86_feature_2_used): Likewise.
(x86_used_note): Likewise.
(_i386_insn): Add has_regmmx, has_regxmm, has_regymm and
has_regzmm.
(build_modrm_byte): Set i.has_regmmx, i.has_regzmm.
i.has_regymm and i.has_regxmm.
(x86_cleanup): New function.
(output_insn): Update x86_isa_1_used and x86_feature_2_used.
(OPTION_X86_USED_NOTE): New.
(md_longopts): Add -mx86-used-note=.
(md_parse_option): Handle OPTION_X86_USED_NOTE.
(md_show_usage): Display -mx86-used-note=.
* config/tc-i386.h (x86_cleanup): New prototype.
(md_cleanup): New.
* doc/c-i386.texi: Document -mx86-used-note=.
2018-08-31 04:31:20 -07:00
H.J. Lu
d871f3f483
x86: Add CpuCMOV and CpuFXSR
...
There are separate CPUID feature bits for fxsave/fxrstor and cmovCC
instructions. This patch adds CpuCMOV and CpuFXSR to replace Cpu686
on corresponding instructions.
gas/
* config/tc-i386.c (cpu_arch): Add .cmov and .fxsr.
(cpu_noarch): Add nocmov and nofxsr.
* doc/c-i386.texi: Document cmov and fxsr.
opcodes/
* i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
(cpu_flags): Add CpuCMOV and CpuFXSR.
* i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2018-08-11 14:37:32 -07:00
Thomas Preud'homme
a05a5b64cf
Fix use of "command line X" in binutils doc
...
Binutils documentation uses a mix of spelling for the compound word
"command-line X". According to [1]:
"Sometimes compound words are written separately (nail polish),
sometimes with a hyphen (short-sighted) and sometimes as one word
(eyelashes). Often new compounds are written as two separate words and,
as they become more familiar, they are either connected with a hyphen
(-) or made into one word."
I think command-line X is common enough in our industry that the two
workds command and line should be connected. Since command-line is more
common than commandline, I propose to update binutils documentation to
consistently use "command-line" when this is used as an adjective to a
noun (eg. command-line argument, command-line switch, command-line
option and command-line flag). I've left occurences of "the command
line" as is. I've also left gdb, sim and readline alone and have only
touched public documentation (texi and NEWS files).
[1]
http://dictionary.cambridge.org/grammar/british-grammar/word-formation/compounds
2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
bfd/
* doc/bfdint.texi: Use command-line consistently when used in a
compount word.
* doc/bfdsumm.texi: Likewise.
binutils/
* NEWS: Use command-line consistently when used in a compount word.
* doc/binutils.texi: Likewise and fix trailing whitespace on same
line.
gas/
* NEWS: Use command-line consistently when used in a compount word.
* doc/as.texi: Likewise.
* doc/c-aarch64.texi: Likewise.
* doc/c-alpha.texi: Likewise.
* doc/c-arc.texi: Likewise.
* doc/c-arm.texi: Likewise.
* doc/c-avr.texi: Likewise.
* doc/c-bfin.texi: Likewise.
* doc/c-cris.texi: Likewise.
* doc/c-epiphany.texi: Likewise.
* doc/c-i386.texi: Likewise.
* doc/c-ia64.texi: Likewise.
* doc/c-lm32.texi: Likewise.
* doc/c-m32r.texi: Likewise.
* doc/c-m68k.texi: Likewise.
* doc/c-mips.texi: Likewise.
* doc/c-mmix.texi: Likewise.
* doc/c-msp430.texi: Likewise.
* doc/c-mt.texi: Likewise.
* doc/c-nios2.texi: Likewise.
* doc/c-ppc.texi: Likewise.
* doc/c-pru.texi: Likewise.
* doc/c-rl78.texi: Likewise.
* doc/c-rx.texi: Likewise.
* doc/c-tic6x.texi: Likewise.
* doc/c-v850.texi: Likewise.
* doc/c-vax.texi: Likewise.
* doc/c-visium.texi: Likewise.
* doc/c-xstormy16.texi: Likewise.
* doc/c-xtensa.texi: Likewise.
* doc/c-z80.texi: Likewise.
* doc/c-z8k.texi: Likewise.
* doc/internals.texi: Likewise.
gprof/
* gprof.texi: Use command-line consistently when used in a compount
word.
ld/
* NEWS: Use command-line consistently when used in a compount word.
* ld.texinfo: Likewise.
* ldint.texinfo: Likewise.
2018-07-02 11:18:24 +01:00
Amit Pawar
a9660a6f40
Add znver2 support.
...
gas/
* config/tc-i386.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
* doc/c-i386.texi : Document znver2.
* gas/testsuite/gas/i386/arch-13.s: Updated for znver2.
* gas/testsuite/gas/i386/arch-13.d: Updated.
* gas/testsuite/gas/i386/arch-13-znver1.d: Updated.
* gas/testsuite/gas/i386/arch-13-znver2.d: New file.
* gas/testsuite/gas/i386/x86-64-arch-3.s: Updated for znver2.
* gas/testsuite/gas/i386/x86-64-arch-3.d: Updated.
* gas/testsuite/gas/i386/x86-64-arch-3-znver1.d: Updated.
* gas/testsuite/gas/i386/x86-64-arch-3-znver2.d: New file.
* gas/testsuite/gas/i386/i386.exp: Updated for new test.
opcode/
* i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
* i386-init.h : Regenerated.
2018-05-30 12:27:35 +05:30
H.J. Lu
c0a30a9f0a
Enable Intel MOVDIRI, MOVDIR64B instructions
...
gas/
* config/tc-i386.c (cpu_arch): Add .movdir, .movdir64b.
(cpu_noarch): Likewise.
(process_suffix): Add check for register size.
* doc/c-i386.texi: Document movdiri, movdir64b.
* testsuite/gas/i386/i386.exp: Run MOVDIR{I,64B} tests.
* testsuite/gas/i386/movdir-intel.d: New file.
* testsuite/gas/i386/movdir.d: Likewise.
* testsuite/gas/i386/movdir.s: Likewise.
* testsuite/gas/i386/movdir64b-reg.s: Likewise.
* testsuite/gas/i386/movdir64b-reg.l: Likewise.
* testsuite/gas/i386/x86-64-movdir-intel.d: Likewise.
* testsuite/gas/i386/x86-64-movdir.d: Likewise.
* testsuite/gas/i386/x86-64-movdir.s: Likewise.
* testsuite/gas/i386/x86-64-movdir64b-reg.s: Likewise.
* testsuite/gas/i386/x86-64-movdir64b-reg.l: Likewise.
opcodes/
* i386-dis.c (Gva): New.
(enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
(prefix_table): New instructions (see prefix above).
(mod_table): New instructions (see prefix above).
(OP_G): Handle va_mode.
* i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
CPU_MOVDIR64B_FLAGS.
(cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
* i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
(i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
* i386-opc.tbl: Add movidir{i,64b}.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2018-05-07 16:57:48 -07:00
Igor Tsimbalist
aa17843739
Revert "Enable Intel MOVDIRI, MOVDIR64B instructions."
...
This reverts commit a914a7c958
2018-04-27 14:34:13 +02:00
Igor Tsimbalist
a914a7c958
Enable Intel MOVDIRI, MOVDIR64B instructions.
...
gas/
* config/tc-i386.c (cpu_arch): Add .movdir, .movdir64b.
(cpu_noarch): Likewise.
(process_suffix): Add check for register size.
* doc/c-i386.texi: Document movdiri, movdir64b.
* testsuite/gas/i386/i386.exp: Run MOVDIR{I,64B} tests.
* testsuite/gas/i386/movdir-intel.d: New test.
* testsuite/gas/i386/movdir.d: Likewise.
* testsuite/gas/i386/movdir.s: Likewise.
* testsuite/gas/i386/movdir64b-reg.s: Likewise.
* testsuite/gas/i386/movdir64b-reg.l: Likewise.
* testsuite/gas/i386/x86-64-movdir-intel.d: Likewise.
* testsuite/gas/i386/x86-64-movdir.d: Likewise.
* testsuite/gas/i386/x86-64-movdir.s: Likewise.
* testsuite/gas/i386/x86-64-movdir64b-reg.s: Likewise.
* testsuite/gas/i386/x86-64-movdir64b-reg.l: Likewise.
opcodes/
* i386-dis.c (enum): Add PREFIX_0F38F8, PREFIX_0F38F9.
(prefix_table): New instructions (see prefix above).
Add Gva macro and handling in OP_G.
* i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
CPU_MOVDIR64B_FLAGS.
(cpu_flags): Likewise.
(opcode_modifiers): Add AddrPrefixOpReg.
(i386_opcode_modifier): Likewise.
* i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
(i386_cpu_flags): Likewise.
* i386-opc.tbl: Add movidir{i,64b}.
* i386-init.h: Regenerate.
* i386-tbl.h: Likewise.
2018-04-26 23:34:04 +02:00
Igor Tsimbalist
c48935d75f
Enable Intel CLDEMOTE instruction.
...
gas/
* config/tc-i386.c (cpu_arch): Add .cldemote.
* doc/c-i386.texi: Document cldemote/.cldemote.
* testsuite/gas/i386/cldemote-intel.d: New.
* testsuite/gas/i386/cldemote.d: Likewise.
* testsuite/gas/i386/cldemote.s: Likewise.
* testsuite/gas/i386/i386.exp: Run new tests.
* testsuite/gas/i386/x86-64-cldemote-intel.d: New.
* testsuite/gas/i386/x86-64-cldemote.d: Likewise.
* testsuite/gas/i386/x86-64-cldemote.s: Likewise.
* testsuite/gas/i386/ilp32/x86-64-nops.d: Remove 0x0f1c
NOP encoding that maps to cldemote.
* testsuite/gas/i386/nops.d: Likewise.
* testsuite/gas/i386/nops.s: Likewise.
* testsuite/gas/i386/x86-64-nops.d: Likewise.
* testsuite/gas/i386/x86-64-nops.s: Likewise.
opcode/
* i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
PREFIX_0F1C.
* i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
(cpu_flags): Add CpuCLDEMOTE.
* i386-init.h: Regenerate.
* i386-opc.h (enum): Add CpuCLDEMOTE,
(i386_cpu_flags): Add cpucldemote.
* i386-opc.tbl: Add cldemote.
* i386-tbl.h: Regenerate.
2018-04-17 11:56:34 +02:00
Igor Tsimbalist
de89d0a34d
Enable Intel WAITPKG instructions.
...
Intel has disclosed a set of new instructions for Tremont processor.
The spec is
https://software.intel.com/en-us/intel-architecture-instruction-set-extensions-programming-reference
This patch enables Intel WAITPKG instructions.
gas/
* config/tc-i386.c (cpu_arch): Add WAITPKG.
(cpu_noarch): Likewise.
* doc/c-i386.texi: Document WAITPKG.
* i386/i386.exp: Run WAITPKG tests.
* testsuite/gas/i386/waitpkg-intel.d: New test.
* testsuite/gas/i386/waitpkg.d: Likewise.
* testsuite/gas/i386/waitpkg.s: Likewise.
* testsuite/gas/i386/x86-64-waitpkg-intel.d: Likewise.
* testsuite/gas/i386/x86-64-waitpkg.d: Likewise.
* testsuite/gas/i386/x86-64-waitpkg.s: Likewise.
opcodes/
* i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
PREFIX_MOD_1_0FAE_REG_6.
(va_mode): New.
(OP_E_register): Use va_mode.
* i386-dis-evex.h (prefix_table):
New instructions (see prefixes above).
* i386-gen.c (cpu_flag_init): Add WAITPKG.
(cpu_flags): Likewise.
* i386-opc.h (enum): Likewise.
(i386_cpu_flags): Likewise.
* i386-opc.tbl: Add umonitor, umwait, tpause.
* i386-init.h: Regenerate.
* i386-tbl.h: Likewise.
2018-04-11 21:37:12 +02:00
H.J. Lu
b6f8c7c452
x86: Add -O[2|s] assembler command-line options
...
On x86, some instructions have alternate shorter encodings:
1. When the upper 32 bits of destination registers of
andq $imm31, %r64
testq $imm31, %r64
xorq %r64, %r64
subq %r64, %r64
known to be zero, we can encode them without the REX_W bit:
andl $imm31, %r32
testl $imm31, %r32
xorl %r32, %r32
subl %r32, %r32
This optimization is enabled with -O, -O2 and -Os.
2. Since 0xb0 mov with 32-bit destination registers zero-extends 32-bit
immediate to 64-bit destination register, we can use it to encode 64-bit
mov with 32-bit immediates. This optimization is enabled with -O, -O2
and -Os.
3. Since the upper bits of destination registers of VEX128 and EVEX128
instructions are extended to zero, if all bits of destination registers
of AVX256 or AVX512 instructions are zero, we can use VEX128 or EVEX128
encoding to encode AVX256 or AVX512 instructions. When 2 source
registers are identical, AVX256 and AVX512 andn and xor instructions:
VOP %reg, %reg, %dest_reg
can be encoded with
VOP128 %reg, %reg, %dest_reg
This optimization is enabled with -O2 and -Os.
4. 16-bit, 32-bit and 64-bit register tests with immediate may be
encoded as 8-bit register test with immediate. This optimization is
enabled with -Os.
This patch does:
1. Add {nooptimize} pseudo prefix to disable instruction size
optimization.
2. Add optimize to i386_opcode_modifier to tell assembler that encoding
of an instruction may be optimized.
gas/
PR gas/22871
* NEWS: Mention -O[2|s].
* config/tc-i386.c (_i386_insn): Add no_optimize.
(optimize): New.
(optimize_for_space): Likewise.
(fits_in_imm7): New function.
(fits_in_imm31): Likewise.
(optimize_encoding): Likewise.
(md_assemble): Call optimize_encoding to optimize encoding.
(parse_insn): Handle {nooptimize}.
(md_shortopts): Append "O::".
(md_parse_option): Handle -On.
* doc/c-i386.texi: Document -O0, -O, -O1, -O2 and -Os as well
as {nooptimize}.
* testsuite/gas/cfi/cfi-x86_64.d: Pass -O0 to assembler.
* testsuite/gas/i386/ilp32/cfi/cfi-x86_64.d: Likewise.
* testsuite/gas/i386/i386.exp: Run optimize-1, optimize-2,
optimize-3, x86-64-optimize-1, x86-64-optimize-2,
x86-64-optimize-3 and x86-64-optimize-4.
* testsuite/gas/i386/optimize-1.d: New file.
* testsuite/gas/i386/optimize-1.s: Likewise.
* testsuite/gas/i386/optimize-2.d: Likewise.
* testsuite/gas/i386/optimize-2.s: Likewise.
* testsuite/gas/i386/optimize-3.d: Likewise.
* testsuite/gas/i386/optimize-3.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-1.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-1.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-2.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-2.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-3.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-3.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-4.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-4.s: Likewise.
opcodes/
PR gas/22871
* i386-gen.c (opcode_modifiers): Add Optimize.
* i386-opc.h (Optimize): New enum.
(i386_opcode_modifier): Add optimize.
* i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
"sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
"and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
"movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
vpxord and vpxorq.
* i386-tbl.h: Regenerated.
2018-02-27 07:36:43 -08:00
H.J. Lu
6b6b680700
x86: Add {rex} pseudo prefix
...
Add {rex} pseudo prefix to generate a REX byte for integer and legacy
vector instructions if possible. Note that this differs from the rex
prefix which generates REX prefix unconditionally.
gas/
* config/tc-i386.c (_i386_insn): Add rex_encoding.
(md_assemble): When i.rex_encoding is true, generate a REX byte
if possible.
(parse_insn): Set i.rex_encoding for {rex}.
* doc/c-i386.texi: Document {rex}.
* testsuite/gas/i386/x86-64-pseudos.s: Add {rex} tests.
* testsuite/gas/i386/x86-64-pseudos.d: Updated.
opcodes/
* i386-opc.tbl: Add {rex},
* i386-tbl.h: Regenerated.
2018-02-22 06:18:39 -08:00
Igor Tsimbalist
be3a8dca2d
Enable Intel PCONFIG instruction.
...
Intel has disclosed a set of new instructions for Icelake processor.
The spec is
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
This patch enables Intel PCONFIG instruction.
gas/
* config/tc-i386.c (cpu_arch): Add .pconfig.
* doc/c-i386.texi: Document .pconfig.
* testsuite/gas/i386/i386.exp: Add PCONFIG tests.
* testsuite/gas/i386/pconfig-intel.d: New test.
* testsuite/gas/i386/pconfig.d: Likewise.
* testsuite/gas/i386/pconfig.s: Likewise.
* testsuite/gas/i386/x86-64-pconfig-intel.d: Likewise.
* testsuite/gas/i386/x86-64-pconfig.d: Likewise.
* testsuite/gas/i386/x86-64-pconfig.s: Likewise.
opcodes/
* i386-dis.c (enum): Add pconfig.
* i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
(cpu_flags): Add CpuPCONFIG.
* i386-opc.h (enum): Add CpuPCONFIG.
(i386_cpu_flags): Add cpupconfig.
* i386-opc.tbl: Add PCONFIG instruction.
* i386-init.h: Regenerate.
* i386-tbl.h: Likewise.
2018-01-23 20:09:35 +03:00
Igor Tsimbalist
3233d7d074
Enable Intel WBNOINVD instruction.
...
Intel has disclosed a set of new instructions for Icelake processor.
The spec is
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
This patch enables Intel WBNOINVD instruction.
gas/
* config/tc-i386.c (cpu_arch): Add .wbnoinvd.
* doc/c-i386.texi: Document .wbnoinvd.
* testsuite/gas/i386/i386.exp: Add WBNOINVD tests.
* testsuite/gas/i386/wbnoinvd-intel.d: New test.
* testsuite/gas/i386/wbnoinvd.d: Likewise.
* testsuite/gas/i386/wbnoinvd.s: Likewise.
* testsuite/gas/i386/x86-64-wbnoinvd-intel.d: Likewise.
* testsuite/gas/i386/x86-64-wbnoinvd.d: Likewise.
* testsuite/gas/i386/x86-64-wbnoinvd.s: Likewise.
opcodes/
* i386-dis.c (enum): Add PREFIX_0F09.
* i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
(cpu_flags): Add CpuWBNOINVD.
* i386-opc.h (enum): Add CpuWBNOINVD.
(i386_cpu_flags): Add cpuwbnoinvd.
* i386-opc.tbl: Add WBNOINVD instruction.
* i386-init.h: Regenerate.
* i386-tbl.h: Likewise.
2018-01-23 20:05:33 +03:00
Igor Tsimbalist
d777820bf5
Replace CET bit with IBT and SHSTK bits.
...
The latest specification for Intel CET technology defined two
new bits instead of previously used CET bit. These are IBT and
SHSTK bits. The patch replaces CET bit with IBT and SHSTK bits.
gas/
* config/tc-i386.c (cpu_arch): Delete .cet. Add .ibt, .shstk.
(cpu_noarch): Add noibt, noshstk.
(parse_insn): Change cpucet to cpuibt.
* doc/c-i386.texi: Delete .cet. Add .ibt, .shstk.
* testsuite/gas/i386/cet-ibt-inval.l: New test.
* testsuite/gas/i386/cet-ibt-inval.s: Likewise.
* testsuite/gas/i386/cet-shstk-inval.l: Likewise.
* testsuite/gas/i386/cet-shstk-inval.s: Likewise.
* testsuite/gas/i386/x86-64-cet-ibt-inval.l: Likewise.
* testsuite/gas/i386/x86-64-cet-ibt-inval.s: Likewise.
* testsuite/gas/i386/x86-64-cet-shstk-inval.l: Likewise.
* testsuite/gas/i386/x86-64-cet-shstk-inval.s: Likewise.
opcodes/
* i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS,
CpuCET. Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
(cpu_flags): Add CpuIBT, CpuSHSTK.
* i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
(i386_cpu_flags): Add cpuibt, cpushstk.
* i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
* i386-init.h: Regenerate.
* i386-tbl.h: Likewise.
2018-01-17 19:48:28 +03:00
Nick Clifton
102e9361c8
Add a description of the X86_64 assembler's .largcomm pseudo-op.
...
PR 22553
* doc/c-i386.texi (i386-Directives): Document the .largecomm
directive.
2018-01-08 09:29:17 +00:00
Alan Modra
219d1afa89
Update year range in copyright notice of binutils files
2018-01-03 17:49:56 +10:30
Jim Wilson
f923328821
In x86 -n docs, mention that you need an explicit nop fill byte.
...
gas/
PR gas/22464
* doc/c-i386.texi (-n): Clarify docs.
2017-11-29 10:22:26 -08:00
Igor Tsimbalist
ee6872beb1
Enable Intel AVX512_BITALG instructions.
...
Intel has disclosed a set of new instructions. The spec is
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
gas/
* config/tc-i386.c (cpu_arch): Add .avx512_bitalg.
(cpu_noarch): noavx512_bitalg.
* doc/c-i386.texi: Document .avx512_bitalg, noavx512_bitalg.
* testsuite/gas/i386/i386.exp: Add AVX512_BITALG tests.
* testsuite/gas/i386/avx512f_bitalg-intel.d: New test.
* testsuite/gas/i386/avx512f_bitalg.d: Likewise.
* testsuite/gas/i386/avx512f_bitalg.s: Likewise.
* testsuite/gas/i386/avx512vl_bitalg-intel.d: Likewise.
* testsuite/gas/i386/avx512vl_bitalg.d: Likewise.
* testsuite/gas/i386/avx512vl_bitalg.s: Likewise.
* testsuite/gas/i386/x86-64-avx512f_bitalg-intel.d: Likewise.
* testsuite/gas/i386/x86-64-avx512f_bitalg.d: Likewise.
* testsuite/gas/i386/x86-64-avx512f_bitalg.s: Likewise.
* testsuite/gas/i386/x86-64-avx512vl_bitalg-intel.d: Likewise.
* testsuite/gas/i386/x86-64-avx512vl_bitalg.d: Likewise.
* testsuite/gas/i386/x86-64-avx512vl_bitalg.s: Likewise.
opcodes/
* i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F.
(enum): Add EVEX_W_0F3854_P_2.
* i386-dis-evex.h (evex_table): Updated.
* i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG,
CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
(cpu_flags): Add CpuAVX512_BITALG.
* i386-opc.h (enum): Add CpuAVX512_BITALG.
(i386_cpu_flags): Add cpuavx512_bitalg..
* i386-opc.tbl: Add Intel AVX512_BITALG instructions.
* i386-init.h: Regenerate.
* i386-tbl.h: Likewise.
2017-10-23 15:58:18 +03:00
Igor Tsimbalist
8cfcb7659c
Enable Intel AVX512_VNNI instructions.
...
Intel has disclosed a set of new instructions. The spec is
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
gas/
* config/tc-i386.c (cpu_arch): Add .avx512_vnni.
(cpu_noarch): Add noavx512_vnni.
* doc/c-i386.texi: Document .avx512_vnni.
* testsuite/gas/i386/i386.exp: Add AVX512_VNNI tests.
* testsuite/gas/i386/avx512vnni-intel.d: New test.
* testsuite/gas/i386/avx512vnni.d: Likewise.
* testsuite/gas/i386/avx512vnni.s: Likewise.
* testsuite/gas/i386/avx512vnni_vl-intel.d: Likewise.
* testsuite/gas/i386/avx512vnni_vl.d: Likewise.
* testsuite/gas/i386/avx512vnni_vl.s: Likewise.
* testsuite/gas/i386/x86-64-avx512vnni-intel.d: Likewise.
* testsuite/gas/i386/x86-64-avx512vnni.d: Likewise.
* testsuite/gas/i386/x86-64-avx512vnni.s: Likewise.
* testsuite/gas/i386/x86-64-avx512vnni_vl-intel.d: Likewise.
* testsuite/gas/i386/x86-64-avx512vnni_vl.d: Likewise.
* testsuite/gas/i386/x86-64-avx512vnni_vl.s: Likewise.
opcodes/
* i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851.
* i386-dis-evex.h (evex_table): Updated.
* i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI,
CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
(cpu_flags): Add CpuAVX512_VNNI.
* i386-opc.h (enum): Add CpuAVX512_VNNI.
(i386_cpu_flags): Add cpuavx512_vnni.
* i386-opc.tbl Add Intel AVX512_VNNI instructions.
* i386-init.h: Regenerate.
* i386-tbl.h: Likewise.
2017-10-23 15:58:18 +03:00
Igor Tsimbalist
ff1982d53a
Enable Intel VPCLMULQDQ instruction.
...
Intel has disclosed a set of new instructions. The spec is
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
gas/
* config/tc-i386.c (cpu_arch): Add VPCLMULQDQ.
* doc/c-i386.texi: Document VPCLMULQDQ.
* testsuite/gas/i386/i386.exp: Run VPCLMULQDQ tests.
* testsuite/gas/i386/avx512f_vpclmulqdq-intel.d: New test.
* testsuite/gas/i386/avx512f_vpclmulqdq-wig.s: Ditto.
* testsuite/gas/i386/avx512f_vpclmulqdq-wig1-intel.d: Ditto.
* testsuite/gas/i386/avx512f_vpclmulqdq-wig1.d: Ditto.
* testsuite/gas/i386/avx512f_vpclmulqdq.d: Ditto.
* testsuite/gas/i386/avx512f_vpclmulqdq.s: Ditto.
* testsuite/gas/i386/avx512vl_vpclmulqdq-intel.d: Ditto.
* testsuite/gas/i386/avx512vl_vpclmulqdq-wig.s: Ditto.
* testsuite/gas/i386/avx512vl_vpclmulqdq-wig1-intel.d: Ditto.
* testsuite/gas/i386/avx512vl_vpclmulqdq-wig1.d: Ditto.
* testsuite/gas/i386/avx512vl_vpclmulqdq.d: Ditto.
* testsuite/gas/i386/avx512vl_vpclmulqdq.s: Ditto.
* testsuite/gas/i386/vpclmulqdq-intel.d: Ditto.
* testsuite/gas/i386/vpclmulqdq.d: Ditto.
* testsuite/gas/i386/vpclmulqdq.s: Ditto.
* testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-intel.d: Ditto.
* testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-wig.s: Ditto.
* testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-wig1-intel.d: Ditto.
* testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-wig1.d: Ditto.
* testsuite/gas/i386/x86-64-avx512f_vpclmulqdq.d: Ditto.
* testsuite/gas/i386/x86-64-avx512f_vpclmulqdq.s: Ditto.
* testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-intel.d: Ditto.
* testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-wig.s: Ditto.
* testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-wig1-intel.d: Ditto.
* testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-wig1.d: Ditto.
* testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq.d: Ditto.
* testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq.s: Ditto.
* testsuite/gas/i386/x86-64-vpclmulqdq-intel.d: Ditto.
* testsuite/gas/i386/x86-64-vpclmulqdq.d: Ditto.
* testsuite/gas/i386/x86-64-vpclmulqdq.s: Ditto.
opcodes/
* i386-dis.c (enum): Add PREFIX_EVEX_0F3A44.
(enum): Remove VEX_LEN_0F3A44_P_2.
(vex_len_table): Ditto.
(enum): Remove VEX_W_0F3A44_P_2.
(vew_w_table): Ditto.
(prefix_table): Adjust instructions (see prefixes above).
* i386-dis-evex.h (evex_table):
Add new instructions (see prefixes above).
* i386-gen.c (cpu_flag_init): Add VPCLMULQDQ.
(bitfield_cpu_flags): Ditto.
* i386-opc.h (enum): Ditto.
(i386_cpu_flags): Ditto.
(CpuUnused): Comment out to avoid zero-width field problem.
* i386-opc.tbl (vpclmulqdq): New instruction.
* i386-init.h: Regenerate.
* i386-tbl.h: Ditto.
2017-10-23 15:58:18 +03:00
Igor Tsimbalist
8dcf1fadf2
Enable Intel VAES instructions.
...
Intel has disclosed a set of new instructions. The spec is
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
gas/
* config/tc-i386.c (cpu_arch): Add VAES.
* doc/c-i386.texi: Document VAES.
* testsuite/gas/i386/i386.exp: Run VAES tests.
* testsuite/gas/i386/avx512f_vaes-intel.d: New test.
* testsuite/gas/i386/avx512f_vaes-wig.s: Ditto.
* testsuite/gas/i386/avx512f_vaes-wig1-intel.d: Ditto.
* testsuite/gas/i386/avx512f_vaes-wig1.d: Ditto.
* testsuite/gas/i386/avx512f_vaes.d: Ditto.
* testsuite/gas/i386/avx512f_vaes.s: Ditto.
* testsuite/gas/i386/avx512vl_vaes-intel.d: Ditto.
* testsuite/gas/i386/avx512vl_vaes-wig.s: Ditto.
* testsuite/gas/i386/avx512vl_vaes-wig1-intel.d: Ditto.
* testsuite/gas/i386/avx512vl_vaes-wig1.d: Ditto.
* testsuite/gas/i386/avx512vl_vaes.d: Ditto.
* testsuite/gas/i386/avx512vl_vaes.s: Ditto.
* testsuite/gas/i386/vaes-intel.d: Ditto.
* testsuite/gas/i386/vaes.d: Ditto.
* testsuite/gas/i386/vaes.s: Ditto.
* testsuite/gas/i386/x86-64-avx512f_vaes-intel.d: Ditto.
* testsuite/gas/i386/x86-64-avx512f_vaes-wig.s: Ditto.
* testsuite/gas/i386/x86-64-avx512f_vaes-wig1-intel.d: Ditto.
* testsuite/gas/i386/x86-64-avx512f_vaes-wig1.d: Ditto.
* testsuite/gas/i386/x86-64-avx512f_vaes.d: Ditto.
* testsuite/gas/i386/x86-64-avx512f_vaes.s: Ditto.
* testsuite/gas/i386/x86-64-avx512vl_vaes-intel.d: Ditto.
* testsuite/gas/i386/x86-64-avx512vl_vaes-wig.s: Ditto.
* testsuite/gas/i386/x86-64-avx512vl_vaes-wig1-intel.d: Ditto.
* testsuite/gas/i386/x86-64-avx512vl_vaes-wig1.d: Ditto.
* testsuite/gas/i386/x86-64-avx512vl_vaes.d: Ditto.
* testsuite/gas/i386/x86-64-avx512vl_vaes.s: Ditto.
* testsuite/gas/i386/x86-64-vaes-intel.d: Ditto.
* testsuite/gas/i386/x86-64-vaes.d: Ditto.
* testsuite/gas/i386/x86-64-vaes.s: Ditto.
opcodes/
* i386-dis.c (enum): Add PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD,
PREFIX_EVEX_0F38DE, PREFIX_EVEX_0F38DF.
(enum): Remove VEX_LEN_0F38DC_P_2, VEX_LEN_0F38DD_P_2,
VEX_LEN_0F38DE_P_2, VEX_LEN_0F38DF_P_2.
(vex_len_table): Ditto.
(enum): Remove VEX_W_0F38DC_P_2, VEX_W_0F38DD_P_2,
VEX_W_0F38DE_P_2, VEX_W_0F38DF_P_2.
(vew_w_table): Ditto.
(prefix_table): Adjust instructions (see prefixes above).
* i386-dis-evex.h (evex_table):
Add new instructions (see prefixes above).
* i386-gen.c (cpu_flag_init): Add VAES.
(bitfield_cpu_flags): Ditto.
* i386-opc.h (enum): Ditto.
(i386_cpu_flags): Ditto.
* i386-opc.tbl (vaes{enc,dec}{last,}): New instructions.
* i386-init.h: Regenerate.
* i386-tbl.h: Ditto.
2017-10-23 15:58:18 +03:00
Igor Tsimbalist
48521003d5
Enable Intel GFNI instructions.
...
Intel has disclosed a set of new instructions. The spec is
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
gas/
* config/tc-i386.c (cpu_arch): Add .gfni.
* doc/c-i386.texi: Document .gfni.
* testsuite/gas/i386/i386.exp: Add GFNI tests.
* testsuite/gas/i386/avx.s: New GFNI test.
* testsuite/gas/i386/x86-64-avx.s: Likewise.
* testsuite/gas/i386/avx.d: Adjust.
* testsuite/gas/i386/avx-intel.d: Likewise
* testsuite/gas/i386/ilp32/x86-64-avx-intel.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-avx.d: Likewise.
* testsuite/gas/i386/avx512f_gfni-intel.d: New test.
* testsuite/gas/i386/avx512f_gfni.d: Likewise.
* testsuite/gas/i386/avx512f_gfni.s: Likewise.
* testsuite/gas/i386/avx512vl_gfni-intel.d: Likewise.
* testsuite/gas/i386/avx512vl_gfni.d: Likewise.
* testsuite/gas/i386/avx512vl_gfni.s: Likewise.
* testsuite/gas/i386/gfni-intel.d: Likewise.
* testsuite/gas/i386/gfni.d: Likewise.
* testsuite/gas/i386/gfni.s: Likewise.
* testsuite/gas/i386/x86-64-avx512f_gfni-intel.d: Likewise.
* testsuite/gas/i386/x86-64-avx512f_gfni.d: Likewise.
* testsuite/gas/i386/x86-64-avx512f_gfni.s: Likewise.
* testsuite/gas/i386/x86-64-avx512vl_gfni-intel.d: Likewise.
* testsuite/gas/i386/x86-64-avx512vl_gfni.d: Likewise.
* testsuite/gas/i386/x86-64-avx512vl_gfni.s: Likewise.
* testsuite/gas/i386/x86-64-avx_gfni-intel.d: Likewise.
* testsuite/gas/i386/x86-64-avx_gfni.d: Likewise.
* testsuite/gas/i386/x86-64-avx_gfni.s: Likewise.
* testsuite/gas/i386/x86-64-gfni-intel.d: Likewise.
* testsuite/gas/i386/x86-64-gfni.d: Likewise.
* testsuite/gas/i386/x86-64-gfni.s: Likewise.
opcodes/
* i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF,
PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF,
PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF.
(enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2,
EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2.
(prefix_table): Updated (see prefixes above).
(three_byte_table): Likewise.
(vex_w_table): Likewise.
* i386-dis-evex.h: Likewise.
* i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI.
(cpu_flags): Add CpuGFNI.
* i386-opc.h (enum): Add CpuGFNI.
(i386_cpu_flags): Add cpugfni.
* i386-opc.tbl: Add Intel GFNI instructions.
* i386-init.h: Regenerate.
* i386-tbl.h: Likewise.
2017-10-23 15:58:13 +03:00
Igor Tsimbalist
53467f5707
Enable Intel AVX512_VBMI2 instructions.
...
Intel has disclosed a set of new instructions. The spec is
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
gas/
* config/tc-i386.c (cpu_arch): Add .avx512_vbmi2.
(cpu_noarch): noavx512_vbmi2.
* doc/c-i386.texi: Document .avx512_vbmi2, noavx512_vbmi2.
* testsuite/gas/i386/i386.exp: Add AVX512_VBMI2 tests.
* testsuite/gas/i386/avx512vbmi2-intel.d: New test.
* testsuite/gas/i386/avx512vbmi2.d: Likewise.
* testsuite/gas/i386/avx512vbmi2.s: Likewise.
* testsuite/gas/i386/avx512vbmi2_vl-intel.d: Likewise.
* testsuite/gas/i386/avx512vbmi2_vl.d: Likewise.
* testsuite/gas/i386/avx512vbmi2_vl.s: Likewise.
* testsuite/gas/i386/x86-64-avx512vbmi2-intel.d: Likewise.
* testsuite/gas/i386/x86-64-avx512vbmi2.d: Likewise.
* testsuite/gas/i386/x86-64-avx512vbmi2.s: Likewise.
* testsuite/gas/i386/x86-64-avx512vbmi2_vl-intel.d: Likewise.
* testsuite/gas/i386/x86-64-avx512vbmi2_vl.d: Likewise.
* testsuite/gas/i386/x86-64-avx512vbmi2_vl.s: Likewise.
opcodes/
* i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode.
Define EXbScalar and EXwScalar for OP_EX.
(enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863,
PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872,
PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73.
(enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2,
EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2,
EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2,
EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2.
(intel_operand_size): Handle b_scalar_mode and w_scalar_mode.
(OP_E_memory): Likewise.
* i386-dis-evex.h: Updated.
* i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2,
CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
(cpu_flags): Add CpuAVX512_VBMI2.
* i386-opc.h (enum): Add CpuAVX512_VBMI2.
(i386_cpu_flags): Add cpuavx512_vbmi2.
* i386-opc.tbl: Add Intel AVX512_VBMI2 instructions.
* i386-init.h: Regenerate.
* i386-tbl.h: Likewise.
2017-10-23 15:58:07 +03:00
H.J. Lu
86fa6981e7
X86: Add pseudo prefixes to control encoding
...
Many x86 instructions have more than one encodings. Assembler picks
the default one, usually the shortest one. Although the ".s", ".d8"
and ".d32" suffixes can be used to swap register operands or specify
displacement size, they aren't very flexible. This patch adds pseudo
prefixes, {xxx}, to control instruction encoding. The available
pseudo prefixes are {disp8}, {disp32}, {load}, {store}, {vex2}, {vex3}
and {evex}. Pseudo prefixes are preferred over the ".s", ".d8" and
".d32" suffixes, which are deprecated.
gas/
* config/tc-i386.c (_i386_insn): Add dir_encoding and
vec_encoding. Remove swap_operand and need_vrex.
(extra_symbol_chars): Add '}'.
(md_begin): Mark '}' with LEX_BEGIN_NAME. Allow '}' in
mnemonic.
(build_vex_prefix): Don't use 2-byte VEX encoding with
{vex3}. Check dir_encoding and load.
(parse_insn): Check pseudo prefixes. Set dir_encoding.
(VEX_check_operands): Likewise.
(match_template): Check dir_encoding and load.
(parse_real_register): Set vec_encoding instead of need_vrex.
(parse_register): Likewise.
* doc/c-i386.texi: Document {disp8}, {disp32}, {load}, {store},
{vex2}, {vex3} and {evex}. Remove ".s", ".d8" and ".d32"
* testsuite/gas/i386/i386.exp: Run pseudos and x86-64-pseudos.
* testsuite/gas/i386/pseudos.d: New file.
* testsuite/gas/i386/pseudos.s: Likewise.
* testsuite/gas/i386/x86-64-pseudos.d: Likewise.
* testsuite/gas/i386/x86-64-pseudos.s: Likewise.
opcodes/
* i386-gen.c (opcode_modifiers): Replace S with Load.
* i386-opc.h (S): Removed.
(Load): New.
(i386_opcode_modifier): Replace s with load.
* i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
and {evex}. Replace S with Load.
* i386-tbl.h: Regenerated.
2017-03-09 09:59:00 -08:00
H.J. Lu
603555e563
Add support for Intel CET instructions
...
Support Intel Control-flow Enforcement Technology (CET) instructions:
https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf
gas/
* config/tc-i386.c (cpu_arch): Add .cet.
* doc/c-i386.texi: Document cet.
* testsuite/gas/i386/cet-intel.d: New file.
* testsuite/gas/i386/cet.d: Likewise.
* testsuite/gas/i386/cet.s: Likewise.
* testsuite/gas/i386/x86-64-cet-intel.d: Likewise.
* testsuite/gas/i386/x86-64-cet.d: Likewise.
* testsuite/gas/i386/x86-64-cet.s: Likewise.
* testsuite/gas/i386/i386.exp: Run Intel CET tests.
opcodes/
* i386-dis.c (REG_0F1E_MOD_3): New enum.
(MOD_0F1E_PREFIX_1): Likewise.
(MOD_0F38F5_PREFIX_2): Likewise.
(MOD_0F38F6_PREFIX_0): Likewise.
(RM_0F1E_MOD_3_REG_7): Likewise.
(PREFIX_MOD_0_0F01_REG_5): Likewise.
(PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
(PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
(PREFIX_0F1E): Likewise.
(PREFIX_MOD_0_0FAE_REG_5): Likewise.
(PREFIX_0F38F5): Likewise.
(dis386_twobyte): Use PREFIX_0F1E.
(reg_table): Add REG_0F1E_MOD_3.
(prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
(three_byte_table): Use PREFIX_0F38F5.
(mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
(rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
PREFIX_MOD_3_0F01_REG_5_RM_2.
* i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
(cpu_flags): Add CpuCET.
* i386-opc.h (CpuCET): New enum.
(CpuUnused): Commented out.
(i386_cpu_flags): Add cpucet.
* i386-opc.tbl: Add Intel CET instructions.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2017-03-06 15:26:37 -08:00
Nick Clifton
33eaf5de31
Fix spelling mistakes and typos in the GAS sources.
...
PR gas/21072
* asintl.h: Fix spelling mistakes and typos.
* atof-generic.c: Likewise.
* bit_fix.h: Likewise.
* config/atof-ieee.c: Likewise.
* config/bfin-defs.h: Likewise.
* config/bfin-parse.y: Likewise.
* config/obj-coff-seh.h: Likewise.
* config/obj-coff.c: Likewise.
* config/obj-evax.c: Likewise.
* config/obj-macho.c: Likewise.
* config/rx-parse.y: Likewise.
* config/tc-aarch64.c: Likewise.
* config/tc-alpha.c: Likewise.
* config/tc-arc.c: Likewise.
* config/tc-arm.c: Likewise.
* config/tc-avr.c: Likewise.
* config/tc-bfin.c: Likewise.
* config/tc-cr16.c: Likewise.
* config/tc-cris.c: Likewise.
* config/tc-crx.c: Likewise.
* config/tc-d10v.c: Likewise.
* config/tc-d30v.c: Likewise.
* config/tc-dlx.c: Likewise.
* config/tc-epiphany.c: Likewise.
* config/tc-frv.c: Likewise.
* config/tc-hppa.c: Likewise.
* config/tc-i370.c: Likewise.
* config/tc-i386-intel.c: Likewise.
* config/tc-i386.c: Likewise.
* config/tc-i960.c: Likewise.
* config/tc-ia64.c: Likewise.
* config/tc-m32r.c: Likewise.
* config/tc-m68hc11.c: Likewise.
* config/tc-m68k.c: Likewise.
* config/tc-mcore.c: Likewise.
* config/tc-mep.c: Likewise.
* config/tc-mep.h: Likewise.
* config/tc-metag.c: Likewise.
* config/tc-microblaze.c: Likewise.
* config/tc-mips.c: Likewise.
* config/tc-mmix.c: Likewise.
* config/tc-mn10200.c: Likewise.
* config/tc-mn10300.c: Likewise.
* config/tc-msp430.c: Likewise.
* config/tc-msp430.h: Likewise.
* config/tc-nds32.c: Likewise.
* config/tc-nds32.h: Likewise.
* config/tc-nios2.c: Likewise.
* config/tc-nios2.h: Likewise.
* config/tc-ns32k.c: Likewise.
* config/tc-pdp11.c: Likewise.
* config/tc-ppc.c: Likewise.
* config/tc-pru.c: Likewise.
* config/tc-rx.c: Likewise.
* config/tc-s390.c: Likewise.
* config/tc-score.c: Likewise.
* config/tc-score7.c: Likewise.
* config/tc-sh.c: Likewise.
* config/tc-sh64.c: Likewise.
* config/tc-sparc.c: Likewise.
* config/tc-tic4x.c: Likewise.
* config/tc-tic54x.c: Likewise.
* config/tc-v850.c: Likewise.
* config/tc-vax.c: Likewise.
* config/tc-visium.c: Likewise.
* config/tc-xgate.c: Likewise.
* config/tc-xtensa.c: Likewise.
* config/tc-z80.c: Likewise.
* config/tc-z8k.c: Likewise.
* config/te-vms.c: Likewise.
* config/xtensa-relax.c: Likewise.
* doc/as.texinfo: Likewise.
* doc/c-arm.texi: Likewise.
* doc/c-hppa.texi: Likewise.
* doc/c-i370.texi: Likewise.
* doc/c-i386.texi: Likewise.
* doc/c-m32r.texi: Likewise.
* doc/c-m68k.texi: Likewise.
* doc/c-mmix.texi: Likewise.
* doc/c-msp430.texi: Likewise.
* doc/c-nds32.texi: Likewise.
* doc/c-ns32k.texi: Likewise.
* doc/c-riscv.texi: Likewise.
* doc/c-rx.texi: Likewise.
* doc/c-s390.texi: Likewise.
* doc/c-tic6x.texi: Likewise.
* doc/c-tilegx.texi: Likewise.
* doc/c-tilepro.texi: Likewise.
* doc/c-v850.texi: Likewise.
* doc/c-xgate.texi: Likewise.
* doc/c-xtensa.texi: Likewise.
* dwarf2dbg.c: Likewise.
* ecoff.c: Likewise.
* itbl-ops.c: Likewise.
* listing.c: Likewise.
* macro.c: Likewise.
* po/gas.pot: Likewise.
* read.c: Likewise.
* struc-symbol.h: Likewise.
* symbols.h: Likewise.
* testsuite/gas/arc/relocs-errors.err: Likewise.
* write.c: Likewise.
2017-01-23 15:23:07 +00:00
Igor Tsimbalist
620214f742
Enable Intel AVX512_VPOPCNTDQ instructions
...
gas/
2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
* config/tc-i386.c (cpu_arch): Add .avx512_vpopcntdq.
(cpu_noarch): Add noavx512_vpopcntdq.
* doc/c-i386.texi: Document avx512_vpopcntdq, noavx512_vpopcntdq.
* testsuite/gas/i386/i386.exp: Run AVX512_VPOPCNTDQ tests.
* testsuite/gas/i386/avx512_vpopcntdqd-intel.d: New file.
* testsuite/gas/i386/avx512_vpopcntdqd.d: Ditto.
* testsuite/gas/i386/avx512_vpopcntdqd.s: Ditto.
* testsuite/gas/i386/x86-64-avx512_vpopcntdqd-intel.d: Ditto.
* testsuite/gas/i386/x86-64-avx512_vpopcntdqd.d: Ditto.
* testsuite/gas/i386/x86-64-avx512_vpopcntdqd.s: Ditto.
opcodes/
2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
* i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
* i386-dis-evex.h (evex_table): Updated.
* i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
(cpu_flags): Add CpuAVX512_VPOPCNTDQ.
* i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
(i386_cpu_flags): Add cpuavx512_vpopcntdq.
* i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
* i386-init.h: Regenerate.
* i386-tbl.h: Ditto.
2017-01-12 08:44:24 -08:00
Alan Modra
2571583aed
Update year range in copyright notice of all files.
2017-01-02 14:08:56 +10:30
Igor Tsimbalist
47acf0bd9f
Enable Intel AVX512_4VNNIW instructions
...
gas/
* config/tc-i386.c: (cpu_arch) Add .avx512_4vnniw.
(cpu_noarch): Add noavx512_4vnniw.
* doc/c-i386.texi: Document avx512_4vnniw, noavx512_4vnniw.
* testsuite/gas/i386/i386.exp: Run AVX512_4VNNIW tests.
* testsuite/gas/i386/avx512_4vnniwd_vl-intel.d: New test.
* testsuite/gas/i386/avx512_4vnniwd_vl.d: Ditto.
* testsuite/gas/i386/avx512_4vnniwd_vl.s: Ditto.
* testsuite/gas/i386/avx512_4vnniwd-intel.d: Ditto.
* testsuite/gas/i386/avx512_4vnniwd.d: Ditto.
* testsuite/gas/i386/avx512_4vnniwd.s: Ditto.
* testsuite/gas/i386/x86-64-avx512_4vnniwd_vl-intel.d: Ditto.
* testsuite/gas/i386/x86-64-avx512_4vnniwd_vl.d: Ditto.
* testsuite/gas/i386/x86-64-avx512_4vnniwd_vl.s: Ditto.
* testsuite/gas/i386/x86-64-avx512_4vnniwd-intel.d: Ditto.
* testsuite/gas/i386/x86-64-avx512_4vnniwd.d: Ditto.
* testsuite/gas/i386/x86-64-avx512_4vnniwd.s: Ditto.
opcodes/
* i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
* i386-dis-evex.h (evex_table): Updated.
* i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
(cpu_flags): Add CpuAVX512_4VNNIW.
* i386-opc.h (enum): (AVX512_4VNNIW): New.
(i386_cpu_flags): Add cpuavx512_4vnniw.
* i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
* i386-init.h: Regenerate.
* i386-tbl.h: Ditto.
2016-11-02 12:31:25 -07:00
Igor Tsimbalist
920d2ddccb
Enable Intel AVX512_4FMAPS instructions
...
gas/
* config/tc-i386.c (cpu_arch): Add .avx512_4fmaps.
(cpu_noarch): Add noavx512_4fmaps.
(process_operands): Handle implicit quad group.
* doc/c-i386.texi: Document avx512_4fmaps, noavx512_4fmaps.
* testsuite/gas/i386/i386.exp: Add AVX512_4FMAPS tests.
* testsuite/gas/i386/avx512_4fmaps_vl-intel.d: New test.
* testsuite/gas/i386/avx512_4fmaps_vl.d: Ditto.
* testsuite/gas/i386/avx512_4fmaps_vl.s: Ditto.
* testsuite/gas/i386/avx512_4fmaps-intel.d: Ditto.
* testsuite/gas/i386/avx512_4fmaps.d: Ditto.
* testsuite/gas/i386/avx512_4fmaps.s: Ditto.
* testsuite/gas/i386/avx512_4fmaps-warn.l: Ditto.
* testsuite/gas/i386/avx512_4fmaps-warn.s: Ditto.
* testsuite/gas/i386/avx512_4fmaps_vl-warn.l: Ditto.
* testsuite/gas/i386/avx512_4fmaps_vl-warn.s: Ditto.
* testsuite/gas/i386/x86-64-avx512_4fmaps_vl-intel.d: Ditto.
* testsuite/gas/i386/x86-64-avx512_4fmaps_vl.d: Ditto.
* testsuite/gas/i386/x86-64-avx512_4fmaps_vl.s: Ditto.
* testsuite/gas/i386/x86-64-avx512_4fmaps-intel.d: Ditto.
* testsuite/gas/i386/x86-64-avx512_4fmaps.d: Ditto.
* testsuite/gas/i386/x86-64-avx512_4fmaps.s: Ditto.
* testsuite/gas/i386/x86-64-avx512_4fmaps-warn.l: Ditto.
* testsuite/gas/i386/x86-64-avx512_4fmaps-warn.s: Ditto.
* testsuite/gas/i386/x86-64-avx512_4fmaps_vl-warn.l: Ditto.
* testsuite/gas/i386/x86-64-avx512_4fmaps_vl-warn.s: Ditto.
opcodes/
* i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
* i386-dis-evex.h (evex_table): Updated.
* i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
(cpu_flags): Add CpuAVX512_4FMAPS.
(opcode_modifiers): Add ImplicitQuadGroup modifier.
* i386-opc.h (AVX512_4FMAP): New.
(i386_cpu_flags): Add cpuavx512_4fmaps.
(ImplicitQuadGroup): New.
(i386_opcode_modifier): Add implicitquadgroup.
* i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
* i386-init.h: Regenerate.
* i386-tbl.h: Ditto.
2016-11-02 12:25:34 -07:00
H.J. Lu
b5cefccad8
X86: Remove pcommit instruction
...
Remove x86 pcommit instruction support, which has been deprecated:
https://software.intel.com/en-us/blogs/2016/09/12/deprecate-pcommit-instruction
gas/
* config/tc-i386.c (cpu_arch): Remove .pcommit.
* doc/c-i386.texi: Likewise.
* testsuite/gas/i386/i386.exp: Remove pcommit tests.
* testsuite/gas/i386/pcommit-intel.d: Removed.
* testsuite/gas/i386/pcommit.d: Likewise.
* testsuite/gas/i386/pcommit.s: Likewise.
* testsuite/gas/i386/x86-64-pcommit-intel.d: Likewise.
* testsuite/gas/i386/x86-64-pcommit.d: Likewise.
* testsuite/gas/i386/x86-64-pcommit.s: Likewise.
opcodes/
* i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
(prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
(rm_table): Update the RM_0FAE_REG_7 entry.
* i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
(cpu_flags): Remove CpuPCOMMIT.
* i386-opc.h (CpuPCOMMIT): Removed.
(i386_cpu_flags): Remove cpupcommit.
* i386-opc.tbl: Remove pcommit.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2016-10-21 12:16:32 -07:00
H.J. Lu
6b40c46231
X86: Add ptwrite instruction
...
Implement ptwrite instruction defined in Intel64 and IA-32 Architectures
Software Developer’s Manual, June 2016.
gas/
* config/tc-i386.c (cpu_arch): Add .ptwrite.
* doc/c-i386.texi: Document ptwrite and .ptwrite.
* testsuite/gas/i386/i386.exp: Run ptwrite, ptwrite-intel,
x86-64-ptwrite and x86-64-ptwrite-intel.
* testsuite/gas/i386/ptwrite-intel.d: New file.
* testsuite/gas/i386/ptwrite.d: Likewise.
* testsuite/gas/i386/ptwrite.s: Likewise.
* testsuite/gas/i386/x86-64-ptwrite-intel.d: Likewise.
* testsuite/gas/i386/x86-64-ptwrite.d: Likewise.
* testsuite/gas/i386/x86-64-ptwrite.s: Likewise.
opcodes/
* i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
(PREFIX_MOD_3_0FAE_REG_4): Likewise.
(prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
PREFIX_MOD_3_0FAE_REG_4.
(mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
PREFIX_MOD_3_0FAE_REG_4.
* i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
(cpu_flags): Add CpuPTWRITE.
* i386-opc.h (CpuPTWRITE): New.
(i386_cpu_flags): Add cpuptwrite.
* i386-opc.tbl: Add ptwrite instruction.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2016-08-24 15:29:39 -07:00
H.J. Lu
144b71e2a8
Add .noavx512XX directives to x86 assembler
...
Add .noavx512f, .noavx512cd, .noavx512er, .noavx512pf, .noavx512dq,
.noavx512bw, .noavx512vl, .noavx512ifma, .noavx512vbmi directives to x86
assembler.
gas/
PR gas/20145
* config/tc-i386.c (cpu_noarch): Add noavx512f, noavx512cd,
noavx512er, noavx512pf, noavx512dq, noavx512bw, noavx512vl,
noavx512ifma and noavx512vbmi.
* doc/c-i386.texi: Mention noavx512f, noavx512cd, noavx512er,
noavx512pf, noavx512dq, noavx512bw, noavx512vl, noavx512ifma
and noavx512vbmi.
* testsuite/gas/i386/i386.exp: Run noavx512-1 and noavx512-2.
* testsuite/gas/i386/noavx512-1.l: New file.
* testsuite/gas/i386/noavx512-1.s: Likewise.
* testsuite/gas/i386/noavx512-2.l: Likewise.
* testsuite/gas/i386/noavx512-2.s: Likewise.
opcodes/
PR gas/20145
* i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
* i386-init.h: Regenerated.
2016-05-29 07:56:23 -07:00
H.J. Lu
1848e56734
Update x86 CPU_XXX_FLAGS handling
...
Support defining CPU_XXX_FLAGS with other CPU_XXX_FLAGS. Update
CPU_XXX_FLAGS to enable more bits like x87 and SYSCALL. Don't enable
MMX when enabling SSE, AVX or AVX512. Don't disable AVX nor AVX512 when
disabling SSE. Don't disable AVX512 when disabling AVX. Disable F16C,
FMA, FMA4 and XOP when disabling AVX. Add 87, no287, no387, no687,
nosse2, nosse3, nossse3, nosse4.1, nosse4.2, nosse4 and noavx2 directives
to x86 assembler.
TODO: Add more .noXXX, like .noavx512f, directives to x86 assembler.
gas/
PR gas/20145
* config/tc-i386.c (cpu_arch): Add 687.
(cpu_noarch): Add no287, no387, no687, nosse2, nosse3, nossse3,
nosse4.1, nosse4.2, nosse4 and noavx2.
(parse_real_register): Check cpuregmmx instead of cpummx for MMX
register. Check cpuregxmm instead of cpusse for XMM register.
Check cpuregymm instead of cpuavx for YMM register. Check
cpuregzmm/cpuregmask instead of cpuavx512f for ZMMM/mask register.
* doc/c-i386.texi: Mention 687, no287, no387, no687, nosse2,
nosse3, nossse3, nosse4.1, nosse4.2, nosse4 and noavx2.
* testsuite/gas/i386/arch-10-prefetchw.d (as): Add mmx.
* testsuite/gas/i386/arch-10.d (as): Likewise.
* testsuite/gas/i386/arch-11.s: Add ".arch .mmx".
* testsuite/gas/i386/i386.exp: Pass mmx to assembler for
arch-10-3 and arch-10-4. Run no87-3, nosse-4, nosse-5, noavx-3
and noavx-4.
* testsuite/gas/i386/no87-3.l: New file.
* testsuite/gas/i386/no87-3.s: Likewise.
* testsuite/gas/i386/noavx-3.l: Likewise.
* testsuite/gas/i386/noavx-3.s: Likewise.
* testsuite/gas/i386/noavx-4.d: Likewise.
* testsuite/gas/i386/noavx-4.s: Likewise.
* testsuite/gas/i386/nosse-4.l: Likewise.
* testsuite/gas/i386/nosse-4.s: Likewise.
* testsuite/gas/i386/nosse-5.d: Likewise.
* testsuite/gas/i386/nosse-5.s: Likewise.
opcodes/
PR gas/20145
* i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
CpuRegMask for AVX512.
(cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
and CpuRegMask.
(set_bitfield_from_cpu_flag_init): New function.
(set_bitfield): Remove const on f. Call
set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
* i386-opc.h (CpuRegMMX): New.
(CpuRegXMM): Likewise.
(CpuRegYMM): Likewise.
(CpuRegZMM): Likewise.
(CpuRegMask): Likewise.
(i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
and cpuregmask.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2016-05-27 10:05:57 -07:00
Alexander Fomin
8bc526963e
Enable Intel RDPID instruction.
...
This patch enables Intel RDPID instruction described in Intel64 and
IA-32 Architectures Software Developer's Manual, April 2016.
gas/
* config/tc-i386.c (cpu_arch): Add RDPID.
* doc/c-i386.texi: Document RDPID.
gas/testsuite/
* gas/i386/i386.exp: Run RDPID tests.
* gas/i386/prefix.d: Adjust.
* gas/i386/rdpid.s: New test.
* gas/i386/rdpid.d: Ditto.
* gas/i386/rdpid-intel.d: Ditto.
* gas/i386/x86-64-rdpid.s: Ditto.
* gas/i386/x86-64-rdpid.d: Ditto.
* gas/i386/x86-64-rdpid-intel.d: Ditto.
opcodes/
* i386-dis.c (prefix_table): Add RDPID instruction.
* i386-gen.c (cpu_flag_init): Add RDPID flag.
(cpu_flags): Add RDPID bitfield.
* i386-opc.h (enum): Add RDPID element.
(i386_cpu_flags): Add RDPID field.
* i386-opc.tbl: Add RDPID instruction.
* i386-init.h: Regenerate.
* i386-tbl.h: Regenerate.
2016-05-10 21:38:39 +03:00
Ulrich Drepper
4bde3cdd70
Update x86 register name documentation.
...
* doc/c-i386.texi (Register Naming): Update to details of the
latest architecture version.
2016-03-15 11:00:28 +00:00
H.J. Lu
0cb4071ef9
Add -mrelax-relocations= to x86 assembler
...
The x86 relax relocations introduced in binutils 2.26 aren't supported
by linker on Solaris older than Solaris 12. To use x86 assembler with
older Solaris linker, this patch adds
1. A command line option -mrelax-relocations= to x86 assembler to
control whether to generate relax relocations.
2. A configure option --enable-x86-relax-relocations to decide whether
x86 assembler should generate relax relocations by default. It is
defaulted to yes, except for x86 Solaris targets older than Solaris 12.
gas/
PR gas/19520
* NEWS: Mention new command line option -mrelax-relocations and
new configure option --enable-x86-relax-relocations for x86
target.
* config.in: Regenerated.
* configure.ac: Add --enable-x86-relax-relocations.
(ac_default_x86_relax_relocations): New. Default to 1 except
for x86 Solaris targets older than Solaris 12.
(DEFAULT_GENERATE_X86_RELAX_RELOCATIONS): Define.
* configure: Likewise.
* config/tc-i386.c (generate_relax_relocations): New.
(OPTION_MRELAX_RELOCATIONS): Likewise.
(output_disp): Don't generate relax relocations if
generate_relax_relocations is 0.
(md_longopts): Add -mrelax-relocations.
(md_show_usage): Likewise.
(md_parse_option): Handle OPTION_MRELAX_RELOCATIONS.
* doc/c-i386.texi: Document -mrelax-relocations=.
* testsuite/gas/i386/got-no-relax.d: New file.
* testsuite/gas/i386/x86-64-gotpcrel-no-relax.d: Likewise.
* testsuite/gas/i386/got.d: Pass -mrelax-relocations=yes to as.
* testsuite/gas/i386/localpic.d: Likewise.
* testsuite/gas/i386/mixed-mode-reloc32.d: Likewise.
* testsuite/gas/i386/reloc32.d: Likewise.
* testsuite/gas/i386/x86-64-gotpcrel.d: Likewise.
* testsuite/gas/i386/x86-64-localpic.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-gotpcrel.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-localpic.d: Likewise.
* testsuite/gas/i386/i386.exp: Run got-no-relax and
x86-64-gotpcrel-no-relax.
ld/
PR gas/19520
* testsuite/ld-i386/branch1.d: Pass -mrelax-relocations=yes to as.
* testsuite/ld-i386/call1.d: Likewise.
* testsuite/ld-i386/call2.d: Likewise.
* testsuite/ld-i386/call3a.d: Likewise.
* testsuite/ld-i386/call3b.d: Likewise.
* testsuite/ld-i386/call3c.d: Likewise.
* testsuite/ld-i386/call3d.d: Likewise.
* testsuite/ld-i386/call3e.d: Likewise.
* testsuite/ld-i386/call3f.d: Likewise.
* testsuite/ld-i386/call3g.d: Likewise.
* testsuite/ld-i386/call3h.d: Likewise.
* testsuite/ld-i386/jmp1.d: Likewise.
* testsuite/ld-i386/jmp2.d: Likewise.
* testsuite/ld-i386/lea1c.d: Likewise.
* testsuite/ld-i386/load1.d: Likewise.
* testsuite/ld-i386/load2.d: Likewise.
* testsuite/ld-i386/load3.d: Likewise.
* testsuite/ld-i386/load4a.d: Likewise.
* testsuite/ld-i386/load5a.d: Likewise.
* testsuite/ld-i386/mov2b.d: Likewise.
* testsuite/ld-i386/mov3.d: Likewise.
* testsuite/ld-ifunc/ifunc-21-x86-64.d: Likewise.
* testsuite/ld-ifunc/ifunc-22-x86-64.d: Likewise.
* testsuite/ld-ifunc/ifunc-5r-local-x86-64.d: Likewise.
* testsuite/ld-x86-64/call1a.d: Likewise.
* testsuite/ld-x86-64/call1b.d: Likewise.
* testsuite/ld-x86-64/call1c.d: Likewise.
* testsuite/ld-x86-64/call1d.d: Likewise.
* testsuite/ld-x86-64/call1e.d: Likewise.
* testsuite/ld-x86-64/call1f.d: Likewise.
* testsuite/ld-x86-64/call1h.d: Likewise.
* testsuite/ld-x86-64/call1i.d: Likewise.
* testsuite/ld-x86-64/load1a.d: Likewise.
* testsuite/ld-x86-64/load1b.d: Likewise.
* testsuite/ld-i386/got1a.S: Load GOT into %ecx and use it.
* testsuite/ld-i386/got1.dd: Updated.
* testsuite/ld-i386/got1d.S (1): Removed.
* testsuite/ld-i386/i386.exp: Add -Wa,-mrelax-relocations=yes.
* testsuite/ld-x86-64/x86-64.exp: Likewise.
2016-02-03 08:25:15 -08:00
Andrew Senkevich
e4e00185b5
Add option -mfence-as-lock-add=[no|yes].
...
With -mfence-as-lock-add=yes lfence, mfence and sfence will be encoded
as lock addl $0x0, (%{r,e}sp).
gas/:
* config/tc-i386.c (avoid_fence): New.
(output_insn): Encode as lock addl $0x0, (%{r,e}sp) if avoid_fence
is true.
(OPTION_FENCE_AS_LOCK_ADD): New.
(md_longopts): Add -mfence-as-lock-add.
(md_parse_option): Handle -mfence-as-lock-add.
(md_show_usage): Add -mfence-as-lock-add=[no|yes].
* doc/c-i386.texi (-mfence-as-lock-add): Document.
gas/testsuite/:
* gas/i386/i386.exp: Run new tests.
* gas/i386/fence-as-lock-add.s: New.
* gas/i386/fence-as-lock-add-yes.d: Likewise.
* gas/i386/fence-as-lock-add-no.d: Likewise.
* gas/i386/x86-64-fence-as-lock-add-yes.d: Likewise.
* gas/i386/x86-64-fence-as-lock-add-no.d: Likewise.
2016-01-29 15:46:50 +03:00
Alan Modra
6f2750feaf
Copyright update for binutils
2016-01-01 23:00:01 +10:30
Amit Pawar
9916071f8d
Add support for monitorx/mwaitx instructions
...
gas/
* config/tc-i386.c (cpu_arch): Add .mwaitx.
(process_immext): Check operands for monitorx/mwaitx instructions.
* doc/c-i386.texi: Document mwaitx.
gas/testsuite/
* gas/i386/i386.exp: Add new mwaitx test cases.
* gas/i386/mwaitx.s: New.
* gas/i386/mwaitx-bdver4.d: New.
* gas/i386/x86-64-mwaitx.s: New.
* gas/i386/x86-64-mwaitx-bdver4.d: New.
* gas/i386/mwaitx-reg.s: New.
* gas/i386/mwaitx-reg.l: New.
* gas/i386/x86-64-mwaitx-reg.l: New.
* gas/i386/x86-64-mwaitx-reg.s: New.
* gas/i386/arch-13.s: Updated.
* gas/i386/arch-13.d: Updated.
* gas/i386/arch-13-znver1.d: Updated.
* gas/i386/x86-64-arch-3.s: Updated.
* gas/i386/x86-64-arch-3.d: Updated.
* gas/i386/x86-64-arch-3-znver1.d: Updated.
opcodes/
* i386-dis.c (OP_Mwaitx): New.
(rm_table): Add monitorx/mwaitx.
* i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS.
(operand_type_init): Add CpuMWAITX.
* i386-opc.h (CpuMWAITX): New.
(i386_cpu_flags): Add cpumwaitx.
* i386-opc.tbl: Add monitorx and mwaitx.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2015-06-30 07:50:12 -07:00
H.J. Lu
5db04b0965
Support AMD64/Intel ISAs in assembler/disassembler
...
AMD64 spec and Intel64 spec differ in direct unconditional branches in
64-bit mode. AMD64 supports direct unconditional branches with 16-bit
offset via the data size prefix, which truncates RIP to 16 bits, while
the data size prefix is ignored by Intel64.
This patch adds -mamd64/-mintel64 option to x86-64 assembler and
-Mamd64/-Mintel64 option to x86-64 disassembler. The most permissive
ISA, which is AMD64, is the default.
GDB can add an option, similar to
(gdb) help set disassembly-flavor
Set the disassembly flavor.
The valid values are "att" and "intel", and the default value is "att".
to select which ISA to disassemble.
binutils/
PR binutis/18386
* doc/binutils.texi: Document -Mamd64 and -Mintel64.
gas/
PR binutis/18386
* config/tc-i386.c (OPTION_MAMD64): New.
(OPTION_MINTEL64): Likewise.
(md_longopts): Add -mamd64 and -mintel64.
(md_parse_option): Handle OPTION_MAMD64 and OPTION_MINTEL64.
(md_show_usage): Add -mamd64 and -mintel64.
* doc/c-i386.texi: Document -mamd64 and -mintel64.
gas/testsuite/
PR binutis/18386
* gas/i386/i386.exp: Run x86-64-branch-2 and x86-64-branch-3.
* gas/i386/x86-64-branch.d: Also pass -Mintel64 to objdump.
* gas/i386/ilp32/x86-64-branch.d: Likewise.
* gas/i386/x86-64-branch-2.d: New file.
* gas/i386/x86-64-branch-2.s: Likewise.
* gas/i386/x86-64-branch-3.l: Likewise.
* gas/i386/x86-64-branch-3.s: Likewise.
ld/testsuite/
PR binutis/18386
* ld-x86-64/tlsgdesc.dd: Also pass -Mintel64 to objdump.
* ld-x86-64/tlspic.dd: Likewise.
* ld-x86-64/x86-64.exp (x86_64tests): Also pass -Mintel64 to
objdump for tlspic.dd and tlsgdesc.dd.
opcodes/
PR binutis/18386
* i386-dis.c: Add comments for '@'.
(x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
(enum x86_64_isa): New.
(isa64): Likewise.
(print_i386_disassembler_options): Add amd64 and intel64.
(print_insn): Handle amd64 and intel64.
(putop): Handle '@'.
(OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
* i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
* i386-opc.h (AMD64): New.
(CpuIntel64): Likewise.
(i386_cpu_flags): Add cpuamd64 and cpuintel64.
* i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
Mark direct call/jmp without Disp16|Disp32 as Intel64.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2015-05-15 09:48:10 -07:00
H.J. Lu
8dcea93252
Add -mshared option to x86 ELF assembler
...
This patch adds -mshared option to x86 ELF assembler. By default,
assembler will optimize out non-PLT relocations against defined non-weak
global branch targets with default visibility. The -mshared option tells
the assembler to generate code which may go into a shared library
where all non-weak global branch targets with default visibility can
be preempted. The resulting code is slightly bigger. This option
only affects the handling of branch instructions.
This Linux kernel patch is needed to create a working x86 Linux kernel if
it hasn't been applied:
diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S
index ae6588b..b91a00c 100644
--- a/arch/x86/kernel/head_64.S
+++ b/arch/x86/kernel/head_64.S
@@ -339,8 +339,8 @@ early_idt_handlers:
i = i + 1
.endr
-/* This is global to keep gas from relaxing the jumps */
-ENTRY(early_idt_handler)
+/* This is weak to keep gas from relaxing the jumps */
+WEAK(early_idt_handler)
cld
cmpl $2,(%rsp) # X86_TRAP_NMI
--
gas/
* config/tc-i386.c (shared): New.
(OPTION_MSHARED): Likewise.
(elf_symbol_resolved_in_segment_p): Add relocation argument.
Check PLT relocations and shared.
(md_estimate_size_before_relax): Pass fragP->fr_var to
elf_symbol_resolved_in_segment_p.
(md_longopts): Add -mshared.
(md_show_usage): Likewise.
(md_parse_option): Handle OPTION_MSHARED.
* doc/c-i386.texi: Document -mshared.
gas/testsuite/
* gas/i386/i386.exp: Don't run pcrel for ELF targets. Run
pcrel-elf, relax-4 and x86-64-relax-3 for ELF targets.
* gas/i386/pcrel-elf.d: New file.
* gas/i386/relax-4.d: Likewise.
* gas/i386/x86-64-relax-3.d: Likewise.
* gas/i386/relax-3.d: Pass -mshared to assembler. Updated.
* gas/i386/x86-64-relax-2.d: Likewise.
* gas/i386/relax-3.s: Add test for PLT relocation.
2015-05-15 03:30:53 -07:00
