Commit Graph

66 Commits

Author SHA1 Message Date
Chris Demetriou b96e7ef1a0 2002-03-05 Chris Demetriou <cgd@broadcom.com>
* sim-main.h (UndefinedResult, Unpredictable): New macros
        which currently do nothing.
2002-03-06 06:46:29 +00:00
Chris Demetriou d35d4f709f 2002-03-05 Chris Demetriou <cgd@broadcom.com>
* sim-main.h (status_UX, status_SX, status_KX, status_TS)
        (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
        (status_CU3): New definitions.

        * sim-main.h (ExceptionCause): Add new values for MIPS32
        and MIPS64: MDMX, MCheck, CacheErr.  Update comments
        for DebugBreakPoint and NMIReset to note their status in
        MIPS32 and MIPS64.
        (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
        (SignalExceptionCacheErr): New exception macros.
2002-03-06 06:21:17 +00:00
Chris Demetriou 3ad6f714f2 2002-03-05 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_fpu): Enable check for coprocessor 1 usability.
        * sim-main.h (COP_Usable): Define, but for now coprocessor 1
        is always enabled.
        (SignalExceptionCoProcessorUnusable): Take as argument the
        unusable coprocessor number.
2002-03-06 05:41:40 +00:00
Chris Demetriou 3dea6720b3 2002-02-05 Chris Demetriou <cgd@broadcom.com>
* sim-main.h (SIGNEXTEND): Remove.
2002-03-05 19:22:13 +00:00
Fred Fish 9e52972e45 2001-11-17 Fred Fish <fnf@redhat.com>
* sim-main.h (float_operation): Move enum declaration outside
	of _sim_cpu struct declaration.
2001-11-18 06:00:29 +00:00
Jim Blandy c0efbca4a3 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
PENDING_FILL.  Use PENDING_SCHED directly to handle the pending
set of the FCSR.
* sim-main.h (COCIDX): Remove definition; this isn't supported by
PENDING_FILL, and you can get the intended effect gracefully by
calling PENDING_SCHED directly.
2001-04-12 14:53:20 +00:00
Ben Elliston fb891446b7 2001-02-23 Ben Elliston <bje@redhat.com>
* sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
	already defined elsewhere.
2001-02-24 02:43:11 +00:00
Ben Elliston 8030f85769 2001-02-19 Ben Elliston <bje@redhat.com>
* sim-main.h (sim_monitor): Return an int.
	* interp.c (sim_monitor): Add return values.
	(signal_exception): Handle error conditions from sim_monitor.
2001-02-19 21:57:03 +00:00
Frank Ch. Eigler d3ee60d90e * cleanup
2000-10-19  Frank Ch. Eigler  <fche@redhat.com>

	On advice from Chris G. Demetriou <cgd@sibyte.com>:
	* sim-main.h (GPR_CLEAR): Remove unused alternative macro.
2000-10-19 10:52:52 +00:00
Nick Clifton 4c0deff44c Define GPR_CLEAR 2000-05-29 19:38:39 +00:00
Stan Shebs c906108c21 Initial creation of sourceware repository 1999-04-16 01:35:26 +00:00
Stan Shebs 071ea11e85 Initial creation of sourceware repository 1999-04-16 01:34:07 +00:00
Frank Ch. Eigler 14bbac6609 * eCos->devo merge; tx3904 sanitize tags removed
1998-12-29  Frank Ch. Eigler  <fche@cygnus.com>
	* interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
	(load_word): Call SIM_CORE_SIGNAL hook on error.
	(signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
	starting.  For exception dispatching, pass PC instead of NULL_CIA.
	(decode_coproc): Use COP0_BADVADDR to store faulting address.
	* sim-main.h (COP0_BADVADDR): Define.
	(SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
	(SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
	(_sim_cpu): Add exc_* fields to store register value snapshots.
	* mips.igen (*): Replace memory-related SignalException* calls
	with references to SIM_CORE_SIGNAL hook.
	* dv-tx3904irc.c (tx3904irc_port_event): printf format warning
	fix.
	* sim-main.c (*): Minor warning cleanups.
1998-12-30 12:21:43 +00:00
Frank Ch. Eigler 1ee7d2b1c8 * sky->devo merge, final part of sim merge
[ChangeLog.sky]
1998-12-08  Frank Ch. Eigler  <fche@cygnus.com>
	* sim-main.h (sim_state): Add multi-phase load tracking fields.
	* sky-gdb.c (sky_option_handler): Add --load-next option handling.
	* mips.igen (BREAK): Add multi-phase load and printf code handling.
1998-12-08 12:23:26 +00:00
Andrew Cagney a83d7d870f Switch mips-lsi-elf mips16 simulator to igen (from gencode). 1998-11-23 05:50:21 +00:00
Andrew Cagney d1cbd70abb Add configury for mips-lsi-elf target (32 bit MIPS16).
Fix numerous problems with PENDING_* code.
In old gencode simulator, don't double tick each cycle.
Add BREAK instruction to MIPS16 gencode simulator.
1998-11-12 06:42:34 +00:00
Frank Ch. Eigler fda83b6795 * MONSTER sky -> devo merge
* ChangeLog / ChangeLog.sky entries were merged with original time stamps;
  a few were moved between the files
1998-10-27 12:48:08 +00:00
Frank Ch. Eigler 9ade226a42 * Patch for PR 17142, brought over from sky branch.
Fri Sep  4 10:37:57 1998  Frank Ch. Eigler  <fche@cygnus.com>
	* r5900.igen (mtsab): Correct typo in input register.
	* sim-main.h (TMP_*): New macros for accessing local 128-bit
	temporary for multimedia instructions.
	* r5900.igen (*): Convert most instructions to use new TMP
	macros to store output result during computation.
1998-09-08 11:09:45 +00:00
Ron Unrau b8140a08bf * sim-main.h: shadow NUM_CORE_REGS from tm-txvu.h
* interp.c: use NUM_CORE_REGS
        * sky-gdb.c (set_fifo_breakpoints): use VIF interrupt bit for break
        * sky-pke.c (pke_issue): use interrupt bit for break points
1998-07-31 22:02:12 +00:00
Gavin Romig-Koch 46eb9e5a57 * interp.c (OPTION_BRANCH_BUG_4011): Add.
(mips_option_handler): Handle OPTION_BRANCH_BUG_4011.
	(mips_options): Define the option.
	* mips.igen (check_4011_branch_bug): New.
	(mark_4011_branch_bug): New.
	(all branch insn): Call mark_branch_bug, and check_branch_bug.
	* sim-main.h (branchbug4011_option, branchbug4011_last_target,
	branchbug4011_last_cia, BRANCHBUG4011_OPTION,
	BRANCHBUG4011_LAST_TARGET, BRANCHBUG4011_LAST_CIA,
	check_branch_bug, mark_branch_bug): Define.
1998-06-29 13:30:01 +00:00
Ron Unrau 2905d173c5 * sky-pke.c(read_pke_pc): return source address of current pc
* sky-pke.c(read_pke_pcx): return index of current pc
        * sky-pke.h: export read_pke_pcx
        * interp.c(sim_fetch_registers): read pke pc/pcx
        * sky-libvpe.c: track name change from GDB
        * sim-main.h: add vif memory based pc
          - extend gdb comm area for fifo breakpoints
          - define SIM_ENGINE_RESTART_HOOK
        * sky-gdb.c: add support for VIF breakpoints
1998-06-16 20:30:20 +00:00
Ron Unrau f083fff397 * sky-engine.c: Set ordering of device issues to match enumerated type
txvu_cpu_context (sim-main.h tm-txvu.h). This also allowed the issue
        structure to be simplified to an array of functions.
1998-06-14 17:01:02 +00:00
Ian Carmichael 895a7dc2aa * Handle 10 and 20-bit versions of Break instruction. Move handling
* of special values from signal_exception() in interp.c into mips.igen.
*
* Modified: gencode.c interp.c mips.igen sim-main.h
1998-06-09 16:54:08 +00:00
Frank Ch. Eigler 3fa454e95f * Monster patch - may destablize MIPS sims for a little while.
* Followup patch for SCEI PR 15853
* First check-in of TX3904 interrupt controller devices for ECC. [sanitized]
* First implementation of MIPS hardware interrupt emulation.
Mon May 18 18:22:42 1998  Frank Ch. Eigler  <fche@cygnus.com>
	* configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
 	modules.  Recognize TX39 target with "mips*tx39" pattern.
	* configure: Rebuilt.
	* sim-main.h (*): Added many macros defining bits in
 	TX39 control registers.
	(SignalInterrupt): Send actual PC instead of NULL.
	(SignalNMIReset): New exception type.
	* interp.c (board): New variable for future use to identify
	a particular board being simulated.
	(mips_option_handler,mips_options): Added "--board" option.
	(interrupt_event): Send actual PC.
	(sim_open): Make memory layout conditional on board setting.
	(signal_exception): Initial implementation of hardware interrupt
 	handling.  Accept another break instruction variant for simulator
 	exit.
	(decode_coproc): Implement RFE instruction for TX39.
	(mips.igen): Decode RFE instruction as such.
start-sanitize-tx3904
	* configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
	* interp.c: Define "jmr3904" and "jmr3904debug" board types and
	bbegin to implement memory map.
	* dv-tx3904cpu.c: New file.
	* dv-tx3904irc.c: New file.
end-sanitize-tx3904
1998-05-18 15:55:05 +00:00
Doug Evans eb00d70698 * sim-main.h (INSN_NAME): New arg `cpu'. 1998-05-07 02:45:07 +00:00
James Lemke 60372a3f96 * sim-main.h, sky-libvpe.c: r59fp_op* functions were called with
1st parm of wrong type.  Converted remaining "/" to "FDiv".
	* interp.c: Make "--float-type host" the default.
1998-04-29 21:17:53 +00:00
James Lemke aefd02b523 Move target specific stuff from sim/common/sim-base.h to sim/mips/sim-main.h 1998-04-22 20:41:04 +00:00
James Lemke 8c8dd0c471 r5900.igen, sim-main.h, sky-libvpe.c: Add run-time option --float-type 1998-04-21 21:33:44 +00:00
Jason Molenda 5fe24ce03a Fix sanitize tag. The proper keyword is "start-sanitize-*", not
"begin-sanitize-*".
1998-04-21 17:55:06 +00:00
Andrew Cagney 421cbaae98 For new IGEN simulators, rewrite checks validating correct use of the
HI/LO registers.  For old gencode simulator, delete all checks.
1998-04-21 01:17:58 +00:00
Andrew Cagney f3bdd368ea Debug tx19 built from igen sources.
Rework ifetch{16,32} to match the more recent do_load function.
1998-04-15 07:23:28 +00:00
Andrew Cagney c0a4c3ba17 Implement 32 bit MIPS16 instructions listed in m16.igen. 1998-04-14 14:34:48 +00:00
Frank Ch. Eigler b0b39eb2de * Backed out week-old attempt at enabling quadword memory access on
MIPS sim; added PKE sim code fixes.  No COP2 testing progress today.

[ChangeLog]

Thu Apr  9 16:38:23 1998  Frank Ch. Eigler  <fche@cygnus.com>

	* r5900.igen (LQC,SQC): Adapted code to DOUBLEWORD accesses
	instead of QUADWORD.

	* sim-main.h: Removed attempt at allowing 128-bit access.

[ChangeLog.sky]

Thu Apr  9 16:42:54 1998  Frank Ch. Eigler  <fche@cygnus.com>

	* sky-pke.c (read_pke_pc): Corrected PKE PC calculation
	to word granularity.
1998-04-09 20:56:00 +00:00
Ian Carmichael 2fd7c40770 * Temporarily change LOADDRMASK in sky build. 1998-04-09 03:17:43 +00:00
Frank Ch. Eigler 2ebb2a6855 * R5900 COP2 is now ready for testing. Let loose the dogs!
Mon Apr  6 19:55:56 1998  Frank Ch. Eigler  <fche@cygnus.com>

	* interp.c (cop_[ls]q): Replaced stub with proper COP2 code.

	* sim-main.h (LOADADDRMASK): Redefine to allow 128-bit accesses
 	for TARGET_SKY.

	* r5900.igen (SQC2): Thinko.
1998-04-07 00:01:31 +00:00
Frank Ch. Eigler ebcfd86a2e * R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF
masking facility for PATH3 transfers.

[ChangeLog.sky]

Sun Apr  5 12:11:45 1998  Frank Ch. Eigler  <fche@cygnus.com>

	* sky-libvpe.c (exec-inst): Added "M" bit detection for upper
 	instruction.

	* sky-pke.c (pke_check_stall): Added more assertions.
	(pke_code_mskpath3): Use new GPUIF M3P control register.

	* sky-pke.h (VU[01]_CIA): New macros that give VU CIA
 	pseudo-register addresses.

	* sky-vu.h (vu_device, VectorUnitState): Merged structs.
	(VectorUnitState.mflag): New field.
	(VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers.

	* sky-vu.c (vu0_busy): New function.
	(vu0_q_busy): New function.
	(vu0_macro_issue): New function.
	(vu0_micro_interlock_released): New function.
	(vu0_busy_in_{micro,macro}_mode): Deleted stubs.
	(vu0_macro_hazard_check): Deleted stubs.
	(vu_attach): Adapted code to merged device & state struct.
	(read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register.

[ChangeLog]
start-sanitize-sky
Sun Apr  5 12:05:44 1998  Frank Ch. Eigler  <fche@cygnus.com>

	* interp.c (*): Adapt code to merged VU device & state structs.
	(decode_coproc): Execute COP2 each macroinstruction without
 	pipelining, by stepping VU to completion state.  Adapted to
	read_vu_*_reg style of register access.

	* mips.igen ([SL]QC2): Removed these COP2 instructions.

	* r5900.igen ([SL]QC2): Transplanted these COP2 instructions here.

	* sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards.

end-sanitize-sky
1998-04-05 16:40:03 +00:00
Andrew Cagney 64ed8b6a8c aclocal.m4: Don't enable inlining when cross-compiling.
mips/*: Tune mips simulator - allow all memory transfer code to be inlined.
1998-04-05 07:16:54 +00:00
Andrew Cagney 69d5a56645 Re-do load/store operations so that they work for both 32 and 64 bit
ISAs.
Enable tx39 as igen again.
1998-04-02 19:35:39 +00:00
Ron Unrau 2151467d63 sky-vu.[ch]: prototype decls, cast floats to ints before register transfer
interp.c: integrate VU register read/writes
sim-main.h : track tm-txvu.h
1998-04-01 17:31:24 +00:00
Frank Ch. Eigler 6ed00b0607 * Continuing sky R5900 / COP2 work. Added extra sanitize tags to hide
128-bit MIPS part.

[ChangeLog]

Mon Mar 30 18:41:43 1998  Frank Ch. Eigler  <fche@cygnus.com>

	* interp.c (decode_coproc): Continuing COP2 work.
  	(cop_[ls]q): Hide 128-bit COP2 more.

	* sim-main.h (COP_[LS]Q): Hide 128-bit COP2 more.

[ChangeLog.sky]

Mon Mar 30 18:44:15 1998  Frank Ch. Eigler  <fche@cygnus.com>

	* sky-libvpe.c: Code too wide - ran indent on SCEI code.

	* sky-vu.h (vu0_busy*, vu0_macro*): New entry points for COP2
 	interface.

	* sky-vu.c (vu0_busy*, vu0_macro*): Stub functions for above.
1998-03-30 23:56:52 +00:00
Frank Ch. Eigler 15232df4a3 * Inserted skeleton of R5900 COP2 simulation. Merged old vu[01].[ch] code
into single PKE-style vu.[ch].


[ChangeLog]

Fri Mar 27 16:19:29 1998  Frank Ch. Eigler  <fche@cygnus.com>

start-sanitize-sky
	* Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o.

	* interp.c (sim_{load,store}_register): Use new vu[01]_device
 	static to access VU registers.
	(decode_coproc): Added skeleton of sky COP2 (VU) instruction
 	decoding.  Work in progress.

	* mips.igen (LDCzz, SDCzz): Removed *5900 case for this
 	overlapping/redundant bit pattern.
	(LQC2, SQC2): Added *5900 COP2 instruction skeleta.  Work in
	progress.

	* sim-main.h (status_CU[012]): Added COP[n]-enabled flags for
 	status register.

end-sanitize-sky

	* interp.c (cop_lq, cop_sq): New functions for future 128-bit
 	access to coprocessor registers.

	* sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above.

[ChangeLog.sky]

	* sky-engine.c (engine_run): Adapted from vu[01] -> vu merge.

	* sky-hardware.c (register_devices): Ditto

	* sky-pke.c (pke_fifo_*): Made these functions private again, now
 	that the GPUIF code does not use them.

	* sky-pke.h (pke_fifo_*): Removed newly private declarations.

	* sky-vu.c (*): Major rework: merge of old sky-vu0.c and
 	sky-vu1.c.  Management of two VU devices parallels two PKEs.
	Work in progress.

	* sky-vu.h (*): Other half of merge.
	(vu_device): New struct, parallel to pke_device.
1998-03-27 22:00:56 +00:00
Andrew Cagney ca6f76d135 Fix DIV, DIV1 (wrong check for overflow) and DIVU1 (shouldn't check
for overflow).
Pacify GCC.
1998-03-03 05:39:49 +00:00
Andrew Cagney 0e701ac37b Add generic sim-info.c:sim_info() function using module mechanism.
Clean up compile probs in mips/vr5400.
1998-02-28 02:51:06 +00:00
Andrew Cagney f89c0689a1 Finish implementation of r5900 instructions. 1998-02-25 15:31:15 +00:00
Andrew Cagney a48e8c8d21 sim-main.h: Re-arange r5900 registers so that they have their own
little struct.
interp.c: Update.  Also add floating point Max/Min functions.
mips.igen: Remove r5900 tag from any floating point instructions.
r5900.igen: Rewrite.  Implement *all* floating point insns (except ld/st).
r5400.igen: Tag mdmx functions as being mdmx specific.
1998-02-23 16:55:38 +00:00
Andrew Cagney 2acd126a47 Rewrite the mipsI/II/III pending-slot code. 1998-02-02 13:49:17 +00:00
Andrew Cagney 01737f42d8 mips: Add multi-processor support for r5900. Others might work.
common, igen: Fix MP related bugs.
1998-02-01 03:29:48 +00:00
Andrew Cagney 9ec6741b17 igen: Fix SMP simulator generator support.
Use the bfd-processor name in the sim-engine switch.
	Add nr_cpus argument to sim_engine_run.
tic80, v850, d30v, mips, common:
	Update
mips:	Fill in bfd-processor field of model records so that
	they match ../bfd/archures.
1998-01-31 06:23:41 +00:00
Andrew Cagney 2d44e12a27 Use macro GPR_SET(N,VAL) to clear zero registers. 1998-01-21 22:08:37 +00:00
Andrew Cagney 232156dee9 o Add SIM_SIGFPE to sim-signals
o Start SIM_SIG* at 64 so that the use of host signal numbers can be
  detected and reported.
o Update MIPS simulator to use sim-signal.
1997-11-20 09:50:36 +00:00