bfd/
2013-11-27 Tristan Gingold <gingold@adacore.com>
* pei-x86_64.c (pex_regs): Make it const. Add comments.
(pex64_get_runtime_function): Do not split UnwindData.
(pex64_get_unwind_info): Extract the chain and the handler.
(pex64_xdata_print_uwd_codes): Rewritten: do not reverse print
the opcode, handle version 2, add consistency check, make the
code host neutral.
(pex64_dump_xdata): Change arguments to pass the section and its
content. Handle version 2, change output.
(pex64_bfd_print_pdata): Add comments, load section for xdata.
Avoid duplicate outputs.
include/coff
2013-11-27 Tristan Gingold <gingold@adacore.com>
* pe.h (struct pex64_runtime_function): Remove isChained.
(UWOP_SAVE_XMM): Add comment.
(struct pex64_unwind_info): Remove extra fields.
gas/
* config/tc-arm.c (arm_archs): New armv7ve architecture option.
(arm_cpus): Replace ARM_ARCH_V7A_IDIV_MP_SEC_VIRT with
ARM_ARCH_V7VE for cortex-a7, cortex-a12 and cortex-a15.
(cpu_arch_ver): Likewise.
* doc/c-arm.texi: Document armv7ve.
gas/testsuite/
* gas/arm/attr-march-armv7ve.d: New test case for armv7ve.
include/opcode/
* arm.h (ARM_AEXT_V7VE): New define.
(ARM_ARCH_V7VE): New define.
(ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
* config/tc-aarch64.c (set_other_error): New function.
(parse_sys_reg): Add new parameter 'sys_reg' and if non-NULL set
the variable to which it points with 'o'.
(parse_operands): Update; check for write to read-only system
registers or read from write-only ones.
gas/testsuite/
* gas/aarch64/diagnostic.s: Add tests.
* gas/aarch64/diagnostic.l: Update.
* gas/aarch64/tracereg-illegal.d: New file.
* gas/aarch64/tracereg-illegal.l: Ditto.
* gas/aarch64/tracereg-illegal.s: Ditto.
* gas/aarch64/tracereg.d: Ditto.
* gas/aarch64/tracereg.s: Ditto.
include/opcode
* aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
(aarch64_sys_reg_writeonly_p): Ditto.
opcodes/
* aarch64-opc.c (CPENT): New define.
(F_READONLY, F_WRITEONLY): Likewise.
(aarch64_sys_regs): Add trace unit registers.
(aarch64_sys_reg_readonly_p): New function.
(aarch64_sys_reg_writeonly_p): Ditto.
* elfnn-aarch64.c (elfNN_aarch64_howto_table): Use
R_AARCH64_TLS_DTPMOD64 instead of R_AARCH64_TLS_DTPMOD;
likewise for R_AARCH64_TLS_DTPREL and R_AARCH64_TLS_TPREL.
include/elf/
* aarch64.h: Define R_AARCH64_TLS_DTPMOD64,
R_AARCH64_TLS_DTPREL64 and R_AARCH64_TLS_TPREL64; guard
R_AARCH64_TLS_DTPMOD, R_AARCH64_TLS_DTPREL and
R_AARCH64_TLS_TPREL with RELOC_MACROS_GEN_FUNC.
* config/tc-aarch64.c (parse_sys_reg): Update to use aarch64_sys_reg;
call aarch64_sys_reg_deprecated_p and warn about the deprecated
system registers.
gas/testsuite/
* gas/aarch64/deprecated.d: New file.
* gas/aarch64/deprecated.l: New file.
* gas/aarch64/deprecated.s: New file.
* gas/aarch64/sysreg-1.s: Add tests.
* gas/aarch64/sysreg-1.d: Add tests.
include/opcode/
* aarch64.h (aarch64_sys_reg): New typedef.
(aarch64_sys_regs): Change to define with the new type.
(aarch64_sys_reg_deprecated_p): Declare.
opcodes/
* aarch64-opc.c (F_DEPRECATED): New macro.
(aarch64_sys_regs): Update; flag "spsr_svc" and "spsr_hyp" with
F_DEPRECATED.
(aarch64_print_operand): Call aarch64_sys_reg_deprecated_p on
AARCH64_OPND_SYSREG.
This removes the DT_PPC_TLSOPT/DT_PPC64_TLSOPT dynamic tag and replaces
it with DT_PPC_OPT/DT_PPC64_OPT tag to provide the same functionality
and more. This isn't backwards compatible, but the TLSOPT tag hasn't
been used since the tls optimisation support was never submitted to
glibc.
/include/elf/
* ppc.h (DT_PPC_TLSOPT): Delete.
(DT_PPC_OPT, PPC_OPT_TLS): Define.
* ppc64.h (DT_PPC64_TLSOPT): Delete.
(DT_PPC64_OPT, PPC64_OPT_TLS, PPC64_OPT_MULTI_TOC): Define.
bfd/
* elf32-ppc.c (ppc_elf_size_dynamic_sections): Use new DT_PPC_OPT
tag to specify tls optimisation.
* elf64-ppc.c (ppc64_elf_size_dynamic_sections): Likewise.
(ppc64_elf_finish_dynamic_sections): Specify whether multiple
toc pointers are used via DT_PPC64_OPT.
binutils/
* readelf.c (get_ppc_dynamic_type): Replace PPC_TLSOPT with PPC_OPT.
(get_ppc64_dynamic_type): Replace PPC64_TLSOPT with PPC64_OPT.
This defines the ELF symbol st_other field used to encode the number
of instructions between a function "global entry" and its "local entry",
and adds support related to the local entry offset.
include/elf/
* ppc64.h (STO_PPC64_LOCAL_BIT, STO_PPC64_LOCAL_MASK): Define.
(ppc64_decode_local_entry, ppc64_encode_local_entry): New functions.
(PPC64_LOCAL_ENTRY_OFFSET, PPC64_SET_LOCAL_ENTRY_OFFSET): Define.
bfd/
* elf64-ppc.c (struct ppc_stub_hash_entry): Add "other".
(stub_hash_newfunc): Init new ppc_stub_hash_entry field, and one
we forgot, "plt_ent".
(ppc64_elf_add_symbol_hook): Check ELFv1 objects don't have
st_other bits only valid in ELFv2.
(ppc64_elf_merge_symbol_attribute): New function.
(ppc_type_of_stub): Add local_off param to test branch range.
(ppc_build_one_stub): Adjust destinations for ELFv2 locals.
(ppc_size_one_stub, toc_adjusting_stub_needed): Similarly.
(ppc64_elf_size_stubs): Pass local_off to ppc_type_of_stub.
Set "other" field.
(ppc64_elf_relocate_section): Adjust destination for ELFv2 local
calls.
gas/
* config/tc-ppc.c (md_pseudo_table): Add .localentry.
(ppc_elf_localentry): New function.
(ppc_force_relocation): Force relocs on all branches to localenty
symbols.
(ppc_fix_adjustable): Don't reduce such symbols to section+offset.
binutils/
* readelf.c (get_ppc64_symbol_other): New function.
(get_symbol_other): Use it for EM_PPC64.
Defines bits in ELF e_flags to differentiate ELFv2 objects from ELFv2,
adds .abiversion directive to explicitly choose the ABI, and code to
check and automatically select ABI.
include/elf/
* ppc64.h (EF_PPC64_ABI): Define.
bfd/
* elf64-ppc.c (abiversion, set_abiversion): New functions.
(ppc64_elf_get_synthetic_symtab): Handle ELFv2 objects without .opd.
(struct ppc_link_hash_table): Add opd_abi.
(ppc64_elf_check_relocs): Check no .opd with ELFv2.
(ppc64_elf_merge_private_bfd_data): New function.
(ppc64_elf_print_private_bfd_data): New function.
(ppc64_elf_tls_setup): Set htab->opd_abi.
(ppc64_elf_size_dynamic_sections): Don't emit OPD related dynamic
tags for ELFv2.
(ppc_build_one_stub): Use R_PPC64_IRELATIVE for ELFv2 ifunc.
(ppc64_elf_finish_dynamic_symbol): Likewise
binutils/
* readelf.c (get_machine_flags): Display ABI version for EM_PPC64.
gas/
* config/tc-ppc.c: Include elf/ppc64.h.
(ppc_abiversion): New variable.
(md_pseudo_table): Add .abiversion.
(ppc_elf_abiversion, ppc_elf_end): New functions.
* config/tc-ppc.h (md_end): Define.
This changes the behaviour of @h and @ha on PowerPC64 to report errors
on 32-bit overflow. The motivation for this change is that on
PowerPC64, most uses of @h and @ha modifiers and their corresponding
relocations are to build up 32-bit offsets. We'd like to know when
such offsets overflow. Only rarely do people use @h or @ha with the
high 32-bit modifiers to build a 64-bit constant. Those uses will now
need to use two new modifiers, @high and @higha, if the constant isn't
known at assembly time. For now, we won't report overflow at assembly
time..
This also fixes an error when applying some of the HIGHER and HIGHEST
relocations.
include/elf/
* ppc64.h (R_PPC64_ADDR16_HIGH, R_PPC64_ADDR16_HIGHA,
R_PPC64_TPREL16_HIGH, R_PPC64_TPREL16_HIGHA,
R_PPC64_DTPREL16_HIGH, R_PPC64_DTPREL16_HIGHA): New.
(IS_PPC64_TLS_RELOC): Match new tls relocs.
bfd/
* reloc.c (BFD_RELOC_PPC64_ADDR16_HIGH, BFD_RELOC_PPC64_ADDR16_HIGHA,
BFD_RELOC_PPC64_TPREL16_HIGH, BFD_RELOC_PPC64_TPREL16_HIGHA,
BFD_RELOC_PPC64_DTPREL16_HIGH, BFD_RELOC_PPC64_DTPREL16_HIGHA): New.
* elf64-ppc.c (ppc64_elf_howto_raw): Add entries for new relocs.
Make all _HA and _HI relocs report signed overflow.
(ppc64_elf_reloc_type_lookup): Handle new relocs.
(must_be_dyn_reloc, ppc64_elf_check_relocs): Likewise.
(dec_dynrel_count, ppc64_elf_relocate_section): Likewise.
(ppc64_elf_relocate_section): Don't apply 0x8000 adjust to
R_PPC64_TPREL16_HIGHER, R_PPC64_TPREL16_HIGHEST,
R_PPC64_DTPREL16_HIGHER, and R_PPC64_DTPREL16_HIGHEST.
* libbfd.h: Regenerate.
* bfd-in2.h: Regenerate.
gas/
* config/tc-ppc.c (SEX16): Don't mask.
(REPORT_OVERFLOW_HI): Define as zero.
(ppc_elf_suffix): Support @high, @higha, @dtprel@high, @dtprel@higha,
@tprel@high, and @tprel@higha modifiers.
(md_assemble): Ignore X_unsigned when applying 16-bit insn fields.
Add (disabled) code to check @h and @ha reloc overflow for powerpc64.
Handle new relocs.
(md_apply_fix): Similarly.
elfcpp/
* powerpc.h (R_PPC64_ADDR16_HIGH, R_PPC64_ADDR16_HIGHA,
R_PPC64_TPREL16_HIGH, R_PPC64_TPREL16_HIGHA,
R_PPC64_DTPREL16_HIGH, R_PPC64_DTPREL16_HIGHA): Define.
gold/
* powerpc.cc (Target_powerpc::Scan::check_non_pic): Handle new relocs.
(Target_powerpc::Scan::global, local): Likewise.
(Target_powerpc::Relocate::relocate): Likewise. Check for overflow
on all ppc64 @h and @ha relocs.
- The Mach exception/signals escaped the TARGET_ -> GDB_ prefix change
done a while ago, but there's no real reason for that. I grepped
for TARGET_EXC and fixed all found, which unsurprisingly, means
darwin-nat.c needed fixing. I think the change there is as obvious
and trivial as it can get, so I'd be quite surprised if this broke
anything there somehow.
- GDB_SIGNAL_LAST's description string was unnecessarily inconsistent
with the enum name.
Built on x86_64 Fedora 17.
gdb/
2013-10-22 Pedro Alves <palves@redhat.com>
* include/gdb/signals.def (TARGET_EXC_BAD_ACCESS): Rename to
GDB_EXC_BAD_ACCESS.
(TARGET_EXC_BAD_INSTRUCTION): Rename to GDB_EXC_BAD_INSTRUCTION.
(TARGET_EXC_ARITHMETIC): Rename to GDB_EXC_ARITHMETIC.
(TARGET_EXC_EMULATION): Rename to GDB_EXC_EMULATION.
(TARGET_EXC_SOFTWARE): Rename to GDB_EXC_SOFTWARE.
(TARGET_EXC_BREAKPOINT): Rename to GDB_EXC_BREAKPOINT.
(GDB_SIGNAL_LAST): Change description string.
* common/signals.c (gdb_signal_from_host, do_gdb_signal_to_host):
Adjust to signal renaming.
* darwin-nat.c (darwin_decode_message): Likewise.
* mips.h (M_DEXT, M_DINS): Delete.
opcodes/
* micromips-opc.c (micromips_opcodes): Replace "dext" and "dins"
macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases.
Use +H rather than +C for the real "dext".
* mips-opc.c (mips_builtin_opcodes): Likewise.
gas/
* config/tc-mips.c (report_bad_range, report_bad_field): Delete.
(macro): Remove M_DEXT and M_DINS handling.
gas/testsuite/
* gas/mips/ext-ill.l, gas/mips/mips64r2-ill.l: Expect DEXT and DINS
error messages to have the same form as the EXT and INS ones.
* gas/mips/micromips-insn32.d, gas/mips/micromips-noinsn32.d,
gas/mips/micromips-trap.d, gas/mips/micromips.d,
gas/mips/micromips@mips64r2.d, gas/mips/mips64r2.d: Expect
"dext" and "dins" instead of "dextm", "dextu", "dinsm" and "dinsu".
2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
Richard Sandiford <rdsandiford@googlemail.com>
* mips.h: Document new VU0 operand characters.
(OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
(OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
(OP_REG_R5900_ACC): New mips_reg_operand_types.
(INSN2_VU0_CHANNEL_SUFFIX): New macro.
(mips_vu0_channel_mask): Declare.
opcodes/
2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
Richard Sandiford <rdsandiford@googlemail.com>
* mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
(print_vu0_channel): New function.
(print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
(print_insn_args): Handle '#'.
(print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX.
* mips-opc.c (mips_vu0_channel_mask): New constant.
(decode_mips_operand): Handle new VU0 operand types.
(VU0, VU0CH): New macros.
(mips_builtin_opcodes): Add VU0 opcodes. Use "+7" rather than "E"
for LQC2 and SQC2. Use "+9" rather than "G" for EE CFC2 and CTC2.
Use "+6" rather than "G" for QMFC2 and QMTC2.
gas/
2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
Richard Sandiford <rdsandiford@googlemail.com>
* config/tc-mips.c (MAX_OPERANDS): Bump to 6.
(RWARN): Bump to 0x8000000.
(RTYPE_VI, RTYPE_VF, RTYPE_R5900_I, RTYPE_R5900_Q, RTYPE_R5900_R)
(RTYPE_R5900_ACC): New register types.
(RTYPE_MASK): Include them.
(R5900_I_NAMES, R5900_Q_NAMES, R5900_R_NAMES, R5900_ACC_NAMES): New
macros.
(reg_names): Include them.
(mips_parse_register_1): New function, split out from...
(mips_parse_register): ...here. Add a channels_ptr parameter.
Look for VU0 channel suffixes when nonnull.
(reg_lookup): Update the call to mips_parse_register.
(mips_parse_vu0_channels): New function.
(OT_CHANNELS, OT_DOUBLE_CHAR): New mips_operand_token_types.
(mips_operand_token): Add a "channels" field to the union.
Extend the comment above "ch" to OT_DOUBLE_CHAR.
(mips_parse_base_start): Match -- and ++. Handle channel suffixes.
(mips_parse_argument_token): Handle channel suffixes here too.
(validate_mips_insn): Handle INSN2_VU0_CHANNEL_SUFFIX.
Ignore OP_VU0_MATCH_SUFFIX when calculating the used bits.
Handle '#' formats.
(md_begin): Register $vfN and $vfI registers.
(operand_reg_mask): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
(convert_reg_type): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
(match_vu0_suffix_operand): New function.
(match_operand): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
(macro): Use "+7" rather than "E" for LDQ2 and STQ2.
(mips_lookup_insn): New function.
(mips_ip): Use it. Allow "+K" operands to be elided at the end
of an instruction. Handle '#' sequences.
gas/testsuite/
2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
* gas/mips/r5900-vu0.d: Expect $vfN and $viN instead of numeric
coprocessor registers.
* gas/mips/r5900-all-vu0.s, gas/mips/r5900-all-vu0.d,
gas/mips/r5900-full-vu0.s, gas/mips/r5900-full-vu0.d,
gas/mips/r5900-error-vu0.s, gas/mips/r5900-error-vu0.l: New tests.
* gas/mips/mips.exp: Run them.
* mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
(mips_int_operand_min, mips_int_operand_max): New functions.
(mips_decode_pcrel_operand): Use mips_decode_int_operand.
opcodes/
* mips-formats.h (PCREL): Reorder parameters and update the definition
to match new mips_pcrel_operand layout.
(JUMP, JALX, BRANCH): Update accordingly.
* mips16-opc.c (decode_mips16_operand): Likewise.
gas/
* config/tc-mips.c (match_int_operand): Use mips_int_operand_min
and mips_int_operand_max.
(mips16_immed_operand, mips16_immed_operands, MIPS16_NUM_IMMED):
Delete.
(mips16_immed_operand, mips16_immed_in_range_p): New functions.
(mips16_immed, mips16_extended_frag): Use them. Use mips_int_operand
instead of mips16_immed_operand.
* mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
(MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
(MIPS16_INSN_COND_BRANCH): Delete.
opcodes/
* mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags.
(WR_SP): Replace with...
(MOD_SP): ...this.
(mips16_opcodes): Update accordingly.
* mips-dis.c (print_insn_mips16): Likewise.
gas/
* config/tc-mips.c (compact_branch_p, uncond_branch_p): Use the same
flags for MIPS16 and non-MIPS16 instructions.
(gpr_mod_mask): Move the INSN2_MOD_SP case outside the micromips block.
(gpr_read_mask): Use INSN2_READ_GPR_31 for MIPS16 instructions too.
(gpr_write_mask): Remove MIPS16_INSN_WRITE_SP handling.
(can_swap_branch_p, get_append_method): Use the same flags for MIPS16
and non-MIPS16 instructions. Fix formatting.
* mips.h (mips_operand_type, mips_reg_operand_type): New enums.
(mips_operand, mips_int_operand, mips_mapped_int_operand)
(mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
(mips_pcrel_operand): New structures.
(mips_insert_operand, mips_extract_operand, mips_signed_operand)
(mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
(decode_mips_operand, decode_micromips_operand): Declare.
opcodes/
* mips-formats.h: New file.
* mips-opc.c: Include mips-formats.h.
(reg_0_map): New static array.
(decode_mips_operand): New function.
* micromips-opc.c: Remove <stdio.h> include. Include mips-formats.h.
(reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
(reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
(int_c_map): New static arrays.
(decode_micromips_operand): New function.
* mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
(micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
(micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
(micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
(micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
(micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
(micromips_imm_b_map, micromips_imm_c_map): Delete.
(print_reg): New function.
(mips_print_arg_state): New structure.
(init_print_arg_state, print_insn_arg): New functions.
(print_insn_args): Change interface and use mips_operand structures.
Delete GET_OP_S. Move GET_OP definition to...
(print_insn_mips): ...here. Update the call to print_insn_args.
(print_insn_micromips): Use print_insn_args.
gas/
* config/tc-mips.c (validate_mips_insn): Move further up file.
Add insn_bits and decode_operand arguments. Use the mips_operand
fields to work out which bits an operand occupies. Detect double
definitions.
(validate_micromips_insn): Move further up file. Call into
validate_mips_insn.
* mips.h (EF_MIPS_NAN2008): New macro.
bfd/
* elfxx-mips.c (_bfd_mips_elf_merge_private_bfd_data): Handle
EF_MIPS_NAN2008.
(_bfd_mips_elf_print_private_bfd_data): Likewise.
binutils/
* readelf.c (get_machine_flags): Handle EF_MIPS_NAN2008.
gas/
* config/tc-mips.c (mips_flag_nan2008): New variable.
(options): Add OPTION_NAN enum value.
(md_longopts): Handle it.
(md_parse_option): Likewise.
(s_nan): New function.
(mips_elf_final_processing): Handle EF_MIPS_NAN2008.
(md_show_usage): Add -mnan.
* doc/as.texinfo (Overview): Add -mnan.
* doc/c-mips.texi (MIPS Opts): Document -mnan.
(MIPS NaN Encodings): New node. Document .nan directive.
(MIPS-Dependent): List the new node.
gas/testsuite/
* gas/mips/nan-2008-1.d: New test.
* gas/mips/nan-2008-2.d: New test.
* gas/mips/nan-2008-3.d: New test.
* gas/mips/nan-2008-4.d: New test.
* gas/mips/nan-legacy-1.d: New test.
* gas/mips/nan-legacy-2.d: New test.
* gas/mips/nan-legacy-3.d: New test.
* gas/mips/nan-legacy-4.d: New test.
* gas/mips/nan-legacy-5.d: New test.
* gas/mips/nan-error-1.l: New list test.
* gas/mips/nan-error-2.l: New list test.
* gas/mips/nan-2008-override.s: New test source.
* gas/mips/nan-2008.s: New test source.
* gas/mips/nan-legacy-override.s: New test source.
* gas/mips/nan-legacy.s: New test source.
* gas/mips/nan-error-1.s: New test source.
* gas/mips/nan-error-2.s: New test source.
* gas/mips/mips.exp: Run the new tests.
ld/testsuite/
* ld-mips-elf/nan-2008.d: New test.
* ld-mips-elf/nan-legacy.d: New test.
* ld-mips-elf/nan-mixed-1.d: New test.
* ld-mips-elf/nan-mixed-2.d: New test.
* ld-mips-elf/nan-2008.s: New test source.
* ld-mips-elf/nan-legacy.s: New test source.
* mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
(M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
(M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
(M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
(M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
(M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
(M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
(M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
(M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
(M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
(M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
(M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
(M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
Rename to...
(M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
(M_USD_AB): ...these.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD
and SD A(B) macros up.
* micromips-opc.c (micromips_opcodes): Likewise.
gas/
* config/tc-mips.c (gprel16_reloc_p): New function.
(macro_read_relocs): Assume BFD_RELOC_LO16 if all relocs are
BFD_RELOC_UNUSED.
(offset_high_part, small_offset_p): New functions.
(nacro): Use them. Remove *_OB and *_DOB cases. For single-
register load and store macros, handle the 16-bit offset case first.
If a 16-bit offset is not suitable for the instruction we're
generating, load it into the temporary register using
ADDRESS_ADDI_INSN. Make the M_LI_DD code fall through into the
M_L_DAB code once the address has been constructed. For double load
and store macros, again handle the 16-bit offset case first.
If the second register cannot be accessed from the same high
part as the first, load it into AT using ADDRESS_ADDI_INSN.
Fix the handling of LD in cases where the first register is the
same as the base. Also handle the case where the offset is
not 16 bits and the second register cannot be accessed from the
same high part as the first. For unaligned loads and stores,
fuse the offbits == 12 and old "ab" handling. Apply this handling
whenever the second offset needs a different high part from the first.
Construct the offset using ADDRESS_ADDI_INSN where possible,
for offbits == 16 as well as offbits == 12. Use offset_reloc
when constructing the individual loads and stores.
(mips_ip): Set up imm_expr, imm2_expr, offset_expr, imm_reloc
and offset_reloc before matching against a particular opcode.
Handle elided 'A' constants. Allow 'A' constants to use
relocation operators.
gas/testsuite/
* gas/mips/ldstla-32.d: Avoid "lui at,0x0" sequences for
truncated constants.
* gas/mips/ldstla-32-shared.d: Likewise.
* gas/mips/mcu.d: Use ADDIU in preference to LI+ADDU when adding
16-bit constants to the base.
* gas/mips/micromips@mcu.d: Likewise.
* gas/mips/micromips@cache.d: Likewise.
* gas/mips/micromips@pref.d: Likewise.
* gas/mips/micromips.d, gas/mips/micromips-insn32.d,
gas/mips/micromips-noinsn32.d, gas/mips/micromips-trap.d: Likewise.
Allow the full 16-bit offset range to be used for SB, LB and LBU in
USH and ULH sequences. Fix the expected output for LD and SD when
the two LW and SW offsets need different high parts.
* gas/mips/eva.s: Test PREFE with relocation operators.
* gas/mips/eva.d: Use ADDIU in preference to LI+ADDU for 16-bit
constants. Update after eva.s change.
* gas/mips/micromips@eva.d: Likewise.
* gas/mips/ld-reloc.s, gas/mips/ld-reloc.d, gas/mips/l_d-reloc.s,
gas/mips/l_d-reloc.d, gas/mips/ulw-reloc.s, gas/mips/ulw-reloc.d,
gas/mips/micromips@ulw-reloc.d, gas/mips/ulh-reloc.s,
gas/mips/ulh-reloc.d: New tests.
* gas/mips/mips.exp: Run them.
* mips.h: Remove documentation of "[" and "]". Update documentation
of "k" and the MDMX formats.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
MDMX-like instructions.
* mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
printing "Q" operands for INSN_5400 instructions.
gas/
* config/tc-mips.c (validate_mips_insn): Remove "[" and "]" handling.
(mips_ip): Likewise. Do not set is_mdmx for INSN_5400 instructions.
Check constraints on the VR5400 RZU.OB, SLL.OB and SRL.OB instructions.
gas/testsuite/
* gas/mips/vr5400-ill.s, gas/mips/vr5400-ill.l: New test.
* gas/mips/mips.exp: Run it.
* mips.h: Update documentation of "+s" and "+S".
opcodes/
* mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
"+S" for "cins".
* mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
Combine cases.
gas/
* config/tc-mips.c (mips_ip): Preserve the real bit number for "+p".
Require the msb to be <= 31 for "+s". Check that the size is <= 31
for both "+s" and "+S".
* mips.h: Document "+i".
opcodes/
* mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
"jalx".
* mips16-opc.c (mips16_opcodes): Likewise.
* micromips-opc.c (micromips_opcodes): Likewise.
* mips-dis.c (print_insn_args, print_mips16_insn_arg)
(print_insn_mips16): Handle "+i".
(print_insn_micromips): Likewise. Conditionally preserve the
ISA bit for "a" but not for "+i".
gas/
* config/tc-mips.c (validate_mips_insn, validate_micromips_insn):
(mips_ip, mips16_ip): Handle "+i".
