Commit ac0ab1842d ("i386: Also check R12-R15 registers when optimizing
testq to testb") didn't go quite far enough: In order to avoid confusing
other code registers would better be converted to byte ones uniformly.
PR 14891
* config/obj-elf.c (obj_elf_section): Fail if the section name is
already defined as a different symbol type.
* testsuite/gas/elf/pr14891.s: New test source file.
* testsuite/gas/elf/pr14891.d: New test driver.
* testsuite/gas/elf/pr14891.s: New test expected error output.
* testsuite/gas/elf/elf.exp: Run the new test.
The fix is the additional ARRAY_SIZE test, the rest just tidies
variable types rather than adding a cast to avoid warnings.
opcodes/
* z8k-dis.c: Include libiberty.h
(instr_data_s): Make max_fetched unsigned.
(z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
Don't exceed byte_info bounds.
(output_instr): Make num_bytes unsigned.
(unpack_instr): Likewise for nibl_count and loop.
* z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
idx unsigned.
* z8k-opc.h: Regenerate.
gas/
* config/tc-z8k.c (md_begin): Make idx unsigned.
(get_specific): Likewise for this_index.
We use gas' expression function to parse the operands of an
instruction in a generic way. There are situations when we have labels
and registers having the same name as well as the substraction sign
doesn't always stands for the arithmetical operation but for the
register range (e.g. enter instruction). This patch improves parsing
symbols found in a instruction operand, cleans up code and avoids
using default or undefined variables.
gas/
xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com>
* config/tc-arc.c (parse_reloc_symbol): New function.
(tokenize_arguments): Clean up, use parse_reloc_symbol function.
(md_operand): Set X_md to absent.
(arc_parse_name): Check for X_md.
PR 25224
bfd * Makefile.am: Add z80-elf target support.
* configure.ac: Likewise.
* targets.c: Likewise.
* config.bfd: Add z80-elf target support and new arches: ez80 and z180.
* elf32-z80.c: New file.
* archures.c: Add new z80 architectures: eZ80 and Z180.
* coffcode.h: Likewise.
* cpu-z80.c: Likewise.
* bfd-in2.h: Likewise plus additional Z80 relocations.
* coff-z80.c: Add new relocations for Z80 target and local label check.
gas * config/tc-z80.c: Add new architectures: Z180 and eZ80. Add support
for assembler code generated by SDCC. Add new relocation types. Add
z80-elf target support.
* config/tc-z80.h: Add z80-elf target support. Enable dollar local
labels. Local labels starts from ".L".
* testsuite/gas/all/fwdexp.d: Fix failure due to symbol conflict.
* testsuite/gas/all/fwdexp.s: Likewise.
* testsuite/gas/z80/suffix.d: Fix failure on ELF target.
* testsuite/gas/z80/z80.exp: Add new tests
* testsuite/gas/z80/dollar.d: New file.
* testsuite/gas/z80/dollar.s: New file.
* testsuite/gas/z80/ez80_adl_all.d: New file.
* testsuite/gas/z80/ez80_adl_all.s: New file.
* testsuite/gas/z80/ez80_adl_suf.d: New file.
* testsuite/gas/z80/ez80_isuf.s: New file.
* testsuite/gas/z80/ez80_z80_all.d: New file.
* testsuite/gas/z80/ez80_z80_all.s: New file.
* testsuite/gas/z80/ez80_z80_suf.d: New file.
* testsuite/gas/z80/r800_extra.d: New file.
* testsuite/gas/z80/r800_extra.s: New file.
* testsuite/gas/z80/r800_ii8.d: New file.
* testsuite/gas/z80/r800_z80_doc.d: New file.
* testsuite/gas/z80/z180.d: New file.
* testsuite/gas/z80/z180.s: New file.
* testsuite/gas/z80/z180_z80_doc.d: New file.
* testsuite/gas/z80/z80_doc.d: New file.
* testsuite/gas/z80/z80_doc.s: New file.
* testsuite/gas/z80/z80_ii8.d: New file.
* testsuite/gas/z80/z80_ii8.s: New file.
* testsuite/gas/z80/z80_in_f_c.d: New file.
* testsuite/gas/z80/z80_in_f_c.s: New file.
* testsuite/gas/z80/z80_op_ii_ld.d: New file.
* testsuite/gas/z80/z80_op_ii_ld.s: New file.
* testsuite/gas/z80/z80_out_c_0.d: New file.
* testsuite/gas/z80/z80_out_c_0.s: New file.
* testsuite/gas/z80/z80_reloc.d: New file.
* testsuite/gas/z80/z80_reloc.s: New file.
* testsuite/gas/z80/z80_sli.d: New file.
* testsuite/gas/z80/z80_sli.s: New file.
ld * Makefile.am: Add new target z80-elf
* configure.tgt: Likewise.
* emultempl/z80.em: Add support for eZ80 and Z180 architectures.
* emulparams/elf32z80.sh: New file.
* emultempl/z80elf.em: Likewise.
* testsuite/ld-z80/arch_ez80_adl.d: Likewise.
* testsuite/ld-z80/arch_ez80_z80.d: Likewise.
* testsuite/ld-z80/arch_r800.d: Likewise.
* testsuite/ld-z80/arch_z180.d: Likewise.
* testsuite/ld-z80/arch_z80.d: Likewise.
* testsuite/ld-z80/comb_arch_ez80_z80.d: Likewise.
* testsuite/ld-z80/comb_arch_z180.d: Likewise.
* testsuite/ld-z80/labels.s: Likewise.
* testsuite/ld-z80/relocs.s: Likewise.
* testsuite/ld-z80/relocs_b_ez80.d: Likewise.
* testsuite/ld-z80/relocs_b_z80.d: Likewise.
* testsuite/ld-z80/relocs_f_z80.d: Likewise.
* testsuite/ld-z80/z80.exp: Likewise.
opcodes * z80-dis.c: Add support for eZ80 and Z80 instructions.
There's no reason to not also issue them in Intel syntax mode, and it
can be quite helpful to mention the actual insn (after all there can be
multiple on a single line).
First and foremost REX must come last. Next JumpInterSegment branches
can't possibly have a REX prefix, as they're consistently CpuNo64. And
finally make BND prefix handling in output_branch() consistent with that
of other prefixes in the same function, and make its placement among
prefixes consistent with output_jump() (which, oddly enough, still isn't
the supposedly canonical order specified by the *_PREFIX definitions).
The expectation of x86-64-branch-3 for "call" / "jmp" with an obvious
direct destination to translate to an indirect _far_ branch is plain
wrong. The operand size prefix should have no effect at all on the
interpretation of the operand. The main underlying issue here is that
the Intel64 templates of the direct branches don't include Disp16, yet
various assumptions exist that it would always be there when there's
also Disp32/Disp32S, toggled by the operand size prefix (which is
being ignored by direct branches in Intel64 mode).
Along these lines it was also wrong to base the displacement width
decision solely on the operand size prefix: REX.W cancels this effect
and hence needs taking into consideration, too.
A disassembler change is needed here as well: XBEGIN was wrongly treated
the same as direct CALL/JMP, which isn't the case - the operand size
prefix does affect displacement size there, it's merely ignored when it
comes to updating [ER]IP.
In memory operand addressing, which forms of displacement are permitted
besides Disp8 is pretty clearly limited
- outside of 64-bit mode, Disp16 or Disp32 only, depending on address
size (MPX being special in not allowing Disp16),
- in 64-bit mode, Disp32s or Disp64 without address size override, and
solely Disp32 with one.
Adjust assembler and i386-gen to match this, observing that templates
already get adjusted before trying to match them against input depending
on the presence of an address size prefix.
This adjustment logic gets extended to all cases, as certain DispNN
values should also be dropped when there's no such prefix. In fact
behavior of the assembler, perhaps besides the exact diagnostics wording,
should not differ between there being templates applicable to 64-bit and
non-64-bit at the same time, or there being fully separate sets of
templates, with their DispNN settings already reduced accordingly.
This adjustment logic further gets guarded such that there wouldn't be
and Disp<N> conversion based on address size prefix when this prefix
doesn't control the width of the displacement (on branches other than
absolute ones).
These adjustments then also allow folding two MOV templates, which had
been split between 64-bit and non-64-bits variants so far.
Once in this area also
- drop the bogus DispNN from JumpByte templates, leaving just the
correct Disp8 there (compensated by i386_finalize_displacement()
now setting Disp8 on their operands),
- add the missing Disp32S to XBEGIN.
Note that the changes make it necessary to temporarily mark a test as
XFAIL; this will get taken care of by a subsequent patch. The failing
parts are entirely bogus and will get replaced.
Similar to SP, BP, SI and DI registers, R12-R15 registers must use REX
prefix for the low byte register when optimizing
test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
PR gas/25274
* config/tc-i386.c (optimize_encoding): Also check R12-R15
registers for "test $imm7, %r64/%r32/%r16 -> test $imm7, %r8"
optimization.
* testsuite/gas/i386/x86-64-optimize-3.s: Add tests for test
with r12.
* testsuite/gas/i386/x86-64-optimize-3.d: Updated.
* testsuite/gas/i386/x86-64-optimize-3b.d: Likewise.
Add 3 command-line options to align branches within a fixed boundary
with segment prefixes or NOPs:
1. -malign-branch-boundary=NUM aligns branches within NUM byte boundary.
2. -malign-branch=TYPE[+TYPE...] specifies types of branches to align.
The supported branches are:
a. Conditional jump.
b. Fused conditional jump.
c. Unconditional jump.
d. Call.
e. Ret.
f. Indirect jump and call.
3. -malign-branch-prefix-size=NUM aligns branches with NUM segment
prefixes per instruction.
3 new rs_machine_dependent frag types are added:
1. BRANCH_PADDING. The variable size frag to insert NOP before branch.
2. BRANCH_PREFIX. The variable size frag to insert segment prefixes to
an instruction. The choices of prefixes are:
a. Use the existing segment prefix if there is one.
b. Use CS segment prefix in 64-bit mode.
c. In 32-bit mode, use SS segment prefix with ESP/EBP base register
and use DS segment prefix without ESP/EBP base register.
3. FUSED_JCC_PADDING. The variable size frag to insert NOP before fused
conditional jump.
The new rs_machine_dependent frags aren't inserted if the previous item
is a prefix or a constant directive, which may be used to hardcode an
instruction, since there is no clear instruction boundary. Segment
prefixes and NOP padding are disabled before relaxable TLS relocations
and tls_get_addr calls to keep TLS instruction sequence unchanged.
md_estimate_size_before_relax() and i386_generic_table_relax_frag() are
used to handled BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags.
i386_generic_table_relax_frag() grows or shrinks sizes of segment prefix
and NOP to align the next branch frag:
1. First try to add segment prefixes to instructions before a branch.
2. If there is no sufficient room to add segment prefixes, NOP will be
inserted before a branch.
* config/tc-i386.c (_i386_insn): Add has_gotpc_tls_reloc.
(tls_get_addr): New.
(last_insn): New.
(align_branch_power): New.
(align_branch_kind): New.
(align_branch_bit): New.
(align_branch): New.
(MAX_FUSED_JCC_PADDING_SIZE): New.
(align_branch_prefix_size): New.
(BRANCH_PADDING): New.
(BRANCH_PREFIX): New.
(FUSED_JCC_PADDING): New.
(i386_generate_nops): Support BRANCH_PADDING and FUSED_JCC_PADDING.
(md_begin): Abort if align_branch_prefix_size <
MAX_FUSED_JCC_PADDING_SIZE.
(md_assemble): Set last_insn.
(maybe_fused_with_jcc_p): New.
(add_fused_jcc_padding_frag_p): New.
(add_branch_prefix_frag_p): New.
(add_branch_padding_frag_p): New.
(output_insn): Generate a BRANCH_PADDING, FUSED_JCC_PADDING or
BRANCH_PREFIX frag and terminate each frag to align branches.
(output_disp): Set i.has_gotpc_tls_reloc to TRUE for GOTPC and
relaxable TLS relocations.
(output_imm): Likewise.
(i386_next_non_empty_frag): New.
(i386_next_jcc_frag): New.
(i386_classify_machine_dependent_frag): New.
(i386_branch_padding_size): New.
(i386_generic_table_relax_frag): New.
(md_estimate_size_before_relax): Handle COND_JUMP_PADDING,
FUSED_JCC_PADDING and COND_JUMP_PREFIX frags.
(md_convert_frag): Handle BRANCH_PADDING, BRANCH_PREFIX and
FUSED_JCC_PADDING frags.
(OPTION_MALIGN_BRANCH_BOUNDARY): New.
(OPTION_MALIGN_BRANCH_PREFIX_SIZE): New.
(OPTION_MALIGN_BRANCH): New.
(md_longopts): Add -malign-branch-boundary=,
-malign-branch-prefix-size= and -malign-branch=.
(md_parse_option): Handle -malign-branch-boundary=,
-malign-branch-prefix-size= and -malign-branch=.
(md_show_usage): Display -malign-branch-boundary=,
-malign-branch-prefix-size= and -malign-branch=.
(i386_target_format): Set tls_get_addr.
(i386_cons_align): New.
* config/tc-i386.h (i386_cons_align): New.
(md_cons_align): New.
(i386_generic_table_relax_frag): New.
(md_generic_table_relax_frag): New.
(i386_tc_frag_data): Add u, padding_address, length,
max_prefix_length, prefix_length, default_prefix, cmp_size,
classified and branch_type.
(TC_FRAG_INIT): Initialize u, padding_address, length,
max_prefix_length, prefix_length, default_prefix, cmp_size,
classified and branch_type.
* doc/c-i386.texi: Document -malign-branch-boundary=,
-malign-branch= and -malign-branch-prefix-size=.
This started out as fixing decode_16, which used a char to index a 256
byte decodings array. When char is signed that could result in an out
of bounds array access. The rest of the patch is for consistency and
just general cleanup.
* config/obj-evax.c (crc32, encode_32, encode_16, decode_16):
Remove unnecessary prototypes.
(number_of_codings): Delete, use ARRAY_SIZE instead throughout.
(codings, decodings): Make arrays of unsigned char.
(crc32): Use unsigned variables. Delete unnecessary mask.
(encode_32, encode_16): Return unsigned char*, and make static
buffer an unsigned char array.
(decode_16): Make arg an unsigned char*. Remove useless casts.
(shorten_identifier): Use unsigned char crc_chars.
(is_truncated_identifier): Make ptr an unsigned char*.
In ("x86: extend SSE check to PCLMULQDQ, AES, and GFNI insns") I went
both a little too far and not quite far enough:
- GFNI insns also have AVX512 variants, which also shouldn't get
diagnosed,
- SSE4a insns should get diagnosed just like SSE4.x ones,
- SHA insns should get diagnosed just like PCLMULQDQ or AES ones.
This patch fixes .arch_extension behaviour.
Currently, context table for '.arch_extension' is only set while
"-march" processing, but it is not set while .arch processing,
so following code is rejected
.syntax unified
.thumb
.arch armv8.1-m.main
.arch_extension mve.fp
unless -march=armv8.1-m.main is given.
Committing on behalf of Vladimir Murzin
gas/ChangeLog:
2019-12-10 Vladimir Murzin <vladimir.murzin@arm.com>
* config/tc-arm.c (s_arm_arch): Set selected_ctx_ext_table.
* testsuite/gas/arm/mve-arch-ext.s: New.
* testsuite/gas/arm/mve-arch-ext.d: New.
This is an alias of "qword ptr", commonly used with MMX insns.
At this occasion also test (alongside the newly supported "mmword")
- "zmmword" used as expression,
- PADDB with "oword ptr" (aliasing "xmmword ptr").
Commit dc2be329b950 ("i386: Only check suffix in instruction mnemonic")
broke rejecting of these for floating point insns. Fix this by setting
the "byte" operand attribute, which will now (again) cause an error.
Furthermore the diagnostic for the "far ptr" case in general and for the
"near ptr" case in the non-float cases became "invalid instruction
suffix" instead of the intended "operand size mismatch". Fix this by
also setting the "tbyte" operand attribute (no insn template accepts
both byte and tbyte operands).
There are extremely few insns accepting "tbyte ptr" operand, so the
"tbyte" operand flag checking done by match_operand_size() is already
sufficient; the setting of the suffix has become meaningless anyway
with dc2be329b950 ("i386: Only check suffix in instruction mnemonic").
Fold the code with that setting the "byte" operand flag to force an
error (no insn at all accepts both "byte ptr" and tbyte ptr" operands,
except for AnySize ones where the two (conflicting) recorded types
don't matter (operand_size_match() doesn't call match_operand_size() in
this case).
No floating point insn accepts an "fword ptr" operand, so the "fword"
operand flag checking done by match_mem_size() is already sufficient;
the setting of the suffix has become meaningless anyway with
dc2be329b950 ("i386: Only check suffix in instruction mnemonic").
LDS et al don't accept "word ptr" operands anyway, as per their insn
templates. Hence there's no need to special case this here; the check
has become dysfunctional anyway by dc2be329b950 ("i386: Only check
suffix in instruction mnemonic").
This, at the assembler level, is just a "brace" feature covering both
AES and SHA2. Hence there's no need for it to have a separate feature
flag, freeing up a bit for future re-use. Along these lines there are
also a number of dead definitions/variables in the opcode table file.
SHA2 is a prereq to SHA3, not part of it aiui. Hence disabling the
latter should not also disable the former.
In the course of adding respective tests also do away with the
duplication of crypto.d's contents in crypto-directive.d.
Since we accept these without suffix / operand size specifier, we should
also do so with one. (The fact that we unilaterally accept these, other
than far branches, rather than limiting them to Intel64 mode, will be
taken care of later on.)
Also take the opportunity and make sure "lfs <reg>, tbyte ptr <mem>"
et al get rejected outside of 64-bit mode. This became broken by
dc2be329b950 ("i386: Only check suffix in instruction mnemonic").
Furthermore cover lgdt et al in the Intel syntax handling as well, which
continued to work after said commit just by coincidence.
While dc2be329b950 ("i386: Only check suffix in instruction mnemonic")
has made the assembler accept these in the first place (they were wrongly
rejected before), the generated code was still wrong in that it lacked
an operand size override. (In 64-bit code, other than in 16- and 32-bit
ones, CALL and JMP with memory operands are all entirely unambiguous: No
operand size can have two meanings.)
While segment registers are registers, their use doesn't allow sizing
of insns without suffix / explicit operand size specifier. Prevent
PUSH and POP of segment registers from entering that path, instead
allowing them to observe the stackop_size setting just like other
PUSH/POP and alike do.
Insns permitting only GPR operands (and hence implicit sizing when
there's no suffix) don't ever have their DefaultSize attribute
inspected, so it shouldn't be there in the first place.
Additionally XBEGIN is like JMP, not CALL, and hence shouldn't be
converted to 32-bit operand size in .code16gcc mode. While the same is
true for SYSRET, it permitting more than one suffix makes it FLDENV-
like, and hence rather than dropping the attribute, for now add it to
the exclusion list to avoid it getting an operand size prefix emitted
in .code16gcc mode. (This will be dealt with later, perhaps together
with FLDENV and friends.)
The flag controlling the default DWARF CIE version to produce now
starts with the value -1. This can be modified with the command line
flag as before, but after command line flag processing, in
md_after_parse_args targets can, if the global still has the value -1,
override this value. This gives a target specific default.
If a CIE version is not select either by command line flag, or a
target specific default, then some new code in dwarf2_init now select
a global default. This remains as version 1 to match previous
behaviour.
This RISC-V has a target specific default of version provided, this
make the return column uleb128, which means we can use all DWARF
registers include CSRs.
I chose to switch to version 3 rather than version 4 as this is most
similar to the global default (version 1). Switching to version 4
adds additional columns to the CIE header.
gas/ChangeLog:
* as.c (flag_dwarf_cie_version): Change initial value to -1, and
update comment.
* config/tc-riscv.c (riscv_after_parse_args): Set
flag_dwarf_cie_version if it has not already been set.
* dwarf2dbg.c (dwarf2_init): Initialise flag_dwarf_cie_version if
needed.
* testsuite/gas/riscv/default-cie-version.d: New file.
* testsuite/gas/riscv/default-cie-version.s: New file.
ld/ChangeLog:
* testsuite/ld-elf/eh5.d: Accept version 3 DWARF CIE.
Change-Id: Ibbfe8f0979fba480bf0a359978b09d2b3055555e
This commit gives DWARF register numbers to the RISC-V CSRs inline
with the RISC-V ELF specification here:
https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md
The CSRs are defined being numbered from 4096 to 8191.
This adds support to the assembler, required in order to reference
CSRs in, for example .cfi directives.
I have then extended dwarf.c in order to support printing CSR names in
the dumped DWARF output. As the CSR name space is quite large and
only sparsely populated, I have provided a new function to perform
RISC-V DWARF register name lookup which uses a switch statement rather
than the table base approach that other architectures use.
Any CSR that does not have a known name will return a name based on
'csr%d' with the %d being replaced by the offset of the CSR from 4096.
gas/ChangeLog:
* config/tc-riscv.c (tc_riscv_regname_to_dw2regnum): Lookup CSR
names too.
* testsuite/gas/riscv/csr-dw-regnums.d: New file.
* testsuite/gas/riscv/csr-dw-regnums.s: New file.
binutils/ChangeLog:
* dwarf.c (regname_internal_riscv): New function.
(init_dwarf_regnames_riscv): Use new function.
Change-Id: I3f70bc24fa8b3c75744e6775eeeb87db70c7ecfb
We build a hash table of all register classes and numbers. The hash
key is the register name and the hash value is the class and number
encoded into a single value, which is of type 'void *'.
When we pull the values out of the hash we cast them to be a pointer
to a structure, however, we never access the fields of that structure,
we just decode the register class and number from the pointer value
itself.
This commit removes the structure and treats the encoded class and
number as a 'void *' during hash lookup.
gas/ChangeLog:
* config/tc-riscv.c (struct regname): Delete.
(hash_reg_names): Handle value as 'void *'.
Change-Id: Ie7d8f46ca3798f56f4af94395279de684f87f9cc
psb CYSNC was not finding that CSYNC was a correct spelling.
The problem was upper case version was being put in the
wrong hashtable. This fixes the problem by using the
correct hashtable.
Also adds testcases for the upper case versions.
* config/tc-aarch64.c (md_begin): Use correct
hash table for uppercase version of hint.
* testsuite/gas/aarch64/system-2.s: Extend psb case to uppercase.
* testsuite/gas/aarch64/system-2.d: Update.
Change-Id: If43f8b85cacd24840d596c3092b0345e5f212766
This patch changes the CRC extension to use the core feature bits instead
of the coproc/fpu feature bits.
CRC is not an fpu feature and it causes issues with the new fpu reset
patch (f439988037a589de3798f44e7268301adaec21a9). CRC can be set using
the '.arch_extension' directive, which sets bits in the coproc bitfield. When
a '.fpu' directive is encountered, the CRC feature bit gets removed and
there is no way to set it back using '.fpu'.
With this patch, CRC will be marked in the feature core bits, which prevents
it from getting removed when setting/changing the fpu options.
gas/ChangeLog:
* config/tc-arm.c (arm_ext_crc): New.
(crc_ext_armv8): Remove.
(insns): Rename crc_ext_armv8 to arm_ext_crc.
(arm_cpus): Replace CRC_EXT_ARMV8 with ARM_EXT2_CRC.
(armv8a_ext_table, armv8r_ext_table,
arm_option_extension_value_table): Redefine the crc
extension in terms of ARM_EXT2_CRC.
* gas/testsuite/gas/arm/crc-ext.s: New.
* gas/testsuite/gas/arm/crc-ext.d: New.
include/ChangeLog:
* opcode/arm.h (ARM_EXT2_CRC): New extension feature
to replace CRC_EXT_ARMV8.
(CRC_EXT_ARMV8): Remove and mark bit as unused.
(ARM_ARCH_V8A_CRC, ARM_ARCH_V8_1A, ARM_ARCH_V8_2A,
ARM_ARCH_V8_3A, ARM_ARCH_V8_4A, ARM_ARCH_V8_5A,
ARM_ARCH_V8_6A): Redefine using ARM_EXT2_CRC instead of
CRC_EXT_ARMV8.
opcodes/ChangeLog:
* opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
Change the coproc CRC conditions to use the extension
feature set, second word, base on ARM_EXT2_CRC.
... instead of an operand one. Which operand it applies to can be
determined from other operand properties, but as it turns out the only
place it is actually used at doesn't even need further qualification.
This patch enables a few instructions for Armv8.1-M MVE. Currently VLDM,
VSTM, VSTR, VLDR, VPUSH and VPOP are enabled only when the Armv8-M
Floating-point Extension is enabled. According to the ARMv8.1-M ARM,
section A.1.4.2[1], they can be enabled by having "Armv8-M Floating-point
Extension and/or Armv8.1-M MVE".
[1]https://developer.arm.com/docs/ddi0553/bh/armv81-m-architecture-reference-manual
2019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>
* config/tc-arm.c (do_vfp_nsyn_push): Move in order to enable it for
both fpu_vfp_ext_v1xd and mve_ext and add call to the aliased vstm
instruction for mve_ext.
(do_vfp_nsyn_pop): Move in order to enable it for both
fpu_vfp_ext_v1xd and mve_ext and add call to the aliased vldm
instruction for mve_ext.
(do_neon_ldm_stm): Add fpu_vfp_ext_v1 and mve_ext checks.
(insns): Enable vldm, vldmia, vldmdb, vstm, vstmia, vstmdb, vpop,
vpush, and fldd, fstd, flds, fsts for arm_ext_v6t2 instead
of fpu_vfp_ext_v1xd.
* testsuite/gas/arm/v8_1m-mve.s: New.
* testsuite/gas/arm/v8_1m-mve.d: New.
This patch updates the decoding of the VMOV and VMVN instructions which depend on cmode.
Previously VMOV and VMVN with cmode 1101 were not allowed.
The cmode changes also required updating of the MVE conflict checking.
Now instructions with opcodes 0xef800d50 and 0xef800e70 correctly get decoded as VMOV
and VMVN, respectively.
2019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>
* opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
cmode 1101.
(is_mve_encoding_conflict): Update cmode conflict checks for
MVE_VMVN_IMM.
2019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>
* gas/config/tc-arm.c (do_neon_mvn): Allow mve_ext cmode=0xd.
* testsuite/gas/arm/mve-vmov-vmvn-vorr-vbic.s: New test.
* testsuite/gas/arm/mve-vmov-vmvn-vorr-vbic.d: Likewise.
EsSeg (a per-operand bit) is used with IsString (a per-insn attribute)
only. Extend the attribute to 2 bits, thus allowing to encode
- not a string insn,
- string insn with neither operand requiring use of %es:,
- string insn with 1st operand requiring use of %es:,
- string insn with 2nd operand requiring use of %es:,
which covers all possible cases, allowing to drop EsSeg.
The (transient) need to comment out the OTUnused #define did uncover an
oversight in the earlier OTMax -> OTNum conversion, which is being taken
care of here.
Drop the remaining instances left in place by commit c3949f432f ("x86:
limit ImmExt abuse), now that we have a way to specify specific GPRs.
Take the opportunity and also introduce proper 16-bit forms of
applicable SVME insns as well as 1-operand forms of CLZERO.
Special register "class" instances can't be combined with one another
(neither in templates nor in register entries), and hence it is not a
good use of resources (memory as well as execution time) to represent
them as individual bits of a bit field.
Furthermore the generalization becoming possible will allow
improvements to the handling of insns accepting only individual
registers as their operands.
We should check suffix in instruction mnemonic when matching instruction.
In Intel syntax, normally we check for memory operand size. But the same
mnemonic with 2 different encodings can have the same memory operand
size and i.suffix is set to LONG_DOUBLE_MNEM_SUFFIX from memory operand
size in Intel syntax to distinguish them. When there is no suffix in
mnemonic, we check LONG_DOUBLE_MNEM_SUFFIX in i.suffix for mnemonic
suffix.
gas/
PR gas/25167
* config/tc-i386.c (match_template): Don't check instruction
suffix set from operand.
* testsuite/gas/i386/code16.d: New file.
* testsuite/gas/i386/code16.s: Likewise.
* testsuite/gas/i386/i386.exp: Run code16.
* testsuite/gas/i386/x86-64-branch-4.l: Updated.
opcodes/
PR gas/25167
* i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
* i386-tbl.h: Regenerated.
