Commit Graph

1163 Commits

Author SHA1 Message Date
Sergey Belyashov
0d832e7f5e Add support for the xdef and xref pseudo-ops to the Z80 assembler.
PR 25690
	* config/tc-z80.c (md_pseudo_table): Add xdef anf xref pseudo ops.
	* doc/c-z80.texi: Update documentation.
2020-03-20 13:53:02 +00:00
H.J. Lu
ae531041c7 i386: Generate lfence with load/indirect branch/ret [CVE-2020-0551]
Add 3 command-line options to generate lfence for load, indirect near
branch and ret to help mitigate:

https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00334.html
http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2020-0551

1. -mlfence-after-load=[no|yes]:
  -mlfence-after-load=yes generates lfence after load instructions.
2. -mlfence-before-indirect-branch=[none|all|memory|register]:
  a. -mlfence-before-indirect-branch=all generates lfence before indirect
  near branches via register and a warning before indirect near branches
  via memory.
  b. -mlfence-before-indirect-branch=memory issue a warning before
  indirect near branches via memory.
  c. -mlfence-before-indirect-branch=register generates lfence before
  indirect near branches via register.
Note that lfence won't be generated before indirect near branches via
register with -mlfence-after-load=yes since lfence will be generated
after loading branch target register.
3. -mlfence-before-ret=[none|or|not]
  a. -mlfence-before-ret=or generates or with lfence before ret.
  b. -mlfence-before-ret=not generates not with lfence before ret.

A warning will be issued and lfence won't be generated before indirect
near branch and ret if the previous item is a prefix or a constant
directive, which may be used to hardcode an instruction, since there
is no clear instruction boundary.

	* config/tc-i386.c (lfence_after_load): New.
	(lfence_before_indirect_branch_kind): New.
	(lfence_before_indirect_branch): New.
	(lfence_before_ret_kind): New.
	(lfence_before_ret): New.
	(last_insn): New.
	(load_insn_p): New.
	(insert_lfence_after): New.
	(insert_lfence_before): New.
	(md_assemble): Call insert_lfence_before and insert_lfence_after.
	Set last_insn.
	(OPTION_MLFENCE_AFTER_LOAD): New.
	(OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH): New.
	(OPTION_MLFENCE_BEFORE_RET): New.
	(md_longopts): Add -mlfence-after-load=,
	-mlfence-before-indirect-branch= and -mlfence-before-ret=.
	(md_parse_option): Handle -mlfence-after-load=,
	-mlfence-before-indirect-branch= and -mlfence-before-ret=.
	(md_show_usage): Display -mlfence-after-load=,
	-mlfence-before-indirect-branch= and -mlfence-before-ret=.
	(i386_cons_align): New.
	* config/tc-i386.h (i386_cons_align): New.
	(md_cons_align): New.
	* doc/c-i386.texi: Document -mlfence-after-load=,
	-mlfence-before-indirect-branch= and -mlfence-before-ret=.
2020-03-11 09:46:19 -07:00
Nick Clifton
5496f3c635 Add support for generating DWARF-5 format directory and file name tables from the assembler.
PR 25611
	PR 25614
	* dwarf.h (DWARF2_Internal_LineInfo): Add li_address_size and
	li_segment_size fields.
	* dwarf.c (read_debug_line_header): Record the address size and
	segment selector size values (if present) in the lineinfo
	structure.
	(display_formatted_table): Warn if the format count is empty but
	the table itself is not empty.
	Display the format count and entry count at the start of the table
	dump.
	(display_debug_lines_raw): Display the address size and segement
	selector size fields, if present.
	* testsuite/binutils-all/dw5.W: Update expected output.

gas	* dwarf2dbg.c (DWARF2_FILE_TIME_NAME): Default to -1.
	(DWARF2_FILE_SIZE_NAME): Default to -1.
	(DWARF2_LINE_VERSION): Default to the current dwarf level or 3,
	whichever is higher.
	(DWARF2_LINE_MAX_OPS_PER_INSN): Provide a default value of 1.
	(NUM_MD5_BYTES): Define.
	(struct file entry): Add md5 field.
	(get_filenum): Delete and replace with...
	(get_basename): New function.
	(get_directory_table_entry): New function.
	(allocate_filenum): New function.
	(allocate_filename_to_slot): New function.
	(dwarf2_where): Use new functions.
	(dwarf2_directive_filename): Add support for extended .file
	pseudo-op.
	(dwarf2_directive_loc): Allow the use of file number zero with
	DWARF 5 or higher.
	(out_file_list): Rename to...
	(out_dir_and_file_list): Add DWARF 5 support.
	(out_debug_line): Emit extra values into the section header for
	DWARF 5.
	(out_debug_str): Allow for file 0 to be used with DWARF 5.
	* doc/as.texi (.file): Update the description of this pseudo-op.
	* testsuite/gas/elf-dwarf-5-file0.s: Add more lines.
	* testsuite/gas/elf-dwarf-5-file0.d: Update expected dump output.
	* testsuite/gas/lns/lns-diag-1.l: Update expected error message.
	* NEWS: Mention the new feature.
2020-03-11 10:17:14 +00:00
Nick Clifton
84d9ab33f3 Add support for a ".file 0" directive if supporting DWARF 5 or higher.
PR 25614
	* dwarf2dbg.c (dwarf2_directive_filename): Allow a file number of
	0 if the dwarf_level is 5 or more.  Complain if a filename follows
	a file 0.
	* testsuite/gas/elf/dwarf-5-file0.s: New test.
	* testsuite/gas/elf/dwarf-5-file0.d: New test driver.
	* testsuite/gas/elf/elf.exp: Run the new test.

	PR 25612
	* config/tc-ia64.h (DWARF2_VERISION): Fix typo.
	* doc/as.texi: Fix another typo.
2020-03-06 17:13:22 +00:00
Nick Clifton
31bf18645d Add support for --dwarf-[3|4|5] to assembler command line.
PR 25612
	* as.c (dwarf_level): Define.
	(show_usage): Add --gdwarf-3, --gdwarf-4 and --gdwarf-5.
	(parse_args): Add support for the new options.
	as.h (dwarf_level): Prototype.
	* dwarf2dbg.c (DWARF2_VERSION): Use dwarf_level as default version
	value.
	* config/tc-ia64.h (DWARF2_VERISION): Update definition.
	(DWARF2_LINE_VERSION): Remove definition.
	* doc/as.texi: Document the new options.
2020-03-06 14:52:14 +00:00
Nelson Chu
dee35d026c RISC-V: Support assembler modifier %got_pcrel_hi.
gas/
	* config/tc-riscv.c: Support the modifier %got_pcrel_hi.
	* doc/c-riscv.texi: Add documentation.
	* testsuite/gas/riscv/no-relax-reloc.d: Add test case for the new
	modifier %got_pcrel_hi.
	* testsuite/gas/riscv/no-relax-reloc.s: Likewise.
	* testsuite/gas/riscv/relax-reloc.d: Likewise.
	* testsuite/gas/riscv/relax-reloc.s: Likewise.
2020-03-04 17:11:37 -08:00
Nelson Chu
de48783e2f RISC-V: Add description for RISC-V Modifiers to as doc.
gas/
	* doc/c-riscv.texi (relocation modifiers): Add documentation.
	(RISC-V-Formats): Update the section name from "Instruction Formats"
	to "RISC-V Instruction Formats".
2020-03-04 17:11:37 -08:00
Jan Beulich
a847e32224 x86: support VMGEXIT
It has been publicly documented for quite some time, albeit not in the
"General-Purpose and System Instructions" volume:
https://www.amd.com/system/files/TechDocs/24593.pdf.
2020-03-04 08:58:13 +01:00
Nelson Chu
2ca89224b1 RISC-V: Disable the CSR checking by default.
Add new .option `csr-check/no-csr-check` and GAS option `-mcsr-check
/-mno-csr-check` to enbale/disable the CSR checking.  Disable the CSR
checking by default.

	gas/
	* config/tc-riscv.c: Add new .option and GAS options to enbale/disable
	the CSR checking.  We disable the CSR checking by default.
	(reg_lookup_internal): Check the `riscv_opts.csr_check`
	before we doing the CSR checking.

	* doc/c-riscv.texi: Add description for the new .option and assembler
	options.

	* testsuite/gas/riscv/priv-reg-fail-fext.d: Add `-mcsr-check` to enable
	the CSR checking.
	* testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.
2020-02-20 16:49:09 -08:00
Nelson Chu
bd3380bcdd RISC-V: Add description for -march-attr/-mno-arch-attr options in gas doc.
gas/
	* doc/c-riscv.texi: Add the doc entries for -march-attr/
	-mno-arch-attr command line options.
2020-02-19 17:18:25 -08:00
Sergey Belyashov
fcaaac0a0d Various fixes for the Z80 support.
PR 25537
ld	* emultempl/z80.em: Remove machine compatability checking.

	PR 25517
	* testsuite/ld-z80/arch_ez80_adl.d: Update command line.
	* testsuite/ld-z80/arch_ez80_z80.d: Likewise.
	* testsuite/ld-z80/arch_r800.d: Likewise.
	* testsuite/ld-z80/arch_z180.d: Likewise.
	* testsuite/ld-z80/arch_z80n.d: Likewise.
	* testsuite/ld-z80/comb_arch_ez80_z80.d: Likewise.
	* testsuite/ld-z80/comb_arch_z180_z80.d: Likewise.
	* testsuite/ld-z80/comb_arch_z80_ez80.d: Likewise.
	* testsuite/ld-z80/comb_arch_z80_z180.d: Likewise.
	* testsuite/ld-z80/comb_arch_z80_z80n.d: Likewise.
	* testsuite/ld-z80/relocs_b_ez80.d: Likewise.
	* testsuite/ld-z80/relocs_b_z80.d: Likewise.
	* testsuite/ld-z80/relocs_f_ez80.d: Likewise.
	* testsuite/ld-z80/relocs_f_z80.d: Likewise.
	* testsuite/ld-z80/relocs_f_z80n.d: Likewise.

bfd
	* cpu-z80.c: Add machine type compatibility checking.

gas
	* config/tc-z80.c (md_parse_option): Do not use an underscore
	prefix for local labels in SDCC compatability mode.
	(z80_start_line_hook): Remove SDCC dollar label support.
	* testsuite/gas/z80/sdcc.d: Update expected disassembly.
	* testsuite/gas/z80/sdcc.s: Likewise.

	* config/tc-z80.c: Add -march option.
	* doc/as.texi: Update Z80 documentation.
	* doc/c-z80.texi: Likewise.
	* testsuite/gas/z80/ez80_adl_all.d: Update command line.
	* testsuite/gas/z80/ez80_adl_suf.d: Likewise.
	* testsuite/gas/z80/ez80_pref_dis.d: Likewise.
	* testsuite/gas/z80/ez80_z80_all.d: Likewise.
	* testsuite/gas/z80/ez80_z80_suf.d: Likewise.
	* testsuite/gas/z80/gbz80_all.d: Likewise.
	* testsuite/gas/z80/r800_extra.d: Likewise.
	* testsuite/gas/z80/r800_ii8.d: Likewise.
	* testsuite/gas/z80/r800_z80_doc.d: Likewise.
	* testsuite/gas/z80/sdcc.d: Likewise.
	* testsuite/gas/z80/z180.d: Likewise.
	* testsuite/gas/z80/z180_z80_doc.d: Likewise.
	* testsuite/gas/z80/z80_doc.d: Likewise.
	* testsuite/gas/z80/z80_ii8.d: Likewise.
	* testsuite/gas/z80/z80_in_f_c.d: Likewise.
	* testsuite/gas/z80/z80_op_ii_ld.d: Likewise.
	* testsuite/gas/z80/z80_out_c_0.d: Likewise.
	* testsuite/gas/z80/z80_sli.d: Likewise.
	* testsuite/gas/z80/z80n_all.d: Likewise.
	* testsuite/gas/z80/z80n_reloc.d: Likewise.
2020-02-19 17:46:10 +00:00
H.J. Lu
272a84b120 x86: Remove CpuABM and add CpuPOPCNT
AMD ABM has 2 instructions: popcnt and lzcnt.  ABM CPUID feature bit has
been reused for lzcnt and a POPCNT CPUID feature bit is added for popcnt
which used to be the part of SSE4.2.  This patch removes CpuABM and adds
CpuPOPCNT.  It changes ABM to enable both lzcnt and popcnt, changes SSE4.2
to also enable popcnt.

gas/

	* config/tc-i386.c (cpu_arch): Add .popcnt.
	* doc/c-i386.texi: Remove abm and .abm.  Add popcnt and .popcnt.
	Add a tab before @samp{.sse4a}.

opcodes/

	* i386-gen.c (cpu_flag_init): Replace CpuABM with
	CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
	CPU_POPCNT_FLAGS.
	(cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
	* i386-opc.h (CpuABM): Removed.
	(CpuPOPCNT): New.
	(i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
	* i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
	popcnt.  Remove CpuABM from lzcnt.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
2020-02-17 07:31:28 -08:00
H.J. Lu
af5c13b01e x86: Don't disable SSE4a when disabling SSE4
commit 7deea9aad8 changed nosse4 to include CpuSSE4a.  But AMD SSE4a is
a superset of SSE3 and Intel SSE4 is a superset of SSSE3.  Disable Intel
SSE4 shouldn't disable AMD SSE4a.  This patch restores nosse4.  It also
adds .sse4a and nosse4a.

gas/

	* config/tc-i386.c (cpu_arch): Add .sse4a and nosse4a.  Restore
	nosse4.
	* doc/c-i386.texi: Document sse4a and nosse4a.

opcodes/

	* i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
	CPU_ANY_SSE4_FLAGS.
2020-02-16 08:45:34 -08:00
H.J. Lu
07d9838745 Remove the old movsx and movzx documentation for AT&T syntax
* doc/c-i386.texi: Remove the old movsx and movzx documentation
	for AT&T syntax.
2020-02-14 06:09:28 -08:00
H.J. Lu
0e6724dee4 x86: Document movsx/movsxd/movzx for AT&T syntax
Document different mnemonics of movsx, movsxd and movzx in AT&T syntax.

	PR gas/25438
	* doc/c-i386.texi: Document movsx, movsxd and movzx for AT&T
	syntax.
2020-02-14 04:57:16 -08:00
Jan Beulich
5990e377e5 x86-64: Intel64 adjustments for insns dealing with far pointers
AMD and Intel differ in their handling of far indirect branches as well
as LFS/LGS/LSS: AMD CPUs ignore REX.W while Intel ones honors it. (Note
how the latter three were hybrids so far, while far branches were fully
AMD-like.)
2020-02-12 16:19:03 +01:00
Matthew Malcomson
4934a27c8c [binutils][arm] arm support for ARMv8.m Custom Datapath Extension
This patch is part of a series that adds support for the Armv8.m
ARMv8.m Custom Datapath Extension to binutils.

This patch introduces the Custom Instructions Class 1/2/3 (Single/
Dual, Accumulator/Non-accumulator varianats) to the arm backend.

The following Custom Instructions are added: cx1, cx1a,
cx1d, cx1da, cx2, cx2a, cx2d, cx2da, cx3, cx3a, cx3d, cx3da.

Specification can be found at
https://developer.arm.com/docs/ddi0607/latest

This patch distinguishes between enabling CDE for different coprocessor
numbers by defining multiple architecture flags.  This means that the
parsing of the architecture extension flags is kept entirely in the
existing code path.

We introduce a new IT block state to indicate the behaviour of these
instructions.  This new state allows being used in an IT block or
outside an IT block, but does not allow the instruction to be used
inside a VPT block.
We need this since the CX*A instruction versions can be used in IT
blocks, but they aren't to have the conditional suffixes on them.  Hence
we need to mark an instruction as allowed in either position.

We also need a new flag to objdump, in order to determine whether to
disassemble an instruction as CDE related or not.

Successfully regression tested on arm-none-eabi, and arm-wince-pe.

gas/ChangeLog:

2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
	    Matthew Malcomson  <matthew.malcomson@arm.com>

	* config/tc-arm.c (arm_ext_cde*): New feature sets for each
	CDE coprocessor that can be enabled.
	(enum pred_instruction_type): New pred type.
	(BAD_NO_VPT): New error message.
	(BAD_CDE): New error message.
	(BAD_CDE_COPROC): New error message.
	(enum operand_parse_code): Add new immediate operands.
	(parse_operands): Account for new immediate operands.
	(check_cde_operand): New.
	(cde_coproc_enabled): New.
	(cde_coproc_pos): New.
	(cde_handle_coproc): New.
	(cxn_handle_predication): New.
	(do_custom_instruction_1): New.
	(do_custom_instruction_2): New.
	(do_custom_instruction_3): New.
	(do_cx1): New.
	(do_cx1a): New.
	(do_cx1d): New.
	(do_cx1da): New.
	(do_cx2): New.
	(do_cx2a): New.
	(do_cx2d): New.
	(do_cx2da): New.
	(do_cx3): New.
	(do_cx3a): New.
	(do_cx3d): New.
	(do_cx3da): New.
	(handle_pred_state): Define new IT block behaviour.
	(insns): Add newn CX*{,d}{,a} instructions.
	(CDE_EXTENSIONS,armv8m_main_ext_table,armv8_1m_main_ext_table):
	Define new cdecp extension strings.
	* doc/c-arm.texi: Document new cdecp extension arguments.
	* testsuite/gas/arm/cde-scalar.d: New test.
	* testsuite/gas/arm/cde-scalar.s: New test.
	* testsuite/gas/arm/cde-warnings.d: New test.
	* testsuite/gas/arm/cde-warnings.l: New test.
	* testsuite/gas/arm/cde-warnings.s: New test.
	* testsuite/gas/arm/cde.d: New test.
	* testsuite/gas/arm/cde.s: New test.

include/ChangeLog:

2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
	    Matthew Malcomson  <matthew.malcomson@arm.com>

	* opcode/arm.h (ARM_EXT2_CDE): New extension macro.
	(ARM_EXT2_CDE0): New extension macro.
	(ARM_EXT2_CDE1): New extension macro.
	(ARM_EXT2_CDE2): New extension macro.
	(ARM_EXT2_CDE3): New extension macro.
	(ARM_EXT2_CDE4): New extension macro.
	(ARM_EXT2_CDE5): New extension macro.
	(ARM_EXT2_CDE6): New extension macro.
	(ARM_EXT2_CDE7): New extension macro.

opcodes/ChangeLog:

2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
	    Matthew Malcomson  <matthew.malcomson@arm.com>

	* arm-dis.c (struct cdeopcode32): New.
	(CDE_OPCODE): New macro.
	(cde_opcodes): New disassembly table.
	(regnames): New option to table.
	(cde_coprocs): New global variable.
	(print_insn_cde): New
	(print_insn_thumb32): Use print_insn_cde.
	(parse_arm_disassembler_options): Parse coprocN args.
2020-02-10 16:50:14 +00:00
H.J. Lu
4b5aaf5f69 x86: Accept Intel64 only instruction by default
Commit d835a58baa disabled sysenter/sysenter in 64-bit mode by
default.  By default, assembler should accept common, Intel64 only
and AMD64 ISAs since there are no conflicts.

gas/

	PR gas/25516
	* config/tc-i386.c (intel64): Renamed to ...
	(isa64): This.
	(match_template): Accept Intel64 only instruction by default.
	(i386_displacement): Updated.
	(md_parse_option): Updated.
	* c-i386.texi: Update -mamd64/-mintel64 documentation.
	* testsuite/gas/i386/i386.exp: Run x86-64-sysenter.  Pass
	-mamd64 to x86-64-sysenter-amd.
	* testsuite/gas/i386/x86-64-sysenter.d: New file.

opcodes/

	PR gas/25516
	* i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
	with ISA64.
	* i386-opc.h (AMD64): Removed.
	(Intel64): Likewose.
	(AMD64): New.
	(INTEL64): Likewise.
	(INTEL64ONLY): Likewise.
	(i386_opcode_modifier): Replace amd64 and intel64 with isa64.
	* i386-opc.tbl (Amd64): New.
	(Intel64): Likewise.
	(Intel64Only): Likewise.
	Replace AMD64 with Amd64.  Update sysenter/sysenter with
	Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
	* i386-tbl.h: Regenerated.
2020-02-10 08:37:36 -08:00
Sergey Belyashov
9fc0b501af Add support for the GBZ80 and Z80N variants of the Z80 architecture, and add DWARF debug info support to the Z80 assembler.
PR 25469
bfd	* archures.c: Add GBZ80 and Z80N machine values.
	* reloc.c: Add BFD_RELOC_Z80_16_BE.
	* coff-z80.c: Add support for new reloc.
	* coffcode.h: Add support for new machine values.
	* cpu-z80.c: Add support for new machine names.
	* elf32-z80.c: Add support for new reloc.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Regenerate.

binutils* readelf.c (get_machine_flags): Add support for Z80N machine
	number.

gas	* config/tc-z80.c: Add -gbz80 command line option to generate code
	for the GameBoy Z80.  Add support for generating DWARF.
	* config/tc-z80.h: Add support for DWARF debug information
	generation.
	* doc/c-z80.texi: Document new command line option.
	* testsuite/gas/z80/gbz80_all.d: New file.
	* testsuite/gas/z80/gbz80_all.s: New file.
	* testsuite/gas/z80/z80.exp: Run the new tests.
	* testsuite/gas/z80/z80n_all.d: New file.
	* testsuite/gas/z80/z80n_all.s: New file.
	* testsuite/gas/z80/z80n_reloc.d: New file.

include	* coff/internal.h (R_IMM16BE): Define.
	* elf/z80.h (EF_Z80_MACH_Z80N): Define.
	(R_Z80_16_BE): New reloc.

ld	* emulparams/elf32z80.sh: Use z80 emulation.
	* emultempl/z80.em: Make generic to both COFF and ELF Z80 emulations.
	* emultempl/z80elf.em: Delete.
	* testsuite/ld-elf/pr22450.d: Expect to fail for the Z80.
	* testsuite/ld-elf/sec64k.exp: Fix Z80 assembly.
	* testsuite/ld-unique/pr21529.s: Avoid register name conflict.
	* testsuite/ld-unique/unique.s: Likewise.
	* testsuite/ld-unique/unique_empty.s: Likewise.
	* testsuite/ld-unique/unique_shared.s: Likewise.
	* testsuite/ld-unique/unique.d: Updated expected output.
	* testsuite/ld-z80/arch_z80n.d: New file.
	* testsuite/ld-z80/comb_arch_z80_z80n.d: New file.
	* testsuite/ld-z80/labels.s: Add more labels.
	* testsuite/ld-z80/relocs.s: Add more reloc tests.
	* testsuite/ld-z80/relocs_f_z80n.d: New file

opcodes	* z80-dis.c: Add support for GBZ80 opcodes.
2020-02-07 14:53:46 +00:00
H.J. Lu
b7d0721677 ELF: Support the section flag 'o' in .section directive
As shown in

https://sourceware.org/bugzilla/show_bug.cgi?id=25490

--gc-sections will silently remove __patchable_function_entries section
and generate corrupt result.  This patch adds the section flag 'o' to
.section directive:

.section __patchable_function_entries,"awo",@progbits,foo
.section __patchable_function_entries,"awoG",@progbits,foo,foo,comdat
.section __patchable_function_entries,"awo",@progbits,bar,unique,4
.section __patchable_function_entries,"awoG",@progbits,foo,foo,comdat,unique,1

which specifies the symbol name which the section references.  Assmebler
will set its elf_linked_to_section to a local section where the symbol
is defined.

Linker is updated to call mark_hook if gc_mark of any of its linked-to
sections is set after all sections, except for backend specific ones,
have been garbage collected.

bfd/

	PR gas/25381
	* bfd-in2.h: Regenerated.
	* elflink.c (_bfd_elf_gc_mark_extra_sections): Call mark_hook
	on section if gc_mark of any of its linked-to sections is set
	and don't set gc_mark again.
	* section.c (asection): Add linked_to_symbol_name to map_head
	union.

gas/

	PR gas/25381
	* config/obj-elf.c (get_section): Also check
	linked_to_symbol_name.
	(obj_elf_change_section): Also set map_head.linked_to_symbol_name.
	(obj_elf_parse_section_letters): Handle the 'o' flag.
	(build_group_lists): Renamed to ...
	(build_additional_section_info): This.  Set elf_linked_to_section
	from map_head.linked_to_symbol_name.
	(elf_adjust_symtab): Updated.
	* config/obj-elf.h (elf_section_match): Add linked_to_symbol_name.
	* doc/as.texi: Document the 'o' flag.
	* testsuite/gas/elf/elf.exp: Run PR gas/25381 tests.
	* testsuite/gas/elf/section18.d: New file.
	* testsuite/gas/elf/section18.s: Likewise.
	* testsuite/gas/elf/section19.d: Likewise.
	* testsuite/gas/elf/section19.s: Likewise.
	* testsuite/gas/elf/section20.d: Likewise.
	* testsuite/gas/elf/section20.s: Likewise.
	* testsuite/gas/elf/section21.d: Likewise.
	* testsuite/gas/elf/section21.l: Likewise.
	* testsuite/gas/elf/section21.s: Likewise.

ld/

	PR ld/24526
	PR ld/25021
	PR ld/25490
	* testsuite/ld-elf/elf.exp: Run PR ld/25490 tests.
	* testsuite/ld-elf/pr24526.d: New file.
	* testsuite/ld-elf/pr24526.s: Likewise.
	* testsuite/ld-elf/pr25021.d: Likewise.
	* testsuite/ld-elf/pr25021.s: Likewise.
	* testsuite/ld-elf/pr25490-2-16.rd: Likewise.
	* testsuite/ld-elf/pr25490-2-32.rd: Likewise.
	* testsuite/ld-elf/pr25490-2-64.rd: Likewise.
	* testsuite/ld-elf/pr25490-2.s: Likewise.
	* testsuite/ld-elf/pr25490-3-16.rd: Likewise.
	* testsuite/ld-elf/pr25490-3-32.rd: Likewise.
	* testsuite/ld-elf/pr25490-3-64.rd: Likewise.
	* testsuite/ld-elf/pr25490-3.s: Likewise.
	* testsuite/ld-elf/pr25490-4-16.rd: Likewise.
	* testsuite/ld-elf/pr25490-4-32.rd: Likewise.
	* testsuite/ld-elf/pr25490-4-64.rd: Likewise.
	* testsuite/ld-elf/pr25490-4.s: Likewise.
	* testsuite/ld-elf/pr25490-5-16.rd: Likewise.
	* testsuite/ld-elf/pr25490-5-32.rd: Likewise.
	* testsuite/ld-elf/pr25490-5-64.rd: Likewise.
	* testsuite/ld-elf/pr25490-5.s: Likewise.
	* testsuite/ld-elf/pr25490-6-16.rd: Likewise.
	* testsuite/ld-elf/pr25490-6-32.rd: Likewise.
	* testsuite/ld-elf/pr25490-6-64.rd: Likewise.
	* testsuite/ld-elf/pr25490-6.s: Likewise.
2020-02-06 18:05:10 -08:00
H.J. Lu
a8c4d40b57 ELF: Add support for unique section ID to assembler
Clang's integrated assembler supports multiple section with the same
name:

	.section .text,"ax",@progbits,unique,1
	nop
	.section .text,"ax",@progbits,unique,2
	nop

"unique,N" assigns the number, N, as the section ID, to a section.  The
valid values of the section ID are between 0 and 4294967295.  It can be
used to distinguish different sections with the same section name.

This is useful with -fno-unique-section-names -ffunction-sections.
-ffunction-sections by default generates .text.foo, .text.bar, etc.
Using the same string can save lots of space in .strtab.

This patch adds section_id to bfd_section and reuses the linker
internal bit in BFD section flags, SEC_LINKER_CREATED, for assmebler
internal use to mark valid section_id.  It also updates objdump to
compare section pointers if 2 sections comes from the same file since
2 different sections can have the same section name.

bfd/

	PR gas/25380
	* bfd-in2.h: Regenerated.
	* ecoff.c (bfd_debug_section): Add section_id.
	* section.c (bfd_section): Add section_id.
	(SEC_ASSEMBLER_SECTION_ID): New.
	(BFD_FAKE_SECTION): Add section_id.

binutils/

	PR gas/25380
	* objdump.c (sym_ok): Return FALSE if 2 sections are in the
	same file with different section pointers.

gas/

	PR gas/25380
	* config/obj-elf.c (section_match): Removed.
	(get_section): Also match SEC_ASSEMBLER_SECTION_ID and
	section_id.
	(obj_elf_change_section): Replace info and group_name arguments
	with match_p.  Also update the section ID and flags from match_p.
	(obj_elf_section): Handle "unique,N".  Update call to
	obj_elf_change_section.
	* config/obj-elf.h (elf_section_match): New.
	(obj_elf_change_section): Updated.
	* config/tc-arm.c (start_unwind_section): Update call to
	obj_elf_change_section.
	* config/tc-ia64.c (obj_elf_vms_common): Likewise.
	* config/tc-microblaze.c (microblaze_s_data): Likewise.
	(microblaze_s_sdata): Likewise.
	(microblaze_s_rdata): Likewise.
	(microblaze_s_bss): Likewise.
	* config/tc-mips.c (s_change_section): Likewise.
	* config/tc-msp430.c (msp430_profiler): Likewise.
	* config/tc-rx.c (parse_rx_section): Likewise.
	* config/tc-tic6x.c (tic6x_start_unwind_section): Likewise.
	* doc/as.texi: Document "unique,N" in .section directive.
	* testsuite/gas/elf/elf.exp: Run "unique,N" tests.
	* testsuite/gas/elf/section15.d: New file.
	* testsuite/gas/elf/section15.s: Likewise.
	* testsuite/gas/elf/section16.s: Likewise.
	* testsuite/gas/elf/section16a.d: Likewise.
	* testsuite/gas/elf/section16b.d: Likewise.
	* testsuite/gas/elf/section17.d: Likewise.
	* testsuite/gas/elf/section17.l: Likewise.
	* testsuite/gas/elf/section17.s: Likewise.
	* testsuite/gas/i386/unique.d: Likewise.
	* testsuite/gas/i386/unique.s: Likewise.
	* testsuite/gas/i386/x86-64-unique.d: Likewise.
	* testsuite/gas/i386/i386.exp: Run unique and x86-64-unique.

ld/

	PR gas/25380
	* testsuite/ld-i386/pr22001-1c.S: Use "unique,N" in .section
	directives.
	* testsuite/ld-i386/tls-gd1.S: Likewise.
	* testsuite/ld-x86-64/pr21481b.S: Likewise.
2020-02-02 17:08:01 -08:00
H.J. Lu
bc31405ebb x86-64: Properly encode and decode movsxd
movsxd is a 64-bit only instruction.  It supports both 16-bit and 32-bit
destination registers.  Its AT&T mnemonic is movslq which only supports
64-bit destination register.  There is also a discrepancy between AMD64
and Intel64 on movsxd with 16-bit destination register.  AMD64 supports
32-bit source operand and Intel64 supports 16-bit source operand.

This patch updates movsxd encoding and decoding to alow 16-bit and 32-bit
destination registers.  It also handles movsxd with 16-bit destination
register for AMD64 and Intel 64.

gas/

	PR binutils/25445
	* config/tc-i386.c (check_long_reg): Also convert to QWORD for
	movsxd.
	* doc/c-i386.texi: Add a node for AMD64 vs. Intel64 ISA
	differences.  Document movslq and movsxd.
	* testsuite/gas/i386/i386.exp: Run PR binutils/25445 tests.
	* testsuite/gas/i386/x86-64-movsxd-intel.d: New file.
	* testsuite/gas/i386/x86-64-movsxd-intel64-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-movsxd-intel64-inval.l: Likewise.
	* testsuite/gas/i386/x86-64-movsxd-intel64-inval.s: Likewise.
	* testsuite/gas/i386/x86-64-movsxd-intel64.d: Likewise.
	* testsuite/gas/i386/x86-64-movsxd-intel64.s: Likewise.
	* testsuite/gas/i386/x86-64-movsxd-inval.l: Likewise.
	* testsuite/gas/i386/x86-64-movsxd-inval.s: Likewise.
	* testsuite/gas/i386/x86-64-movsxd.d: Likewise.
	* testsuite/gas/i386/x86-64-movsxd.s: Likewise.

opcodes/

	PR binutils/25445
	* i386-dis.c (MOVSXD_Fixup): New function.
	(movsxd_mode): New enum.
	(x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
	(intel_operand_size): Handle movsxd_mode.
	(OP_E_register): Likewise.
	(OP_G): Likewise.
	* i386-opc.tbl: Remove Rex64 and allow 32-bit destination
	register on movsxd.  Add movsxd with 16-bit destination register
	for AMD64 and Intel64 ISAs.
	* i386-tbl.h: Regenerated.
2020-01-27 04:38:29 -08:00
Jan Beulich
c006a730e9 x86: improve handling of insns with ambiguous operand sizes
Commit b76bc5d54e ("x86: don't default variable shift count insns to
8-bit operand size") pointed out a very bad case, but the underlying
problem is, as mentioned on various occasions, much larger: Silently
selecting a (nowhere documented afaict) certain default operand size
when there's no "sizing" suffix and no suitable register operand(s) is
simply dangerous (for the programmer to make mistakes).

While in Intel syntax mode such mistakes already lead to an error (which
is going to remain that way), AT&T syntax mode now gains warnings in
such cases by default, which can be suppressed or promoted to an error
if so desired by the programmer. Furthermore at least general purpose
insns now consistently have a default applied (alongside the warning
emission), rather than accepting some and refusing others.

No warnings are (as before) to be generated for "DefaultSize" insns as
well as ones acting on selector and other fixed-width values. For
SYSRET, however, the DefaultSize needs to be dropped - it had been
wrongly put there in the first place, as it's unrelated to .code16gcc
(no stack accesses involved).

As set forth as a prereq when I first mentioned this intended change a
few years back, Linux as well as gcc have meanwhile been patched to
avoid (emission of) ambiguous operands (and hence triggering of the new
warning).

Note that I think that in 64-bit mode IRET and far RET would better get
a diagnostic too, as it's reasonably likely that a suffix-less instance
really is meant to be a 64-bit one. But I guess I better make this a
separate follow-on patch.

Note further that floating point operations with integer operands are an
exception for now: They continue to use short (16-bit) operands by
default even in 32- and 64-bit modes.

Finally note that while {,V}PCMPESTR{I,M} would, strictly speaking, also
need to be diagnosed, with their 64-bit forms not being very useful I
think it is better to continue to avoid warning about them (by way of
them carrying IgnoreSize attributes).
2020-01-21 08:28:25 +01:00
H.J. Lu
42e04b3601 x86: Add {vex} pseudo prefix
There are 2-byte VEX prefix and 3-byte VEX prefix.  2-byte VEX prefix
can't encode all operands.  By default, assembler tries 2-byte VEX prefix
first.  {vex3} can be used to force 3-byte VEX prefix.  This patch adds
{vex} pseudo prefix and keeps {vex2} for backward compatibility.

gas/

	* config/tc-i386.c (_i386_insn): Replace vex_encoding_vex2
	with vex_encoding_vex.
	(parse_insn): Likewise.
	* doc/c-i386.texi: Replace {vex2} with {vex}.  Update {vex}
	and {vex3} documentation.
	* testsuite/gas/i386/pseudos.s: Replace 3 {vex2} tests with
	{vex}.
	* testsuite/gas/i386/x86-64-pseudos.s: Likewise.

opcodes/

	* i386-opc.tbl: Add {vex} pseudo prefix.
	* i386-tbl.h: Regenerated.
2020-01-17 07:07:55 -08:00
Sergey Belyashov
7a6bf3becb Fix various assembler testsuite failures for the Z80 target.
PR 25377
gas	* config/tc-z80.c: Add support for half precision, single
	precision and double precision floating point values.
	* config/tc-z80.h b/gas/config/tc-z80.h: Disable string escapes.
	* doc/as.texi: Add new z80 command line options.
	* doc/c-z80.texi: Document new z80 command line options.
	* testsuite/gas/z80/ez80_pref_dis.s: New test.
	* testsuite/gas/z80/ez80_pref_dis.d: New test driver.
	* testsuite/gas/z80/z80.exp: Run the new test.
	* testsuite/gas/z80/fp_math48.d: Use correct command line option.
	* testsuite/gas/z80/fp_zeda32.d: Likewise.
	* testsuite/gas/z80/strings.d: Update expected output.

opcodes	* z80-dis.c (suffix): Use .db instruction to generate double
	prefix.
2020-01-14 13:13:57 +00:00
Nick Clifton
915808f652 Document the fact that the assembler's alignment pseudo-ops can be issued without any argumemtns.
PR 25284
	* doc/as.texi (Align): Document the fact that all arguments can be
	omitted.
	(Balign): Likewise.
	(P2align): Likewise.
2020-01-08 17:00:54 +00:00
Sergey Belyashov
6655dba246 Add support for the GBZ80, Z180, and eZ80 variants of the Z80 architecure. Add an ELF based target for these as well.
PR 25224
bfd	* Makefile.am: Add z80-elf target support.
	* configure.ac: Likewise.
	* targets.c: Likewise.
	* config.bfd: Add z80-elf target support and new arches: ez80 and z180.
	* elf32-z80.c: New file.
	* archures.c: Add new z80 architectures: eZ80 and Z180.
	* coffcode.h: Likewise.
	* cpu-z80.c: Likewise.
	* bfd-in2.h: Likewise plus additional Z80 relocations.
	* coff-z80.c: Add new relocations for Z80 target and local label check.

gas	* config/tc-z80.c: Add new architectures: Z180 and eZ80. Add support
	for assembler code generated by SDCC. Add new relocation types. Add
	z80-elf target support.
	* config/tc-z80.h: Add z80-elf target support. Enable dollar local
	labels. Local labels starts from ".L".
	* testsuite/gas/all/fwdexp.d: Fix failure due to symbol conflict.
	* testsuite/gas/all/fwdexp.s: Likewise.
	* testsuite/gas/z80/suffix.d: Fix failure on ELF target.
	* testsuite/gas/z80/z80.exp: Add new tests
	* testsuite/gas/z80/dollar.d: New file.
	* testsuite/gas/z80/dollar.s: New file.
	* testsuite/gas/z80/ez80_adl_all.d: New file.
	* testsuite/gas/z80/ez80_adl_all.s: New file.
	* testsuite/gas/z80/ez80_adl_suf.d: New file.
	* testsuite/gas/z80/ez80_isuf.s: New file.
	* testsuite/gas/z80/ez80_z80_all.d: New file.
	* testsuite/gas/z80/ez80_z80_all.s: New file.
	* testsuite/gas/z80/ez80_z80_suf.d: New file.
	* testsuite/gas/z80/r800_extra.d: New file.
	* testsuite/gas/z80/r800_extra.s: New file.
	* testsuite/gas/z80/r800_ii8.d: New file.
	* testsuite/gas/z80/r800_z80_doc.d: New file.
	* testsuite/gas/z80/z180.d: New file.
	* testsuite/gas/z80/z180.s: New file.
	* testsuite/gas/z80/z180_z80_doc.d: New file.
	* testsuite/gas/z80/z80_doc.d: New file.
	* testsuite/gas/z80/z80_doc.s: New file.
	* testsuite/gas/z80/z80_ii8.d: New file.
	* testsuite/gas/z80/z80_ii8.s: New file.
	* testsuite/gas/z80/z80_in_f_c.d: New file.
	* testsuite/gas/z80/z80_in_f_c.s: New file.
	* testsuite/gas/z80/z80_op_ii_ld.d: New file.
	* testsuite/gas/z80/z80_op_ii_ld.s: New file.
	* testsuite/gas/z80/z80_out_c_0.d: New file.
	* testsuite/gas/z80/z80_out_c_0.s: New file.
	* testsuite/gas/z80/z80_reloc.d: New file.
	* testsuite/gas/z80/z80_reloc.s: New file.
	* testsuite/gas/z80/z80_sli.d: New file.
	* testsuite/gas/z80/z80_sli.s: New file.

ld	* Makefile.am: Add new target z80-elf
	* configure.tgt: Likewise.
	* emultempl/z80.em: Add support for eZ80 and Z180 architectures.
	* emulparams/elf32z80.sh: New file.
	* emultempl/z80elf.em: Likewise.
	* testsuite/ld-z80/arch_ez80_adl.d: Likewise.
	* testsuite/ld-z80/arch_ez80_z80.d: Likewise.
	* testsuite/ld-z80/arch_r800.d: Likewise.
	* testsuite/ld-z80/arch_z180.d: Likewise.
	* testsuite/ld-z80/arch_z80.d: Likewise.
	* testsuite/ld-z80/comb_arch_ez80_z80.d: Likewise.
	* testsuite/ld-z80/comb_arch_z180.d: Likewise.
	* testsuite/ld-z80/labels.s: Likewise.
	* testsuite/ld-z80/relocs.s: Likewise.
	* testsuite/ld-z80/relocs_b_ez80.d: Likewise.
	* testsuite/ld-z80/relocs_b_z80.d: Likewise.
	* testsuite/ld-z80/relocs_f_z80.d: Likewise.
	* testsuite/ld-z80/z80.exp: Likewise.

opcodes	* z80-dis.c: Add support for eZ80 and Z80 instructions.
2020-01-02 14:14:59 +00:00
Alan Modra
b3adc24a07 Update year range in copyright notice of binutils files 2020-01-01 18:42:54 +10:30
Alan Modra
5b660084e2 Remove tic80 support
This is one way of fixing ubsan bug reports, just delete the code.

The assembler support was removed back in 2005 along with other
non-BFD assemblers, but somehow the remainder of the port stayed in.

bfd/
	* coff-tic80.c: Delete file.
	* cpu-tic80.c: Delete file.
	* archures.c: Remove tic80 support.
	* coffcode.h: Likewise.
	* coffswap.h: Likewise.
	* targets.c: Likewise.
	* config.bfd: Likewise.
	* configure.ac: Likewise.
	* Makefile.am: Likewise.
	* Makefile.in: Regenerate.
	* bfd-in2.h: Regenerate.
	* configure: Regenerate.
	* po/SRC-POTFILES.in: Regenerate.
binutils/
	* testsuite/binutils-all/objcopy.exp: Remove tic80 support.
	* testsuite/binutils-all/objdump.exp: Likewise.
gas/
	* doc/as.texi: Remove mention of tic80.
include/
	* coff/tic80.h: Delete file.
	* opcode/tic80.h: Delete file.
ld/
	* emulparams/tic80coff.sh: Delete file.
	* scripttempl/tic80coff.sc: Delete file.
	* configure.tgt: Remove tic80 support.
	* Makefile.am: Likewise.
	* Makefile.in: Regenerate.
	* po/BLD-POTFILES.in: Regenerate.
opcodes/
	* tic80-dis.c: Delete file.
	* tic80-opc.c: Delete file.
	* disassemble.c: Remove tic80 support.
	* disassemble.h: Likewise.
	* Makefile.am: Likewise.
	* configure.ac: Likewise.
	* Makefile.in: Regenerate.
	* configure: Regenerate.
	* po/POTFILES.in: Regenerate.
2019-12-17 16:36:54 +10:30
H.J. Lu
76cf450b4c i386: Add -mbranches-within-32B-boundaries
Add -mbranches-within-32B-boundaries to enable

-malign-branch-boundary=32
-malign-branch=jcc+fused+jmp
-malign-branch-prefix-size=5

	* config/tc-i386.c (OPTION_MBRANCHES_WITH_32B_BOUNDARIES): New.
	(md_longopts): Add -mbranches-within-32B-boundaries.
	(md_parse_option): Handle -mbranches-within-32B-boundaries.
	(md_show_usage): Add -mbranches-within-32B-boundaries.
2019-12-12 12:03:45 -08:00
H.J. Lu
e379e5f385 i386: Align branches within a fixed boundary
Add 3 command-line options to align branches within a fixed boundary
with segment prefixes or NOPs:

1. -malign-branch-boundary=NUM aligns branches within NUM byte boundary.
2. -malign-branch=TYPE[+TYPE...] specifies types of branches to align.
The supported branches are:
  a. Conditional jump.
  b. Fused conditional jump.
  c. Unconditional jump.
  d. Call.
  e. Ret.
  f. Indirect jump and call.
3. -malign-branch-prefix-size=NUM aligns branches with NUM segment
prefixes per instruction.

3 new rs_machine_dependent frag types are added:

1. BRANCH_PADDING.  The variable size frag to insert NOP before branch.
2. BRANCH_PREFIX.  The variable size frag to insert segment prefixes to
an instruction.  The choices of prefixes are:
   a. Use the existing segment prefix if there is one.
   b. Use CS segment prefix in 64-bit mode.
   c. In 32-bit mode, use SS segment prefix with ESP/EBP base register
   and use DS segment prefix without ESP/EBP base register.
3. FUSED_JCC_PADDING.  The variable size frag to insert NOP before fused
conditional jump.

The new rs_machine_dependent frags aren't inserted if the previous item
is a prefix or a constant directive, which may be used to hardcode an
instruction, since there is no clear instruction boundary.  Segment
prefixes and NOP padding are disabled before relaxable TLS relocations
and tls_get_addr calls to keep TLS instruction sequence unchanged.

md_estimate_size_before_relax() and i386_generic_table_relax_frag() are
used to handled BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags.
i386_generic_table_relax_frag() grows or shrinks sizes of segment prefix
and NOP to align the next branch frag:

1. First try to add segment prefixes to instructions before a branch.
2. If there is no sufficient room to add segment prefixes, NOP will be
inserted before a branch.

	* config/tc-i386.c (_i386_insn): Add has_gotpc_tls_reloc.
	(tls_get_addr): New.
	(last_insn): New.
	(align_branch_power): New.
	(align_branch_kind): New.
	(align_branch_bit): New.
	(align_branch): New.
	(MAX_FUSED_JCC_PADDING_SIZE): New.
	(align_branch_prefix_size): New.
	(BRANCH_PADDING): New.
	(BRANCH_PREFIX): New.
	(FUSED_JCC_PADDING): New.
	(i386_generate_nops): Support BRANCH_PADDING and FUSED_JCC_PADDING.
	(md_begin): Abort if align_branch_prefix_size <
	MAX_FUSED_JCC_PADDING_SIZE.
	(md_assemble): Set last_insn.
	(maybe_fused_with_jcc_p): New.
	(add_fused_jcc_padding_frag_p): New.
	(add_branch_prefix_frag_p): New.
	(add_branch_padding_frag_p): New.
	(output_insn): Generate a BRANCH_PADDING, FUSED_JCC_PADDING or
	BRANCH_PREFIX frag and terminate each frag to align branches.
	(output_disp): Set i.has_gotpc_tls_reloc to TRUE for GOTPC and
	relaxable TLS relocations.
	(output_imm): Likewise.
	(i386_next_non_empty_frag): New.
	(i386_next_jcc_frag): New.
	(i386_classify_machine_dependent_frag): New.
	(i386_branch_padding_size): New.
	(i386_generic_table_relax_frag): New.
	(md_estimate_size_before_relax): Handle COND_JUMP_PADDING,
	FUSED_JCC_PADDING and COND_JUMP_PREFIX frags.
	(md_convert_frag): Handle BRANCH_PADDING, BRANCH_PREFIX and
	FUSED_JCC_PADDING frags.
	(OPTION_MALIGN_BRANCH_BOUNDARY): New.
	(OPTION_MALIGN_BRANCH_PREFIX_SIZE): New.
	(OPTION_MALIGN_BRANCH): New.
	(md_longopts): Add -malign-branch-boundary=,
	-malign-branch-prefix-size= and -malign-branch=.
	(md_parse_option): Handle -malign-branch-boundary=,
	-malign-branch-prefix-size= and -malign-branch=.
	(md_show_usage): Display -malign-branch-boundary=,
	-malign-branch-prefix-size= and -malign-branch=.
	(i386_target_format): Set tls_get_addr.
	(i386_cons_align): New.
	* config/tc-i386.h (i386_cons_align): New.
	(md_cons_align): New.
	(i386_generic_table_relax_frag): New.
	(md_generic_table_relax_frag): New.
	(i386_tc_frag_data): Add u, padding_address, length,
	max_prefix_length, prefix_length, default_prefix, cmp_size,
	classified and branch_type.
	(TC_FRAG_INIT): Initialize u, padding_address, length,
	max_prefix_length, prefix_length, default_prefix, cmp_size,
	classified and branch_type.
	* doc/c-i386.texi: Document -malign-branch-boundary=,
	-malign-branch= and -malign-branch-prefix-size=.
2019-12-12 12:03:45 -08:00
H.J. Lu
b65d68b8d6 gas: Add md_generic_table_relax_frag
Add md_generic_table_relax_frag for TC_GENERIC_RELAX_TABLE targets so
that a backend can extend relax_frag beyond TC_GENERIC_RELAX_TABLE.

	* write.c (md_generic_table_relax_frag): New.  Defined to
	relax_frag if not defined.
	(relax_segment): Call md_generic_table_relax_frag instead of
	relax_frag.
2019-12-12 12:03:45 -08:00
Andrew Burgess
66f8b2cbbb gas: Add --gdwarf-cie-version command line flag
Add a flag to control the version of CIE that is generated.  By
default gas produces CIE version 1, and this continues to be the
default after this patch.

However, a user can now provide --gdwarf-cie-version=NUMBER to switch
to either version 3 or version 4 of CIE, version 2 was never released,
and so causes an error as does any number less than 1 or greater than
4.

Producing version 4 CIE requires two new fields to be added to the
CIE, an address size field, and an segment selector field.  For a flat
address space the DWARF specification indicates that the segment
selector should be 0, and the address size fields just contains the
address size in bytes.  For now we support 4 or 8 byte addresses, and
the segment selector is always produced as 0.  At some future time we
might need to allow targets to override this.

gas/ChangeLog:

	* as.c (parse_args): Parse --gdwarf-cie-version option.
	(flag_dwarf_cie_version): New variable.
	* as.h (flag_dwarf_cie_version): Declare.
	* dw2gencfi.c (output_cie): Switch from DW_CIE_VERSION to
	flag_dwarf_cie_version.
	* doc/as.texi (Overview): Document --gdwarf-cie-version.
	* NEWS: Likewise.
	* testsuite/gas/cfi/cfi.exp: Add new tests.
	* testsuite/gas/cfi/cie-version-0.d: New file.
	* testsuite/gas/cfi/cie-version-1.d: New file.
	* testsuite/gas/cfi/cie-version-2.d: New file.
	* testsuite/gas/cfi/cie-version-3.d: New file.
	* testsuite/gas/cfi/cie-version-4.d: New file.
	* testsuite/gas/cfi/cie-version.s: New file.

include/ChangeLog:

	* dwarf2.h (DW_CIE_VERSION): Delete.

Change-Id: I9de19461aeb8332b5a57bbfe802953d0725a7ae8
2019-11-18 10:30:21 +00:00
Matthew Malcomson
616ce08e1c [Patch][binutils][arm] Armv8.6-A Matrix Multiply extension [9/10]
Hi,

This patch is part of a series that adds support for Armv8.6-A
(Matrix Multiply and BFloat16 extensions) to binutils.

This patch introduces the Matrix Multiply (Int8, F32, F64) extensions
to the arm backend.

The following Matrix Multiply instructions are added: vummla, vsmmla,
vusmmla, vusdot, vsudot[1].

[1]https://developer.arm.com/docs/ddi0597/latest/simd-and-floating-point-instructions-alphabetic-order

Committed on behalf of Mihail Ionescu.

gas/ChangeLog:

2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>

	* config/tc-arm.c (arm_ext_i8mm): New feature set.
	(do_vusdot): New.
	(do_vsudot): New.
	(do_vsmmla): New.
	(do_vummla): New.
	(insns): Add vsmmla, vummla, vusmmla, vusdot, vsudot mnemonics.
	(armv86a_ext_table): Add i8mm extension.
	(arm_extensions): Move bf16 extension to context sensitive table.
	(armv82a_ext_table, armv84a_ext_table, armv85a_ext_table):
	Move bf16 extension to context sensitive table.
	(armv86a_ext_table): Add i8mm extension.
	* doc/c-arm.texi: Document i8mm extension.
	* testsuite/gas/arm/i8mm.s: New test.
	* testsuite/gas/arm/i8mm.d: New test.
	* testsuite/gas/arm/bfloat17-cmdline-bad-3.d: Update test.

include/ChangeLog:

2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>

	* opcode/arm.h (ARM_EXT2_I8MM): New feature macro.

opcodes/ChangeLog:

2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>

	* arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.

Regression tested on arm-none-eabi.
Is this ok for trunk?

Regards,
Mihail
2019-11-07 17:20:08 +00:00
Matthew Malcomson
8382113fdb [binutils][aarch64] Matrix Multiply extension enablement [8/X]
Hi,

This patch is part of a series that adds support for Armv8.6-A
(Matrix Multiply and BFloat16 extensions) to binutils.

This patch introduces the Matrix Multiply (Int8, F32, F64) extensions
to the aarch64 backend.

The following instructions are added: {s/u}mmla, usmmla, {us/su}dot,
fmmla, ld1rob, ld1roh, d1row, ld1rod, uzip{1/2}, trn{1/2}.

Committed on behalf of Mihail Ionescu.

gas/ChangeLog:

2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>

	* config/tc-aarch64.c: Add new arch fetures to suppport the mm extension.
	(parse_operands): Add new operand.
	* testsuite/gas/aarch64/i8mm.s: New test.
	* testsuite/gas/aarch64/i8mm.d: New test.
	* testsuite/gas/aarch64/f32mm.s: New test.
	* testsuite/gas/aarch64/f32mm.d: New test.
	* testsuite/gas/aarch64/f64mm.s: New test.
	* testsuite/gas/aarch64/f64mm.d: New test.
	* testsuite/gas/aarch64/sve-movprfx-mm.s: New test.
	* testsuite/gas/aarch64/sve-movprfx-mm.d: New test.

include/ChangeLog:

2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>

	* opcode/aarch64.h (AARCH64_FEATURE_I8MM): New.
	(AARCH64_FEATURE_F32MM): New.
	(AARCH64_FEATURE_F64MM): New.
	(AARCH64_OPND_SVE_ADDR_RI_S4x32): New.
	(enum aarch64_insn_class): Add new instruction class "aarch64_misc" for
	instructions that do not require special handling.

opcodes/ChangeLog:

2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>

	* aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
	aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
	aarch64_feature_f64mm): New feature sets.
	(INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
	F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
	instructions.
	(I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
	macros.
	(QL_MMLA64, OP_SVE_SBB): New qualifiers.
	(OP_SVE_QQQ): New qualifier.
	(INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
	F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
	the movprfx constraint.
	(aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
	(aarch64_opcode_table): Define new instructions smmla,
	ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod
	uzip{1/2}, trn{1/2}.
	* aarch64-opc.c (operand_general_constraint_met_p): Handle
	AARCH64_OPND_SVE_ADDR_RI_S4x32.
	(aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
	* aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
	Account for new instructions.
	* opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
	S4x32 operand.
	* aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.

Regression tested on arm-none-eabi.

Is it ok for trunk?

Regards,
Mihail
2019-11-07 17:11:52 +00:00
Matthew Malcomson
aab2c27d9f [binutils][arm] BFloat16 enablement [4/X]
Hi,

This patch is part of a series that adds support for Armv8.6-A
(Matrix Multiply and BFloat16 extensions) to binutils.

This patch introduces BFloat16 instructions to the arm backend.
The following BFloat16 instructions are added: vdot, vfma{l/t},
vmmla, vfmal{t/b}, vcvt, vcvt{t/b}.

gas/ChangeLog:

2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>

	* config/tc-arm.c (arm_archs): Add armv8.6-a option.
	(cpu_arch_ver): Add TAG_CPU_ARCH_V8 tag for Armv8.6-a.
	* doc/c-arm.texi (-march): New armv8.6-a arch.
	* config/tc-arm.c (arm_ext_bf16): New feature set.
	(enum neon_el_type): Add NT_bfloat value.
	(B_MNEM_vfmat, B_MNEM_vfmab): New bfloat16 encoder
	helpers.
	(BAD_BF16): New message.
	(parse_neon_type): Add bf16 type specifier.
	(enum neon_type_mask): Add N_BF16 type.
	(type_chk_of_el_type): Account for NT_bfloat.
	(el_type_of_type_chk): Account for N_BF16.
	(neon_three_args): Split out from neon_three_same.
	(neon_three_same): Part split out into neon_three_args.
	(CVT_FLAVOUR_VAR): Add bf16_f32 cvt flavour.
	(do_neon_cvt_1): Account for vcvt.bf16.f32.
	(do_bfloat_vmla): New.
	(do_mve_vfma): New function to deal with the mnemonic clash between the BF16
	vfmat and the MVE vfma in a VPT block with a 't'rue condition.
	(do_neon_cvttb_1): Account for vcvt{t,b}.bf16.f32.
	(do_vdot): New
	(do_vmmla): New
	(insns): Add vdot and vmmla mnemonics.
	(arm_extensions): Add "bf16" extension.
	* doc/c-arm.texi: Document "bf16" extension.
	* testsuite/gas/arm/attr-march-armv8_6-a.d: New test.
	* testsuite/gas/arm/bfloat16-bad.d: New test.
	* testsuite/gas/arm/bfloat16-bad.l: New test.
	* testsuite/gas/arm/bfloat16-bad.s: New test.
	* testsuite/gas/arm/bfloat16-cmdline-bad-2.d: New test.
	* testsuite/gas/arm/bfloat16-cmdline-bad-3.d: New test.
	* testsuite/gas/arm/bfloat16-cmdline-bad.d: New test.
	* testsuite/gas/arm/bfloat16-neon.s: New test.
	* testsuite/gas/arm/bfloat16-non-neon.s: New test.
	* testsuite/gas/arm/bfloat16-thumb-bad.d: New test.
	* testsuite/gas/arm/bfloat16-thumb-bad.l: New test.
	* testsuite/gas/arm/bfloat16-thumb.d: New test.
	* testsuite/gas/arm/bfloat16-vfp.d: New test.
	* testsuite/gas/arm/bfloat16.d: New test.
	* testsuite/gas/arm/bfloat16.s: New test.

include/ChangeLog:

2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>

	* opcode/arm.h (ARM_EXT2_V8_6A, ARM_AEXT2_V8_6A,
	ARM_ARCH_V8_6A): New.
	* opcode/arm.h (ARM_EXT2_BF16): New feature macro.
	(ARM_AEXT2_V8_6A): Include above macro in definition.

opcodes/ChangeLog:

2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>

	* arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
	Armv8.6-A.
	(coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
	(neon_opcodes): Add bfloat SIMD instructions.
	(print_insn_coprocessor): Add new control character %b to print
	condition code without checking cp_num.
	(print_insn_neon): Account for BFloat16 instructions that have no
	special top-byte handling.

Regression tested on arm-none-eabi.

Is it ok for trunk?

Regards,
Mihail
2019-11-07 16:56:12 +00:00
Matthew Malcomson
df6780137d [binutils][aarch64] Bfloat16 enablement [2/X]
Hi,

This patch is part of a series that adds support for Armv8.6-A
(Matrix Multiply and BFloat16 extensions) to binutils.

This patch introduces the following BFloat16 instructions to the
aarch64 backend: bfdot, bfmmla, bfcvt, bfcvtnt, bfmlal[t/b],
bfcvtn2.

Committed on behalf of Mihail Ionescu.

gas/ChangeLog:

2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>

	* config/tc-aarch64.c (vectype_to_qualifier): Special case the
	S_2H operand qualifier.
	* doc/c-aarch64.texi: Document bf16 and bf16mmla4 extensions.
	* testsuite/gas/aarch64/bfloat16.d: New test.
	* testsuite/gas/aarch64/bfloat16.s: New test.
	* testsuite/gas/aarch64/illegal-bfloat16.d: New test.
	* testsuite/gas/aarch64/illegal-bfloat16.l: New test.
	* testsuite/gas/aarch64/illegal-bfloat16.s: New test.
	* testsuite/gas/aarch64/sve-bfloat-movprfx.s: New test.
	* testsuite/gas/aarch64/sve-bfloat-movprfx.d: New test.

include/ChangeLog:

2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>

	* opcode/aarch64.h (AARCH64_FEATURE_BFLOAT16): New feature macros.
	(AARCH64_ARCH_V8_6): Include BFloat16 feature macros.
	(enum aarch64_opnd_qualifier): Introduce new operand qualifier
	AARCH64_OPND_QLF_S_2H.
	(enum aarch64_insn_class): Introduce new class "bfloat16".
	(BFLOAT16_SVE_INSNC): New feature set for bfloat16
	instructions to support the movprfx constraint.

opcodes/ChangeLog:

2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>

	* aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
	in reglane special case.
	* aarch64-dis-2.c (aarch64_opcode_lookup_1,
	aarch64_find_next_opcode): Account for new instructions.
	* aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
	in reglane special case.
	* aarch64-opc.c (struct operand_qualifier_data): Add data for
	new AARCH64_OPND_QLF_S_2H qualifier.
	* aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
	QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
	(aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve,
	aarch64_feature_bfloat16_bfmmla4): New feature sets.
	(BFLOAT_SVE, BFLOAT): New feature set macros.
	(BFLOAT_SVE_INSN, BFLOAT_BFMMLA4_INSN, BFLOAT_INSN): New macros
	to define BFloat16 instructions.
	(aarch64_opcode_table): Define new instructions bfdot,
	bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
	bfcvtn2, bfcvt.

Regression tested on aarch64-elf.

Is it ok for trunk?

Regards,
Mihail
2019-11-07 16:42:36 +00:00
Matthew Malcomson
8ae2d3d9ea [gas][aarch64] Armv8.6-a option [1/X]
Hi,

This patch is part of a series that adds support for Armv8.6-A
to binutils.
This first patch adds the Armv8.6-A flag to binutils.
No instructions are behind it at the moment.

Commited on behalf of Mihail Ionescu.

gas/ChangeLog:

2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>

	* config/tc-aarch64.c (armv8.6-a): New arch.
	* doc/c-aarch64.texi (armv8.6-a): Document new arch.

include/ChangeLog:

2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>

	* opcode/aarch64.h (AARCH64_FEATURE_V8_6): New.
	(AARCH64_ARCH_V8_6): New.

opcodes/ChangeLog:

2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>

	* aarch64-tbl.h (ARMV8_6): New macro.

Is it ok for trunk?

Regards,
Mihail
2019-11-07 16:21:17 +00:00
Jan Beulich
142861dfd5 x86: support further AMD Zen2 instructions
Both RDPRU and MCOMMIT have been publicly documented meanwhile:
https://www.amd.com/system/files/TechDocs/24594.pdf.
2019-11-07 09:29:14 +01:00
Andreas Krebbel
46e292ab0a S/390: Add support for z15 as CPU name.
So far z15 was identified as arch13. After the machine has been
announced we can now add the real name.

gas/ChangeLog:

2019-10-08  Andreas Krebbel  <krebbel@linux.ibm.com>

	* config/tc-s390.c (s390_parse_cpu): Add z15 as alternate CPU
	name.
	* doc/as.texi: Add z15 to CPU string list.
	* doc/c-s390.texi: Likewise.

opcodes/ChangeLog:

2019-10-08  Andreas Krebbel  <krebbel@linux.ibm.com>

	* s390-mkopc.c (main): Enable z15 as CPU string in the opcode
	table.
2019-10-08 11:24:29 +02:00
Jozef Lawrynowicz
c0ea7c52e1 Add support for new functionality in the msp430 backend of GCC.
This functionality will generate a new GNU object attribute for the "data region"
has been added. This object attribute is used
mark whether the compiler has generated code assuming that data could be in the
upper or lower memory regions.

Code which assumes data is always in the lower memory region is incompatible
with code which uses the full memory range for data.

The patch also adds a new assembler directive ".mspabi_attribute" to handle the
existing MSPABI object attributes. GCC will now emit both .gnu_attribute and
.mspabi_attribute directives to indicate what options the source file was
compiled with.

The assembler will now check the values set in these directives against the
options that the it has been invoked with. If there is a discrepancy, the
assembler will exit with an error.

bfd	* elf32-msp430.c (elf32_msp430_merge_mspabi_attributes): Rename to..
	(elf32_msp430_merge_msp430_attributes): Add support for merging the GNU
	object attribute for data region.

binutils* readelf.c (display_msp430_gnu_attribute): New.
	(process_arch_specific): Use msp430 specific handler for GNU
	attributes.

gas	* config/tc-msp430.c (md_parse_option): Set lower_data_region_only to
	FALSE if the data region is set to "upper", "either" or "none".
	(msp430_object_attribute): New.
	(md_pseudo_table): Handle .mspabi_attribute and .gnu_attribute.
	(msp430_md_end): Replace hard-coded attribute values with enums.
	Handle data region object attribute.
	* doc/as.texi: Document MSP430 Data Region object attribute.
	* doc/c-msp430.texi: Document the .mspabi_attribute directive.
	* testsuite/gas/msp430/attr-430-small-bad.d: New test.
	* testsuite/gas/msp430/attr-430-small-bad.l: New test.
	* testsuite/gas/msp430/attr-430-small-good.d: New test.
	* testsuite/gas/msp430/attr-430-small.s: New test.
	* testsuite/gas/msp430/attr-430x-large-any-bad.d: New test.
	* testsuite/gas/msp430/attr-430x-large-any-bad.l: New test.
	* testsuite/gas/msp430/attr-430x-large-any-good.d: New test.
	* testsuite/gas/msp430/attr-430x-large-any.s: New test.
	* testsuite/gas/msp430/attr-430x-large-lower-bad.d: New test.
	* testsuite/gas/msp430/attr-430x-large-lower-bad.l: New test.
	* testsuite/gas/msp430/attr-430x-large-lower-good.d: New test.
	* testsuite/gas/msp430/attr-430x-large-lower.s: New test.
	* testsuite/gas/msp430/msp430.exp: Run new tests.

include	* elf/msp430.h: Add enums for MSPABI and GNU object attribute tag names
	and values.

ld	* testsuite/ld-msp430-elf/attr-gnu-main.s: New test.
	* testsuite/ld-msp430-elf/attr-gnu-obj.s: New test.
	* testsuite/ld-msp430-elf/attr-gnu-region-lower-upper.d: New test.
	* testsuite/ld-msp430-elf/attr-gnu-region-lower.d: New test.
	* testsuite/ld-msp430-elf/attr-gnu-region-upper.d: New test.
	* testsuite/ld-msp430-elf/msp430-elf.exp: Run new tests.
2019-10-07 16:34:31 +01:00
Simon Marchi
e0b2a78c83 Re-generate many configure and Makefile.in files
I get some spurious changes when running autoconf/automake for various
projects in the tree.  This is likely because they were generated using
distro-patched tools last time.

I ran `autoreconf -f` in the various automake projects of the
binutils-gdb tree, and this is the result.  The tools I am using have
been compiled from source, from the upstream release.

bfd/ChangeLog:

	* Makefile.in: Re-generate.
	* configure: Re-generate.
	* doc/Makefile.in: Re-generate.

binutils/ChangeLog:

	* Makefile.in: Re-generate.
	* configure: Re-generate.
	* doc/Makefile.in: Re-generate.

gas/ChangeLog:

	* Makefile.in: Re-generate.
	* configure: Re-generate.
	* doc/Makefile.in: Re-generate.

gold/ChangeLog:

	* testsuite/Makefile.in: Re-generate.

gprof/ChangeLog:

	* Makefile.in: Re-generate.
	* configure: Re-generate.

ld/ChangeLog:

	* Makefile.in: Re-generate.
	* configure: Re-generate.

opcodes/ChangeLog:

	* Makefile.in: Re-generate.
	* configure: Re-generate.
2019-09-18 09:09:15 -04:00
Phil Blundell
bb6959602b Update version to 2.33.50 and regenerate configure scripts. 2019-09-16 11:03:53 +01:00
Dennis Zhang
0535e5d74d Arm: Add support for missing CPUs
This patch adds support for following CPUs:
Cortex-M35P, Cortex-A77, Cortex-A76AE.

Related specifications can be found at https://developer.arm.com/ip-products/processors.

gas/ChangeLog:

	* config/tc-arm.c: New entries for Cortex-M35P, Cortex-A77,
	and Cortex-A76AE.
	* doc/c-arm.texi: Document new processors.
	* testsuite/gas/arm/cpu-cortex-a76ae.d: New test.
	* testsuite/gas/arm/cpu-cortex-a77.d: New test.
	* testsuite/gas/arm/cpu-cortex-m35p.d: New test.

bfd/ChangeLog:

	* cpu-arm.c: New entries for Cortex-M35P, Cortex-A77, Cortex-A76AE.
2019-08-22 15:35:43 +01:00
Barnaby Wilks
b20d385926 Implement a float16 directive for assembling 16 bit IEEE 754 floating point numbers for the AArch64 assembler.
The syntax of the directive is:

     .float16 <0-n decimal numbers>
e.g.
     .float16 0.5
     .float16 10.2, NaN, 452.09

The floats will always be encoded using the binary16 format as described in the
IEEE 754-2008 standard. There is no need to support Arm's alternative half-precision
format since AArch64 only supports the IEEE format.

gas	* config/tc-aarch64.c: Add float16 directive and add "Hh" to
	acceptable float characters.
	* doc/c-aarch64.texi: Documentation for float16 directive.
	* testsuite/gas/aarch64/float16-be.d: New test.
	* testsuite/gas/aarch64/float16-le.d: New test.
	* testsuite/gas/aarch64/float16.s: New test.
	* NEWS: Add NEWS entry.
2019-08-22 11:13:23 +01:00
Dennis Zhang
546053acfa Adds support for following CPUs to the ARM and Aarch64 assemblers: Cortex-A77, Cortex-A76AE, Cortex-A34, Cortex-A65, and Cortex-A65AE.
Related specifications can be found at
https://developer.arm.com/ip-products/processors.

gas	* NEWS: Mention the Arm and AArch64 new processors.
	* config/tc-aarch64.c: New entries for Cortex-A34, Cortex-A65,
	Cortex-A77, cortex-A65AE, and Cortex-A76AE.
	* doc/c-aarch64.texi: Document new CPUs.
	* testsuite/gas/aarch64/cpu-cortex-a34.d: New test.
	* testsuite/gas/aarch64/cpu-cortex-a65.d: New test.
	* testsuite/gas/aarch64/cpu-cortex-a65ae.d: New test.
	* testsuite/gas/aarch64/cpu-cortex-a76ae.d: New test.
	* testsuite/gas/aarch64/cpu-cortex-a77.d: New test.
	* testsuite/gas/aarch64/nop-asm.s: New test.

bfd	* cpu-aarch64.c: New entries for Cortex-A34, Cortex-A65,
	 Cortex-A77, cortex-A65AE, and Cortex-A76AE.
2019-08-20 17:13:29 +01:00
Barnaby Wilks
5312fe52e9 Add generic and ARM specific support for half-precision IEEE 754 floating point numbers to the assembler.
Half precision floating point numbers will be encoded using the IEEE 754
half precision floating point format - 16 bits in total, 1 for sign, 5
for exponent and 10 bits of  mantissa.

This patch implements the float16 directive for both the IEEE 754 format
and the Arm alternative format for the Arm backend.

The syntax of the directive is:

  .float16 <0-n decimal numbers>
e.g.
  .float16 12.0
  .float16 0.23, 433.1, 0.06

The Arm alternative format is almost identical to the IEEE 754 format,
except that it doesn't encode for NaNs or Infinity (instead an exponent
of 0x1F represents a normalized number in the range 65536 to 131008).

The alternative format is documented in the reference manual:

  https://static.docs.arm.com/ddi0487/db/DDI0487D_b_armv8_arm.pdf?_ga=2.72318806.49764181.1561632697-999473562.1560847439

Which format is used is controlled by the .float16_format <format>
directive, where if <format> = ieee, then use the IEEE 754
half-precision format else if <format> = alternative, then use the
Arm alternative format

Or the format can be set on the command line via the -mfp16-format
option that has a similar syntax.  -mfp16-format=<ieee|alternative>.
This also fixes the format and it cannot be changed by any directives.

Once the format has been set (either by the command line option or a directive) it cannot be changed,
and any attempts to change it (i.e. with the float16_format directive) will result in a warning and the
line being ignored.

For ELF targets the appropriate EABI attribute will be written out at the end of assembling
if the format has been explicitly specified. If no format has been explicitly specified then no
EABI attributes will be written.

If the format is not explicitly specified then any float16 directives are encoding using the IEEE 754-2008
format by default until the format is fixed or changed with the float16_format directive.

gas	* config/tc-arm.c (enum fp_16bit_format): Add enum to represent the 2 float16 encodings.
	(md_atof): Set precision for float16 type.
	(arm_is_largest_exponent_ok): Check for whether to encode with the IEEE or alternative
	format.
	(set_fp16_format): Parse a float16_format directive.
	(arm_parse_fp16_opt): Parse the fp16-format command line option.
	(aeabi_set_public_attributes): For ELF encode the FP16 format EABI attribute.
	* config/tc-arm.h (TC_LARGEST_EXPONENT_IS_NORMAL): Macro that expands to
	arm_is_largest_exponent_ok.
	(arm_is_largest_exponent_ok): Add prototype for arm_is_largest_exponent_ok function.
	* doc/c-arm.texi: Add documentation for .float16, .float16_format and -mfp16-format=
	* testsuite/gas/arm/float16-bad.d: New test.
	* testsuite/gas/arm/float16-bad.l: New test.
	* testsuite/gas/arm/float16-bad.s: New test.
	* testsuite/gas/arm/float16-be.d: New test.
	* testsuite/gas/arm/float16-format-bad.d: New test.
	* testsuite/gas/arm/float16-format-bad.l: New test.
	* testsuite/gas/arm/float16-format-bad.s: New test.
	* testsuite/gas/arm/float16-format-opt-bad.d: New test.
	* testsuite/gas/arm/float16-format-opt-bad.l: New test.
	* testsuite/gas/arm/float16-le.d: New test.
	* testsuite/gas/arm/float16.s: New test.
	* testsuite/gas/arm/float16-eabi-alternative-format.d: New test.
	* testsuite/gas/arm/float16-eabi-ieee-format.d: New test.
	* testsuite/gas/arm/float16-eabi-no-format.d: New test.
	* testsuite/gas/arm/float16-eabi.s: New test.

	* config/atof-ieee.c (H_PRECISION): Macro for precision of float16
	type.
	(atof_ieee): Set precision and exponent bits for encoding float16
	types.
	(gen_to_words): NaN and Infinity encoding for float16.
	(ieee_md_atof): Set precision for encoding float16 type.
2019-08-12 11:08:36 +01:00
Richard Sandiford
ccbdd22fb9 [AArch64] Rename +bitperm to +sve2-bitperm
After some discussion, we've decided to rename the +bitperm feature
flag to +sve2-bitperm, so that it's consistent with the other SVE2
feature flags.  The associated internal macros already used
"SVE2_BITPERM", so only the feature flag itself needs to change.

2019-07-19  Richard Sandiford  <richard.sandiford@arm.com>

gas/
	* doc/c-aarch64.texi: Remame the +bitperm extension to +sve2-bitperm.
	* config/tc-aarch64.c (aarch64_features): Likewise.
	* testsuite/gas/aarch64/illegal-sve2-aes.d: Update accordingly.
	* testsuite/gas/aarch64/illegal-sve2-sha3.d: Likewise.
	* testsuite/gas/aarch64/illegal-sve2-sm4.d: Likewise.
	* testsuite/gas/aarch64/illegal-sve2.d: Likewise.
	* testsuite/gas/aarch64/sve2.d: Likewise.
2019-07-19 12:18:02 +01:00
Jose E. Marchesi
e0b989a6d7 gas: support .half, .word and .dword directives in eBPF
This little patch adds support to the eBPF port of GAS for a few data
directives.  The names for the directives have been chosen to be
coherent with the suffixes used in eBPF instructions: b, h, w and dw
for 8, 16, 32 and 64-bit values respectively.

Documentation and tests included.
Tested in a x86_64 host.

gas/ChangeLog:

2019-07-17  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* config/tc-bpf.c (md_pseudo_table): .half, .word and .dword.
	* testsuite/gas/bpf/data.s: New file.
	* testsuite/gas/bpf/data.d: Likewise.
	* testsuite/gas/bpf/data-be.d: Likewise.
	* testsuite/gas/bpf/bpf.exp: Run data and data-be.
	* doc/c-bpf.texi (BPF Directives): New section.
2019-07-17 22:57:23 +02:00
Jose E. Marchesi
3719fd55b6 cpu,opcodes,gas: fix explicit arguments to eBPF ldabs instructions
This patch fixes the eBPF CPU description in order to reflect the
right explicit arguments passed to the ldabs{b,h,w,dw} instructions,
updates the corresponding GAS tests, and updates the BPF section of
the GAS manual.

cpu/ChangeLog:

2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf.cpu (dlabs): New pmacro.
	(dlind): Likewise.

opcodes/ChangeLog:

2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf-desc.c: Regenerate.
	* bpf-opc.c: Likewise.
	* bpf-opc.h: Likewise.

gas/ChangeLog:

2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* testsuite/gas/bpf/mem.s: ldabs instructions do not take a `src'
	register as an argument.
	* testsuite/gas/bpf/mem.d: Updated accordingly.
	* testsuite/gas/bpf/mem-be.d: Likewise.
	* doc/c-bpf.texi (BPF Opcodes): Update to reflect the correct
	explicit arguments to ldabs and ldind instructions.
2019-07-15 16:00:28 +02:00