Changes the result of ld expressions that were previously plain
numbers to be an absolute address, in the same circumstances where
numbers are treated as absolute addresses.
* ld.texinfo (Expression Section): Update result of arithmetic
expressions.
* ldexp.c (arith_result_section): New function.
(fold_binary): Use it.
Commit b751e639 regressed arm linux kernel builds, that have an
ASSERT (((__hyp_idmap_text_end - (__hyp_idmap_text_start
& ~ (((0x1 << 0xc) - 0x1))))
<= (0x1 << 0xc)), HYP init code too big or misaligned)
Due to some insanity in ld expression evaluation, the integer values
0x1 and 0xc above are treated as absolute addresses (ie. they have an
associated section, *ABS*, see exp_fold_tree_1 case etree_value) while
the expression (0x1 << 0xc) has a plain number result. The left hand
side of the inequality happens to evaluate to a "negative" .text
section relative value. Comparing a section relative value against an
absolute value works since the section relative value is first
converted to absolute. Comparing a section relative value against a
number just compares the offsets, which fails since the "negative"
offset is really a very large positive number.
This patch works around the problem by folding integer expressions, so
the assert again becomes
ASSERT (((__hyp_idmap_text_end - (__hyp_idmap_text_start
& 0xfffffffffffff000))
<= 0x1000), HYP init code too big or misaligned)
* ldexp.c (exp_value_fold): New function.
(exp_unop, exp_binop, exp_trinop): Use it.
This should mean the 2010-10-28 change for ld -r --gc-sections can
be reverted.
* scripttempl/v850.sc: Don't reference __ctbp, __ep, __gp when
not relocating.
* scripttempl/v850_rh850.sc: Likewise.
* ldmain.c (default_bfd_error_handler): New function pointer.
(ld_bfd_error_handler): New function.
(main): Arrange to call it on bfd errors/warnings.
(ld_bfd_assert_handler): Enable tail call.
It was like printf, which means you can't use bfd_set_error_handler to
hook in a function to do something and then call the original handler.
The patch also deletes some unused functions and makes pointers local.
bfd/
* bfd-in.h: Include stdarg.h.
* bfd.c (bfd_error_handler_type): Make like vprintf.
(_bfd_error_internal): Rename from _bfd_error_handler. Make static.
(error_handler_internal): New function, split out from..
(_bfd_default_error_handler): ..here. Rename to _bfd_error_handler.
(bfd_set_error_handler): Update.
(bfd_get_error_handler, bfd_get_assert_handler): Delete.
(_bfd_assert_handler): Make static.
* coffgen.c (null_error_handler): Update params.
* elf-bfd.h (struct elf_backend_data <link_order_error_handler>):
Don't use bfd_error_handler_type.
* elf64-mmix.c (mmix_dump_bpo_gregs): Likewise.
* elfxx-target.h (elf_backend_link_order_error_handler): Default
to _bfd_error_handler.
* libbfd-in.h (_bfd_default_error_handler): Don't declare.
(bfd_assert_handler_type): Likewise.
(_bfd_error_handler): Update.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
ld/
* ldlang.c (ignore_bfd_errors): Update params.
SEC_EXCLUDE is ignored when doing a relocatable link. But we can't
merge 2 input sections with the same name when only one of them has
SHF_EXCLUDE.
PR ld/20528
* emultempl/elf32.em (gld${EMULATION_NAME}_place_orphan): Don't
merge 2 sections with different SHF_EXCLUDE.
* testsuite/ld-elf/pr20528a.d: New file.
* testsuite/ld-elf/pr20528a.s: Likewise.
* testsuite/ld-elf/pr20528b.d: Likewise.
* testsuite/ld-elf/pr20528b.s: Likewise.
2016-09-28 Christophe Lyon <christophe.lyon@linaro.org>
PR ld/20608
bfd/
* elf32-arm.c (arm_type_of_stub): Handle the case when the pre-PLT
Thumb-ARM stub is too far.
ld
* testsuite/ld-arm/arm-elf.exp: Handle new testcase.
* testsuite/ld-arm/farcall-mixed-app2.d: New file.
* testsuite/ld-arm/farcall-mixed-app2.r: Likewise.
* testsuite/ld-arm/farcall-mixed-app2.s: Likewise.
* testsuite/ld-arm/farcall-mixed-app2.sym: Likewise.
This patch extends Tag_GNU_Power_ABI_FP to cover long double ABIs,
makes the assembler warn about undefined tag values, and removes
similar warnings from the linker. I think it is better to not
warn in the linker about undefined tag values as future extensions to
the tags then won't result in likely bogus warnings. This is
consistent with the fact that an older linker won't warn on an
entirely new tag.
include/
* elf/ppc.h (Tag_GNU_Power_ABI_FP): Comment.
bfd/
* elf-bfd.h (_bfd_elf_ppc_merge_fp_attributes): Declare.
* elf32-ppc.c (_bfd_elf_ppc_merge_fp_attributes): New function.
(ppc_elf_merge_obj_attributes): Use it. Don't copy first file
attributes, merge them. Don't warn about undefined tag bits,
or copy unknown values to output.
* elf64-ppc.c (ppc64_elf_merge_private_bfd_data): Call
_bfd_elf_ppc_merge_fp_attributes.
binutils/
* readelf.c (display_power_gnu_attribute): Catch truncated section
for all powerpc attributes. Display long double ABI. Don't
capitalize words, except for names. Show known bits of tag values
when some unknown bits are present. Whitespace fixes.
gas/
* config/tc-ppc.c (ppc_elf_gnu_attribute): New function.
(md_pseudo_table <ELF>): Handle "gnu_attribute".
ld/
* testsuite/ld-powerpc/attr-gnu-4-4.s: Delete.
* testsuite/ld-powerpc/attr-gnu-4-14.d: Delete.
* testsuite/ld-powerpc/attr-gnu-4-24.d: Delete.
* testsuite/ld-powerpc/attr-gnu-4-34.d: Delete.
* testsuite/ld-powerpc/attr-gnu-4-41.d: Delete.
* testsuite/ld-powerpc/attr-gnu-4-32.d: Adjust expected warning.
* testsuite/ld-powerpc/attr-gnu-8-23.d: Likewise.
* testsuite/ld-powerpc/attr-gnu-4-01.d: Adjust expected output.
* testsuite/ld-powerpc/attr-gnu-4-02.d: Likewise.
* testsuite/ld-powerpc/attr-gnu-4-03.d: Likewise.
* testsuite/ld-powerpc/attr-gnu-4-10.d: Likewise.
* testsuite/ld-powerpc/attr-gnu-4-11.d: Likewise.
* testsuite/ld-powerpc/attr-gnu-4-20.d: Likewise.
* testsuite/ld-powerpc/attr-gnu-4-22.d: Likewise.
* testsuite/ld-powerpc/attr-gnu-4-33.d: Likewise.
* testsuite/ld-powerpc/attr-gnu-8-11.d: Likewise.
* testsuite/ld-powerpc/powerpc.exp: Don't run deleted tests.
PR ld/20595
ld * testsuite/ld-arm/unwind-4.d: Add -q option to linker command
line and -r option to objdump command line. Match emitted relocs
to make sure that superflous relocs are not generated.
bfd * elf-bfd.h (struct elf_backend_data): Add
elf_backend_count_output_relocs callback to count relocations in
the final output.
* elf-arm.c (elf32_arm_add_relocation): Deleted.
(elf32_arm_write_section): Move additional relocation to emit_relocs.
(elf32_arm_count_output_relocs): New function.
(emit_relocs): New function.
(elf32_arm_emit_relocs): New function.
(elf32_arm_vxworks_emit_relocs): New function.
(elf_backend_emit_relocs): Updated to use the new functions.
(elf_backend_count_output_relocs): New define.
* bfd/elflink.c (bfd_elf_final_link): Do not add additional_reloc_count
to the relocation count.
(_bfd_elf_link_size_reloc_section): Use callback to count the
relocations which will be in output.
(_bfd_elf_default_count_output_relocs): New function.
* bfd/elfxx-target.h (elf_backend_count_output_relocs): New define.
SVE defines new names for existing NZCV conditions, to reflect the
result of instructions like PTEST. This patch adds support for these
names.
The patch also adds comments to the disassembly output to show the
alternative names of a condition code. For example:
cinv x0, x1, cc
becomes:
cinv x0, x1, cc // cc = lo, ul, last
and:
b.cc f0 <...>
becomes:
b.cc f0 <...> // b.lo, b.ul, b.last
Doing this for the SVE names follows the practice recommended by the
SVE specification and is definitely useful when reading SVE code.
If the feeling is that it's too distracting elsewhere, we could add
an option to turn it off.
include/
* opcode/aarch64.h (aarch64_cond): Bump array size to 4.
opcodes/
* aarch64-dis.c (remove_dot_suffix): New function, split out from...
(print_mnemonic_name): ...here.
(print_comment): New function.
(print_aarch64_insn): Call it.
* aarch64-opc.c (aarch64_conds): Add SVE names.
(aarch64_print_operand): Print alternative condition names in
a comment.
gas/
* config/tc-aarch64.c (opcode_lookup): Search for the end of
a condition name, rather than assuming that it will have exactly
2 characters.
(parse_operands): Likewise.
* testsuite/gas/aarch64/alias.d: Add new condition-code comments
to the expected output.
* testsuite/gas/aarch64/beq_1.d: Likewise.
* testsuite/gas/aarch64/float-fp16.d: Likewise.
* testsuite/gas/aarch64/int-insns.d: Likewise.
* testsuite/gas/aarch64/no-aliases.d: Likewise.
* testsuite/gas/aarch64/programmer-friendly.d: Likewise.
* testsuite/gas/aarch64/reloc-insn.d: Likewise.
* testsuite/gas/aarch64/b_c_1.d, testsuite/gas/aarch64/b_c_1.s:
New test.
ld/
* testsuite/ld-aarch64/emit-relocs-280.d: Match branch comments.
* testsuite/ld-aarch64/weak-undefined.d: Likewise.
There was a gap in the documentation of EXCLUDE_FILE that could cause
confusion to a user. When writing an input section specifier like this:
*(EXCLUDE_FILE (somefile.o) .text .text.*)
this could mean one of the following:
1. All '.text' and '.text.*' from all files except for 'somefile.o',
or
2. All '.text' from all files except 'somefile.o', and all '.text.*'
sections from all files.
It turns out that the second interpretation is correct, but the manual
does not make this clear (to me at least). Hopefully this patch makes
things clearer.
ld/ChangeLog:
* ld/ld.texinfo (Input Section Basics): Expand the description of
EXCLUDE_FILE.
bfd/
2016-09-14 Thomas Preud'homme <thomas.preudhomme@arm.com>
* elf32-arm.c (elf32_arm_gc_mark_extra_sections): Only mark section
not already marked.
ld/
2016-09-14 Thomas Preud'homme <thomas.preudhomme@arm.com>
* testsuite/ld-arm/cmse-veneers.s: Add a test for ARMv8-M Security
Extensions entry functions in absolute section.
* testsuite/ld-arm/cmse-veneers.rd: Adapt expected output accordingly.
The assembler accepts dtpoff complex relocation expression like
identifier@dtpoff + const. However, it doesn't accept an expression such
as identifier@dtpoff@base + const. This patch solves this issue, and adds
a number of tests.
ld/
2016-09-14 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/ld-arc/tls-dtpoff.dd: New file.
* testsuite/ld-arc/tls-dtpoff.rd: Likewise.
* testsuite/ld-arc/tls-dtpoff.s: Likewise.
* testsuite/ld-arc/tls-relocs.ld: Likewise.
* testsuite/ld-arc/arc.exp: Add new tdpoff test.
gas/
2016-09-14 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/tls-relocs2.d: New file.
* testsuite/gas/arc/tls-relocs2.s: Likewise.
* config/tc-arc.c (tokenize_arguments): Accept offsets when base
is used.
PR ld/20537
* emultempl/elf32.em: More OPTION_xxx values into an enum. Add
OPTION_NO_EH_FRAME_HDR.
(_add_options): Add support for --no-eh-frame-hdr.
* ld.texinfo: Document new option.
* lexsup.c (elf_shlib_list_options): List new option.
* NEWS: Mention the new option.
We can resolve size relocation against symbol which needs copy relocation
when building executable.
bfd/
PR ld/20550
* elf64-x86-64.c (elf_x86_64_relocate_section): Resolve size
relocation with copy relocation when building executable.
ld/
PR ld/20550
* testsuite/ld-x86-64/pr20550a.s: New file.
* testsuite/ld-x86-64/pr20550b.s: Likewise.
* testsuite/ld-x86-64/x86-64.exp (x86_64tests): Add tests for
PR ld/20550.
* Makefile.am (CFLAGS_FOR_TARGET): Define as a copy of CFLAGS but
without any sanitization options.
(CXXFLAGS_FOR_TARGET): Define as a copy of CXXFLAGS but without
any sanitization options.
(check-DEJAGNU): Pass CFLAGS_FOR_TARGET and CXXFLAGS_FOR_TARGET
as CFLAGS and CXXFLAGS respectively.
Prior to the patch, addends for relocs were being adjusted even if
they went beyond an alignment boundary. This is wrong - to
preserve alignment constraints, the relaxation logic adds as many padding
bytes at the alignment boundary as was deleted, so addends beyond the
boundary should not be adjusted. avr-prop-7.s reproduces this
scenario.
Also, prior to this patch, the relaxation logic assumed that the addr
parameter pointed to the middle of the instruction to be deleted, and
that addr - count would therefore be the shrinked instruction's
address. This is true when actually shrinking instructions.
The alignment constraints handling logic also invokes the same logic
though, with addr as the starting offset of padding bytes and
with count as the number of bytes to be deleted. Calculating the
shrinked insn's address as addr - count is obviously wrong in this
case - that offset would point to count bytes before the last
non-padded byte. avr-prop-8.s reproduces this scenario.
To fix scenario 1, the patch adds an additional check to ensure reloc addends
aren't adjusted if they cross a shrink boundary. The shrink boundary
is either the section size or an alignment boundary. Addends pointing
at an alignment boundary don't need to be adjusted, as padding would
occur and keep the boundary the same. Addends pointing at section size
need to be adjusted though, as no padding occurs and the section size
itself would get decremented. The patch records whether padding
occured (did_pad) and uses that to detect and handle this condition.
To fix scenario 2, the patch adds an additional parameter
(delete_shrinks_insn) to elf32_avr_relax_delete_bytes to distinguish
instruction bytes deletion from padding bytes deletion. It then uses that to
correctly set shrinked_insn_address.
bfd/ChangeLog:
2016-09-02 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
PR ld/20545
* elf32-avr.c (elf32_avr_relax_delete_bytes): Add parameter
delete_shrinks_insn. Modify computation of shrinked_insn_address.
Compute shrink_boundary and adjust addend only if
addend_within_shrink_boundary.
(elf32_avr_relax_section): Modify calls to
elf32_avr_relax_delete_bytes to pass extra parameter.
ld/ChangeLog:
2016-09-02 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
PR ld/20545
* testsuite/ld-avr/avr-prop-7.d: New test.
* testsuite/ld-avr/avr-prop-7.s: New test.
* testsuite/ld-avr/avr-prop-8.d: New test.
* testsuite/ld-avr/avr-prop-8.s: New test.
ld/ChangeLog:
Cupertino Miranda <cmiranda@synopsys.com>
* testsuite/ld-arc/tls_gs-01.d: Set to XFAIL on arc*-*-elf*.
* testsuite/ld-arc/tls_ie-01.d: Likewise.
On i386, IFUNC function must be called via PLT. Since PLT in PIC
object uses EBX register, R_386_PLT32 relocation must be used to
call IFUNC function even when IFUNC function is defined locally.
Linker should issue an error when R_386_PC32 relocation is used
to call IFUNC function.
Since PR ld/19784 tests doesn't use PLT relocation to local IFUNC
function, they are moved to the x86-64 test directory.
bfd/
PR ld/14961
PR ld/20515
* elf32-i386.c (elf_i386_check_relocs): Issue an error when
R_386_PC32 relocation is used to call IFUNC function in PIC
object.
ld/
PR ld/14961
PR ld/20515
* testsuite/ld-i386/i386.exp: Run pr20515.
* testsuite/ld-i386/pr20515.d: New file.
* testsuite/ld-i386/pr20515.s: Likewise.
* testsuite/ld-ifunc/ifunc-14a.s: Use R_386_PLT32 to call IFUNC
function.
* testsuite/ld-ifunc/ifunc-14c.s: Likewise.
* testsuite/ld-ifunc/ifunc-2-i386.s: Likewise.
* testsuite/ld-ifunc/ifunc-2-local-i386.s: Likewise.
* testsuite/ld-ifunc/ifunc.exp: Move PR ld/19784 tests to ...
* testsuite/ld-x86-64/x86-64.exp: Here.
* testsuite/ld-ifunc/pr19784a.c: Moved to ...
* testsuite/ld-x86-64/pr19784a.c: Here.
* testsuite/ld-ifunc/pr19784b.c: Moved to ...
* testsuite/ld-x86-64/pr19784b.c: Here.
* testsuite/ld-ifunc/pr19784c.c: Moved to ...
* testsuite/ld-x86-64/pr19784c.c: Here.
2016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
bfd/
* bfd-in.h (struct elf32_arm_params): Define.
(bfd_elf32_arm_set_target_relocs): Rename into ...
(bfd_elf32_arm_set_target_params): This. Use a struct
elf32_arm_params to pass all parameters but the bfd and bfd_link_info.
* bfd-in2.h: Regenerate.
* elf32-arm.c (bfd_elf32_arm_set_target_relocs): Rename into ...
(bfd_elf32_arm_set_target_params): This. Pass all values via a struct
elf32_arm_params rather than as individual parameters.
ld/
* emultempl/armelf.em (params): New static variable.
(thumb_entry_symbol, byteswap_code, target1_is_rel, target2_type,
fix_v4bx, use_blx, vfp11_denorm_fix, stm32l4xx_fix, fix_cortex_a8,
no_enum_size_warning, no_wchar_size_warning, pic_veneer,
merge_exidx_entries, fix_arm1176, cmse_implib): move as part of the
above new structure.
(arm_elf_before_allocation): Access static variable from the params
structure.
(gld${EMULATION_NAME}_finish): Likewise.
(arm_elf_create_output_section_statements): Likewise and pass the
address of that structure to bfd_elf32_arm_set_target_relocs instead
of the static variables.
(PARSE_AND_LIST_ARGS_CASES): Access static variable from the params
structure.
Forgot to set should_relocate to TRUE in case of GOT and TLS relocations of
undefined symbols for shared libraries.
In dynamic libraries if symbol is not known the instruction relocation would
not be resolved to point to the respective .got entry.
A test was created to detect similar future mistakes.
bfd/ChangeLog:
Cupertino Miranda <cmiranda@synopsys.com>
* elf32-arc.c (elf_arc_relocate_section): Changed. Set should_relocate
to TRUE for GOT and TLS relocs.
ld/ChangeLog:
Cupertino Miranda <cmiranda@synopsys.com>
* ld/testsuite/ld-arc/tls_gd-01.s: Added a testcase for this patch.
* ld/testsuite/ld-arc/tls_gd-01.d: Likewise.
When no dynamic relocation was generated the .got content would not be
updated for the TLS_IE_GOT relocation addresses.
bfd/ChangeLog:
Cupertino Miranda <cmiranda@synopsys.com>
* arc-got.h (relocate_fix_got_relocs_for_got_info): Fixed addresses in
debug comments. Fixed address in .got related to TLS_IE_GOT dynamic
relocation.
ld/ChangeLog:
Cupertino Miranda <cmiranda@synopsys.com>
* testsuite/ld-arc/tls_ie-01.s: Added to verify associated fix.
* testsuite/ld-arc/tls_ie-01.d: Likewise
2016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
bfd/
* bfd-in.h (bfd_elf32_arm_set_target_relocs): Add a new parameter for
the input import library bfd.
* bfd-in2.h: Regenerate.
* elf32-arm.c (struct elf32_arm_link_hash_table): New in_implib_bfd
and new_cmse_stub_offset fields.
(stub_hash_newfunc): Initialize stub_offset and stub_template_size to
-1.
(elf32_arm_add_stub): Likewise for stub_offset.
(arm_new_stubs_start_offset_ptr): New function.
(arm_build_one_stub): Only allocate a stub_offset if it is -1. Allow
empty SG veneers to have zero relocations.
(arm_size_one_stub): Only initialize stub size and template
information for non empty veneers. Do not update veneer section size
if veneer already has an offset.
(elf32_arm_create_stub): Return the stub entry pointer or NULL instead
of a boolean indicating success or failure.
(cmse_scan): Change stub_changed parameter into an integer pointer
parameter cmse_stub_created to count the number of stub created and
adapt to change of return value in elf32_arm_create_stub.
(cmse_entry_fct_p): New function.
(arm_list_new_cmse_stub): Likewise.
(set_cmse_veneer_addr_from_implib): Likewise.
(elf32_arm_size_stubs): Define cmse_stub_created, pass its address to
cmse_scan instead of that of cmse_stub_changed to compute the number
of stub created and use it to initialize stub_changed. Call
set_cmse_veneer_addr_from_implib after all cmse_scan. Adapt to change
of return value in elf32_arm_create_stub. Use
arm_stub_section_start_offset () if not NULL to initialize size of
secure gateway veneers section. Initialize stub_offset of Cortex-A8
erratum fix to -1. Use ret to hold return value.
(elf32_arm_build_stubs): Use arm_stub_section_start_offset () if not
NULL to initialize size of secure gateway veneers section. Adapt
comment to stress the importance of zeroing veneer section content.
(bfd_elf32_arm_set_target_relocs): Add new in_implib_bfd parameter to
initialize eponymous field in struct elf32_arm_link_hash_table.
ld/
* emultempl/armelf.em (in_implib_filename): Declare and initialize new
variable.
(arm_elf_create_output_section_statements): Open import input library
file for writing and pass resulting in_implib_bfd to
bfd_elf32_arm_set_target_relocs.
(PARSE_AND_LIST_PROLOGUE): Define OPTION_IN_IMPLIB option.
(PARSE_AND_LIST_LONGOPTS): Define --in-implib option.
(PARSE_AND_LIST_OPTIONS): Add help message for --in-implib option.
(PARSE_AND_LIST_ARGS_CASES): Handle new OPTION_IN_IMPLIB case.
* ld.texinfo (--cmse-implib): Update to mention --in-implib.
(--in-implib): Document new option.
* NEWS: Likewise.
* testsuite/ld-arm/arm-elf.exp
(Secure gateway import library generation): add --defsym VER=1 to gas
CLI.
(Secure gateway import library generation: errors): Likewise.
(Input secure gateway import library): New test.
(Input secure gateway import library: no output import library):
Likewise.
(Input secure gateway import library: not an SG input import library):
Likewise.
(Input secure gateway import library: earlier stub section base):
Likewise.
(Input secure gateway import library: later stub section base):
Likewise.
(Input secure gateway import library: veneer comeback): Likewise.
(Input secure gateway import library: entry function change):
Likewise.
* testsuite/ld-arm/cmse-implib.s: Add input import library testing.
* testsuite/ld-arm/cmse-implib.rd: Update accordingly.
* testsuite/ld-arm/cmse-new-implib.out: New file.
* testsuite/ld-arm/cmse-new-implib.rd: Likewise.
* testsuite/ld-arm/cmse-new-implib-no-output.out: Likewise.
* testsuite/ld-arm/cmse-new-implib-not-sg-in-implib.out: Likewise.
* testsuite/ld-arm/cmse-new-earlier-later-implib.out: Likewise.
* testsuite/ld-arm/cmse-new-comeback-implib.rd: Likewise.
* testsuite/ld-arm/cmse-new-wrong-implib.out: Likewise.
This fixes a few problems in the powerpc ld configury.
1) Using powerpc*le-* to test for powerpcle and powerpc64le would
incorrectly match a target triple like powerpc-apple-elf.
2) In the same vein, *64* could match 64 in the user supplied MANUF-OS
part of the target triple.
3) tooldir vars were missing, and some target aliases would result in
ridiculous values for those tdir_* vars given.
4) Since 2016-04-25, BE support was added automatically when asking
for an LE target. If that is a good idea, then so is adding LE
support when asking for BE.
* configure.tgt (powerpc*-*-linux* et al): Rewrite, adding LE
support for BE. First output all target endian configury
values, then opposite endian. Handle more tooldirs. Fix
bogus matches with strings in MANUF-OS part of target triple.
* testsuite/ld-undefined/weak-fundef.s: New.
* testsuite/ld-undefined/weak-undef.t: Don't specify filename.
* testsuite/ld-undefined/weak-undef.exp: Run new tests. Rearrange
much of old code. Use is_elf_format to select targets.
PR ld/20436
* testsuite/lib/ld-lib.exp (check_gcc_plugin_enabled): When not
testing remotely, check to see if target compiler is installed
before trying to run it.
Complement commit b75d42bce5 ("Fix mips segfault on GOT access of
absolute symbol") and unmark the `__ehdr_start' test 2 as known to fail
for the n32 and n64 ABIs, as with the change referred in place the
causing issue has been properly addressed and consequently the tests do
not fail anymore and neither are supposed to.
ld/
PR ld/15428
* testsuite/ld-mips-elf/mips-elf.exp: Un-KFAIL `__ehdr_start'
test 2.
Repeat `PIC and non-PIC test 1' checks for microMIPS LA25 stubs,
covering code generation and stub symbol annotation.
ld/
* testsuite/ld-mips-elf/pic-and-nonpic-1-micromips-rel.dd: New
test.
* testsuite/ld-mips-elf/pic-and-nonpic-1-micromips-rel.nd: New
test.
* testsuite/ld-mips-elf/pic-and-nonpic-1-micromips.dd: New test.
* testsuite/ld-mips-elf/pic-and-nonpic-1-micromips.nd: New test.
* testsuite/ld-mips-elf/pic-and-nonpic-1a-micromips.s: New test
source.
* testsuite/ld-mips-elf/pic-and-nonpic-1b-micromips.s: New test
source.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
Don't run LTO tests if compiler is configured with --disable-plugin.
PR ld/20436
* testsuite/lib/ld-lib.exp (check_gcc_plugin_enabled): New
proc.
(check_lto_available): Return 0 if check_gcc_plugin_enabled
returns 0.
(check_lto_fat_available): Likewise.
(check_lto_shared_available): Likewise.
bfd/
* elf32-arm.c (CMSE_PREFIX): Define macro.
(elf32_arm_stub_cmse_branch_thumb_only): Define stub sequence.
(cmse_branch_thumb_only): Declare stub.
(struct elf32_arm_link_hash_table): Define cmse_stub_sec field.
(elf32_arm_get_plt_info): Add globals parameter. Use it to return
FALSE if there is no PLT.
(arm_type_of_stub): Adapt to new elf32_arm_get_plt_info signature.
(elf32_arm_final_link_relocate): Likewise.
(elf32_arm_gc_sweep_hook): Likewise.
(elf32_arm_gc_mark_extra_sections): Mark sections holding ARMv8-M
secure entry functions.
(arm_stub_is_thumb): Add case for arm_stub_cmse_branch_thumb_only.
(arm_dedicated_stub_output_section_required): Change to a switch case
and add a case for arm_stub_cmse_branch_thumb_only.
(arm_dedicated_stub_output_section_required_alignment): Likewise.
(arm_stub_dedicated_output_section_name): Likewise.
(arm_stub_dedicated_input_section_ptr): Likewise and remove
ATTRIBUTE_UNUSED for htab parameter.
(arm_stub_required_alignment): Likewise.
(arm_stub_sym_claimed): Likewise.
(arm_dedicated_stub_section_padding): Likewise.
(cmse_scan): New function.
(elf32_arm_size_stubs): Call cmse_scan for ARM M profile targets.
Set stub_changed to TRUE if such veneers were created.
(elf32_arm_swap_symbol_in): Add detection code for CMSE special
symbols.
include/
* arm.h (ARM_GET_SYM_CMSE_SPCL): Define macro.
(ARM_SET_SYM_CMSE_SPCL): Likewise.
ld/
* ld.texinfo (Placement of SG veneers): New concept entry.
* testsuite/ld-arm/arm-elf.exp
(Secure gateway veneers: no .gnu.sgstubs section): New test.
(Secure gateway veneers: wrong entry functions): Likewise.
(Secure gateway veneers (ARMv8-M Baseline)): Likewise.
(Secure gateway veneers (ARMv8-M Mainline)): Likewise.
* testsuite/ld-arm/cmse-veneers.s: New file.
* testsuite/ld-arm/cmse-veneers.d: Likewise.
* testsuite/ld-arm/cmse-veneers.rd: Likewise.
* testsuite/ld-arm/cmse-veneers.sd: Likewise.
* testsuite/ld-arm/cmse-veneers-no-gnu_sgstubs.out: Likewise.
* testsuite/ld-arm/cmse-veneers-wrong-entryfct.out: Likewise.
Convert microMIPS branches and jumps whose delay slot would be filled by
a generated NOP instruction to the corresponding compact form where one
exists, in a manner similar to MIPS16 JR->JRC and JALR->JALRC swap.
Do so even where the transformation switches from a 16-bit to a 32-bit
branch encoding for no benefit in code size reduction, as this is still
advantageous. This is because a branch/NOP pair takes 2 pipeline slots
or a 2-cycle completion latency except in superscalar implementations.
Whereas a compact branch may or may not stall on its target fetch, so it
will at most have a 2-cycle completion latency and may have only 1 even
in scalar implementations, and in superscalar implementations it is
expected to have no worse latency as a branch/NOP pair has. Also it
won't stall and therefore take the extra latency cycle in the not-taken
case.
Technically this is the same as MIPS16 compaction: for the qualifying
instruction encodings the APPEND_ADD_COMPACT machine code generation
method is selected where APPEND_ADD_WITH_NOP otherwise would and tells
the code generator in `append_insn' to convert the regular form of an
instruction to its corresponding compact form. For this the opcode is
tweaked as necessary and the microMIPS opcode table is scanned for the
matching updated instruction. A non-$0 `rt' operand to BEQ and BNE
instructions is moved to the `rs' operand field of BEQZC and BNEZC
encodings as required.
Unlike with MIPS16 compaction however we need to handle out-of-distance
branch relaxation as well. We do this by deferring the generation of
any delay-slot NOP required to relaxation made in `md_convert_frag', by
converting the APPEND_ADD_WITH_NOP machine code generation to APPEND_ADD
where a relaxed instruction is recorded. Relaxation then, depending on
actual code produced, chooses between either using a compact branch or
jump encoding and emitting the NOP outstanding if no compact encoding is
possible.
For code simplicity's sake the relaxation pass is retained even if the
principle of preferring a compact encoding to a 16-bit branch/NOP pair
means, in the absence of out-of-range branch relaxation, that a single
compact branch machine code instruction will eventually be produced from
a given assembly source instruction.
gas/
* config/tc-mips.c (RELAX_MICROMIPS_ENCODE): Add `nods' flag.
(RELAX_MICROMIPS_RELAX32, RELAX_MICROMIPS_TOOFAR16)
(RELAX_MICROMIPS_MARK_TOOFAR16, RELAX_MICROMIPS_CLEAR_TOOFAR16)
(RELAX_MICROMIPS_TOOFAR32, RELAX_MICROMIPS_MARK_TOOFAR32)
(RELAX_MICROMIPS_CLEAR_TOOFAR32): Shift bits.
(get_append_method): Also return APPEND_ADD_COMPACT for
microMIPS instructions.
(find_altered_mips16_opcode): Exclude macros from matching.
Factor code out...
(find_altered_opcode): ... to this new function.
(find_altered_micromips_opcode): New function.
(frag_branch_delay_slot_size): Likewise.
(append_insn): Handle microMIPS branch/jump compaction.
(macro_start): Likewise.
(relaxed_micromips_32bit_branch_length): Likewise.
(md_convert_frag): Likewise.
* testsuite/gas/mips/micromips.s: Add conditional explicit NOPs
for delay slot filling.
* testsuite/gas/mips/micromips-b16.s: Add explicit NOPs for
delay slot filling.
* testsuite/gas/mips/micromips-size-1.s: Likewise.
* testsuite/gas/mips/micromips.l: Adjust line numbers.
* testsuite/gas/mips/micromips-warn.l: Likewise.
* testsuite/gas/mips/micromips-size-1.l: Likewise.
* testsuite/gas/mips/micromips.d: Adjust padding.
* testsuite/gas/mips/micromips-trap.d: Likewise.
* testsuite/gas/mips/micromips-insn32.d: Likewise.
* testsuite/gas/mips/micromips-noinsn32.d: Likewise.
* testsuite/gas/mips/micromips@beq.d: Update patterns for
branch/jump compaction.
* testsuite/gas/mips/micromips@bge.d: Likewise.
* testsuite/gas/mips/micromips@bgeu.d: Likewise.
* testsuite/gas/mips/micromips@blt.d: Likewise.
* testsuite/gas/mips/micromips@bltu.d: Likewise.
* testsuite/gas/mips/micromips@branch-misc-4.d: Likewise.
* testsuite/gas/mips/micromips@branch-misc-4-64.d: Likewise.
* testsuite/gas/mips/micromips@branch-misc-5.d: Likewise.
* testsuite/gas/mips/micromips@branch-misc-5pic.d: Likewise.
* testsuite/gas/mips/micromips@branch-misc-5-64.d: Likewise.
* testsuite/gas/mips/micromips@branch-misc-5pic-64.d: Likewise.
* testsuite/gas/mips/micromips@jal-svr4pic-local.d: Likewise.
* testsuite/gas/mips/micromips@jal-svr4pic-local-n32.d:
Likewise.
* testsuite/gas/mips/micromips@jal-svr4pic-local-n64.d:
Likewise.
* testsuite/gas/mips/micromips@loc-swap.d: Likewise.
* testsuite/gas/mips/micromips@loc-swap-dis.d: Likewise.
* testsuite/gas/mips/micromips@relax.d: Likewise.
* testsuite/gas/mips/micromips@relax-at.d: Likewise.
* testsuite/gas/mips/micromips@relax-swap3.d: Likewise.
* testsuite/gas/mips/branch-extern-2.d: Likewise.
* testsuite/gas/mips/branch-extern-4.d: Likewise.
* testsuite/gas/mips/branch-section-2.d: Likewise.
* testsuite/gas/mips/branch-section-4.d: Likewise.
* testsuite/gas/mips/branch-weak-2.d: Likewise.
* testsuite/gas/mips/branch-weak-5.d: Likewise.
* testsuite/gas/mips/micromips-branch-absolute.d: Likewise.
* testsuite/gas/mips/micromips-branch-absolute-n32.d: Likewise.
* testsuite/gas/mips/micromips-branch-absolute-n64.d: Likewise.
* testsuite/gas/mips/micromips-branch-absolute-addend.d:
Likewise.
* testsuite/gas/mips/micromips-branch-absolute-addend-n32.d:
Likewise.
* testsuite/gas/mips/micromips-branch-absolute-addend-n64.d:
Likewise.
* testsuite/gas/mips/micromips-compact.d: New test.
* testsuite/gas/mips/mips.exp: Run the new test.
ld/
* testsuite/ld-mips-elf/micromips-branch-absolute.d: Update
patterns for branch compaction.
* testsuite/ld-mips-elf/micromips-branch-absolute-addend.d:
Likewise.
opcodes/
* micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
"beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
"j".
Complement:
commit 1bbce13264
Author: Maciej W. Rozycki <macro@linux-mips.org>
Date: Mon Jun 24 23:55:46 2013 +0000
<https://sourceware.org/ml/binutils/2013-06/msg00077.html>, ("MIPS:
Compressed PLT/stubs support"), and also choose between regular and
compressed PLT entries as appropriate for any branches referring.
bfd/
* elfxx-mips.c (mips_elf_calculate_relocation): Handle branches
in PLT compression selection.
(_bfd_mips_elf_check_relocs): Likewise.
ld/
* testsuite/ld-mips-elf/compressed-plt-1.s: Add branch support.
* testsuite/ld-mips-elf/compressed-plt-1a.s: Likewise.
* testsuite/ld-mips-elf/compressed-plt-1b.s: Likewise.
* testsuite/ld-mips-elf/compressed-plt-1-o32-branch.od: New
test.
* testsuite/ld-mips-elf/compressed-plt-1-o32-branch.rd: New
test.
* testsuite/ld-mips-elf/compressed-plt-1-o32-mips16-bronly.od:
New test.
* testsuite/ld-mips-elf/compressed-plt-1-o32-mips16-bronly.rd:
New test.
* testsuite/ld-mips-elf/compressed-plt-1-o32-mips16-branch.od:
New test.
* testsuite/ld-mips-elf/compressed-plt-1-o32-mips16-branch.rd:
New test.
* testsuite/ld-mips-elf/compressed-plt-1-o32-umips-bronly.od:
New test.
* testsuite/ld-mips-elf/compressed-plt-1-o32-umips-bronly.rd:
New test.
* testsuite/ld-mips-elf/compressed-plt-1-o32-umips-branch.od:
New test.
* testsuite/ld-mips-elf/compressed-plt-1-o32-umips-branch.rd:
New test.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
ld * ldbuildid.c: Changes for MinGW32:
Include windows.h and rpcdce.h.
(validate_build_id_style): Allow "uuid" style.
(generate_build_id): Fill in id_bits using UuidCreate().
* testsuite/ld-elf/sec64k.exp: Run test for arc, msp430, or1k
and m32r. Correct comment. Relax ld -r match to account for
msp increased number of default sections.
bfd * arc-got.h (relocate_fix_got_relocs_for_got_info): Handle the case
where there's no elf_link_hash_entry while processing GOT_NORMAL got
entries.
ld * testsuite/ld-arc/got-01.d: New file.
* testsuite/ld-arc/got-01.s: New file.
If the last parameter of a tcl function is "args" then it can take
zero or more arguments. Make use of this language feature in
run_ld_link_exec_tests.
* testsuite/lib/ld-lib.exp (run_ld_link_exec_tests): Replace
"targets_to_xfail" parameter with "args".
* testsuite/ld-elf/compress.exp: Remove empty list of xfails on
all calls to run_ld_link_exec_tests.
* testsuite/ld-elf/dwarf.exp: Likewise.
* testsuite/ld-elf/indirect.exp: Likewise.
* testsuite/ld-elf/wrap.exp: Likewise.
* testsuite/ld-i386/i386.exp: Likewise.
* testsuite/ld-i386/no-plt.exp: Likewise.
* testsuite/ld-i386/tls.exp: Likewise.
* testsuite/ld-ifunc/ifunc.exp: Likewise.
* testsuite/ld-pie/pie.exp: Likewise.
* testsuite/ld-plugin/lto.exp: Likewise.
* testsuite/ld-size/size.exp: Likewise.
* testsuite/ld-x86-64/mpx.exp: Likewise.
* testsuite/ld-x86-64/no-plt.exp: Likewise.
* testsuite/ld-x86-64/tls.exp: Likewise.
* testsuite/ld-x86-64/x86-64.exp: Likewise.
* testsuite/ld-elf/elf.exp: Likewise. Reorder args when providing
xfails and simplify lists.
* testsuite/ld-elf/shared.exp: Likewise.
bfd/
* elf.c (_bfd_elf_filter_global_symbols): Skip local symbols.
(swap_out_syms): Return an error when not finding ELF output
section rather than asserting.
* elflink.c (elf_output_implib): Call bfd_set_error on no symbols.
ld/
* testsuite/lib/ld-lib.exp (run_ld_link_tests): Add optional
parameter to pass list of xfails.
* testsuite/ld-elf/elf.exp: Add xfails for implib tests. Tidy
implib test formatting. Don't set .data start address.
* testsuite/ld-elf/implib.s: Remove first .bss directive and
replace second one with equivalent .section directive.
* testsuite/ld-elf/empty-implib.out: Add expected final error.
* testsuite/ld-elf/implib.rd: Update.
Issue an error if p_paddr becomes invalid when allocating space for
program headers.
PR ld/20376
* elf.c (assign_file_positions_for_load_sections): Also check
p_paddr for program header space.
Folding a constant expression early can lead to loss of tokens, eg.
ABSOLUTE, that are significant in ld's horrible context sensitive
expression evaluation. Also, MAXPAGESIZE and other "constants" may
not have taken values specified on the command line, leading to the
wrong value being cached.
* ldexp.c (exp_unop, exp_binop, exp_trinop, exp_nameop): Don't
fold expression.
* testsuite/ld-elf/maxpage3b.d: Expect correct maxpagesize.
Convert cross-mode regular MIPS and microMIPS BAL instructions to JALX,
similarly to how JAL instructions are converted.
bfd/
* elfxx-mips.c (mips_elf_perform_relocation): Convert cross-mode
BAL to JALX.
(_bfd_mips_elf_relocate_section) <bfd_reloc_outofrange>: Add a
corresponding error message.
gas/
* config/tc-mips.c (mips_force_relocation, mips_fix_adjustable):
Adjust comments for BAL to JALX linker conversion.
(fix_bad_cross_mode_branch_p): Accept cross-mode BAL.
* testsuite/gas/mips/unaligned-branch-1.l: Update error messages
expected.
* testsuite/gas/mips/unaligned-branch-micromips-1.l: Likewise.
* testsuite/gas/mips/branch-local-4.d: New test.
* testsuite/gas/mips/branch-local-n32-4.d: New test.
* testsuite/gas/mips/branch-local-n64-4.d: New test.
* testsuite/gas/mips/branch-addend.d: New test.
* testsuite/gas/mips/branch-addend-n32.d: New test.
* testsuite/gas/mips/branch-addend-n64.d: New test.
* testsuite/gas/mips/branch-local-4.s: New test source.
* testsuite/gas/mips/branch-addend.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
ld/
* testsuite/ld-mips-elf/unaligned-branch-2.d: Update error
messages expected.
* testsuite/ld-mips-elf/unaligned-branch-r6-1.d: Likewise.
* testsuite/ld-mips-elf/unaligned-branch-mips16.d: Likewise.
* testsuite/ld-mips-elf/unaligned-branch-micromips.d: Likewise.
* testsuite/ld-mips-elf/bal-jalx-addend.d: New test.
* testsuite/ld-mips-elf/bal-jalx-local.d: New test.
* testsuite/ld-mips-elf/bal-jalx-pic.d: New test.
* testsuite/ld-mips-elf/bal-jalx-addend-n32.d: New test.
* testsuite/ld-mips-elf/bal-jalx-local-n32.d: New test.
* testsuite/ld-mips-elf/bal-jalx-pic-n32.d: New test.
* testsuite/ld-mips-elf/bal-jalx-addend-n64.d: New test.
* testsuite/ld-mips-elf/bal-jalx-local-n64.d: New test.
* testsuite/ld-mips-elf/bal-jalx-pic-n64.d: New test.
* testsuite/ld-mips-elf/unaligned-jalx-2.d: New test.
* testsuite/ld-mips-elf/unaligned-jalx-3.d: New test.
* testsuite/ld-mips-elf/unaligned-jalx-addend-2.d: New test.
* testsuite/ld-mips-elf/unaligned-jalx-addend-3.d: New test.
* testsuite/ld-mips-elf/unaligned-jalx-2.s: New test source.
* testsuite/ld-mips-elf/unaligned-jalx-3.s: New test source.
* testsuite/ld-mips-elf/unaligned-jalx-addend-2.s: New test
source.
* testsuite/ld-mips-elf/unaligned-jalx-addend-3.s: New test
source.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
Verify that the ISA mode of branch targets is the same as the referring
relocation, so that an attempt to produce a branch between instructions
encoded in different ISA modes each causes an error rather than silently
producing non-functional code. Make sure that no symbol or addend bits
are silently truncated: terminate with an error if the relocation value
calculated cannot be encoded in the relocatable field of a branch; for
REL targets also applying to any intermediate addend.
Also make jump target's alignment verification consistent with that for
branches.
This change will require an update to some obscure handcoded assembly
sources which make branches to labels placed at data objects, however
for microMIPS code only. These labels will have to be updated with the
`.insn' directive for containing code to assemble and link successfully.
Such code is broken as any such labels have always been required by the
microMIPS architecture specification[1][2] to be annotated this way for
correct interpretation, and with our old code missing `.insn' directives
caused labels to present different semantics depending on whether they
were referred with branch (ISA bit ignored) or other relocations (ISA
bit respected).
Enforcing these checks however will ensure errors in building software,
like mixed regular MIPS and microMIPS code links with branches between,
will be diagnosed at the build time rather than causing odd run-time
errors such as intermittent crashes. It will also let cross-mode BAL
instructions be converted to JALX instructions, with a separate change.
References:
[1] "MIPS Architecture for Programmers, Volume II-B: The microMIPS32
Instruction Set", MIPS Technologies, Inc., Document Number: MD00582,
Revision 5.04, January 15, 2014, Section 7.1 "Assembly-Level
Compatibility", p. 533
[2] "MIPS Architecture for Programmers, Volume II-B: The microMIPS64
Instruction Set", MIPS Technologies, Inc., Document Number: MD00594,
Revision 5.04, January 15, 2014, Section 8.1 "Assembly-Level
Compatibility", p. 623
bfd/
* elfxx-mips.c (b_reloc_p): Add R_MICROMIPS_PC16_S1,
R_MICROMIPS_PC10_S1 and R_MICROMIPS_PC7_S1.
(branch_reloc_p): New function.
(mips_elf_calculate_relocation): Handle ISA mode determination
for relocations against section symbols, against absolute
symbols and absolute relocations. Also set `*cross_mode_jump_p'
for branches.
<R_MIPS16_26, R_MIPS_26, R_MICROMIPS_26_S1>: Suppress alignment
checks for weak undefined symbols. Also check target alignment
within the same ISA mode.
<R_MIPS_PC16, R_MIPS_GNU_REL16_S2>: Handle cross-mode branches
in the alignment check.
<R_MICROMIPS_PC7_S1>: Add an alignment check.
<R_MICROMIPS_PC10_S1>: Likewise.
<R_MICROMIPS_PC16_S1>: Likewise.
(mips_elf_perform_relocation): Report a failure for unsupported
same-mode JALX instructions and cross-mode branches.
(_bfd_mips_elf_relocate_section) <bfd_reloc_outofrange>: Add
error messages for jumps to misaligned addresses.
gas/
* config/tc-mips.c (mips_force_relocation): Also retain branch
relocations against MIPS16 and microMIPS symbols.
(fix_bad_cross_mode_jump_p): New function.
(fix_bad_same_mode_jalx_p): Likewise.
(fix_bad_misaligned_jump_p): Likewise.
(fix_bad_cross_mode_branch_p): Likewise.
(fix_bad_misaligned_branch_p): Likewise.
(fix_validate_branch): Likewise.
(md_apply_fix) <BFD_RELOC_MIPS_JMP, BFD_RELOC_MIPS16_JMP>
<BFD_RELOC_MICROMIPS_JMP>: Separate from BFD_RELOC_MIPS_SHIFT5,
etc. Verify the ISA mode and alignment of the jump target.
<BFD_RELOC_MIPS_21_PCREL_S2>: Replace the inline alignment check
with a call to `fix_validate_branch'.
<BFD_RELOC_MIPS_26_PCREL_S2>: Likewise.
<BFD_RELOC_16_PCREL_S2>: Likewise.
<BFD_RELOC_MICROMIPS_7_PCREL_S1, BFD_RELOC_MICROMIPS_10_PCREL_S1>
<BFD_RELOC_MICROMIPS_16_PCREL_S1>: Retain the original addend.
Verify the ISA mode and alignment of the branch target.
(md_convert_frag): Verify the ISA mode and alignment of resolved
MIPS16 branch targets.
* testsuite/gas/mips/branch-misc-1.s: Annotate non-instruction
branch targets with `.insn'.
* testsuite/gas/mips/branch-misc-5.s: Likewise.
* testsuite/gas/mips/micromips@branch-misc-5-64.d: Update
accordingly.
* testsuite/gas/mips/micromips@branch-misc-5pic-64.d: Likewise.
* testsuite/gas/mips/micromips-branch-relax.s: Annotate
non-instruction branch target with `.insn'.
* testsuite/gas/mips/micromips.s: Replace microMIPS JALX targets
with external symbols.
* testsuite/gas/mips/micromips-insn32.d: Update accordingly.
* testsuite/gas/mips/micromips-noinsn32.d: Likewise.
* testsuite/gas/mips/micromips-trap.d: Likewise.
* testsuite/gas/mips/micromips.d: Likewise.
* testsuite/gas/mips/mips16.s: Annotate non-instruction branch
targets with `.insn'.
* testsuite/gas/mips/mips16.d: Update accordingly.
* testsuite/gas/mips/mips16-64.d: Likewise.
* testsuite/gas/mips/mips16-dwarf2.s: Annotate non-instruction
branch target with `.insn'.
* testsuite/gas/mips/relax-swap3.s: Likewise.
* testsuite/gas/mips/branch-local-2.l: New list test.
* testsuite/gas/mips/branch-local-3.l: New list test.
* testsuite/gas/mips/branch-local-n32-2.l: New list test.
* testsuite/gas/mips/branch-local-n32-3.l: New list test.
* testsuite/gas/mips/branch-local-n64-2.l: New list test.
* testsuite/gas/mips/branch-local-n64-3.l: New list test.
* testsuite/gas/mips/unaligned-jump-1.l: New list test.
* testsuite/gas/mips/unaligned-jump-2.l: New list test.
* testsuite/gas/mips/unaligned-jump-3.d: New test.
* testsuite/gas/mips/unaligned-jump-mips16-1.l: New list test.
* testsuite/gas/mips/unaligned-jump-mips16-2.l: New list test.
* testsuite/gas/mips/unaligned-jump-mips16-3.d: New test.
* testsuite/gas/mips/unaligned-jump-micromips-1.l: New list
test.
* testsuite/gas/mips/unaligned-jump-micromips-2.l: New list
test.
* testsuite/gas/mips/unaligned-jump-micromips-3.d: New test.
* testsuite/gas/mips/unaligned-branch-1.l: New list test.
* testsuite/gas/mips/unaligned-branch-2.l: New list test.
* testsuite/gas/mips/unaligned-branch-3.d: New test.
* testsuite/gas/mips/unaligned-branch-r6-1.l: New list test.
* testsuite/gas/mips/unaligned-branch-r6-2.l: New list test.
* testsuite/gas/mips/unaligned-branch-r6-3.l: New list test.
* testsuite/gas/mips/unaligned-branch-r6-4.l: New list test.
* testsuite/gas/mips/unaligned-branch-r6-5.d: New test.
* testsuite/gas/mips/unaligned-branch-r6-6.d: New test.
* testsuite/gas/mips/unaligned-branch-mips16-1.l: New list test.
* testsuite/gas/mips/unaligned-branch-mips16-2.l: New list test.
* testsuite/gas/mips/unaligned-branch-mips16-3.d: New test.
* testsuite/gas/mips/unaligned-branch-micromips-1.l: New list
test.
* testsuite/gas/mips/unaligned-branch-micromips-2.l: New list
test.
* testsuite/gas/mips/unaligned-branch-micromips-3.d: New test.
* testsuite/gas/mips/branch-local-2.s: New test source.
* testsuite/gas/mips/branch-local-3.s: New test source.
* testsuite/gas/mips/branch-local-n32-2.s: New test source.
* testsuite/gas/mips/branch-local-n32-3.s: New test source.
* testsuite/gas/mips/branch-local-n64-2.s: New test source.
* testsuite/gas/mips/branch-local-n64-3.s: New test source.
* testsuite/gas/mips/unaligned-jump-1.s: New test source.
* testsuite/gas/mips/unaligned-jump-2.s: New test source.
* testsuite/gas/mips/unaligned-jump-mips16-1.s: New test source.
* testsuite/gas/mips/unaligned-jump-mips16-2.s: New test source.
* testsuite/gas/mips/unaligned-jump-micromips-1.s: New test
source.
* testsuite/gas/mips/unaligned-jump-micromips-2.s: New test
source.
* testsuite/gas/mips/unaligned-branch-1.s: New test source.
* testsuite/gas/mips/unaligned-branch-2.s: New test source.
* testsuite/gas/mips/unaligned-branch-r6-1.s: New test source.
* testsuite/gas/mips/unaligned-branch-r6-2.s: New test source.
* testsuite/gas/mips/unaligned-branch-r6-3.s: New test source.
* testsuite/gas/mips/unaligned-branch-r6-4.s: New test source.
* testsuite/gas/mips/unaligned-branch-mips16-1.s: New test
source.
* testsuite/gas/mips/unaligned-branch-mips16-2.s: New test
source.
* testsuite/gas/mips/unaligned-branch-micromips-1.s: New test
source.
* testsuite/gas/mips/unaligned-branch-micromips-2.s: New test
source.
* testsuite/gas/mips/mips.exp: Run the new tests.
ld/
* testsuite/ld-mips-elf/unaligned-jalx-1.d: Update error message
expected.
* testsuite/ld-mips-elf/unaligned-jalx-addend-1.d: Likewise.
* testsuite/ld-mips-elf/unaligned-jalx-addend-mips16-1.d:
Likewise.
* testsuite/ld-mips-elf/unaligned-jalx-addend-micromips-1.d:
Likewise.
* testsuite/ld-mips-elf/unaligned-jalx-mips16-1.d: Likewise.
* testsuite/ld-mips-elf/unaligned-jalx-micromips-1.d: Likewise.
* testsuite/ld-mips-elf/undefweak-overflow.s: Add jumps,
microMIPS BAL and MIPS16 instructions.
* testsuite/ld-mips-elf/undefweak-overflow.d: Update
accordingly.
* testsuite/ld-mips-elf/unaligned-branch-2.d: New test.
* testsuite/ld-mips-elf/unaligned-branch-r6-1.d: New test.
* testsuite/ld-mips-elf/unaligned-branch-r6-2.d: New test.
* testsuite/ld-mips-elf/unaligned-branch-mips16.d: New test.
* testsuite/ld-mips-elf/unaligned-branch-micromips.d: New test.
* testsuite/ld-mips-elf/unaligned-jump-mips16.d: New test.
* testsuite/ld-mips-elf/unaligned-jump-micromips.d: New test.
* testsuite/ld-mips-elf/unaligned-jump.d: New test.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
When using the plugin interface to claim an input file the claim method
from (possible) many plugins can be called on an input file. If these
claim methods read content from the input file then the file offset
stored in the underlying file descriptor will change.
As we share a file descriptor between the plugin interface (created with
dup in ld/plugin.c:plugin_object_p) and the input bfd object, then any
changes to the file offset in the file descriptor will effect the bfd
object. Also, as the changes to the file offset did not originate from
calls through the bfd interface, but instead came from the plugin
directly, then the bfd will not be aware that the file offset has
changed. This is a problem as the bfd library caches the file offset.
If the plugin decides not to claim an input file then, currently, we
leave the bfd in a state where the actual file offset is out of sync
with the cached file offset.
This problem came to light after a recent commit
7d0b9ebc1e (Don't include libbfd.h outside
of bfd, part 6) however, I don't believe that commit actual introduces
the bug, it just exposed the existing issue.
This commit solves the problem by backing up and restoring the file
offset for the file descriptor of the input file. The restore is only
done if the plugin does not claim the input file, as it is in this case
that the bfd library might be used again to try and identify the
unclaimed file.
ld/ChangeLog:
* plugin.c (plugin_call_claim_file): Restore the file offset after
an unsuccessful attempt to claim a file.
* testplug.c (bytes_to_read_before_claim): New global.
(record_read_length): New function, sets new global
bytes_to_read_before_claim.
(parse_option): Handle 'read:<NUMBER>' option.
(onclaim_file): Read file content before checking for claim.
* testsuite/ld-plugin/plugin-30.d: New file.
* testsuite/ld-plugin/plugin.exp: Add new test.
Some messing with plugin code in order to not need arelt_size in
ld code. File descriptor handling in ld/plugin.c is tidied too,
simply duping the open fd rather than opening the file again.
bfd/
* elflink.c: Include plugin-api.h.
* plugin.c (bfd_plugin_open_input): New function, extracted from..
(try_claim): ..here.
* plugin.h: Don't include bfd.h.
(bfd_plugin_open_input): Declare.
binutils/
* ar.c: Include plugin-api.h.
* nm.c: Likewise.
ld/
* plugin.c: Don't include libbfd.h. Include plugin-api.h
before bfd/plugin.h.
(plugin_object_p): Use bfd_plugin_open_input.
Not much to see here, just renaming a function.
bfd/
* targets.c (bfd_seach_for_target): Rename to..
(bfd_iterate_over_targets): ..this. Rewrite doc.
* bfd-in2.h: Regenerate.
ld/
* ldlang.c (open_output): Replace bfd_search_for_target with
bfd_iterate_over_targets. Localize vars.
bfd * elf32-arc.c (PR_DEBUG): Delete.
Fix printing of debug information. Fix formatting of debug
statements.
(debug_arc_reloc): Handle symbols that are not from an input file.
(arc_do_relocation): Remove excessive exclamation points.
(elf_arc_relocate_section): Print an informative message if the
relocation fails, even if debugging is not enabled.
* arc-got.h: Fix formatting. Fix printing of debug information.
(new_got_entry_to_list): Use xmalloc.
* config.bfd: use the big-endian arc vector as the default vector
for big-endian arc targets.
ld * testsuite/ld-arc/arc.exp: Always run the sda-relocs test in
little endian mode.
Don't convert PC-relative REL relocations against absolute symbols to
section-relative references and retain the original symbol reference
instead. Offsets into the absolute section may overflow the limited
range of their in-place addend field, causing an assembly error, e.g.:
$ cat test.s
.text
.globl foo
.ent foo
foo:
b bar
.end foo
.set bar, 0x12345678
$ as -EB -32 -o test.o test.s
test.s: Assembler messages:
test.s:3: Error: relocation overflow
$
With the original reference retained the source can now be assembled and
linked successfully:
$ as -EB -32 -o test.o test.s
$ objdump -dr test.o
test.o: file format elf32-tradbigmips
Disassembly of section .text:
00000000 <foo>:
0: 1000ffff b 0 <foo>
0: R_MIPS_PC16 bar
4: 00000000 nop
...
$ ld -melf32btsmip -Ttext 0x12340000 -e foo -o test test.o
$ objdump -dr test
test: file format elf32-tradbigmips
Disassembly of section .text:
12340000 <foo>:
12340000: 1000159d b 12345678 <bar>
12340004: 00000000 nop
...
$
For simplicity always retain the original symbol reference, even if it
would indeed fit.
Making TC_FORCE_RELOCATION_ABS separate from TC_FORCE_RELOCATION causes
R_MICROMIPS_PC7_S1, R_MICROMIPS_PC10_S1 and R_MICROMIPS_PC16_S1 branch
relocations against absolute symbols to be converted on RELA targets to
section-relative references. This is an intended effect of this change.
Absolute symbols carry no ISA annotation in their `st_other' field and
their value is not going to change with linker relaxation, so it is safe
to discard the original reference and keep the calculated final symbol
value only in the relocation's addend.
Similarly R6 R_MIPS_PCHI16 and R_MIPS_PCLO16 relocations referring
absolute symbols can be safely converted even on REL targets, as there
the in-place addend of these relocations covers the entire 32-bit
address space so it can hold the calculated final symbol value, and
likewise the value referred won't be affected by any linker relaxation.
Add a set of suitable test cases and enable REL linker tests which now
work and were previously used as dump patterns for RELA tests only.
gas/
* config/tc-mips.h (TC_FORCE_RELOCATION_ABS): New macro.
(mips_force_relocation_abs): New prototype.
* config/tc-mips.c (mips_force_relocation_abs): New function.
* testsuite/gas/mips/branch-absolute.d: Adjust dump patterns.
* testsuite/gas/mips/mips16-branch-absolute.d: Likewise.
* testsuite/gas/mips/micromips-branch-absolute-n32.d: Likewise.
* testsuite/gas/mips/micromips-branch-absolute-n64.d: Likewise.
* testsuite/gas/mips/micromips-branch-absolute-addend-n32.d:
Likewise.
* testsuite/gas/mips/micromips-branch-absolute-addend-n64.d:
Likewise.
* testsuite/gas/mips/branch-absolute-addend.d: New test.
* testsuite/gas/mips/mips16-branch-absolute-addend.d: New test.
* testsuite/gas/mips/micromips-branch-absolute-addend.d: New
test.
* testsuite/gas/mips/mips.exp: Run the new tests.
ld/
* testsuite/ld-mips-elf/mips-elf.exp: Run
`branch-absolute-addend', `mips16-branch-absolute',
`mips16-branch-absolute-addend' and
`micromips-branch-absolute-addend'.
Correct a problem with the ISA bit being stripped from the addend of
compressed branch relocations, affecting RELA targets. It has been
there since microMIPS support has been added, with:
commit df58fc944d
Author: Richard Sandiford <rdsandiford@googlemail.com>
Date: Sun Jul 24 14:20:15 2011 +0000
<https://sourceware.org/ml/binutils/2011-07/msg00198.html>, ("MIPS:
microMIPS ASE support") and R_MICROMIPS_PC7_S1, R_MICROMIPS_PC10_S1 and
R_MICROMIPS_PC16_S1 relocations originally affected, and the
R_MIPS16_PC16_S1 relocation recently added with commit c9775dde32
("MIPS16: Add R_MIPS16_PC16_S1 branch relocation support") actually
triggering a linker error, due to its heightened processing strictness
level:
$ cat test.s
.text
.set mips16
foo:
b bar
.set bar, 0x1235
.align 4, 0
$ as -EB -n32 -o test.o test.s
$ objdump -dr test.o
test.o: file format elf32-ntradbigmips
Disassembly of section .text:
00000000 <foo>:
0: f000 1000 b 4 <foo+0x4>
0: R_MIPS16_PC16_S1 *ABS*+0x1230
...
$ ld -melf32btsmipn32 -Ttext 0 -e 0 -o test test.o
test.o: In function `foo':
(.text+0x0): Branch to a non-instruction-aligned address
$
This is because the ISA bit of the branch target does not match the ISA
bit of the referring branch, hardwired to 1 of course.
Retain the ISA bit then, so that the linker knows this is really MIPS16
code referred:
$ objdump -dr fixed.o
fixed.o: file format elf32-ntradbigmips
Disassembly of section .text:
00000000 <foo>:
0: f000 1000 b 4 <foo+0x4>
0: R_MIPS16_PC16_S1 *ABS*+0x1231
...
$ ld -melf32btsmipn32 -Ttext 0 -e 0 -o fixed fixed.o
$
Add a set of MIPS16 tests to cover the relevant cases, excluding linker
tests though which would overflow the in-place addend on REL targets and
use them as dump patterns for RELA targets only.
gas/
* config/tc-mips.c (md_apply_fix) <BFD_RELOC_MIPS16_16_PCREL_S1>
<BFD_RELOC_MICROMIPS_7_PCREL_S1, BFD_RELOC_MICROMIPS_10_PCREL_S1>
<BFD_RELOC_MICROMIPS_16_PCREL_S1>: Keep the ISA bit in the
addend calculated.
* testsuite/gas/mips/mips16-branch-absolute.s: Set the ISA bit
in `bar', export `foo'.
* testsuite/gas/mips/mips16-branch-absolute.d: Adjust
accordingly.
* testsuite/gas/mips/mips16-branch-absolute-n32.d: Likewise.
* testsuite/gas/mips/mips16-branch-absolute-n64.d: Likewise.
* testsuite/gas/mips/mips16-branch-absolute-addend-n32.d:
Likewise.
* testsuite/gas/mips/mips16-branch-absolute-addend-n64.d:
Likewise.
ld/
* testsuite/ld-mips-elf/mips16-branch-absolute.d: New test.
* testsuite/ld-mips-elf/mips16-branch-absolute-n32.d: New test.
* testsuite/ld-mips-elf/mips16-branch-absolute-n64.d: New test.
* testsuite/ld-mips-elf/mips16-branch-absolute-addend.d: New
test.
* testsuite/ld-mips-elf/mips16-branch-absolute-addend-n32.d: New
test.
* testsuite/ld-mips-elf/mips16-branch-absolute-addend-n64.d: New
test.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests, except
from `mips16-branch-absolute' and
`mips16-branch-absolute-addend', referred indirectly only.
Fix a generic BFD issue with relocations against absolute symbols, which
are installed without using any individual relocation handler provided
by the backend. This causes any absolute section's addend to be lost on
REL targets such as o32 MIPS, and also relocation-specific calculation
adjustments are not made.
As an example assembling this program:
$ cat test.s
.text
foo:
b bar
b baz
.set bar, 0x1234
$ as -EB -32 -o test-o32.o test.s
$ as -EB -n32 -o test-n32.o test.s
produces this binary code:
$ objdump -dr test-o32.o test-n32.o
test-o32.o: file format elf32-tradbigmips
Disassembly of section .text:
00000000 <foo>:
0: 10000000 b 4 <foo+0x4>
0: R_MIPS_PC16 *ABS*
4: 00000000 nop
8: 1000ffff b 8 <foo+0x8>
8: R_MIPS_PC16 baz
c: 00000000 nop
test-n32.o: file format elf32-ntradbigmips
Disassembly of section .text:
00000000 <foo>:
0: 10000000 b 4 <foo+0x4>
0: R_MIPS_PC16 *ABS*+0x1230
4: 00000000 nop
8: 10000000 b c <foo+0xc>
8: R_MIPS_PC16 baz-0x4
c: 00000000 nop
$
where it is clearly visible in `test-o32.o', which uses REL relocations,
that the absolute section's addend equivalent to the value of `bar' -- a
reference to which cannot be fully resolved at the assembly time,
because the reference is PC-relative -- has been lost, as has been the
relocation-specific adjustment of -4, required to take into account the
PC+4-relative calculation made by hardware with branches and seen in the
external symbol reference to `baz' as the `ffff' addend encoded in the
instruction word. In `test-n32.o', which uses RELA relocations, the
absolute section's addend has been correctly retained.
Give precedence then in `bfd_perform_relocation' and
`bfd_install_relocation' to any individual relocation handler the
backend selected may have provided, while still resorting to the generic
calculation otherwise. This retains the semantics which we've had since
forever or before the beginning of our repository history, and is at the
very least compatible with `bfd_elf_generic_reloc' being used as the
handler.
Retain the `bfd_is_und_section' check unchanged at the beginning of
`bfd_perform_relocation' since this does not affect the semantics of the
function. The check returns the same `bfd_reloc_undefined' code the
check for a null `howto' does, so swapping the two does not matter.
Also the check is is mutually exclusive with the `bfd_is_abs_section'
check, since a section cannot be absolute and undefined both at once, so
swapping the two does not matter either.
With this change applied the program quoted above now has the in-place
addend correctly calculated and installed in the field being relocated:
$ objdump -dr fixed-o32.o
fixed-o32.o: file format elf32-tradbigmips
Disassembly of section .text:
00000000 <foo>:
0: 1000048c b 1234 <bar>
0: R_MIPS_PC16 *ABS*
4: 00000000 nop
8: 1000ffff b 8 <foo+0x8>
8: R_MIPS_PC16 baz
c: 00000000 nop
$
Add a set of MIPS tests to cover the relevant cases, including absolute
symbols with addends, and verifying that PC-relative relocations against
symbols concerned resolve to the same value in the final link regardless
of whether the REL or the RELA relocation form is used. Exclude linker
tests though which would overflow the in-place addend on REL targets and
use them as dump patterns for RELA targets only.
bfd/
* reloc.c (bfd_perform_relocation): Try the `howto' handler
first with relocations against absolute symbols.
(bfd_install_relocation): Likewise.
gas/
* testsuite/gas/mips/mips16-branch-absolute.d: Update patterns.
* testsuite/gas/mips/branch-absolute.d: New test.
* testsuite/gas/mips/branch-absolute-n32.d: New test.
* testsuite/gas/mips/branch-absolute-n64.d: New test.
* testsuite/gas/mips/branch-absolute-addend-n32.d: New test.
* testsuite/gas/mips/branch-absolute-addend-n64.d: New test.
* testsuite/gas/mips/mips16-branch-absolute-n32.d: New test.
* testsuite/gas/mips/mips16-branch-absolute-n64.d: New test.
* testsuite/gas/mips/mips16-branch-absolute-addend-n32.d: New
test.
* testsuite/gas/mips/mips16-branch-absolute-addend-n64.d: New
test.
* testsuite/gas/mips/micromips-branch-absolute.d: New test.
* testsuite/gas/mips/micromips-branch-absolute-n32.d: New test.
* testsuite/gas/mips/micromips-branch-absolute-n64.d: New test.
* testsuite/gas/mips/micromips-branch-absolute-addend-n32.d: New
test.
* testsuite/gas/mips/micromips-branch-absolute-addend-n64.d: New
test.
* testsuite/gas/mips/branch-absolute.s: New test source.
* testsuite/gas/mips/branch-absolute-addend.s: New test source.
* testsuite/gas/mips/mips16-branch-absolute-addend.s: New test
source.
* testsuite/gas/mips/micromips-branch-absolute.s: New test
source.
* testsuite/gas/mips/micromips-branch-absolute-addend.s: New
test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
ld/
* testsuite/ld-mips-elf/branch-absolute.d: New test.
* testsuite/ld-mips-elf/branch-absolute-n32.d: New test.
* testsuite/ld-mips-elf/branch-absolute-n64.d: New test.
* testsuite/ld-mips-elf/branch-absolute-addend.d: New test.
* testsuite/ld-mips-elf/branch-absolute-addend-n32.d: New test.
* testsuite/ld-mips-elf/branch-absolute-addend-n64.d: New test.
* testsuite/ld-mips-elf/micromips-branch-absolute.d: New test.
* testsuite/ld-mips-elf/micromips-branch-absolute-n32.d: New
test.
* testsuite/ld-mips-elf/micromips-branch-absolute-n64.d: New
test.
* testsuite/ld-mips-elf/micromips-branch-absolute-addend.d: New
test.
* testsuite/ld-mips-elf/micromips-branch-absolute-addend-n32.d:
New test.
* testsuite/ld-mips-elf/micromips-branch-absolute-addend-n64.d:
New test.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests, except
from `branch-absolute-addend' and
`micromips-branch-absolute-addend', referred indirectly only.
The R_ARC_SDA32 is wrongly described as a ME relocation, fix it. Offset the
__SDATA_BEGIN__ to take advantage of the signed 9-bit field of the
load/store instructions.
include/
2016-07-08 Claudiu Zissulescu <claziss@synopsys.com>
* elf/arc-reloc.def (ARC_SDA32): Don't use ME transformation.
ld/
2016-07-08 Claudiu Zissulescu <claziss@synopsys.com>
* emulparams/arcelf.sh (SDATA_START_SYMBOLS): Add offset.
* testsuite/ld-arc/sda-relocs.dd: New file.
* testsuite/ld-arc/sda-relocs.ld: Likewise.
* testsuite/ld-arc/sda-relocs.rd: Likewise.
* testsuite/ld-arc/sda-relocs.s: Likewise.
* testsuite/ld-arc/arc.exp: Add SDA tests.
binutils/
PR binutils/20337
* objdump.c (compare_symbols): For ELF, sort same value/type
symbols according to size.
ld/
* testsuite/ld-powerpc/elfv2exe.d: Update.
Fix a typo (__PMSIZE was written as __PMSIZE_) and add section alignment
for DATA and BSS.
ld/ChangeLog:
* scripttempl/ft32.sc (__PMSIZE): Correct __PMSIZE_.
(DATA): add ALIGN.
(BSS): add ALIGN
Before GCC 4.9, -flto is required for final LTO link. Add -flto to PR
ld/20321 test to support older versions of GCC.
* testsuite/ld-plugin/lto.exp: Add -flto to PR ld/20321 test.
2016-07-05 Andre Vieria <andre.simoesdiasvieira@arm.com>
* elf32-arm.c (THUMB32_MOVT): New veneer macro.
(THUMB32_MOVW): Likewise.
(elf32_arm_stub_long_branch_thumb2_only_pure): New.
(DEF_STUBS): Define long_branch_thumb2_only_pure.
(arm_stub_is_thumb): Add new veneer stub.
(arm_type_of_stub): Use new veneer.
(arm_stub_required_alignment): Add new veneer.
2016-07-05 Andre Vieria <andre.simoesdiasvieira@arm.com>
* testsuite/ld-arm/farcall-thumb2-purecode.d: New test result.
* testsuite/ld-arm/farcall-thumb2-purecode.s: New test.
* testsuite/ld-arm/arm-elf.exp: Run it.
If a plugin has been loaded already, we should warn and return, instead
of adding it on the plugin list.
PR ld/20321
* plugin.c (plugin_opt_plugin): Warn and return if plugin has
been loaded already.
* testsuite/ld-plugin/lto.exp: Run PR ld/20321 test.
* testsuite/ld-plugin/pr20321.c: New file.
* scripttempl/ft32.sc (__PMSIZE_): If not defined, set to 256K.
(__RAMSIZE): If not defined, set to 64K.
(MEMORY): Set the flash region size to __PMSIZE and the ram region
size to __RAMSIZE.
2016-07-01 Thomas Preud'homme <thomas.preudhomme@arm.com>
bfd/
* elf32-arm.c (using_thumb2_bl): New function.
(arm_type_of_stub): Declare thumb2 variable together and change type
to bfd_boolean. Use using_thumb2_bl () to determine whether
THM_MAX_FWD_BRANCH_OFFSET or THM2_MAX_FWD_BRANCH_OFFSET should be
checked for BL range.
(elf32_arm_final_link_relocate): Use using_thumb2_bl () to determine
the bit size of BL offset.
ld/
* testsuite/ld-arm/arm-elf.exp (Thumb-2 BL): Assemble for ARMv7.
(Thumb-2 BL on ARMv6-M): New testcase.
* testsuite/ld-arm/thumb2-bl.d: Do not try to match testcase filename.
* testsuite/ld-arm/thumb2-bl.s: Do not select architecture.
No need to check version if symbol is unreferenced and undefined.
bfd/
PR ld/20306
* elflink.c (elf_link_check_versioned_symbol): Return false
for unreferenced undefined symbol.
ld/testsuite/
* testsuite/ld-gc/gc.exp: Run pr20306 test.
* ld-gc/pr20306.c: New file.
* ld-gc/pr20306.d: Likewise.
bfin * elf32-bfin.c (bfin_adjust_dynamic_symbol): Fail if a COPY reloc
is needed.
ld * testsuite/ld-elf/comm-data.exp: Expect comm-data2 test to fail
for bfin.
* testsuite/ld-elf/elf.exp: Expect pr14170 and symbolic function
tests to fail for bfin.
* testsuite/ld-elf/endsym.d: Expect to fail with cr16, crx, dlx,
nds32 and visium.
* testsuite/ld-elf/var1.d: Expect to fail with d30v, dlx, ft32 and
microblaze.
* testsuite/ld-pe/pe.exp: Expect foreign symbol test to fail for
mcore-pe.
ld * testsuite/ld-elf/merge.d: Add m68hc11 to list of targets that
expect to fail this test.
* testsuite/ld-scripts/overlay-size.d: Skip the entire test for
RX.
* testsuite/ld-scripts/rgn-at10.d: No longer expect this test to
fail for the RX.
* testsuite/ld-scripts/rgn-at11.d: Likewise.
* testsuite/ld-scripts/rgn-at2.d: Likewise.
* testsuite/ld-scripts/rgn-at6.d: Likewise.
* testsuite/ld-scripts/rgn-at7.d: Likewise.
* testsuite/ld-scripts/rgn-at8.d: Likewise.
bfd * elfxx-sparc.c (_bfd_sparc_elf_relocate_section): Don't convert
R_SPARC_32 to R_SPARC_RELATIVE if class is ELFCLASS64.
gold * sparc.cc (Target_sparc::Scan::local): Don't convert R_SPARC_32
to R_SPARC_RELATIVE if class is ELFCLASS64.
(Target_sparc::Scan::global): Likewise.
ld * testsuite/ld-elf/symbolic-func.r: Allow non-zero offsets from
.text.
PR ld/20302
* lexsup.c (set_segment_start): If resetting the start address of
a section, remember to generate a new script element as well.
* testsuite/ld-scripts/pr20302.d: New test.
* testsuite/ld-scripts/scripts.exp: Run the new test.
Add a configure option --enable-relro to decide whether -z relro should
be enabled in ELF linker by default. Default to yes for all Linux
targets, except FRV, HPPA, IA64 and MIPS, since many relro tests fail
on these targets.
PR ld/20283
* NEWS: Mention --enable-relro.
* configure.ac: Add --enable-relro.
(DEFAULT_LD_Z_RELRO): New. Set by --enable-relro.
* configure.tgt (ac_default_ld_z_relro): Default it to 1 for
some Linux targets.
* config.in: Regenerated.
* configure: Likewise.
* emultempl/elf32.em (gld${EMULATION_NAME}_before_parse): Set
link_info.relro to DEFAULT_LD_Z_RELRO.
* testsuite/config/default.exp (ld_elf_shared_opt): New.
* testsuite/lib/ld-lib.exp (run_dump_test): Pass
$ld_elf_shared_opt to ld for ELF targets with shared object
support.
(run_ld_link_tests): Likewise.
As with commit ed53407eec ("MIPS/BFD: Don't stop processing on
`bfd_reloc_outofrange'") don't bail out right away and instead continue
processing on a cross-mode jump conversion error, so that any further
issues are also reported. Adjust message formatting accordingly, using
`%X' to abort processing at conclusion. Remove the full stop from the
end of the message, for consistency across error reporting.
Adjust the corresponding test case accordingly and make it trigger the
error twice.
bfd/
* elfxx-mips.c (mips_elf_perform_relocation): Call
`info->callbacks->einfo' rather than `*_bfd_error_handler' and
use the `%X%H' format for the cross-mode jump conversion error
message. Remove the full stop from the end of the message.
Continue processing rather than returning failure.
ld/
* testsuite/ld-mips-elf/mode-change-error-1a.s: Trigger an error
twice rather than once.
* testsuite/ld-mips-elf/mode-change-error-1.d: Adjust
accordingly. Remove the full stop from the end of the message.
ELF linker shouldn't skip the IR object when searching the symbol table
of an archive element. If linker doesn't know if the object file is an
IR object, it should give LTO plugin a chance to get the correct symbol
table and use the IR symbol table if the input is an IR object.
bfd/
PR ld/18250
PR ld/20267
* elflink.c: Include plugin.h if BFD_SUPPORTS_PLUGINS is
defined.
(elf_link_is_defined_archive_symbol): Call
bfd_link_plugin_object_p on unknown plugin object and use the
IR symbol table if the input is an IR object.
* plugin.c (bfd_link_plugin_object_p): New function.
* plugin.h (bfd_link_plugin_object_p): New prototype.
ld/
PR ld/20267
* testsuite/ld-plugin/lto.exp (lto_link_tests): Add test for
PR ld/20267.
(lto_run_tests): Likewise.
* testsuite/ld-plugin/pr20267a.c: New file.
* testsuite/ld-plugin/pr20267b.c: Likewise.
Also, don't check alignment on symbol from plugin dummy input.
bfd/
PR ld/20276
* elflink.c (elf_link_add_object_symbols): Don't check alignment
on symbol from plugin dummy input.
ld/
PR ld/20276
* plugin.c (plugin_notice): Set non_ir_ref on common symbols.
* testsuite/ld-plugin/lto.exp (lto_link_tests): Add test for
PR ld/20276.
(lto_run_tests): Likewise.
* testsuite/ld-plugin/pass.out: New file.
* testsuite/ld-plugin/pr20276a.c: Likewise.
* testsuite/ld-plugin/pr20276b.c: Likewise.
2016-06-17 Thomas Preud'homme <thomas.preudhomme@arm.com>
Tony Wang <tony.wang@arm.com>
bfd/
* elf32-arm.c (elf32_arm_stub_long_branch_thumb2_only): Define stub
sequence.
(stub_long_branch_thumb2_only): Define stub.
(arm_stub_is_thumb): Add case for arm_stub_long_branch_thumb2_only.
(arm_stub_long_branch_thumb2_only): Likewise.
(arm_type_of_stub): Use arm_stub_long_branch_thumb2_only for Thumb-2
capable targets.
ld/
* testsuite/ld-arm/arm-elf.exp (Thumb-Thumb farcall M profile):
Assemble for ARMv6-M.
(Thumb2-Thumb2 farcall M profile): New testcase.
* testsuite/ld-arm/farcall-thumb2-thumb2-m.d: New file.
* testsuite/ld-arm/jump-reloc-veneers-cond-long-backward.d: Update to
reflect the use of Thumb-2 veneers for Thumb-2 capable targets.
* testsuite/ld-arm/jump-reloc-veneers-cond-long.d: Likewise.
Since x86 elf_*_check_relocs is called after all symbols have been
resolved, there is no need to check undefined symbols for relocations
against IFUNC symbols.
bfd/
* elf32-i386.c (elf_i386_check_relocs): Don't check undefined
symbols for relocations against IFUNC symbols.
* elf64-x86-64.c (elf_x86_64_check_relocs): Likewise.
ld/
* testsuite/ld-i386/i386.exp: Run pr19636-2e-nacl.
* testsuite/ld-i386/pr19636-2e.d: Skip for NaCl targets.
Remove .rel.plt section.
* testsuite/ld-i386/pr19636-2e-nacl.d: New file.
This patch fixes another edge case related to alignment property
records - reloc offsets adjacent to property record offsets were not
getting adjusted during relaxation.
bfd/
PR ld/20254
* elf32-avr.c (elf32_avr_relax_delete_bytes): Adjust reloc
offsets until reloc_toaddr.
ld/
PR ld/20254
* testsuite/ld-avr/avr-prop-6.d: New test.
* testsuite/ld-avr/avr-prop-6.s: New test.
Many more places use abfd->my_archive rather than bfd_my_archive (abfd),
so let's make the code consistently use the first idiom.
bfd/
* bfd-in.h (bfd_my_archive): Delete.
* bfd-in2.h: Regenerate.
binutils/
* ar.c: Expand uses of bfd_my_archive.
* size.c: Likewise.
ld/
* ldlang.c: Expand uses of bfd_my_archive.
* ldmain.c: Likewise.
* ldmisc.c: Likewise.
* plugin.c: Likewise.
LTO plugin support in plugin_maybe_claim wants to close the IR bfd
after replacing it with the recompiled object, but can't do so for
archive elements due to various pointers that access the archive bfd.
Thin archives have the same problem. They too cannot have their
element bfds closed.
PR ld/20241
bfd/
* archive.c (open_nested_file): Set my_archive.
* bfd.c (_bfd_default_error_handler <%B>): Exclude archive file name
for thin archives.
* bfdio.c (bfd_tell): Don't adjust origin for thin archives.
(bfd_seek): Likewise.
* bfdwin.c (bfd_get_file_window): Likewise.
* cache.c (cache_bmmap): Likewise.
(bfd_cache_lookup_worker): Don't look in my_archive for thin archives.
* mach-o.c (bfd_mach_o_follow_dsym): Don't open my_archive for
thin archives.
* plugin.c (try_claim): Likewise.
* xcofflink.c (xcoff_link_add_dynamic_symbols): Use import path of
file within thin archive, not the archive.
binutils/
* bucomm.c (bfd_get_archive_filename): Return file name within thin
archive.
ld/
* ldmain.c (add_archive_element): Just print file name of file within
thin archives.
* ldmisc.c (vfinfo): Likewise.
* plugin.c (plugin_object_p): Open file within thin archives.
(plugin_maybe_claim): Expand comment.
Add the GOT base for R_386_GOT32/R_386_GOT32X relocations against IFUNC
symbols if there is no base register and disallow them for PIC.
bfd/
PR ld/20244
* elf32-i386.c (elf_i386_relocate_section): Add the .got.plt
section address for R_386_GOT32/R_386_GOT32X relocations against
IFUNC symbols if there is no base register and return error for
PIC.
ld/
PR ld/20244
* testsuite/ld-i386/i386.exp: Run pr20244-2a, pr20244-2b,
pr20244-2c and pr20244-2d.
* testsuite/ld-i386/no-plt.exp: Run pr20244-3a and pr20244-3b.
* testsuite/ld-i386/pr20244-2.s: New file.
* testsuite/ld-i386/pr20244-2a.d: Likewise.
* testsuite/ld-i386/pr20244-2b.d: Likewise.
* testsuite/ld-i386/pr20244-2c.d: Likewise.
* testsuite/ld-i386/pr20244-2d.d: Likewise.
* testsuite/ld-i386/pr20244-3a.c: Likewise.
* testsuite/ld-i386/pr20244-3b.S: Likewise.
* testsuite/ld-i386/pr20244-3c.S: Likewise.
* testsuite/ld-i386/pr20244-3d.S: Likewise.
When relocating R_386_GOT32 in "op $0, bar@GOT", we shouldn't subtract
GOT base without a base register and we should disallow it without a
base register for PIC.
bfd/
PR ld/20244
* elf32-i386.c (elf_i386_relocate_section): When relocating
R_386_GOT32, return error without a base register for PIC and
subtract the .got.plt section address only with a base register.
ld/
PR ld/20244
* testsuite/ld-i386/i386.exp: Run pr20244-1a and pr20244-1b.
* testsuite/ld-i386/pr20244-1.s: New file.
* testsuite/ld-i386/pr20244-1a.d: Likewise.
* testsuite/ld-i386/pr20244-1b.d: Likewise.
* testsuite/ld-i386/pr20244-1c.d: Likewise.
This patch fixes an edge case in linker relaxation that causes symbol
values to be computed incorrectly in the presence of align directives
in input source code.
bfd/
* elf32-avr.c (elf32_avr_relax_delete_bytes): Adjust syms
and relocs only if shrinking occurred.
ld/
* testsuite/ld-avr/avr-prop-5.d: New.
* testsuite/ld-avr/avr-prop-5.s: New.
This patch adds default data address space origin (0x800000) to the symbol addresses.
when disassemble lds/sts instructions. So that symbol names shall be printed in comments
for lds/sts instructions disassemble.
ld/
* testsuite/ld-avr/lds-mega.d: New test.
* testsuite/ld-avr/lds-mega.s: New test source.
* testsuite/ld-avr/lds-tiny.d: New test.
* testsuite/ld-avr/lds-tiny.s: New test source.
opcodes/
* avr-dis.c (avr_operand): Add default data address space origin (0x800000) to the
address and set as symbol address for LDS/ STS immediate operands.
To call an external function, the direct branch to the PLT entry can be
replaced by an indirect branch via the GOT slot, which is similar to the
first instruction in the PLT slot. Instead using the PLT slot as function
address, the function address is retrieved from the GOT slot. The
R_386_GOT32X relocation can be used to compute the address of the symbol’s
GOT entry without base register when PIC is disabled. In non-PIC
executable,
call/jmp *func@GOT
should be used for indirect branch via the GOT slot and
movl func@GOT, %eax
should be used to load function address. Unlike PIC case, no register
is needed to access GOT. If linker determines the function is defined
locally, it converts indirect branch via the GOT slot to direct branch
with a nop prefix and converts load via the GOT slot to load immediate
or lea.
* testsuite/ld-i386/libno-plt-1b.dd: New file.
* testsuite/ld-i386/libno-plt-1b.rd: Likewise.
* testsuite/ld-i386/no-plt-1a.dd: Likewise.
* testsuite/ld-i386/no-plt-1a.rd: Likewise.
* testsuite/ld-i386/no-plt-1b.dd: Likewise.
* testsuite/ld-i386/no-plt-1b.rd: Likewise.
* testsuite/ld-i386/no-plt-1c.dd: Likewise.
* testsuite/ld-i386/no-plt-1c.rd: Likewise.
* testsuite/ld-i386/no-plt-1d.dd: Likewise.
* testsuite/ld-i386/no-plt-1d.rd: Likewise.
* testsuite/ld-i386/no-plt-1e.dd: Likewise.
* testsuite/ld-i386/no-plt-1e.rd: Likewise.
* testsuite/ld-i386/no-plt-1f.dd: Likewise.
* testsuite/ld-i386/no-plt-1f.rd: Likewise.
* testsuite/ld-i386/no-plt-1g.dd: Likewise.
* testsuite/ld-i386/no-plt-1g.rd: Likewise.
* testsuite/ld-i386/no-plt-1h.dd: Likewise.
* testsuite/ld-i386/no-plt-1h.rd: Likewise.
* testsuite/ld-i386/no-plt-1i.dd: Likewise.
* testsuite/ld-i386/no-plt-1i.rd: Likewise.
* testsuite/ld-i386/no-plt-1j.dd: Likewise.
* testsuite/ld-i386/no-plt-1j.rd: Likewise.
* testsuite/ld-i386/no-plt-check1a.S: Likewise.
* testsuite/ld-i386/no-plt-check1b.S: Likewise.
* testsuite/ld-i386/no-plt-extern1a.S: Likewise.
* testsuite/ld-i386/no-plt-extern1b.S: Likewise.
* testsuite/ld-i386/no-plt-func1.c: Likewise.
* testsuite/ld-i386/no-plt-main1.c: Likewise.
* testsuite/ld-i386/no-plt.exp: Likewise.
We can generate i386 TLS code sequences for general and local dynamic
models without PLT, which uses indirect call via GOT:
call *___tls_get_addr@GOT(%reg)
where EBX register isn't required as GOT base, instead of direct call:
call ___tls_get_addr[@PLT]
which requires EBX register as GOT base.
Since direct call is 4-byte long and indirect call, is 5-byte long, the
extra one byte must be handled properly.
For general dynamic model, 7-byte lea instruction before call instruction
is replaced by 6-byte one to make room for indirect call. For local
dynamic model, we simply use 5-byte indirect call.
TLS linker optimization is updated to recognize new instruction patterns.
For local dynamic model to local exec model transition, we generate
a 6-byte lea instruction as nop, instead of a 1-byte nop plus a 4-byte
lea instruction. Since linker may convert
call ___tls_get_addr[@PLT]
to
addr32 call ____tls_get_addr
when producing static executable, both patterns are recognized.
bfd/
* elf64-i386.c (elf_i386_link_hash_entry): Add tls_get_addr.
(elf_i386_link_hash_newfunc): Initialize tls_get_addr to 2.
(elf_i386_check_tls_transition): Check indirect call and direct
call with the addr32 prefix for general and local dynamic models.
Set the tls_get_addr feild.
(elf_i386_convert_load_reloc): Always use addr32 prefix for
indirect ___tls_get_addr call via GOT.
(elf_i386_relocate_section): Handle GD->LE, GD->IE and LD->LE
transitions with indirect call and direct call with the addr32
prefix.
ld/
* testsuite/ld-i386/i386.exp: Run libtlspic2.so, tlsbin2,
tlsgd3, tlsld2, tlsgd4, tlspie3a, tlspie3b and tlspie3c.
* testsuite/ld-i386/pass.out: New file.
* testsuite/ld-i386/tls-def1.c: Likewise.
* testsuite/ld-i386/tls-gd1.S: Likewise.
* testsuite/ld-i386/tls-ld1.S: Likewise.
* testsuite/ld-i386/tls-main1.c: Likewise.
* testsuite/ld-i386/tls.exp: Likewise.
* testsuite/ld-i386/tlsbin2-nacl.rd: Likewise.
* testsuite/ld-i386/tlsbin2.dd: Likewise.
* testsuite/ld-i386/tlsbin2.rd: Likewise.
* testsuite/ld-i386/tlsbin2.sd: Likewise.
* testsuite/ld-i386/tlsbin2.td: Likewise.
* testsuite/ld-i386/tlsbinpic2.s: Likewise.
* testsuite/ld-i386/tlsgd3.dd: Likewise.
* testsuite/ld-i386/tlsgd3.s: Likewise.
* testsuite/ld-i386/tlsgd4.d: Likewise.
* testsuite/ld-i386/tlsgd4.s: Likewise.
* testsuite/ld-i386/tlsld2.s: Likewise.
* testsuite/ld-i386/tlspic2-nacl.rd: Likewise.
* testsuite/ld-i386/tlspic2.dd: Likewise.
* testsuite/ld-i386/tlspic2.rd: Likewise.
* testsuite/ld-i386/tlspic2.sd: Likewise.
* testsuite/ld-i386/tlspic2.td: Likewise.
* testsuite/ld-i386/tlspic3.s: Likewise.
* testsuite/ld-i386/tlspie3.s: Likewise.
* testsuite/ld-i386/tlspie3a.d: Likewise.
* testsuite/ld-i386/tlspie3b.d: Likewise.
* testsuite/ld-i386/tlspie3c.d: Likewise.
To call an external function, the direct branch to the PLT entry can be
replaced by an indirect branch via the GOT slot, which is similar to the
first instruction in the PLT slot. Instead using the PLT slot as function
address, the function address is retrieved from the GOT slot. If linker
determines the function is defined locally, it converts indirect branch
via the GOT slot to direct branch with a nop prefix and converts load via
the GOT slot to load immediate or lea,
* testsuite/ld-x86-64/libno-plt-1b.dd: Likewise.
* testsuite/ld-x86-64/libno-plt-1b.rd: Likewise.
* testsuite/ld-x86-64/no-plt-1a.dd: Likewise.
* testsuite/ld-x86-64/no-plt-1a.rd: Likewise.
* testsuite/ld-x86-64/no-plt-1b.dd: Likewise.
* testsuite/ld-x86-64/no-plt-1b.rd: Likewise.
* testsuite/ld-x86-64/no-plt-1c.dd: Likewise.
* testsuite/ld-x86-64/no-plt-1c.rd: Likewise.
* testsuite/ld-x86-64/no-plt-1d.dd: Likewise.
* testsuite/ld-x86-64/no-plt-1d.rd: Likewise.
* testsuite/ld-x86-64/no-plt-1e.dd: Likewise.
* testsuite/ld-x86-64/no-plt-1e.rd: Likewise.
* testsuite/ld-x86-64/no-plt-1f.dd: Likewise.
* testsuite/ld-x86-64/no-plt-1f.rd: Likewise.
* testsuite/ld-x86-64/no-plt-1g.dd: Likewise.
* testsuite/ld-x86-64/no-plt-1g.rd: Likewise.
* testsuite/ld-x86-64/no-plt-check1.S: Likewise.
* testsuite/ld-x86-64/no-plt.exp: Likewise.
* testsuite/ld-x86-64/no-plt-extern1.S: Likewise.
* testsuite/ld-x86-64/no-plt-func1.c: Likewise.
* testsuite/ld-x86-64/no-plt-main1.c: Likewise.
Revert the addition of `ft32-*-*' to this test case made with commit
d1f70bdcab ("Fix lots of linker testsuite failures for the FT32
target.") as this case scores an XPASS now.
ld/
* testsuite/ld-elf/init-fini-arrays.d: Remove `ft32-*-*' xfail.
Embedding the .plt section in another revealed a bug in the way the
larl operand of the first magic plt entry is being calculated. Fixed
with the attached patch.
bfd/ChangeLog:
* elf64-s390.c (elf_s390_finish_dynamic_sections): Subtract plt
section offset when calculation the larl operand in the first PLT
entry.
ld/ChangeLog:
* testsuite/ld-s390/pltoffset-1.dd: New test.
* testsuite/ld-s390/pltoffset-1.ld: New test.
* testsuite/ld-s390/pltoffset-1.s: New test.
* testsuite/ld-s390/s390.exp: Run new test.
VLE is an encoding, not a particular processor architecture, so it
isn't really proper to select insns based on PPC_OPCODE_VLE. For
example
{"evaddw", VX (4, 512), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"vaddubs", VX (4, 512), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
shows two insns that have the same encoding, both available with VLE.
Enabling both with VLE means we can't disassemble the second variant
even if -Maltivec is given rather than -Mspe. Also, we don't check
user assembly against the processor type as well as we could.
Another problem is that when using the VLE encoding, insns from the
main ppc opcode table are not available, except those using opcode 4
and 31. Correcting this revealed two errors in the ld testsuite,
use of "nop" and "rfmci" when -mvle.
This patch fixes those problems in the opcode table, and removes
PPCNONE. I find a plain 0 distracts less from other values.
In addition, I've implemented code to recognize some machine values
from the apuinfo note present in ppc32 objects. It's not a complete
disambiguation since we're lacking info to detect newer chips, but
what we have should help with disassembly.
include/
* elf/ppc.h (APUINFO_SECTION_NAME, APUINFO_LABEL, PPC_APUINFO_ISEL,
PPC_APUINFO_PMR, PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK,
PPC_APUINFO_SPE, PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK,
PPC_APUINFO_VLE: Define.
opcodes/
* ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
cpu for "vle" to e500.
* ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
(NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
(PPCNONE): Delete, substitute throughout.
(powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
except for major opcode 4 and 31.
(vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
bfd/
* cpu-powerpc.c (powerpc_compatible): Allow bfd_mach_ppc_vle entry
to match other 32-bit archs.
* elf32-ppc.c (_bfd_elf_ppc_set_arch): New function.
(ppc_elf_object_p): Call it.
(ppc_elf_special_sections): Use APUINFO_SECTION_NAME. Fix
overlong line.
(APUINFO_SECTION_NAME, APUINFO_LABEL): Don't define here.
* elf64-ppc.c (ppc64_elf_object_p): Call _bfd_elf_ppc_set_arch.
* bfd-in.h (_bfd_elf_ppc_at_tls_transform,
_bfd_elf_ppc_at_tprel_transform): Move to..
* elf-bfd.h: ..here.
(_bfd_elf_ppc_set_arch): Declare.
* bfd-in2.h: Regenerate.
gas/
* config/tc-ppc.c (PPC_APUINFO_ISEL, PPC_APUINFO_PMR,
PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK, PPC_APUINFO_SPE,
PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK, PPC_APUINFO_VLE): Don't define.
(ppc_setup_opcodes): Check vle disables powerpc_opcodes overridden
by vle_opcodes, and that vle flag doesn't enable opcodes. Don't
add vle_opcodes twice.
(ppc_cleanup): Use APUINFO_SECTION_NAME and APUINFO_LABEL.
ld/
* testsuite/ld-powerpc/apuinfo1.s: Delete nop.
* testsuite/ld-powerpc/apuinfo-vle2.s: New.
* testsuite/ld-powerpc/powerpc.exp: Use apuinfo-vle2.s.
We can generate x86-64 TLS code sequences for general and local dynamic
models without PLT, which uses indirect call via GOT:
call *__tls_get_addr@GOTPCREL(%rip)
instead of direct call:
call __tls_get_addr[@PLT]
Since direct call is 4-byte long and indirect call, is 5-byte long, the
extra one byte must be handled properly.
For general dynamic model, one 0x66 prefix before call instruction is
removed to make room for indirect call. For local dynamic model, we
simply use 5-byte indirect call.
TLS linker optimization is updated to recognize new instruction patterns.
For local dynamic model to local exec model transition, we generate
4 0x66 prefixes, instead of 3, before mov instruction in 64-bit and
generate a 5-byte nop, instead of 4-byte, before mov instruction in
32-bit. Since linker may convert
call *__tls_get_addr@GOTPCREL(%rip)
to
addr32 call __tls_get_addr
when producing static executable, both patterns are recognized.
bfd/
* elf64-x86-64.c (elf_x86_64_link_hash_entry): Add tls_get_addr.
(elf_x86_64_link_hash_newfunc): Initialize tls_get_addr to 2.
(elf_x86_64_check_tls_transition): Check indirect call and
direct call with the addr32 prefix for general and local dynamic
models. Set the tls_get_addr feild.
(elf_x86_64_convert_load_reloc): Always use addr32 prefix for
indirect __tls_get_addr call via GOT.
(elf_x86_64_relocate_section): Handle GD->LE, GD->IE and LD->LE
transitions with indirect call and direct call with the addr32
prefix.
ld/
* testsuite/ld-x86-64/pass.out: New file.
* testsuite/ld-x86-64/tls-def1.c: Likewise.
* testsuite/ld-x86-64/tls-gd1.S: Likewise.
* testsuite/ld-x86-64/tls-ld1.S: Likewise.
* testsuite/ld-x86-64/tls-main1.c: Likewise.
* testsuite/ld-x86-64/tls.exp: Likewise.
* testsuite/ld-x86-64/tlsbin2-nacl.rd: Likewise.
* testsuite/ld-x86-64/tlsbin2.dd: Likewise.
* testsuite/ld-x86-64/tlsbin2.rd: Likewise.
* testsuite/ld-x86-64/tlsbin2.sd: Likewise.
* testsuite/ld-x86-64/tlsbin2.td: Likewise.
* testsuite/ld-x86-64/tlsbinpic2.s: Likewise.
* testsuite/ld-x86-64/tlsgd10.dd: Likewise.
* testsuite/ld-x86-64/tlsgd10.s: Likewise.
* testsuite/ld-x86-64/tlsgd11.dd: Likewise.
* testsuite/ld-x86-64/tlsgd11.s: Likewise.
* testsuite/ld-x86-64/tlsgd12.d: Likewise.
* testsuite/ld-x86-64/tlsgd12.s: Likewise.
* testsuite/ld-x86-64/tlsgd13.d: Likewise.
* testsuite/ld-x86-64/tlsgd13.s: Likewise.
* testsuite/ld-x86-64/tlsgd14.dd: Likewise.
* testsuite/ld-x86-64/tlsgd14.s: Likewise.
* testsuite/ld-x86-64/tlsgd5c.s: Likewise.
* testsuite/ld-x86-64/tlsgd6c.s: Likewise.
* testsuite/ld-x86-64/tlsgd9.dd: Likewise.
* testsuite/ld-x86-64/tlsgd9.s: Likewise.
* testsuite/ld-x86-64/tlsld4.dd: Likewise.
* testsuite/ld-x86-64/tlsld4.s: Likewise.
* testsuite/ld-x86-64/tlsld5.dd: Likewise.
* testsuite/ld-x86-64/tlsld5.s: Likewise.
* testsuite/ld-x86-64/tlsld6.dd: Likewise.
* testsuite/ld-x86-64/tlsld6.s: Likewise.
* testsuite/ld-x86-64/tlspic2-nacl.rd: Likewise.
* testsuite/ld-x86-64/tlspic2.dd: Likewise.
* testsuite/ld-x86-64/tlspic2.rd: Likewise.
* testsuite/ld-x86-64/tlspic2.sd: Likewise.
* testsuite/ld-x86-64/tlspic2.td: Likewise.
* testsuite/ld-x86-64/tlspic3.s: Likewise.
* testsuite/ld-x86-64/tlspie2.s: Likewise.
* testsuite/ld-x86-64/tlspie2a.d: Likewise.
* testsuite/ld-x86-64/tlspie2b.d: Likewise.
* testsuite/ld-x86-64/tlspie2c.d: Likewise.
* testsuite/ld-x86-64/tlsgd5.dd: Updated.
* testsuite/ld-x86-64/tlsgd6.dd: Likewise.
* testsuite/ld-x86-64/x86-64.exp: Run libtlspic2.so, tlsbin2,
tlsgd5b, tlsgd6b, tlsld4, tlsld5, tlsld6, tlsgd9, tlsgd10,
tlsgd11, tlsgd14, tlsgd12, tlsgd13, tlspie2a, tlspie2b and
tlspie2c.
bfd/
* coff-z8k.c (extra_case): Fix range check for R_JR relocation.
ld/
* ld/testsuite/ld-z8k/0filler.s: New file.
* ld/testsuite/ld-z8k/branch-target.s: New file.
* ld/testsuite/ld-z8k/branch-target2.s: New file.
* ld/testsuite/ld-z8k/calr-back-8001.d: New file.
* ld/testsuite/ld-z8k/calr-back-8002.d: New file.
* ld/testsuite/ld-z8k/calr-back-fail-8001.d: New file.
* ld/testsuite/ld-z8k/calr-back-fail-8002.d: New file.
* ld/testsuite/ld-z8k/calr-forw-8001.d: New file.
* ld/testsuite/ld-z8k/calr-forw-8002.d: New file.
* ld/testsuite/ld-z8k/calr-forw-fail-8001.d: New file.
* ld/testsuite/ld-z8k/calr-forw-fail-8002.d: New file.
* ld/testsuite/ld-z8k/calr-opcode.s: New file.
* ld/testsuite/ld-z8k/dbjnz-forw-8001.d: New file.
* ld/testsuite/ld-z8k/dbjnz-forw-8002.d: New file.
* ld/testsuite/ld-z8k/dbjnz-forw-fail-8001.d: New file.
* ld/testsuite/ld-z8k/dbjnz-forw-fail-8002.d: New file.
* ld/testsuite/ld-z8k/dbjnz-opcode.s: New file.
* ld/testsuite/ld-z8k/djnz-back-8001.d: New file.
* ld/testsuite/ld-z8k/djnz-back-8002.d: New file.
* ld/testsuite/ld-z8k/djnz-back-fail-8001.d: New file.
* ld/testsuite/ld-z8k/djnz-back-fail-8002.d: New file.
* ld/testsuite/ld-z8k/djnz-forw-8001.d: New file.
* ld/testsuite/ld-z8k/djnz-forw-8002.d: New file.
* ld/testsuite/ld-z8k/djnz-forw-fail-8001.d: New file.
* ld/testsuite/ld-z8k/djnz-forw-fail-8002.d: New file.
* ld/testsuite/ld-z8k/djnz-opcode.s: New file.
* ld/testsuite/ld-z8k/filler.s: New file.
* ld/testsuite/ld-z8k/jr-back-8001.d: New file.
* ld/testsuite/ld-z8k/jr-back-8002.d: New file.
* ld/testsuite/ld-z8k/jr-back-fail-8001.d: New file.
* ld/testsuite/ld-z8k/jr-back-fail-8002.d: New file.
* ld/testsuite/ld-z8k/jr-forw-8001.d: New file.
* ld/testsuite/ld-z8k/jr-forw-8002.d: New file.
* ld/testsuite/ld-z8k/jr-forw-fail-8001.d: New file.
* ld/testsuite/ld-z8k/jr-forw-fail-8002.d: New file.
* ld/testsuite/ld-z8k/jr-opcode.s: New file.
* ld/testsuite/ld-z8k/ldr-back-8001.d: New file.
* ld/testsuite/ld-z8k/ldr-back-8002.d: New file.
* ld/testsuite/ld-z8k/ldr-back-fail-8001.d: New file.
* ld/testsuite/ld-z8k/ldr-back-fail-8002.d: New file.
* ld/testsuite/ld-z8k/ldr-forw-8001.d: New file.
* ld/testsuite/ld-z8k/ldr-forw-8002.d: New file.
* ld/testsuite/ld-z8k/ldr-forw-fail-8001.d: New file.
* ld/testsuite/ld-z8k/ldr-forw-fail-8002.d: New file.
* ld/testsuite/ld-z8k/ldr-opcode.s: New file.
* ld/testsuite/ld-z8k/ldrb-forw-8001.d: New file.
* ld/testsuite/ld-z8k/ldrb-forw-8002.d: New file.
* ld/testsuite/ld-z8k/ldrb-forw-fail-8001.d: New file.
* ld/testsuite/ld-z8k/ldrb-forw-fail-8002.d: New file.
* ld/testsuite/ld-z8k/ldrb-opcode.s: New file.
* ld/testsuite/ld-z8k/ldrb-opcode2.s: New file.
* ld/testsuite/ld-z8k/other-file.s: New file.
* ld/testsuite/ld-z8k/reloc.dd: New file.
* ld/testsuite/ld-z8k/reloc.ld: New file.
* ld/testsuite/ld-z8k/relocseg.dd: New file.
* ld/testsuite/ld-z8k/relocseg.ld: New file.
* ld/testsuite/ld-z8k/relocseg1.dd: New file.
* ld/testsuite/ld-z8k/test-ld.sh: New file.
* ld/testsuite/ld-z8k/this-file.s: New file.
* ld/testsuite/ld-z8k/z8k.exp: New file.
Fix internal errors like:
ld: BFD (GNU Binutils) 2.26.51.20160526 internal error, aborting at .../bfd/elfxx-mips.c:10278 in _bfd_mips_elf_relocate_section
ld: Please report this bug.
triggered by the `bfd_reloc_outofrange' condition on branch relocations.
bfd/
* elfxx-mips.c (b_reloc_p): New function.
(_bfd_mips_elf_relocate_section) <bfd_reloc_outofrange>: Handle
branch relocations.
ld/
* testsuite/ld-mips-elf/unaligned-branch.d: New test.
* testsuite/ld-mips-elf/unaligned-branch.s: New test source.
* testsuite/ld-mips-elf/unaligned-text.s: New test source.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new test.
The original MIPS SVR4 psABI defines the calculation for the R_MIPS_26
relocation in a complex way, as follows[1]:
Name Value Field Symbol Calculation
R_MIPS_26 4 T-targ26 local (((A << 2) | \
(P & 0xf0000000)) + S) >> 2
4 T-targ26 external (sign-extend(A << 2) + S) >> 2
This is further clarified, by correcting typos (already applied in the
excerpt above) in the 64-bit psABI extension[2]. A note is included in
both documents to specify that for the purpose of relocation processing
a local symbol is one with binding STB_LOCAL and type STT_SECTION, and
otherwise, a symbol is external.
We have both calculations implemented for the R_MIPS_26 relocation, and
by extension also for the R_MIPS16_26 and R_MICROMIPS_26_S1 relocations,
from now on collectively called jump relocations. However our code uses
a different condition to tell local and external symbols apart, that is
it only checks for the STB_LOCAL binding and ignores the symbol type,
however for REL relocations only. The external calculation is used for
all RELA jump relocations.
In reality the difference matters for jump relocations referring local
MIPS16 and, as from recent commit 44d3da2338 ("MIPS/GAS: Treat local
jump relocs the same no matter if REL or RELA"), also local microMIPS
symbols. Such relocations are not converted to refer to corresponding
section symbols instead and retain the original local symbol reference.
It can be inferred from the relocation calculation definitions that the
addend is effectively unsigned for the local case and explicitly signed
for the external case. With the REL relocation format it makes sense
given the limited range provided for by the field being relocated: the
use of an unsigned addend expands the range by one bit for the local
case, because a negative offset from a section symbol makes no sense,
and any usable negative offset from the original local symbol will have
worked out positive if converted to a section-relative reference. In
the external case a signed addend gives more flexibility as offsets both
negative and positive can be used with a symbol. Any such offsets will
typically have a small value.
The inclusion of the (P & 0xf0000000) component, ORed in the calculation
in the local case, seems questionable as bits 31:28 are not included in
the relocatable field and are masked out as the relocation is applied.
Their value is therefore irrelevant for output processing, the relocated
field ends up the same regardless of their value. They could be used
for overflow detection, however this is precluded by adding them to bits
31:28 of the symbol referred, as the sum will not correspond to the
value calculated by the processor at run time whenever bits 31:28 of the
symbol referred are not all zeros, even though it is valid as long they
are the same as bits 31:28 of P.
We deal with this problem by ignoring any overflow resulting from the
local calculation. This however makes us miss genuine overflow cases,
where 31:28 of the symbol referred are different from bits 31:28 of P,
and non-functional code is produced.
Given the situation, for the purpose of overflow detection we can change
our code to follow the original psABI and only treat the in-place addend
as unsigned in the section symbol case, permitting jumps to offsets
128MiB and above into section. Sections so large may be uncommon, but
still a reasonable use case. On the other hand such large offsets from
regular local symbols are not expected and it makes sense to support
(possibly small) negative offsets instead, also in consistency with what
we do for global symbols.
Drop the (P & 0xf0000000) component then, treat the addend as signed
with local non-section symbols and also detect an overflow in the result
of such calculation with local symbols. NB it does not affect the value
computed for the relocatable field, it only affects overflow detection.
References:
[1] "SYSTEM V APPLICATION BINARY INTERFACE, MIPS RISC Processor
Supplement, 3rd Edition", Figure 4-11: "Relocation Types", p. 4-19
<http://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf>
[2] "64-bit ELF Object File Specification, Draft Version 2.5", Table 32
"Relocation Types", p. 45
<http://techpubs.sgi.com/library/manuals/4000/007-4658-001/pdf/007-4658-001.pdf>
bfd/
* elfxx-mips.c (mips_elf_calculate_relocation): <R_MIPS16_26>
<R_MIPS_26, R_MICROMIPS_26_S1>: Drop the region bits of the
reloc location from calculation, treat the addend as signed with
local non-section symbols and enable overflow detection.
ld/
* testsuite/ld-mips-elf/jal-global-overflow-0.d: New test.
* testsuite/ld-mips-elf/jal-global-overflow-1.d: New test.
* testsuite/ld-mips-elf/jal-local-overflow-0.d: New test.
* testsuite/ld-mips-elf/jal-local-overflow-1.d: New test.
* testsuite/ld-mips-elf/jal-global-overflow.s: New test source.
* testsuite/ld-mips-elf/jal-local-overflow.s: New test source.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
On RELA targets the addend can affect JALX target's alignment, so only
verify it once the whole relocation calculation has completed.
bfd/
* elfxx-mips.c (mips_elf_calculate_relocation) <R_MIPS16_26>
<R_MIPS_26, R_MICROMIPS_26_S1>: Include the addend in JALX's
target alignment verification.
ld/
* testsuite/ld-mips-elf/unaligned-jalx-addend-0.d: New test.
* testsuite/ld-mips-elf/unaligned-jalx-addend-1.d: New test.
* testsuite/ld-mips-elf/unaligned-jalx-addend-mips16-0.d: New
test.
* testsuite/ld-mips-elf/unaligned-jalx-addend-mips16-1.d: New
test.
* testsuite/ld-mips-elf/unaligned-jalx-addend-micromips-0.d: New
test.
* testsuite/ld-mips-elf/unaligned-jalx-addend-micromips-1.d: New
test.
* testsuite/ld-mips-elf/unaligned-jalx-addend-0.s: New test
source.
* testsuite/ld-mips-elf/unaligned-jalx-addend-1.s: New test
source.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
Symbol table entries for section symbols are different between IRIX and
traditional MIPS ELF targets in that IRIX entries have their `st_name'
member pointing at the section's name in the string table section, while
traditional entries have 0 there and the section header string table has
to be referred via the relevant section header's `shn_name' member
instead.
This is chosen with the `elf_backend_name_local_section_symbols' backend
and can be observed with `readelf -s' output for an IRIX object:
Symbol table '.symtab' contains 12 entries:
Num: Value Size Type Bind Vis Ndx Name
0: 00000000 0 NOTYPE LOCAL DEFAULT UND
1: 00000000 0 SECTION LOCAL DEFAULT 1 .text
2: 00000000 0 SECTION LOCAL DEFAULT 3 .data
3: 00000000 0 SECTION LOCAL DEFAULT 4 .bss
4: 00000000 0 SECTION LOCAL DEFAULT 5 .reginfo
5: 00000000 0 SECTION LOCAL DEFAULT 6 .MIPS.abiflags
6: 00000000 0 SECTION LOCAL DEFAULT 7 .pdr
7: 00000000 0 SECTION LOCAL DEFAULT 9 .gnu.attributes
8: 00002000 16 FUNC GLOBAL DEFAULT 1 foo
9: 00004008 0 FUNC LOCAL DEFAULT 1 abar
10: 00002008 0 FUNC LOCAL DEFAULT 1 afoo
11: 00004000 16 FUNC GLOBAL DEFAULT 1 bar
and a corresponding traditional object:
Symbol table '.symtab' contains 12 entries:
Num: Value Size Type Bind Vis Ndx Name
0: 00000000 0 NOTYPE LOCAL DEFAULT UND
1: 00000000 0 SECTION LOCAL DEFAULT 1
2: 00000000 0 SECTION LOCAL DEFAULT 3
3: 00000000 0 SECTION LOCAL DEFAULT 4
4: 00004008 0 FUNC LOCAL DEFAULT 1 abar
5: 00002008 0 FUNC LOCAL DEFAULT 1 afoo
6: 00000000 0 SECTION LOCAL DEFAULT 5
7: 00000000 0 SECTION LOCAL DEFAULT 6
8: 00000000 0 SECTION LOCAL DEFAULT 7
9: 00000000 0 SECTION LOCAL DEFAULT 9
10: 00002000 16 FUNC GLOBAL DEFAULT 1 foo
11: 00004000 16 FUNC GLOBAL DEFAULT 1 bar
respectively. Consequently the right way to retrieve a section symbol's
name has to be chosen in `mips_elf_calculate_relocation' for the purpose
of error reporting.
Originally we produced symbol tables in the traditional object format
only and we handled it correctly until it was lost in a rewrite with:
commit 7403cb6305
Author: Mark Mitchell <mark@codesourcery.com>
Date: Wed Jun 30 20:13:43 1999 +0000
probably because of the extra pointer indirection added which made the
same expression have a different meaning.
With the addition of IRIX symbol table format with:
commit 174fd7f955
Author: Richard Sandiford <rdsandiford@googlemail.com>
Date: Mon Feb 9 08:04:00 2004 +0000
the bug has been partially covered and now when a relocation error is
triggered with an IRIX object the offending section symbol is correctly
reported:
tmpdir/dump0.o: In function `foo':
(.text+0x2000): relocation truncated to fit: R_MIPS_26 against `.text'
tmpdir/dump0.o: In function `bar':
(.text+0x4000): relocation truncated to fit: R_MIPS_26 against `.text'
because `bfd_elf_string_from_elf_section' retrieves the name from the
string table section. With a traditional object however the function
returns an empty string and consequently `no symbol' is printed instead:
tmpdir/dump0.o: In function `foo':
(.text+0x2000): relocation truncated to fit: R_MIPS_26 against `no symbol'
tmpdir/dump0.o: In function `bar':
(.text+0x4000): relocation truncated to fit: R_MIPS_26 against `no symbol'
Restore the original semantics so that the section name is always
correctly retrieved.
bfd/
* elfxx-mips.c (mips_elf_calculate_relocation): Also use the
section name if `bfd_elf_string_from_elf_section' returns an
empty string.
ld/
* testsuite/ld-mips-elf/reloc-local-overflow.d: New test.
* testsuite/ld-mips-elf/reloc-local-overflow.s: Source for the
new test.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new test.
Upon a `bfd_reloc_outofrange' error continue processing so that any
further issues are also reported, similarly to how `bfd_reloc_overflow'
is handled. Adjust message formatting accordingly, using `%X' to abort
processing at conclusion.
Reduce the number of test cases by grouping relocations the handling of
which can now be verified together with a single source and dump.
bfd/
* elfxx-mips.c (_bfd_mips_elf_relocate_section)
<bfd_reloc_outofrange>: Use the `%X%H' rather than `%C' format
for message. Continue processing rather than returning failure.
ld/
* testsuite/ld-mips-elf/unaligned-jalx-0.d: Fold
`unaligned-jalx-2' here.
* testsuite/ld-mips-elf/unaligned-jalx-mips16-0.d: Fold
`unaligned-jalx-mips16-2' here.
* testsuite/ld-mips-elf/unaligned-jalx-micromips-0.d: Fold
`unaligned-jalx-micromips-2' here.
* testsuite/ld-mips-elf/unaligned-jalx-0.s: Update accordingly.
* testsuite/ld-mips-elf/unaligned-jalx-1.d: Update error
message.
* testsuite/ld-mips-elf/unaligned-jalx-mips16-1.d: Likewise.
* testsuite/ld-mips-elf/unaligned-jalx-micromips-1.d: Likewise.
* testsuite/ld-mips-elf/unaligned-jalx-2.d: Remove test.
* testsuite/ld-mips-elf/unaligned-jalx-mips16-2.d: Remove test.
* testsuite/ld-mips-elf/unaligned-jalx-micromips-2.d: Remove
test.
* testsuite/ld-mips-elf/unaligned-jalx-2.s: Remove test source.
* testsuite/ld-mips-elf/unaligned-lwpc-0.d: Fold
`unaligned-lwpc-3' here.
* testsuite/ld-mips-elf/unaligned-lwpc-0.s: Update accordingly.
* testsuite/ld-mips-elf/unaligned-lwpc-1.d: Fold
`unaligned-lwpc-2' here.
* testsuite/ld-mips-elf/unaligned-lwpc-1.s: Update accordingly.
* testsuite/ld-mips-elf/unaligned-lwpc-2.d: Remove test.
* testsuite/ld-mips-elf/unaligned-lwpc-2.s: Remove test source.
* testsuite/ld-mips-elf/unaligned-lwpc-3.d: Remove test.
* testsuite/ld-mips-elf/unaligned-lwpc-3.s: Remove test source.
* testsuite/ld-mips-elf/unaligned-ldpc-0.d: Fold
`unaligned-ldpc-4' here.
* testsuite/ld-mips-elf/unaligned-ldpc-0.s: Update accordingly.
* testsuite/ld-mips-elf/unaligned-ldpc-1.d: Update error
message. Fold `unaligned-ldpc-2' and `unaligned-ldpc-3' here.
* testsuite/ld-mips-elf/unaligned-ldpc-1.s: Update accordingly.
* testsuite/ld-mips-elf/unaligned-ldpc-2.d: Remove test.
* testsuite/ld-mips-elf/unaligned-ldpc-2.s: Remove test source.
* testsuite/ld-mips-elf/unaligned-ldpc-3.d: Remove test.
* testsuite/ld-mips-elf/unaligned-ldpc-3.s: Remove test source.
* testsuite/ld-mips-elf/unaligned-ldpc-4.d: Remove test.
* testsuite/ld-mips-elf/unaligned-ldpc-4.s: Remove test source.
* testsuite/ld-mips-elf/mips-elf.exp: Delete removed tests.
A `bfd_reloc_outofrange' condition from `mips_elf_calculate_relocation'
currently triggers the warning callback, which in the case of LD prints
messages like:
foo.o: In function `foo':
(.text+0x0): warning: JALX to a non-word-aligned address
or:
foo.o: In function `foo':
(.text+0x0): warning: PC-relative load from unaligned address
and nothing else, which suggests this is a benign condition and link has
otherwise successfully run to completion. This is however not the case,
the link terminates right away with no further messages and no output
produced.
Use the general error or warning info callback then, preserving the
message format. Also set a BFD error condition so that a failure is
unambiguously reported. Complement the change with a set of suitable
test suite additions.
bfd/
* elfxx-mips.c (_bfd_mips_elf_relocate_section)
<bfd_reloc_outofrange>: Call `->einfo' rather than `->warning'.
Call `bfd_set_error'.
ld/
* testsuite/ld-mips-elf/unaligned-jalx-0.d: New test.
* testsuite/ld-mips-elf/unaligned-jalx-1.d: New test.
* testsuite/ld-mips-elf/unaligned-jalx-2.d: New test.
* testsuite/ld-mips-elf/unaligned-jalx-mips16-0.d: New test.
* testsuite/ld-mips-elf/unaligned-jalx-mips16-1.d: New test.
* testsuite/ld-mips-elf/unaligned-jalx-mips16-2.d: New test.
* testsuite/ld-mips-elf/unaligned-jalx-micromips-0.d: New test.
* testsuite/ld-mips-elf/unaligned-jalx-micromips-1.d: New test.
* testsuite/ld-mips-elf/unaligned-jalx-micromips-2.d: New test.
* testsuite/ld-mips-elf/unaligned-lwpc-0.d: New test.
* testsuite/ld-mips-elf/unaligned-lwpc-1.d: New test.
* testsuite/ld-mips-elf/unaligned-lwpc-2.d: New test.
* testsuite/ld-mips-elf/unaligned-lwpc-3.d: New test.
* testsuite/ld-mips-elf/unaligned-ldpc-0.d: New test.
* testsuite/ld-mips-elf/unaligned-ldpc-1.d: New test.
* testsuite/ld-mips-elf/unaligned-ldpc-2.d: New test.
* testsuite/ld-mips-elf/unaligned-ldpc-3.d: New test.
* testsuite/ld-mips-elf/unaligned-ldpc-4.d: New test.
* testsuite/ld-mips-elf/unaligned-jalx-0.s: New test source.
* testsuite/ld-mips-elf/unaligned-jalx-1.s: New test source.
* testsuite/ld-mips-elf/unaligned-jalx-2.s: New test source.
* testsuite/ld-mips-elf/unaligned-insn.s: New test source.
* testsuite/ld-mips-elf/unaligned-lwpc-0.s: New test source.
* testsuite/ld-mips-elf/unaligned-lwpc-1.s: New test source.
* testsuite/ld-mips-elf/unaligned-lwpc-2.s: New test source.
* testsuite/ld-mips-elf/unaligned-lwpc-3.s: New test source.
* testsuite/ld-mips-elf/unaligned-ldpc-0.s: New test source.
* testsuite/ld-mips-elf/unaligned-ldpc-1.s: New test source.
* testsuite/ld-mips-elf/unaligned-ldpc-2.s: New test source.
* testsuite/ld-mips-elf/unaligned-ldpc-3.s: New test source.
* testsuite/ld-mips-elf/unaligned-ldpc-4.s: New test source.
* testsuite/ld-mips-elf/unaligned-syms.s: New test source.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
During archive rescan to resolve symbol references for files added by
LTO, linker add_archive_element callback is called to check if an
archive element should added. After all IR symbols have been claimed,
linker won't claim new IR symbols and shouldn't add the LTO archive
element. This patch updates linker add_archive_element callback to
return FALSE when seeing an LTO archive element during rescan and
changes ELF linker to skip such archive element.
bfd/
PR ld/20103
* cofflink.c (coff_link_check_archive_element): Return TRUE if
linker add_archive_element callback returns FALSE.
* ecoff.c (ecoff_link_check_archive_element): Likewise.
* elf64-ia64-vms.c (elf64_vms_link_add_archive_symbols): Skip
archive element if linker add_archive_element callback returns
FALSE.
* elflink.c (elf_link_add_archive_symbols): Likewise.
* pdp11.c (aout_link_check_ar_symbols): Likewise.
* vms-alpha.c (alpha_vms_link_add_archive_symbols): Likewise.
* xcofflink.c (xcoff_link_check_dynamic_ar_symbols): Likewise.
(xcoff_link_check_ar_symbols): Likewise.
ld/
PR ld/20103
* ldmain.c (add_archive_element): Don't claim new IR symbols
after all IR symbols have been claimed.
* plugin.c (plugin_call_claim_file): Remove no_more_claiming
check.
* testsuite/ld-plugin/lto.exp (pr20103): New proc.
Run PR ld/20103 tests.
* testsuite/ld-plugin/pr20103a.c: New file.
* testsuite/ld-plugin/pr20103b.c: Likewise.
* testsuite/ld-plugin/pr20103c.c: Likewise.
Do not convert jump relocs against local MIPS16 or microMIPS symbols to
refer to a section symbol instead even on RELA targets, as it makes it
impossible for the linker to make a JAL to JALX conversion based on ISA
symbol annotation, breaking regular and compressed MIPS interlinking.
gas/
* config/tc-mips.c (mips_fix_adjustable): Also return 0 for
jump relocations against MIPS16 or microMIPS symbols on RELA
targets.
* testsuite/gas/mips/jalx-local.d: New test.
* testsuite/gas/mips/jalx-local-n32.d: New test.
* testsuite/gas/mips/jalx-local-n64.d: New test.
* testsuite/gas/mips/jalx-local.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
ld/
* testsuite/ld-mips-elf/jalx-local.d: New test.
* testsuite/ld-mips-elf/jalx-local-n32.d: New test.
* testsuite/ld-mips-elf/jalx-local-n64.d: New test.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
2016-05-23 Thomas Preud'homme <thomas.preudhomme@arm.com>
bfd/
* bfd-in.h (bfd_elf32_arm_keep_private_stub_output_sections): Declare
bfd hook.
* bfd-in2.h: Regenerate.
* elf32-arm.c (arm_dedicated_stub_output_section_required): New
function.
(arm_dedicated_stub_output_section_required_alignment): Likewise.
(arm_dedicated_stub_output_section_name): Likewise.
(arm_dedicated_stub_input_section_ptr): Likewise.
(elf32_arm_create_or_find_stub_sec): Add stub type parameter and
function description comment. Add support for dedicated output stub
section to given stub types.
(elf32_arm_add_stub): Add a stub type parameter and pass it down to
elf32_arm_create_or_find_stub_sec.
(elf32_arm_create_stub): Pass stub type down to elf32_arm_add_stub.
(elf32_arm_size_stubs): Pass stub type when calling
elf32_arm_create_or_find_stub_sec for Cortex-A8 erratum veneers.
(bfd_elf32_arm_keep_private_stub_output_sections): New function.
ld/
* emultempl/armelf.em (arm_elf_before_allocation): Call
bfd_elf32_arm_keep_private_stub_output_sections before generic
before_allocation function.
The microMIPS JALX instruction shares the R_MICROMIPS_26_S1 relocation
with microMIPS J/JAL/JALS instructions, however unlike the latters its
encoded immediate argument is unusually shifted left by 2 rather than 1
in calculating the value used for the operation requested.
We already handle this exception in `mips_elf_calculate_relocation' in
LD, in a scenario where JALX is produced as a result of relaxing JAL for
the purpose of making a cross-mode jump. We also get it right in the
disassembler in `decode_micromips_operand'.
What we don't correctly do however is processing microMIPS JALX produced
by GAS from an assembly source, where a non-zero constant argument or a
symbol reference with a non-zero in-place addend has been used. In this
case the same calculation is made as for microMIPS J/JAL/JALS, causing
the wrong encoding to be produced by GAS on making an object file, and
then again by LD in the final link. The latter in particular causes the
calculation, where the addend fits in the relocatable field, to produce
different final addresses for the same source code depending on whether
REL or RELA relocations are used.
Correct these issues by special-casing microMIPS JALX in the places that
have been previously missed.
bfd/
* elfxx-mips.c (mips_elf_read_rel_addend): Adjust the addend for
microMIPS JALX.
gas/
* config/tc-mips.c (append_insn): Correct the encoding of a
constant argument for microMIPS JALX.
(tc_gen_reloc): Correct the encoding of an in-place addend for
microMIPS JALX.
* testsuite/gas/mips/jalx-addend.d: New test.
* testsuite/gas/mips/jalx-addend-n32.d: New test.
* testsuite/gas/mips/jalx-addend-n64.d: New test.
* testsuite/gas/mips/jalx-imm.d: New test.
* testsuite/gas/mips/jalx-imm-n32.d: New test.
* testsuite/gas/mips/jalx-imm-n64.d: New test.
* testsuite/gas/mips/jalx-addend.s: New test source.
* testsuite/gas/mips/jalx-imm.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
ld/
* testsuite/ld-mips-elf/jalx-addend.d: New test.
* testsuite/ld-mips-elf/jalx-addend-n32.d: New test.
* testsuite/ld-mips-elf/jalx-addend-n64.d: New test.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
Don't convert R_386_GOT32 since we can't tell if it is applied
to "mov $foo@GOT, %reg" which isn't a load via GOT.
bfd/
PR ld/20117
* elf32-i386.c (elf_i386_convert_load_reloc): Don't check
R_386_GOT32X.
(elf_i386_convert_load): Don't convert R_386_GOT32.
ld/
PR ld/20117
* testsuite/ld-i386/i386.exp: Run pr20117.
* testsuite/ld-i386/pr19609-1i.d: Updated.
* testsuite/ld-i386/pr20117.d: New file.
* testsuite/ld-i386/pr20117.s: Likewise.
2016-05-19 Cupertino Miranda <cmiranda@synopsys.com>
* emulparams/arcelf.sh: Changed.
* emulparams/arclinux.sh: Likewise.
* scripttempl/arclinux.sc: Moved to a more standard implementation
similar to elf.sc.
The `am34-*-linux*' target cannot be configured for, `am34' is not a CPU
name recognized by `config.sub'. It has never been, required code has
not been contributed to GNU config, neither before nor since the
addition of the target triplet to our configury with commit bfff164249
("Add MN10300 linker relaxation support for symbol differences") back in
2007. Also there is no difference in actual tool configuration between
the `am34-*-linux*' and `am33_2.0-*-linux*' targets, except from a
different executable prefix and tooldir name.
Given the above remove the target triplet from our configuration.
bfd/
* config.bfd: Remove `am34-*-linux*' support.
ld/
* configure.tgt: Remove `am34-*-linux*' support.
A different set of hacks to make the crossref tests pass on powerpc64
and powerpc64le.
* testsuite/ld-scripts/crossref.exp: Remove -mcall-aixdesc hack.
* testsuite/ld-scripts/cross2.t: Tweak .opd and .toc placement.
* testsuite/ld-scripts/cross3.t: Likewise.
* testsuite/ld-scripts/cross4.t: Likewise.
* testsuite/ld-scripts/cross5.t: Likewise.
* testsuite/ld-scripts/cross6.t: Likewise.
* testsuite/ld-scripts/cross7.t: Likewise.
Tweaks to make it easier to re-run these testcases by hand.
* testsuite/ld-elf/shared.exp (mix_pic_and_non_pic): Pass in
exe name rather than constructing testname. Fix typo in
sub-test name. Log copying. Use -rpath rather than -R.
* scripttempl/ft32.sc: Use fixed constants for memory region
lengths. Include DWARF debug sections.
(.data .bss): Do not assign locations during relocatable links.
* testsuite/ld-elf/compressed1d.d: Skip for FT32.
* testsuite/ld-elf/sec-to-seg.exp: Likewise.
* testsuite/ld-elf/sec64k.exp: Likewise.
* testsuite/ld-elf/init-fini-array.d: XFail for FT32.
* testsuite/ld-elf/merge.d: Likewise.
* testsuite/ld-elf/orphan-region.d: Likewise.
* testsuite/ld-elf/orphan.s: Likewise.
* testsuite/ld-elf/orphan3.d: Likewise.
* testsuite/ld-elf/pr349.d: Likewise.
* testsuite/ld-elf/warn2.d: Likewise.
* testsuite/lib/ld-lib.exp (check_shared_lib_support): Note
that the FT32 does not support shared libraries.
The plugin is called to claim symbols in an archive element from
plugin_object_p. But those symbols aren't needed to create output.
They are defined and referenced only within IR. get_symbols should
return resolution based on IR symbol kinds.
PR ld/20070
* Makefile.am (noinst_LTLIBRARIES): Add libldtestplug4.la.
(libldtestplug4_la_SOURCES): New.
(libldtestplug4_la_CFLAGS): Likewise.
(libldtestplug4_la_LDFLAGS): Likewise.
* Makefile.in: Regenerated.
* plugin.c (get_symbols): Return resolution based on IR symbol
kinds for symbols defined/referenced only within IR.
* testplug4.c: New file.
* ld/testsuite/ld-plugin/pr20070.d: Likewise.
* ld/testsuite/ld-plugin/pr20070a.c: Likewise.
* ld/testsuite/ld-plugin/pr20070b.c: Likewise.
* testsuite/ld-plugin/plugin.exp (plugin4_name): New.
(plugin4_path): Likewise.
Add a test for ld/20070.
2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
bfd/
* elf32-arm.c (elf32_arm_size_stubs): Use new macros
ARM_GET_SYM_BRANCH_TYPE and ARM_SET_SYM_BRANCH_TYPE to respectively get
and set branch type of a symbol.
(bfd_elf32_arm_process_before_allocation): Likewise.
(elf32_arm_relocate_section): Likewise and fix identation along the
way.
(allocate_dynrelocs_for_symbol): Likewise.
(elf32_arm_finish_dynamic_symbol): Likewise.
(elf32_arm_swap_symbol_in): Likewise.
(elf32_arm_swap_symbol_out): Likewise.
gas/
* config/tc-arm.c (arm_adjust_symtab): Use ARM_SET_SYM_BRANCH_TYPE to
set branch type of a symbol.
gdb/
* arm-tdep.c (arm_elf_make_msymbol_special): Use
ARM_GET_SYM_BRANCH_TYPE to get branch type of a symbol.
include/
* arm.h (enum arm_st_branch_type): Add new ST_BRANCH_ENUM_SIZE
enumerator.
(NUM_ENUM_ARM_ST_BRANCH_TYPE_BITS): New macro.
(ENUM_ARM_ST_BRANCH_TYPE_BITMASK): Likewise.
(ARM_SYM_BRANCH_TYPE): Replace by ...
(ARM_GET_SYM_BRANCH_TYPE): This and ...
(ARM_SET_SYM_BRANCH_TYPE): This in two versions depending on whether
BFD_ASSERT is defined or not.
ld/
* emultempl/armelf.em (gld${EMULATION_NAME}_finish): Use
ARM_GET_SYM_BRANCH_TYPE to get branch type of a symbol.
opcodes/
* arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
branch type of a symbol.
(print_insn): Likewise.
2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
bfd/
* bfd-in.h (elf32_arm_size_stubs): Add an output section parameter.
* bfd-in2.h: Regenerated.
* elf32-arm.c (struct elf32_arm_link_hash_table): Add an output section
parameter to add_stub_section callback.
(elf32_arm_create_or_find_stub_sec): Get output section from link_sec
and pass it down to add_stub_section.
(elf32_arm_add_stub): Set section to stub_sec if NULL before using it
for error message.
(elf32_arm_size_stubs): Add output section parameter to
add_stub_section function pointer parameter.
ld/
* emultempl/armelf.em (elf32_arm_add_stub_section): Add output_section
parameter and rename input_section parameter to after_input_section.
Append input stub section to the output section if after_input_section
is NULL.
We don't want this to match .rela.text or similar.
* testsuite/ld-scripts/pr14962-2.t: Match .text, not *.text.
* testsuite/ld-scripts/rgn-at5.t: Similarly, .sec not *.sec.
* testsuite/ld-scripts/section-match-1.t: Likewise.
When a global symbol is defined in COMDAT group, we shouldn't leave an
undefined symbol in symbol table when the symbol section is discarded
unless there is a reference to the symbol outside of COMDAT group.
bfd/
PR ld/17550
* elf-bfd.h (elf_link_hash_entry): Update comments for indx,
documenting that indx == -3 if symbol is defined in a discarded
section.
* elflink.c (elf_link_add_object_symbols): Set indx to -3 if
symbol is defined in a discarded section.
(elf_link_output_extsym): Strip a global symbol defined in a
discarded section.
ld/
PR ld/17550
* testsuite/ld-elf/pr17550-1.s: New file.
* testsuite/ld-elf/pr17550-2.s: Likewise.
* testsuite/ld-elf/pr17550-3.s: Likewise.
* testsuite/ld-elf/pr17550-4.s: Likewise.
* testsuite/ld-elf/pr17550a.d: Likewise.
* testsuite/ld-elf/pr17550b.d: Likewise.
* testsuite/ld-elf/pr17550c.d: Likewise.
* testsuite/ld-elf/pr17550d.d: Likewise.
Some targets are only really, or at least regularly, regression-tested
in a crossed configuration. Currently we only have native compiled test
cases for the STB_GNU_UNIQUE feature in the linker test suite. This is
nice, covering run-time semantics even, but quite often not run at all.
Consequently a regression may remain unnoticed for long.
Add a simple test case then to provide basic linker coverage with no
need for a compiler or a native toolchain.
ld/
* testsuite/ld-unique/unique.d: New test.
* testsuite/ld-unique/unique.exp: Run the new test. Adjust
messages for compiled tests.
binutils* testsuite/lib/binutils-common.exp (is_elf_format): Add avr-*-*.
ld * testsuite/ld-elf/pr18735.d: Allow other symbols.
* testsuite/ld-elf/sec64k.exp: Skip 64ksec for avr.
* testsuite/ld-gc/pr14265.d: Allow other symbols.
* testsuite/ld-plugin/plugin.exp: Add PR ld/17973 to
plugin_tests only if check_shared_lib_support is true.
* testsuite/ld-selective/selective.exp: Add --section-start
flag for avr.
When handling absolute relocations for global symbols bind within the
shared object, AArch64 will generate one dynamic RELATIVE relocation,
but won't apply the value for this absolution relocations at static
linking stage. This is different from AArch64 gold linker and x86-64.
This is not a bug as AArch64 is RELA, there is only guarantee that
relocation addend is placed in the relocation entry. But some
system softwares originally writen for x86-64 might assume AArch64
bfd linker gets the same behavior as x86-64, then they could take
advantage of this buy skipping those RELATIVE dynamic relocations
if the load address is the same as the static linking address.
This patch makes AArch64 BFD linker applies absolution relocations at
static linking stage for scenario described above. Meanwhile old AArch64
android loader has a bug (PR19163) which relies on current linker behavior
as a workaround, so the same option --no-apply-dynamic-relocs added.
There is no need to download source if we aren't on remote host.
Otherwise, each ld test run on local host leaves behind a couple
test files.
* config/default.exp (NOPIE_CFLAGS): Download source only on
remote host.
(NOPIE_LDFLAGS): Likewise.
* testsuite/lib/ld-lib.exp (check_lto_available): Likewise.
(check_lto_fat_available): Likewise.
(check_lto_shared_available): Likewise.
(check_ifunc_available): Likewise.
(check_ifunc_attribute_available): Likewise.
Since not all ELF targets use the elf.em emulation to support ld option:
--compress-debug-sections=zlib-gnu, limit compressed1b.d to Linux/GNU
targets.
* testsuite/ld-elf/compressed1b.d: Only run for Linux/GNU targets.
Skip debug sections when estimating distances between output sections
since compressed_size is used to compress debug sections and debug
sections aren't excluded from distances between output sections.
bfd/
PR ld/20006
* elf64-x86-64.c (elf_x86_64_convert_load): Skip debug sections
when estimating distances between output sections.
ld/
PR ld/20006
* testsuite/ld-elfvsb/elfvsb.exp (COMPRESS_LDFLAG): New.
(visibility_run): Pass COMPRESS_LDFLAG to visibility_test on
ELF targets.
Since ld may generate compressed debug sections by default, pass
--compress-debug-sections=none to ld to avoid compressed debug
sections.
* ld-elf/compressed1b.d: Pass --compress-debug-sections=none
to ld.
* ld-elf/compressed1c.d: Likewise.
Check for LTO availability will hide LTO bugs in ld. Since GCC 4.9 adds
-ffat-lto-objects, we always run LTO tests on Linux with GCC 4.9 or newer.
* testsuite/lib/ld-lib.exp (check_lto_available): Return 1 on
Linux with GCC 4.9 or newer.
(check_lto_fat_available): Likewise.
(check_lto_shared_available): Likewise.
Fixes failures on hppa-linux and alpha-linux due to not merging
.data.* and .sdata into .data. cross3.t modified too since it is the
template for the NOCROSSREFS_TO scripts.
* testsuite/ld-scripts/cross3.t: Add commonly used data
and text section names to output section statements.
* testsuite/ld-scripts/cross4.t: Likewise.
* testsuite/ld-scripts/cross5.t: Likewise.
* testsuite/ld-scripts/cross6.t: Likewise.
* testsuite/ld-scripts/cross7.t: Likewise.
Move ELF relocation check after lang_gc_sections so that all the
reference counting code for plt and got relocs can be removed. This
only affects ELF targets which check relocations after opening all
input file.
* ldlang.c (lang_check_relocs): New function.
(lang_process): Call lang_check_relocs after lang_gc_sections.
* emultempl/elf32.em (gld${EMULATION_NAME}_before_parse): Don't
call _bfd_elf_link_check_relocs here.
There is no need for run-time relocation when converting pointers
in .eh_frame section to DW_EH_PE_pcrel encoding. R_386_NONE and
R_X86_64_NONE are expected since the space for run-time relocation
has been allocated. This is an optimization.
PR ld/19972
* testsuite/ld-elf/eh6.d: Pass -rW to readelf and check for
R_386_NONE or R_X86_64_NONE.
Since elf_x86_64_check_relocs is called after opening all input files,
we can detect dynamic R_X86_64_32 relocation overflow there.
bfd/
PR ld/19969
* elf64-x86-64.c (check_relocs_failed): New.
(elf_x86_64_need_pic): Moved before elf_x86_64_check_relocs.
Support relocation agaist local symbol. Set check_relocs_failed.
(elf_x86_64_check_relocs): Use elf_x86_64_need_pic. Check
R_X86_64_32 relocation overflow.
(elf_x86_64_relocate_section): Skip if check_relocs failed.
Update one elf_x86_64_need_pic and remove one elf_x86_64_need_pic.
ld/
PR ld/19969
* testsuite/ld-x86-64/pr19969.d: New file.
* testsuite/ld-x86-64/pr19969a.S: Likewise.
* testsuite/ld-x86-64/pr19969b.S: Likewise.
* testsuite/ld-x86-64/x86-64.exp: Run pr19969 tests.
Delaying checking ELF relocations until opening all input files so
that symbol information is final when relocations are checked. This
is only enabled for x86 targets.
bfd/
* elf-bfd.h (_bfd_elf_link_check_relocs): New.
* elflink.c (_bfd_elf_link_check_relocs): New function.
(elf_link_add_object_symbols): Call _bfd_elf_link_check_relocs
if check_relocs_after_open_input is FALSE.
include/
* bfdlink.h (bfd_link_info): Add check_relocs_after_open_input.
ld/
* emulparams/elf32_x86_64.sh (CHECK_RELOCS_AFTER_OPEN_INPUT):
New.
* emulparams/elf_i386.sh (CHECK_RELOCS_AFTER_OPEN_INPUT):
Likewise.
* emulparams/elf_i386_be.sh (CHECK_RELOCS_AFTER_OPEN_INPUT):
Likewise.
* emulparams/elf_i386_chaos.sh (CHECK_RELOCS_AFTER_OPEN_INPUT):
Likewise.
* emulparams/elf_i386_ldso.sh (CHECK_RELOCS_AFTER_OPEN_INPUT):
Likewise.
* emulparams/elf_i386_vxworks.sh (CHECK_RELOCS_AFTER_OPEN_INPUT):
Likewise.
* emulparams/elf_x86_64.sh (CHECK_RELOCS_AFTER_OPEN_INPUT):
Likewise.
* emulparams/i386nto.sh (CHECK_RELOCS_AFTER_OPEN_INPUT):
Likewise.
* emultempl/elf32.em (gld${EMULATION_NAME}_before_parse):
Set check_relocs_after_open_input to TRUE if
CHECK_RELOCS_AFTER_OPEN_INPUT is yes.
(gld${EMULATION_NAME}_after_open): Call
_bfd_elf_link_check_relocs on all inputs if
check_relocs_after_open_input is TRUE.
This test checks run-time relocation overflow with GOT relocation and
32-bit relocation against the same symbol.
PR ld/19719
* testsuite/ld-x86-64/pr19719.d: New file.
* testsuite/ld-x86-64/pr19719.s: Likewise.
* testsuite/ld-x86-64/x86-64.exp: Run pr19719.
NOCROSSREFS_TO is similar to the existing NOCROSSREFS command but only
checks one direction of cross referencing.
ld/ChangeLog
* ld.texinfo: Document NOCROSSREFS_TO script command.
* ldlang.h (struct lang_nocrossrefs): Add onlyfirst field.
(lang_add_nocrossref_to): New prototype.
* ldcref.c (check_local_sym_xref): Use onlyfirst to only look for
symbols defined in the first section.
(check_nocrossref): Likewise.
* ldgram.y (NOCROSSREFS_TO): New script command.
* ldlang.c (lang_add_nocrossref): Set onlyfirst to FALSE.
(lang_add_nocrossref_to): New function.
* ldlex.l (NOCROSSREFS_TO): New token.
* NEWS: Mention NOCROSSREFS_TO.
* testsuite/ld-scripts/cross4.t: New file.
* testsuite/ld-scripts/cross5.t: Likewise.
* testsuite/ld-scripts/cross6.t: Likewise.
* testsuite/ld-scripts/cross7.t: Likewise.
* testsuite/ld-scripts/crossref.exp: Run 4 new NOCROSSREFS_TO
tests.
Add support for arc/nps400 cmem instructions, these load and store
instructions are hard-wired to access "0x57f00000 + 16-bit-offset".
Supporting this relocation required some additions to the arc relocation
handling in the bfd library, as well as the standard changes required to
add a new relocation type.
There's a test of the new instructions in the assembler, and a test of
the relocation in the linker.
bfd/ChangeLog:
* reloc.c: Add BFD_RELOC_ARC_NPS_CMEM16 entry.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
* elf32-arc.c: Add 'opcode/arc.h' include.
(struct arc_relocation_data): Add symbol_name.
(arc_special_overflow_checks): New function.
(arc_do_relocation): Use arc_special_overflow_checks, reindent as
required, add an extra comment.
(elf_arc_relocate_section): Setup symbol_name in reloc_data.
gas/ChangeLog:
* testsuite/gas/arc/nps400-3.d: New file.
* testsuite/gas/arc/nps400-3.s: New file.
include/ChangeLog:
* elf/arc-reloc.def: Add ARC_NPS_CMEM16 reloc.
* opcode/arc.h (NPS_CMEM_HIGH_VALUE): Define.
ld/ChangeLog:
* testsuite/ld-arc/arc.exp: New file.
* testsuite/ld-arc/nps-1.s: New file.
* testsuite/ld-arc/nps-1a.d: New file.
* testsuite/ld-arc/nps-1b.d: New file.
* testsuite/ld-arc/nps-1b.err: New file.
opcodes/ChangeLog:
* arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
instructions.
* arc-opc.c (insert_nps_cmem_uimm16): New function.
(extract_nps_cmem_uimm16): New function.
(arc_operands): Add NPS_XLDST_UIMM16 operand.
In some cases a variable could be left uninitialised and then an attempt
made to read this variable, resulting in a tcl error. This commit
initialises the variable in all cases.
ld/ChangeLog:
* testsuite/lib/ld-lib.exp (run_dump_test): Initialise
check_ld(terminal).
Since compiler may pass --as-needed to ld by default, link .o file
before .so file in x86-64 tests.
PR ld/19774
* testsuite/ld-x86-64/x86-64.exp: Link tmpdir/pr17689b.o before
tmpdir/pr17689.so, fix gotpcrel1 test and add more --as-needed
tests.
We shouldn't issue an error for read-only segment with dynamic IFUNC
relocations when dynamic relocations are against normal symbols.
bfd/
PR ld/19939
* elf-bfd.h (_bfd_elf_allocate_ifunc_dyn_relocs): Add a pointer
to bfd_boolean.
* elf-ifunc.c (_bfd_elf_allocate_ifunc_dyn_relocs): Updated.
Set *readonly_dynrelocs_against_ifunc_p to TRUE if dynamic reloc
applies to read-only section.
* elf32-i386.c (elf_i386_link_hash_table): Add
readonly_dynrelocs_against_ifunc.
(elf_i386_allocate_dynrelocs): Updated.
(elf_i386_size_dynamic_sections): Issue an error for read-only
segment with dynamic IFUNC relocations only if
readonly_dynrelocs_against_ifunc is TRUE.
* elf64-x86-64.c (elf_x86_64_link_hash_table): Add
readonly_dynrelocs_against_ifunc.
(elf_x86_64_allocate_dynrelocs): Updated.
(elf_x86_64_size_dynamic_sections): Issue an error for read-only
segment with dynamic IFUNC relocations only if
readonly_dynrelocs_against_ifunc is TRUE.
* elfnn-aarch64.c (elfNN_aarch64_allocate_ifunc_dynrelocs):
Updated.
ld/
PR ld/19939
* testsuite/ld-i386/i386.exp: Run PR ld/19939 tests.
* testsuite/ld-x86-64/x86-64.exp: Likewise.
* testsuite/ld-i386/pr19939.s: New file.
* testsuite/ld-i386/pr19939a.d: Likewise.
* testsuite/ld-i386/pr19939b.d: Likewise.
* testsuite/ld-x86-64/pr19939.s: Likewise.
* testsuite/ld-x86-64/pr19939a.d: Likewise.
* testsuite/ld-x86-64/pr19939b.d: Likewise.
* ldlang.c (print_output_section_statement): Show minfo size
in target machine address units.
(print_reloc_statement): Likewise.
(print_padding_statement): Likewise.
(print_data_statement): Likewise. Ensure minimum print_dot
increment of one address unit.
When building with --enable-targets=all the target string is not set to
something that matches the pattern arc*-*, and so the script used to
decide if we should build big or little endian linker script currently
exits with an error.
This commit makes little endian linker script be the default, which will
be used when building for all targets, this matches the behaviour from
before I made the endianness switchable, when we only ever built little
endian linker scripts anyway.
ld/ChangeLog:
* emulparams/arc-endianness.sh: Make little endian default choice.
This aims to bring the linker for big-endian arc targets into line with
the linker for (the default) little endian arc targets.
The bulk of the changes are to extend the target pattern in the test
files from 'arc-*...' to 'arc*-*...' and so match both big and little
endian arc targets.
In the ld/emulparams/ directory the existing scripts checked for a
variable ARC_ENDIAN to switch between big and little endian targets,
however, this variable is never set up.
So, a new script snippet is introduced which sets up ARC_ENDIAN based on
the value of target, this snippet is then included from all of the
existing arc scripts.
The existing big-endian variants of all the scripts, which existed, but
were never used, are deleted in this commit.
ld/ChangeLog:
* emulparams/arc-endianness.sh: New file.
* emulparams/arcebelf.sh: Deleted.
* emulparams/arcebelf_prof.sh: Deleted.
* emulparams/arceblinux.sh: Deleted.
* emulparams/arceblinux_prof.sh: Deleted.
* emulparams/arcelf.sh: Include arc-endinness.sh.
* emulparams/arcelf_prof.sh: Include arc-endinness.sh.
* emulparams/arclinux.sh: Include arc-endinness.sh.
* emulparams/arclinux_prof.sh: Include arc-endinness.sh.
* emulparams/arcv2elf.sh: Include arc-endinness.sh.
* emulparams/arcv2elfx.sh: Include arc-endinness.sh.
* testsuite/ld-elf/compressed1d.d: Update pattern for big and
little endian arc targets.
* testsuite/ld-elf/eh-frame-hdr.d: Likewise.
* testsuite/ld-elf/group1.d: Likewise.
* testsuite/ld-elf/group3b.d: Likewise.
* testsuite/ld-elf/group8a.d: Likewise.
* testsuite/ld-elf/group8b.d: Likewise.
* testsuite/ld-elf/group9a.d: Likewise.
* testsuite/ld-elf/group9b.d: Likewise.
* testsuite/ld-elf/linkonce2.d: Likewise.
* testsuite/ld-elf/pr12851.d: Likewise.
* testsuite/ld-elf/pr12975.d: Likewise.
* testsuite/ld-elf/pr13177.d: Likewise.
* testsuite/ld-elf/pr13195.d: Likewise.
* testsuite/ld-elf/pr17615.d: Likewise.
* testsuite/ld-elf/pr19162.d: Likewise.
* testsuite/ld-elf/sec64k.exp: Likewise.
* testsuite/lib/ld-lib.exp: Likewise.
Always turn hidden and internal symbols which have a dynamic index into
local ones. This is required by the the ELF gABI[1]:
"A hidden symbol contained in a relocatable object must be either
removed or converted to STB_LOCAL binding by the link-editor when the
relocatable object is included in an executable file or shared object."
"An internal symbol contained in a relocatable object must be either
removed or converted to STB_LOCAL binding by the link-editor when the
relocatable object is included in an executable file or shared object."
The ELF linker usually respects this requirement, however in the case
where a dynamic symbol has been preallocated due to a reference of the
default export class aka visibility from the object being linked, and
then merged with a hidden or internal symbol definition from within the
same object, then the original export class is carried over to the
output dynamic symbol table, because while merging the generic ELF
linker only converts affected dynamic symbols to local when they are
defined or referenced by the object being linked and a dynamic object
involved in the link both at a time.
The dynamic symbol produced confuses then the dynamic loader at the run
time -- the hidden or internal export class is ignored and the symbol
follows preemption rules as with the default export class.
In the MIPS target it happens when `mips_elf_record_global_got_symbol'
creates a dynamic symbol when a call relocation is encountered.
Additionally if the undefined symbol referred by such a relocation does
specify the intended export class, then a local dynamic symbol is
created instead, which is harmless and allowed, but useless. Normally
no local dynamic symbols are created, except for a single dummy one at
the beginning.
Correct the problem by removing the extra check for a dynamic symbol
being defined or referenced by the object being linked and a dynamic
object involved in the link both at a time. The test cases included
cover the internal and hidden symbol cases, as well as a protected
symbol for a reference, the handling of which is unchanged by this fix.
Both cases described above are covered, that is where an internal or
hidden dynamic symbol is produced and where a local one is.
NB this change affects CRIS results where some symbols in the static
table produced in a final link are now converted from STV_HIDDEN to
STB_LOCAL. This happens whenever the `elf_backend_hide_symbol' handler
is called, so the affected symbols must have been chosen for entering
into the dynamic symbol table, except in these test cases no such symbol
table is produced. In fully linked binaries the static symbol table is
only used for debugging though, so such a change is fine.
References:
[1] "System V Application Binary Interface - DRAFT - 24 April 2001",
The Santa Cruz Operation, Inc., "Symbol Table",
<http://www.sco.com/developers/gabi/2001-04-24/ch4.symtab.html>
bfd/
PR ld/19908
* elflink.c (elf_link_add_object_symbols): Always turn hidden
and internal symbols which have a dynamic index into local
ones.
ld/
PR ld/19908
* testsuite/ld-cris/tls-e-20.d: Adjust for hidden symbol
handling fix.
* testsuite/ld-cris/tls-e-20a.d: Likewise.
* testsuite/ld-cris/tls-e-21.d: Likewise.
* testsuite/ld-cris/tls-e-23.d: Likewise.
* testsuite/ld-cris/tls-e-80.d: Likewise.
* testsuite/ld-cris/tls-gd-3h.d: Likewise.
* testsuite/ld-cris/tls-leie-19.d: Likewise.
* testsuite/ld-mips-elf/export-class-ref-lib.sd: New test.
* testsuite/ld-mips-elf/export-hidden-ref.sd: New test.
* testsuite/ld-mips-elf/export-internal-ref.sd: New test.
* testsuite/ld-mips-elf/export-protected-ref.sd: New test.
* testsuite/ld-mips-elf/export-class-ref-f0.s: New test source.
* testsuite/ld-mips-elf/export-class-ref-f1.s: New test source.
* testsuite/ld-mips-elf/export-class-ref-f2.s: New test source.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
PR 19803
* emultempl/pe.em (change_undef): New function. Encapsulates
duplicated code in pe_fixup_stdcalls and adds the newly defined
sym to the gc root list.
(pe_fixup_stdcall): Use the new function.
* pe-dll.c (process_def_file_and_drectve); Add alias of exported
symbol to gc root list.
PR 19872
bfd * dwarf2.c (parse_comp_unit): Skip warning about unrecognised
version number if the version is zero.
bin * dwarf.c (display_debug_aranges): Skip warning about unrecognised
version number if the version is zero.
and one extraneous occurrence.
* ldlang.c (TO_ADDR, TO_SIZE, opb_shift): Move earlier in file.
(lang_insert_orphan): Use TO_ADDR in __stop sym calculation.
(print_input_section): Don't use TO_ADDR when printing section
size.
(lang_size_sections_1): Use TO_ADDR in overlay lma calculation.
(lang_size_sections): Use TO_ADDR in relro end calculation.
The options warning_output and error_output to the run_dump_test
function were incorrectly checking the return value from the regexp_diff
function, and so, as a result failing tests were showing as a pass.
Fixed in this commit.
ld/ChangeLog:
* testsuite/lib/ld-lib.exp (run_dump_test): Fix check of return
value from regexp_diff.
* testsuite/ld-elf/orphan-5.l: Fix expected output.
* testsuite/ld-elf/orphan-6.l: Likewise.
PR 18452
* ldlang.c (maybe_overlays): New static var.
(lang_size_sections_1): Set it here.
(struct check_sec): New.
(sort_sections_by_lma): Adjust for array of structs.
(sort_sections_by_vma): New function.
(lang_check_section_addresses): Check both LMA and VMA for overlap.
* testsuite/ld-scripts/rgn-over7.d: Adjust.
Some places tested SEC_LOAD, others SEC_HAS_CONTENTS.
* ldlang.c (IS_TBSS): New macro, extracted from..
(IGNORE_SECTION): ..here.
(lang_size_sections_1): Use IS_TBSS and IGNORE_SECTION.
(lang_size_sections, lang_do_assignments_1): Use IS_TBSS.
PR ld/19803
* ldlang.c (lang_add_gc_name): New function. Adds the provided
symbol name to the list of gc symbols.
(lang_process): Call lang_add_gc_name with entry_symbol_default if
entry_symbol.name is NULL. Use lang_add_gc_name to add the init
and fini function names.
* pe-dll.c (process_def_file_and_drectve): Add exported names to
the gc symbol list.
* testsuite/ld-pe/pr19803.s: Do not export _testval symbol.
* testsuite/ld-pe/pr19803.d: Tweak expected output.
bfd * warning.m4 (GCC_WARN_CFLAGS): Only add -Wstack-usage if using a
sufficiently recent version of GCC.
* configure: Regenerate.
others * configure: Regenerate.
Symbols defined in PIE should be bound locally, the same as -shared
-Bsymbolic.
bfd/
PR ld/19827
* elf32-i386.c (elf_i386_check_relocs): Bind defined symbol
locally in PIE.
(elf_i386_relocate_section): Likewise.
* elf64-x86-64.c (elf_x86_64_check_relocs): Likewise.
(elf_x86_64_relocate_section): Likewise.
ld/
PR ld/19827
* testsuite/ld-i386/i386.exp: Run PR ld/19827 tests.
* testsuite/ld-x86-64/x86-64.exp: Likewise.
* testsuite/ld-i386/pr19827.rd: New file.
* testsuite/ld-i386/pr19827a.S: Likewise.
* testsuite/ld-i386/pr19827b.S: Likewise.
* testsuite/ld-x86-64/pr19827.rd: Likewise.
* testsuite/ld-x86-64/pr19827a.S: Likewise.
* testsuite/ld-x86-64/pr19827b.S: Likewise.
Currently, it's not possible to manually set some of the v850 archs in
gdb:
(gdb) set architecture v850<TAB>
v850 (using old gcc ABI)
v850-rh850
v850e
v850e (using old gcc ABI)
v850e1
[...]
(gdb) set architecture v850 (using old gcc ABI)
Ambiguous item "v850 (using old gcc ABI)".
The problem is that "set architecture" is a GDB "enum command", and
GDB only considers an enum value to be the string up until the first
space. So writing "v850 (using old gcc ABI)" is the same as writing
"v850", and then that's not an unambiguous arch printable name prefix.
v850 is actually the only arch that has spaces in its printable name.
One can conveniently see that with e.g.:
(gdb) set max-completions unlimited
(gdb) complete set architecture
...
Rather than hack GDB into accepting this somehow, make v850 arch
printable names more like the printable names of the other archs, and
put the abi variant in the "machine" part, after a ':'.
We now get:
(gdb) set architecture v850<TAB>
v850:old-gcc-abi
v850:rh850
v850e
v850e1
v850e1:old-gcc-abi
v850e2
v850e2:old-gcc-abi
[...]
And now "set architecture v850:old-gcc-abi" works as expected.
I ran the binutils/gas/ld testsuites, and found no regressions. I
don't have a cross compiler handy, but I ran the gdb tests anyway,
which covers at least some snoke testing.
I think that the OUTPUT_ARCH in ld/scripttempl/v850.sc may have got
broken with the previous 2012 change, since I hacked v850_rh850.sc to
output "v850" and ld failed to grok it. I think it only works if the
old GCC ABI is the configured v850 default ABI. That's now fixed by
changing to use explicit v850:old-gcc-abi.
Also, this actually "fixes" an existing GDB test, which isn't likewise
expecting spaces in arch names, when GDB is configured for
--target=v850:
(gdb) FAIL: gdb.xml/tdesc-arch.exp: read valid architectures
bfd/ChangeLog:
2016-03-09 Pedro Alves <palves@redhat.com>
* cpu-v850.c (N): Append ":old-gcc-abi" instead of " (using old
gcc ABI)" to printable name.
* cpu-v850_rh850.c (bfd_v850_rh850_arch): Use "v850:rh850" instead
of "v850-rh850" as printable name.
ld/ChangeLog:
2016-03-09 Pedro Alves <palves@redhat.com>
* scripttempl/v850.sc: Use "v850:old-gcc-abi" as OUTPUT_ARCH.
* scripttempl/v850_rh850.sc: Use "v850:rh850" as OUTPUT_ARCH.
Since dynamic sections aren't applicable to relocatable file, don't
create dynamic sections for -E/--dynamic-list when relocatable.
bfd/
PR ld/19789
* elflink.c (elf_link_add_object_symbols): Create dynamic sections
for -E/--dynamic-list only when not relocatable.
ld/
PR ld/19789
* testsuite/ld-elf/pr19789.d: New file.
* testsuite/ld-elf/pr19789.s: Likewise.
Increment PLT reference count for locally defined local IFUNC symbols
in shared object since STT_GNU_IFUNC symbol must go through PLT even
if it is locally defined and undefined symbol may turn out to be a
STT_GNU_IFUNC symbol later.
bfd/
PR ld/19784
* elf32-i386.c (elf_i386_check_relocs): Increment PLT reference
count for locally defined local IFUNC symbols in shared object.
* elf64-x86-64.c (elf_x86_64_check_relocs): Likewise.
ld/
PR ld/19784
* testsuite/ld-i386/i386.exp: Remove pr19636-2e-nacl test.
* testsuite/ld-i386/pr19636-2e-nacl.d: Moved to ...
* testsuite/ld-i386/pr19636-2e.d: Here. Remove notarget.
* testsuite/ld-ifunc/ifunc.exp: Run PR ld/19784 tests.
* testsuite/ld-ifunc/pass.out: New file.
* testsuite/ld-ifunc/pr19784a.c: Likewise.
* testsuite/ld-ifunc/pr19784b.c: Likewise.
* testsuite/ld-ifunc/pr19784c.c: Likewise.
Since compiler may pass --as-needed to ld by default, link .o file
before .so file in ifunc tests.
PR ld/19774
* testsuite/ld-ifunc/ifunc.exp: Link tmpdir/pr18808a.o before
tmpdir/libpr18808.so. Link tmpdir/pr18841a.o before
tmpdir/libpr18841b.so and tmpdir/libpr18841c.so. Test
--as-needed for pr18841c.
Alan Modra
H.J. Lu
Christophe Lyon
Vlad Zakharov
Akihiko Odaki
Andreas Krebbel
Nick Clifton
Richard Sandiford
Andrew Burgess
Thomas Preud'homme
Claudiu Zissulescu
Senthil Kumar Selvaraj
Cupertino Miranda
Maciej W. Rozycki
Roland McGrath
Igor Kudrin
Roland McGrath
jamesbowman
Andre Vieria
Jan Beulich
Tristan Gingold
James Clarke
Graham Markall
Denis Chertykov
Christian Groessler
Vineet Gupta
Kuba Sejdak
Christophe Monat
Pitchumani Sivanupandi
Jiong Wang
Trevor Saunders
Matthew Fortune
Oleg Endo
Dan Gisselquist
Awson
Mickael Guene
Pedro Alves