This patch makes a few minor improvements to the catchpoint
documentation:
* "catch exception" and "catch handlers" now mention the argument in
the @item.
* "catch exception unhandled" is moved to be closer to "catch
exception", rather than after "catch handlers".
* "catch load" and "catch unload" now wrap the argument in @var.
gdb/doc/ChangeLog
2019-05-10 Tom Tromey <tromey@adacore.com>
* gdb.texinfo (Set Catchpoints): Add text for parameter to "catch
exception" and "catch handlers". Move "catch exception unhandled"
text. Use @var for "catch load" and "catch unload"
git commit 2379f9c475 introduced an rx-elf test failure. This fixes it.
* testsuite/binutils-all/objdump.exp (test_objdump_disas_limited),
(test_objdump_content_limited): Add text arg, use in place of .text.
(bintest_signed.o): Call get_standard_section_names for name of
text section.
I noticed a couple of spots where a "char *" was used where a
"const char *" made more sense. This patch fixes both of them.
Tested by rebuilding.
gdb/ChangeLog
2019-05-10 Tom Tromey <tromey@adacore.com>
* thread.c (print_thread_info): Make "requested_threads" const.
* gdbthread.h (print_thread_info): Make "requested_threads"
const.
* ada-tasks.c (print_ada_task_info): Make "taskno_str" const.
* ada-lang.h (print_ada_task_info): Make "taskno_str" const.
opcodes/
* ppc-dis.c (skip_optional_operands): Change return type and returns.
(print_insn_powerpc) <skip_optional>: Change type.
Call skip_optional_operands if we have not skipped any operands.
gas/
* testsuite/gas/ppc/476.d: Update expected output.
* testsuite/gas/ppc/power6.d: Likewise.
My testcase matched against a file format of elf64-littleaarch64 in the
objdump output. This was unnecessarily restrictive and causes testcase
failures on aarch64_be.
Here we remove that restriction.
Committed as obvious.
Testing done on aarch64_be-none-elf gas to see the failure goes away.
gas/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* testsuite/gas/aarch64/sve2.d: Remove file format restriction.
The test-case gdb.arch/amd64-tailcall-self.exp fails here:
...
if ![runto b] {
return -1
}
...
like:
...
(gdb) file build/gdb/testsuite/outputs/gdb.arch/amd64-tailcall-self/\
amd64-tailcall-self
Reading symbols from build/gdb/testsuite/outputs/gdb.arch/\
amd64-tailcall-self/amd64-tailcall-self...
Dwarf Error: Cannot find DIE at 0x1f5 referenced from DIE at 0x107 [in \
module build/gdb/testsuite/outputs/gdb.arch/amd64-tailcall-self/\
amd64-tailcall-self]
...
The problem is that in amd64-tailcall-self.S, CU-relative references are
assigned .debug_info section relative values. [ This is similar to the
problem fixed by "Fix gdb.arch/amd64-entry-value-paramref.S". ]
Fix this by assigning CU-relative references instead.
Tested on x86_64-linux.
gdb/testsuite/ChangeLog:
2019-05-09 Tom de Vries <tdevries@suse.de>
* gdb.arch/amd64-tailcall-self.S: Make DW_FORM_ref4 references
CU-relative.
Add tests that SVE2 instructions are encoded as they should be, and
tests that invalid instructions have their problems reported.
Also check that each sve2 cryptographic extension is required to use the
corresponding cryptographic instructions.
Finally, test to ensure that sve2 instructions using mnemonics that
exist in sve1 still need the sve2 feature to be used.
gas/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* testsuite/gas/aarch64/illegal-sve2-aes.d: New test.
* testsuite/gas/aarch64/illegal-sve2-bitperm.d: New test.
* testsuite/gas/aarch64/illegal-sve2-sha3.d: Test new instructions.
* testsuite/gas/aarch64/illegal-sve2-sm4.d: Test new instructions.
* testsuite/gas/aarch64/illegal-sve2-sve1ext.d: Test new instructions.
* testsuite/gas/aarch64/illegal-sve2-sve1ext.l: Test new instructions.
* testsuite/gas/aarch64/illegal-sve2.d: Test new instructions.
* testsuite/gas/aarch64/illegal-sve2.l: Test new instructions.
* testsuite/gas/aarch64/illegal-sve2.s: Test new instructions.
* testsuite/gas/aarch64/sve1-extended-sve2.s: New test.
* testsuite/gas/aarch64/sve2.d: Test new instructions.
* testsuite/gas/aarch64/sve2.s: Test new instructions.
This patch adds all the SVE2 instructions and their associated qualifier
sets.
Ok for trunk?
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-dis-2.c: Regenerate.
* aarch64-tbl.h (OP_SVE_BBU): New variant set.
(OP_SVE_BBB): New variant set.
(OP_SVE_DDDD): New variant set.
(OP_SVE_HHH): New variant set.
(OP_SVE_HHHU): New variant set.
(OP_SVE_SSS): New variant set.
(OP_SVE_SSSU): New variant set.
(OP_SVE_SHH): New variant set.
(OP_SVE_SBBU): New variant set.
(OP_SVE_DSS): New variant set.
(OP_SVE_DHHU): New variant set.
(OP_SVE_VMV_HSD_BHS): New variant set.
(OP_SVE_VVU_HSD_BHS): New variant set.
(OP_SVE_VVVU_SD_BH): New variant set.
(OP_SVE_VVVU_BHSD): New variant set.
(OP_SVE_VVV_QHD_DBS): New variant set.
(OP_SVE_VVV_HSD_BHS): New variant set.
(OP_SVE_VVV_HSD_BHS2): New variant set.
(OP_SVE_VVV_BHS_HSD): New variant set.
(OP_SVE_VV_BHS_HSD): New variant set.
(OP_SVE_VVV_SD): New variant set.
(OP_SVE_VVU_BHS_HSD): New variant set.
(OP_SVE_VZVV_SD): New variant set.
(OP_SVE_VZVV_BH): New variant set.
(OP_SVE_VZV_SD): New variant set.
(aarch64_opcode_table): Add sve2 instructions.
New operand describes a shift-left immediate encoded in bits
22:20-19:18-16 where UInt(bits) - esize == shift.
This operand is useful for instructions like sshllb.
gas/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (parse_operands): Handle new SVE_SHLIMM_UNPRED_22
operand.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): New SVE_SHLIMM_UNPRED_22
operand.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
for SVE_SHLIMM_UNPRED_22.
(aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
operand.
Add sve_size_tsz_bhs iclass needed for sqxtnb and similar instructions.
This iclass encodes one of three variants by the most significant bit
set in a 3-bit value where only one bit may be set.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_tsz_bhs
iclass.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
sve_size_tsz_bhs iclass encode.
* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
sve_size_tsz_bhs iclass decode.
This includes defining a new single bit field SVE_i2h at position 20.
SVE_Zm4_11_INDEX handles indexed Zn registers where the index is encoded
in bits 20:11 and the register is chosed from range z0-z15 in bits 19-16.
gas/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (parse_operands): Handle new SVE_Zm4_11_INDEX
operand.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): New SVE_Zm4_11_INDEX operand.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
for SVE_Zm4_11_INDEX.
(aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
(fields): Handle SVE_i2h field.
* aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
This new iclass encodes the variant by which is the most significant bit
used of bits 23-22:20-19, where those bits are usually part of a
given constant operand.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_insn_class): Add sve_shift_tsz_bhsd
iclass.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
sve_shift_tsz_bhsd iclass encode.
* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
sve_shift_tsz_bhsd iclass decode.
Include a new iclass to extract the variant from the most significant 3
bits of this operand.
Instructions such as rshrnb include a constant shift amount as an
operand, where the most significant three bits of this operand determine
what size elements the instruction is operating on.
The new SVE_SHRIMM_UNPRED_22 operand denotes this constant encoded in
bits 22:20-19:18-16 while the new sve_shift_tsz_hsd iclass denotes that
the SVE qualifier is encoded in bits 22:20-19.
gas/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (parse_operands): Handle new SVE_SHRIMM_UNPRED_22
operand.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): New SVE_SHRIMM_UNPRED_22
operand.
(enum aarch64_insn_class): Add sve_shift_tsz_hsd iclass.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
* aarch64-asm.c (aarch64_ins_sve_shrimm):
(aarch64_encode_variant_using_iclass): Handle
sve_shift_tsz_hsd iclass encode.
* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
sve_shift_tsz_hsd iclass decode.
* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
for SVE_SHRIMM_UNPRED_22.
(aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
operand.
Add sve_size_013 instruction class
This new iclass handles instructions such as pmullb whose size specifier
can only be encoded as 0, 1, or 3.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_013 iclass.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
sve_size_013 iclass encode.
* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
sve_size_013 iclass decode.
Add new iclass sve_size_bh to handle instructions that have two variants
encoded with the SVE_sz field.
This iclass behaves the same as the sve_size_sd iclass, but it has a
nicer name for those instructions that choose between variants using the
"B" and "H" size qualifiers.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_bh iclass.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
sve_size_bh iclass encode.
* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
sve_size_bh iclass decode.
Add AARCH64_OPND_SVE_ADDR_ZX operand that allows a vector of addresses
in a Zn register, offset by an Xm register.
This is used with scatter/gather SVE2 instructions.
gas/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (REG_ZR): Macro specifying zero register.
(parse_address_main): Account for new addressing mode [Zn.S, Xm].
(parse_operands): Handle new SVE_ADDR_ZX operand.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): New SVE_ADDR_ZX operand.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
for SVE_ADDR_ZX.
(aarch64_print_operand): Add printing for SVE_ADDR_ZX.
* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
Introduce new operand SVE_Zm3_11_INDEX that indicates a register between
z0-z7 stored in bits 18-16 and an index stored in bits 20-19:11.
gas/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (parse_operands): Handle new SVE_Zm3_11_INDEX
operand.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): New SVE_Zm3_11_INDEX operand.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
for SVE_Zm3_11_INDEX.
(aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
(fields): Handle SVE_i3l and SVE_i3h2 fields.
* aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
fields.
* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
New operand AARCH64_OPND_SVE_IMM_ROT3 handles a single bit rotate
operand encoded at bit position 10.
gas/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (parse_operands): Handle new SVE_IMM_ROT3 operand.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): New SVE_IMM_ROT3 operand.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
for SVE_IMM_ROT3.
(aarch64_print_operand): Add printing for SVE_IMM_ROT3.
(fields): Handle SVE_rot3 field.
* aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
SVE2 introduces a number of new instructions that work with the movprfx
instruction. This commit ensures that SVE2 instructions are accounted
for.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-opc.c (verify_constraints): Check for movprfx for sve2
instructions.
Include all feature flag macros.
The "sve2" extension that enables the core sve2 instructions.
This also enables the sve extension, since sve is a requirement of sve2.
Extra optional sve2 features are the bitperm, sm4, aes, and sha3 extensions.
These are all given extra feature flags, "bitperm", "sve2-sm4",
"sve2-aes", and "sve2-sha3" respectively.
The sm4, aes, and sha3 extensions are explicitly marked as sve2
extensions to distinguish them from the corresponding NEON extensions.
Rather than continue extending the current feature flag numbers, I used
some bits that have been skipped.
gas/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c: Add command line architecture feature flags
"sve2", "sve2-sm4", "sve2-aes", "sve2-sha3", "bitperm".
* doc/c-aarch64.texi: Document new architecture feature flags.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_SVE2
AARCH64_FEATURE_SVE2_AES, AARCH64_FEATURE_SVE2_BITPERM,
AARCH64_FEATURE_SVE2_SM4, AARCH64_FEATURE_SVE2_SHA3): New
feature macros.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-tbl.h
(aarch64_feature_sve2, aarch64_feature_sve2aes,
aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
aarch64_feature_sve2bitperm): New feature sets.
(SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
for feature set addresses.
(SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
The file gdb.arch/amd64-entry-value-paramref.S contains a DIE for function
bar:
...
DIE29: .uleb128 0x2 # (DIE (0x29) DW_TAG_subprogram)
.ascii "bar\0" # DW_AT_name
.byte 0x1 # DW_AT_decl_file (gdb.arch/amd64-entry-value-paramref.cc)
.byte 0x15 # DW_AT_decl_line
.long DIE45 # DW_AT_type
.byte 0x1 # DW_AT_inline
...
which refers to DIE45:
...
DIE45: .uleb128 0x4 # (DIE (0x45) DW_TAG_base_type)
.byte 0x4 # DW_AT_byte_size
.byte 0x5 # DW_AT_encoding
.ascii "int\0" # DW_AT_name
...
using a form DW_FORM_ref4:
...
.uleb128 0x2 # (abbrev code)
.uleb128 0x2e # (TAG: DW_TAG_subprogram)
.byte 0x1 # DW_children_yes
...
.uleb128 0x49 # (DW_AT_type)
.uleb128 0x13 # (DW_FORM_ref4)
...
However, the DW_FORM_ref4 is a CU-relative reference, while using a label for
the value will result in a section-relative value.
So, if linked in object files contain dwarf info and are placed in the
.debug_info section before the compilation units generated from
amd64-entry-value-paramref.S, then the referenced type is at 0x108:
...
<1><108>: Abbrev Number: 4 (DW_TAG_base_type)
<109> DW_AT_byte_size : 4
<10a> DW_AT_encoding : 5 (signed)
<10b> DW_AT_name : int
...
but the reference will point to a non-existing DIE at 0x1cf:
...
<1><f0>: Abbrev Number: 2 (DW_TAG_subprogram)
<f1> DW_AT_name : bar
<f5> DW_AT_decl_file : 1
<f6> DW_AT_decl_line : 21
<f7> DW_AT_type : <0x1cf>
<fb> DW_AT_inline : 1 (inlined)
...
which happens to cause a GDB internal error described in PR23270 - "GDB
internal error: dwarf2read.c:18656: internal-error: could not find partial
DIE 0x1b7 in cache".
Fix the invalid DWARF by making the reference value CU-relative:
...
- .long DIE45 # DW_AT_type
+ .long DIE45 - .Ldebug_info0 # DW_AT_type
...
Tested on x86_64-linux.
gdb/testsuite/ChangeLog:
2019-05-09 Tom de Vries <tdevries@suse.de>
* gdb.arch/amd64-entry-value-paramref.S: Make DW_FORM_ref4 references
CU-relative.
This changes gdbtypes.c to use the type-safe registry API.
gdb/ChangeLog
2019-05-08 Tom Tromey <tom@tromey.com>
* gdbtypes.c (objfile_type_data): Change type.
(objfile_type, _initialize_gdbtypes): Update.
This changes dwarf2-frame.c to use the type-safe registry API.
gdb/ChangeLog
2019-05-08 Tom Tromey <tom@tromey.com>
* dwarf2-frame.c (dwarf2_frame_objfile_data): Change type.
(dwarf2_frame_find_fde, dwarf2_build_frame_info)
(_initialize_dwarf2_frame): Update.
This changes objc-lang.c to use the type-safe registry API.
gdb/ChangeLog
2019-05-08 Tom Tromey <tom@tromey.com>
* objc-lang.c (objc_objfile_data): Change type.
(find_methods): Update.
(_initialize_objc_lang): Remove.
This changes stabsread.c to use the type-safe registry API.
gdb/ChangeLog
2019-05-08 Tom Tromey <tom@tromey.com>
* stabsread.c (rs6000_builtin_type_data): Change type.
(rs6000_builtin_type, _initialize_stabsread): Update.
mips_pdr_data is unused, so this patch removes it.
gdb/ChangeLog
2019-05-08 Tom Tromey <tom@tromey.com>
* mips-tdep.c (mips_pdr_data): Remove.
(_initialize_mips_tdep): Update.
This changes hppa-tdep.c to use the type-safe registry API.
gdb/ChangeLog
2019-05-08 Tom Tromey <tom@tromey.com>
* hppa-tdep.c (hppa_objfile_priv_data): Change type.
(hppa_init_objfile_priv_data, read_unwind_info)
(find_unwind_entry, _initialize_hppa_tdep): Update.
This changes elfread.c to use the type-safe registry API. This also
fixes a potential memory leak, by changing the hash table so that it
is no longer allocated on an obstack.
gdb/ChangeLog
2019-05-08 Tom Tromey <tom@tromey.com>
* elfread.c (elf_objfile_gnu_ifunc_cache_data): Change type.
(elf_gnu_ifunc_record_cache): Update. Don't allocate hash table
on obstack.
(elf_gnu_ifunc_resolve_by_cache, _initialize_elfread): Update.
This changes mdebugread.c to use the type-safe registry API.
gdb/ChangeLog
2019-05-08 Tom Tromey <tom@tromey.com>
* mdebugread.c (basic_type_data): Change type.
(basic_type, _initialize_mdebugread): Update.
This adds a no-op deleter, which is used in subsequent patches.
gdb/ChangeLog
2019-05-08 Tom Tromey <tom@tromey.com>
* common/gdb_unique_ptr.h (struct noop_deleter): New.
This changes the probes code in elfread.c to use the type-safe
registry API. While doing this, I saw that the caller of get_probes
owns the probes, so I went through the code and changed the vectors to
store unique_ptrs, making the ownership relationship more clear.
gdb/ChangeLog
2019-05-08 Tom Tromey <tom@tromey.com>
* symfile.h (struct sym_probe_fns) <sym_get_probes>: Change type.
* symfile-debug.c (debug_sym_get_probes): Change type.
* stap-probe.c (handle_stap_probe):
(stap_static_probe_ops::get_probes): Change type.
* probe.h (class static_probe_ops) <get_probes>: Change type.
* probe.c (class any_static_probe_ops) <get_probes>: Change type.
(parse_probes_in_pspace): Update.
(find_probes_in_objfile, find_probe_by_pc, collect_probes):
Update.
(any_static_probe_ops::get_probes): Change type.
* elfread.c (elfread_data): New typedef.
(probe_key): Change type.
(elf_get_probes): Likewise. Update.
(probe_key_free): Remove.
(_initialize_elfread): Update.
* dtrace-probe.c (class dtrace_static_probe_ops) <get_probes>:
Change type.
(dtrace_process_dof_probe, dtrace_process_dof)
(dtrace_static_probe_ops::get_probe): Change type.
This changes xcoffread.c to use the type-safe registry API. It also
renames coff_symfile_info to xcoff_symfile_info, to avoid any possible
ODR violation.
gdb/ChangeLog
2019-05-08 Tom Tromey <tom@tromey.com>
* xcoffread.c (struct xcoff_symfile_info): Rename from
coff_symfile_info. Add initializers.
(xcoff_objfile_data_key): Move lower. Change type.
(XCOFF_DATA): Rewrite.
(xcoff_free_info): Remove.
(xcoff_symfile_init, _initialize_xcoffread, read_xcoff_symtab)
(read_symbol, read_symbol_lineno, find_linenos, init_stringtab)
(xcoff_initial_scan): Update.
This changes solib-svr4y.c to use the type-safe registry API.
gdb/ChangeLog
2019-05-08 Tom Tromey <tom@tromey.com>
* solib-svr4.c (struct svr4_info): Add initializers and
destructor.
<probes_table>: Now an htab_up.
(solib_svr4_pspace_data): Change type.
(free_probes_table): Simplify.
(~svr4_info): Rename from svr4_pspace_data_cleanup.
(get_svr4_info, probes_table_htab_remove_objfile_probes)
(probes_table_remove_objfile_probes, register_solib_event_probe)
(solib_event_probe_at, svr4_update_solib_event_breakpoint)
(_initialize_svr4_solib): Update.
This changes remote.c to use the type-safe registry API.
gdb/ChangeLog
2019-05-08 Tom Tromey <tom@tromey.com>
* remote.c (remote_pspace_data): Change type.
(remote_pspace_data_cleanup): Remove.
(get_remote_exec_file, set_pspace_remote_exec_file)
(_initialize_remote): Update.
This changes breakpoint.c to use the type-safe registry API.
gdb/ChangeLog
2019-05-08 Tom Tromey <tom@tromey.com>
* breakpoint.c (breakpoint_objfile_key): Change type.
(get_breakpoint_objfile_data): Update.
(free_breakpoint_objfile_data): Remove.
(_initialize_breakpoint): Update.
This changes dwarf2_per_objfile to use the type-safe registry API.
This also changes dwarf2_per_objfile not to be allocated on an
obstack. It seemed clearer to me to simply allocate it on the heap;
and I didn't see a drawback from doing so.
gdb/ChangeLog
2019-05-08 Tom Tromey <tom@tromey.com>
* dwarf2read.h (struct dwarf2_per_objfile): Don't inherit from
allocate_on_obstack.
* dwarf2read.c (dwarf2_objfile_data_key): Change type.
(get_dwarf2_per_objfile): Update.
(set_dwarf2_per_objfile): Remove.
(dwarf2_has_info, dwarf2_get_section_info): Update.
(dwarf2_free_objfile): Remove.
(_initialize_dwarf2_read): Update.
This changes auto-load.c to use the type-safe registry API. It also
changes a couple of types to "bool", removing uses of "FALSE".
gdb/ChangeLog
2019-05-08 Tom Tromey <tom@tromey.com>
* auto-load.c (struct auto_load_pspace_info): Add destructor and
initializers.
<unsupported_script_warning_printed,
script_not_found_warning_printed>: Now bool.
(auto_load_pspace_data): Change type.
(~auto_load_pspace_info): Rename from
auto_load_pspace_data_cleanup.
(get_auto_load_pspace_data, init_loaded_scripts_info)
(clear_section_scripts, maybe_print_unsupported_script_warning)
(maybe_print_script_not_found_warning, _initialize_auto_load):
Update.
