The PE targets don't support mapping symbols and so the disassembler is unable
to correctly output thumb instructions when the input was thumb.
So for testcases that only have thumb output, I have copied them and skipped the
ones for which auto-detection is supposed to work on PE, and added a new one
that will force thumb output. This so that the tests still check the mapping
symbols.
For the tests that switch between thumb and arm in one file I just skip them
entirely on PE targets.
This cleans up the PE GAS testsuite.
gas/
* testsuite/gas/arm/archv6t2-1-pe.d: New test.
* testsuite/gas/arm/archv6t2-1.d: Skip pe.
* testsuite/gas/arm/csdb.d: Skip pe.
* testsuite/gas/arm/sb-thumb1-pe.d: New test.
* testsuite/gas/arm/sb-thumb1.d: Skip pe.
* testsuite/gas/arm/sb-thumb2-pe.d: New test.
* testsuite/gas/arm/sb-thumb2.d: Skip pe.
* testsuite/gas/arm/udf.d: Skip pe.
2019-01-16 Kito Cheng <kito@andestech.com>
bfd/
* elf-attrs.c (vendor_obj_attr_size): Return 0 if size is 0 even
for OBJ_ATTR_PROC.
gas/
* testsuite/gas/riscv/attribute-empty.d: New.
The assembler incorrectly recognised "c" as a register name, and
refused to allow it where it expected a symbol/label.
gas/
* config/tc-s12z.c (lex_reg_name): Compare the length of the strings
before the contents.
* testsuite/gas/s12z/labels.d: New file.
* testsuite/gas/s12z/labels.s: New file.
* testsuite/gas/s12z/s12z.exp: Add them.
Other assemblers permit "extending" a register into a register of a
smaller size or the same size. It doesn't make much sense to do this
but would appear to be a valid instruction. So change the error to a
warning.
gas/
* config/tc-s12z.c (tfr): Change as_bad to as_warn.
Also fix message typo and semantics.
gas/
* testsuite/gas/s12z/jsr.s: New case.
* testsuite/gas/s12z/jsr.d: New case.
opcodes/
* s12z-dis.c (opr_emit_disassembly): Do not omit an index if it is
zero.
This adds support for the Arm Ares CPU for AArch64.
It implements the Armv8.2-A architecture with the optional features
of statistical profiling, dot product and FP16 on by default.
Note: Ares is a codename to enable early adopters and in time
we will add the final product name once it's announced.
* config/tc-aarch64.c (aarch64_cpus): Add ares.
* doc/c-aarch64.texi (-mcpu): Document ares value.
This adds support for the Arm Ares CPU in the arm port.
It implements the Armv8.2-A architecture with the relevant optional
features
of dot product and FP16 on by default.
Note: Ares is a codename to enable early adopters and in time
we will add the final product name once it's announced.
* config/tc-arm.c (arm_cpus): Add ares.
* doc/c-arm.texi (-mcpu): Document ares value.
For PLT expressions, we should subtract the PLT relocation size only for
jump instructions. Since PLT relocations are PC relative, we only allow
"symbol@PLT" in PLT expression.
gas/
PR gas/23997
* config/tc-i386.c (x86_cons): Check for invalid PLT expression.
(md_apply_fix): Subtract the PLT relocation size only for jump
instructions.
* testsuite/gas/i386/reloc32.s: Add test for invalid PLT
expression.
* testsuite/gas/i386/reloc64.s: Likewise.
* testsuite/gas/i386/ilp32/reloc64.s: Likewise.
* testsuite/gas/i386/reloc32.l: Updated.
* testsuite/gas/i386/reloc64.l: Likewise.
* testsuite/gas/i386/ilp32/reloc64.l: Likewise.
ld/
PR gas/23997
* testsuite/ld-i386/i386.exp: Run PR gas/23997 test.
* testsuite/ld-x86-64/x86-64.exp: Likewise.
* testsuite/ld-x86-64/pr23997a.s: New file.
* testsuite/ld-x86-64/pr23997b.c: Likewise.
* testsuite/ld-x86-64/pr23997c.c: Likewise.
Linkers group input note sections with the same name into one output
note section with the same name. One output note section is placed in
one PT_NOTE segment. New linkers merge all input .note.gnu.property
sections into one output .note.gnu.property section with a single
NT_GNU_PROPERTY_TYPE_0 note in a single PT_NOTE segment. Since older
linkers treat input .note.gnu.property section as a generic note section
and just concatenate all input .note.gnu.property sections into one
output .note.gnu.property section without merging them, we may
see one or more NT_GNU_PROPERTY_TYPE_0 notes in PT_NOTE segment, which
are invalid.
GNU_PROPERTY_X86_UINT32_VALID was defined to address this issue such
that linker sets the bit for non-relocatable outputs. But it isn't
sufficient:
1. It doesn't cover generic properties.
2. When -mx86-used-note=yes is passed to x86 assembler, the
GNU_PROPERTY_X86_UINT32_VALID bit is set in GNU_PROPERTY_X86_ISA_1_USED
property in object file and older linkers generate invalid
NT_GNU_PROPERTY_TYPE_0 notes with the GNU_PROPERTY_X86_UINT32_VALID bit
set.
I am proposing the following changes:
1. Add PT_GNU_PROPERTY segment type:
# define PT_GNU_PROPERTY (PT_LOOS + 0x474e553)
which covers .note.gnu.property section.
2. Remove GNU_PROPERTY_X86_UINT32_VALID.
bfd/
PR ld/23900
* elf.c (get_program_header_size): Add a PT_GNU_PROPERTY
segment for NOTE_GNU_PROPERTY_SECTION_NAME.
(_bfd_elf_map_sections_to_segments): Create a PT_GNU_PROPERTY
segment for NOTE_GNU_PROPERTY_SECTION_NAME.
* elfxx-x86.c (_bfd_elf_link_setup_gnu_properties): Don't set
GNU_PROPERTY_X86_UINT32_VALID.
binutils/
PR ld/23900
* readelf.c (get_segment_type): Support PT_GNU_PROPERTY.
(decode_x86_isa): Don't check GNU_PROPERTY_X86_UINT32_VALID.
(decode_x86_feature_1): Likewise.
(decode_x86_feature_2): Likewise.
(print_gnu_property_note): Remove GNU_PROPERTY_X86_UINT32_VALID
check.
* testsuite/binutils-all/i386/empty.d: Updated.
* testsuite/binutils-all/x86-64/empty-x32.d: Likewise.
* testsuite/binutils-all/x86-64/empty.d: Likewise.
* testsuite/binutils-all/i386/pr21231b.s: Change
GNU_PROPERTY_X86_ISA_1_USED bits to 0x7fffffff.
* testsuite/binutils-all/x86-64/pr21231b.s: Likewise.
gas/
PR ld/23900
* config/tc-i386.c (x86_cleanup): Don't set
GNU_PROPERTY_X86_UINT32_VALID.
* testsuite/gas/i386/property-1.s: Change
GNU_PROPERTY_X86_ISA_1_USED bits to 0.
include/
PR ld/23900
* elf/common.h (PT_GNU_PROPERTY): New.
(GNU_PROPERTY_X86_UINT32_VALID): Removed.
ld/
PR ld/23900
* testsuite/ld-elf/elf.exp: Run PR ld/23900 test.
* testsuite/ld-elf/pr23900-1-32.rd: New file.
* testsuite/ld-elf/pr23900-1-64.rd: Likewise.
* testsuite/ld-elf/pr23900-1.d: Likewise.
* testsuite/ld-elf/pr23900-1.s: Likewise.
* testsuite/ld-elf/pr23900-2.s: Likewise.
* testsuite/ld-elf/pr23900-2a.d: Likewise.
* testsuite/ld-elf/pr23900-2b.d: Likewise.
* testsuite/ld-i386/ibt-plt-1.d: Adjusted.
* testsuite/ld-i386/ibt-plt-2c.d: Likewise.
* testsuite/ld-i386/ibt-plt-2d.d: Likewise.
* testsuite/ld-i386/ibt-plt-3d.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-1-x32.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-1.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-2c-x32.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-2c.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-2d-x32.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-2c.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-3c-x32.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-3c.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-3d-x32.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-3d.d: Likewise.
* testsuite/ld-i386/pr23372c.d: Expect <None>
for GNU_PROPERTY_X86_ISA_1_USED.
* testsuite/ld-x86-64/pr23372c-x32.d: Likewise.
* testsuite/ld-x86-64/pr23372c.d: Likewise.
* testsuite/ld-x86-64/pr23372d-x32.d: Likewise.
* testsuite/ld-x86-64/pr23372d.d: Likewise.
* testsuite/ld-x86-64/property-x86-5a.s: Change
GNU_PROPERTY_X86_ISA_1_USED bits to 0.
* testsuite/ld-x86-64/property-x86-5b.s: Likewise.
gas/
PR gas/23954
* config/tc-riscv.c (my_getSmallExpression): Expand comment for
register support. Set expr_end if parse a register.
(riscv_ip) <'u'>: Break if imm_expr is not a symbol or constant.
* testsuite/gas/riscv/auipc-parsing.d: New.
* testsuite/gas/riscv/auipc-parsing.l: New.
* testsuite/gas/riscv/auipc-parsing.s: New.
Put back BFD_RELOC_X86_64_GOTPCREL in TC_FORCE_RELOCATION_LOCAL, which
was removed by
commit 56ceb5b540
Author: H.J. Lu <hjl.tools@gmail.com>
Date: Thu Oct 22 04:49:20 2015 -0700
Add R_X86_64_[REX_]GOTPCRELX support to gas and ld
by accident.
PR gas/23956
gas/
* config/tc-riscv.c (validate_riscv_insn) <'1'>: New case.
(percent_op_null): New.
(riscv_ip) <'j'>: Set imm_reloc before p.
<'1'>: New case.
<'0'>: Use percent_op_null and don't set imm_reloc.
<alu_op>: Handle *args == '1'.
* testsuite/gas/riscv/tprel-add.d: New.
* testsuite/gas/riscv/tprel-add.l: New.
* testsuite/gas/riscv/tprel-add.s: New.
opcodes/
* riscv-opc.c (riscv_opcodes) <"add">: Use 1 not 0 for fourth arg.
This patch started off just adding the warnings in tc-ppc.c about
incorrect usage of @l, @h and @ha in instructions that don't have
16-bit D-form fields. That unfortunately showed up three warnings in
ld/testsuite/ld-powerpc/vle-multiseg.s on instructions like
e_li r3, IV_table@l+0x00
which was being assembled to
8: 70 60 00 00 e_li r3,0
a: R_PPC_ADDR16_LO IV_table
The ADDR16_LO reloc is of course completely bogus on e_li, which has
a split 20-bit signed integer field in bits 0x1f7fff, the low 11 bit
in 0x7ff, the next 5 bits in 0x1f0000, and the high 4 bits in 0x7800.
Applying an ADDR16_LO reloc to the instruction potentially changes
the e_li instruction to e_add2i., e_add2is, e_cmp16i, e_mull2i,
e_cmpl16i, e_cmph16i, e_cmphl16i, e_or2i, e_and2i., e_or2is, e_lis,
e_and2is, or some invalid encodings.
Now there is a relocation that suits e_li, R_PPC_VLE_ADDR20, which was
added 2017-09-05 but I can't see code in gas to generate the
relocation. In any case, VLE_ADDR20 probably doesn't have the correct
semantics for @l since ideally you'd want an @l to pair with @h or @ha
to generate a 32-bit constant. Thus @l should only produce a 16-bit
value, I think. So we need some more relocations to handle e_li it
seems, or as I do in this patch, modify the behaviour of existing
relocations when applied to e_li instructions.
include/
* opcode/ppc.h (E_OPCODE_MASK, E_LI_MASK, E_LI_INSN): Define.
bfd/
* elf32-ppc.c (ppc_elf_howto_raw <R_PPC_VLE_ADDR20>): Correct
mask and shift value.
(ppc_elf_vle_split16): Use E_OPCODE_MASK. Handle e_li
specially.
gas/
* config/tc-ppc.c (md_assemble): Adjust relocs for VLE before
TLS tweaks. Handle e_li. Warn on unexpected operand field
for lo16/hi16/ha16 relocs.
The RISC-V assembler generates fake labels with the name '.L0 ' as
part of the debug information (see
gas/config/tc-riscv.h:FAKE_LABEL_NAME).
The problem is that currently, when disassembling an object file, the
output looks like this (this is an example from the GDB testsuite, but
is pretty representative of anything with debug information):
000000000000001e <main>:
1e: 7179 addi sp,sp,-48
20: f406 sd ra,40(sp)
22: f022 sd s0,32(sp)
24: 1800 addi s0,sp,48
0000000000000026 <.L0 >:
26: 87aa mv a5,a0
28: feb43023 sd a1,-32(s0)
2c: fcc43c23 sd a2,-40(s0)
30: fef42623 sw a5,-20(s0)
0000000000000034 <.L0 >:
34: fec42783 lw a5,-20(s0)
38: 0007871b sext.w a4,a5
3c: 678d lui a5,0x3
3e: 03978793 addi a5,a5,57 # 3039 <.LASF30+0x2a9d>
42: 02f71463 bne a4,a5,6a <.L0 >
0000000000000046 <.L0 >:
46: 000007b7 lui a5,0x0
4a: 0007b783 ld a5,0(a5) # 0 <need_malloc>
4e: 6f9c ld a5,24(a5)
0000000000000050 <.L0 >:
50: 86be mv a3,a5
52: 466d li a2,27
54: 4585 li a1,1
56: 000007b7 lui a5,0x0
5a: 00078513 mv a0,a5
5e: 00000097 auipc ra,0x0
62: 000080e7 jalr ra # 5e <.L0 +0xe>
0000000000000066 <.L0 >:
66: 4785 li a5,1
68: a869 j 102 <.L0 >
000000000000006a <.L0 >:
6a: 000007b7 lui a5,0x0
6e: 00078513 mv a0,a5
72: 00000097 auipc ra,0x0
76: 000080e7 jalr ra # 72 <.L0 +0x8>
The frequent repeated '.L0 ' labels are pointless, as they are
non-unique there's no way to match a use of '.L0 ' to its appearence
in the output, so we'd be better off just not printing it at all.
That's what this patch does by defining a 'symbol_is_valid' method for
RISC-V. With this commit, the same disassembly now looks like this:
000000000000001e <main>:
1e: 7179 addi sp,sp,-48
20: f406 sd ra,40(sp)
22: f022 sd s0,32(sp)
24: 1800 addi s0,sp,48
26: 87aa mv a5,a0
28: feb43023 sd a1,-32(s0)
2c: fcc43c23 sd a2,-40(s0)
30: fef42623 sw a5,-20(s0)
34: fec42783 lw a5,-20(s0)
38: 0007871b sext.w a4,a5
3c: 678d lui a5,0x3
3e: 03978793 addi a5,a5,57 # 3039 <.LASF30+0x2a9d>
42: 02f71463 bne a4,a5,6a <.L4>
46: 000007b7 lui a5,0x0
4a: 0007b783 ld a5,0(a5) # 0 <need_malloc>
4e: 6f9c ld a5,24(a5)
50: 86be mv a3,a5
52: 466d li a2,27
54: 4585 li a1,1
56: 000007b7 lui a5,0x0
5a: 00078513 mv a0,a5
5e: 00000097 auipc ra,0x0
62: 000080e7 jalr ra # 5e <main+0x40>
66: 4785 li a5,1
68: a869 j 102 <.L5>
000000000000006a <.L4>:
6a: 000007b7 lui a5,0x0
6e: 00078513 mv a0,a5
72: 00000097 auipc ra,0x0
76: 000080e7 jalr ra # 72 <.L4+0x8>
In order to share the fake label between the assembler and the
libopcodes library, I've added some new defines RISCV_FAKE_LABEL_NAME
and RISCV_FAKE_LABEL_CHAR in include/opcode/riscv.h. I could have
just moved FAKE_LABEL_NAME to the include file, however, I thnk this
would be confusing, someone working on the assembler would likely not
expect to find FAKE_LABEL_NAME defined outside of the assembler source
tree. By introducing the RISCV_FAKE_LABEL_* defines I can leave the
assembler standard FAKE_LABEL_ defines in the assembler source, but
still share the RISCV_FAKE_LABEL_* with libopcodes.
gas/ChangeLog:
* config/tc-riscv.h (FAKE_LABEL_NAME): Define as
RISCV_FAKE_LABEL_NAME.
(FAKE_LABEL_CHAR): Define as RISCV_FAKE_LABEL_CHAR.
include/ChangeLog:
* dis-asm.h (riscv_symbol_is_valid): Declare.
* opcode/riscv.h (RISCV_FAKE_LABEL_NAME): Define.
(RISCV_FAKE_LABEL_CHAR): Define.
opcodes/ChangeLog:
* disassembler.c (disassemble_init_for_target): Add RISC-V
initialisation.
* riscv-dis.c (riscv_symbol_is_valid): New function.
Armv8.3-A has another key used in pointer authentication called the
B-key (other than the A-key that is already supported). In order for
stack unwinders to work it is necessary to be able to identify frames
that have been signed with the B-key rather than the A-key and it was
felt that keeping this as an augmentation character in the CIE was the
best bet. The DWARF extensions for ARM therefore propose to add a new
augmentation character 'B' to the CIE augmentation string and the
corresponding cfi directive ".cfi_b_key_frame". I've made the relevant
changes to GAS and LD to add support for B-key unwinding, which required
modifying LD to check for 'B' in the augmentation string, adding the
".cfi_b_key_frame" directive to GAS and adding a "pauth_key" field to
GAS's fde_entry and cie_entry structs.
The pointer authentication instructions will behave as NOPs on
architectures that don't support them, and so a check for the
architecture being assembled for is not necessary since there will be no
behavioural difference between augmentation strings with and without the
'B' character on such architectures.
2018-12-05 Sam Tebbs <sam.tebbs@arm.com>
bfd/
* elf-eh-frame.c (_bfd_elf_parse_eh_frame): Add check for 'B'.
gas/
* dw2gencfi.c (struct cie_entry): Add tc_cie_entry_extras invocation.
(alloc_fde_entry): Add tc_fde_entry_init_extra invocation.
(output_cie): Add tc_output_cie_extra invocation.
(select_cie_for_fde): Add tc_cie_fde_equivalent_extra and
tc_cie_entry_init_extra invocation.
(frch_cfi_data, cfa_save_data): Move to dwgencfi.h.
* config/tc-aarch64.c (s_aarch64_cfi_b_key_frame): Declare.
(md_pseudo_table): Add "cfi_b_key_frame".
* config/tc-aarch64.h (tc_fde_entry_extras, tc_cie_entry_extras,
tc_fde_entry_init_extra, tc_output_cie_extra,
tc_cie_fde_equivalent_extra, tc_cie_entry_init_extra): Define.
* dw2gencfi.h (struct fde_entry): Add tc_fde_entry_extras invocation.
(pointer_auth_key): Define.
(frch_cfi_data, cfa_save_data): Move from dwgencfi.c.
* doc/c-aarch64.texi (.cfi_b_key_frame): Add documentation.
* testsuite/gas/aarch64/(pac_ab_key.d, pac_ab_key.s): New file.
ARM Architecture Reference Manual for the profile ARMv8-A, Issue C.a,
states that MOV (register) is an alias of the ORR (shifted register)
iff shift == '00' && imm6 == '000000' && Rn == '11111'. However, mov
is currently preferred for a broader range of orr instructions, which
is incorrect.
2018-12-03 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
opcodes:
PR 23193
PR 19721
* aarch64-tbl.h (aarch64_opcode_table): Only disassemble an ORR
encoding as MOV if the shift operation is a left shift of zero.
gas:
PR 23193
PR 19721
* testsuite/gas/aarch64/pr19721.s: Add new test cases.
* testsuite/gas/aarch64/pr19721.d: Correct existing test
cases and add new ones.
This removes ineffectual and wrong code caching section names in
gas/stabs.c. Code like
seg = subseg_new (name, 0);
...
if (seg->name == name)
seg->name = xstrdup (name);
with the idea of being able to unconditionally free "name" later no
longer works. "name" is referenced by the section hash table as well
as in the section->name field. It would be possible to use
"bfd_rename_section (stdoutput, seg, xstrdup (name))", but instead I
opted for a fairly straight-forward approach of adding extra
parameters to two functions to indicate section name strings should be
freed if possible.
PR 23938
* read.h (get_stab_string_offset): Update prototype.
* stabs.c (get_stab_string_offset): Add free_stabstr_secname
parameter. Free stabstr_secname if unused as section name.
Don't xstrdup name when used.
(s_stab_generic): Remove forward declaration. Add
stab_secname_obstack_end param. Reference notes obstack via
macros. Delete cached_secname. Adjust get_stab_string_offset
call. Free stab_secname if unused as section name.
(s_stab): Adjust s_stab_generic call.
(s_xstab): Likewise. Delete saved_secname and saved_strsecname.
* config/obj-elf.c (obj_elf_init_stab_section): Adjust
get_stab_string_offset call.
* config/obj-coff.c (obj_coff_init_stab_section): Likewise.
* config/obj-som.c (obj_som_init_stab_section): Likewise.
* testsuite/gas/all/pr23938.s: New test.
* testsuite/gas/all/gas.exp: Run it.
`-march=r5900' already enables the R5900 short loop workaround.
However, the R5900 ISA and most other MIPS ISAs are mutually
exclusive since R5900-specific instructions are generated as well.
The `-mfix-r5900' option can be used in combination with e.g.
`-mips2' or `-mips3' to generate generic MIPS binaries that also
work with the R5900 target.
This change has been tested with `make RUNTESTFLAGS=mips.exp
check-gas' for the targets `mipsr5900el-unknown-linux-gnu',
`mipsr5900el-elf' and `mips3-unknown-linux-gnu'.
gas/
* config/tc-mips.c (mips_fix_r5900, mips_fix_r5900_explicit):
New variables.
(options): Add OPTION_FIX_R5900 and OPTION_NO_FIX_R5900
enumeration constants.
(md_longopts): Add "mfix-r5900" and "mno-fix-r5900" options.
(can_swap_branch_p, md_parse_option, mips_after_parse_args):
Handle the new options.
(md_show_usage): Document the `-mfix-r5900' option.
* doc/as.texi: Likewise.
* doc/c-mips.texi: Likewise.
* testsuite/gas/mips/mips.exp: Run R5900 dump tests.
* testsuite/gas/mips/r5900-fix.d: Test `-mfix-r5900' option.
* testsuite/gas/mips/r5900-fix.s: Likewise.
* testsuite/gas/mips/r5900-no-fix.d: Test `-mno-fix-r5900'.
* testsuite/gas/mips/r5900-no-fix.s: Likewise.
Shift and rotate instructions when the number of bit positions
was an immediate value greater than 1 were incorrectly disassembled.
This change fixes that problem and extends the test to check for
it.
gas/ChangeLog:
testsuite/gas/s12z/shift.s: Add new test case.
testsuite/gas/s12z/shift.d: Add expected result.
opcodes/ChangeLog:
s12z-dis.c (print_insn_shift) [SB_REG_REG_N]: Enter special case
if the postbyte matches the appropriate pattern.
These are documented by NXP as alternative mnemonics for BCC and BCS
respectively.
gas/ChangeLog:
* config/tc-s12z.c (opcodes): bhs, blo: New members.
* testsuite/gas/s12z/bra.d: Add tests for aliases.
* testsuite/gas/s12z/bra.s: Add tests for aliases.
This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions which is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.
This patch adds all the data cache instructions that are part of this
extension:
- DC IGVAC, Xt
- DC IGSW, Xt
- DC CGSW, Xt
- DC CIGSW, Xt
- DC CGVAC, Xt
- DC CGVAP, Xt
- DC CGVADP, Xt
- DC CIGVAC, Xt
- DC GVA, Xt
- DC IGDVAC, Xt
- DC IGDSW, Xt
- DC CGDSW, Xt
- DC CIGDSW, Xt
- DC CGDVAC, Xt
- DC CGDVAP, Xt
- DC CGDVADP, Xt
- DC CIGDVAC, Xt
- DC GZVA, Xt
*** opcodes/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.c (aarch64_sys_regs_dc): New entries for
IGVAC, IGSW, CGSW, CIGSW, CGVAC, CGVAP, CGVADP, CIGVAC, GVA,
IGDVAC, IGDSW, CGDSW, CIGDSW, CGDVAC, CGDVAP, CGDVADP,
CIGDVAC and GZVA.
(aarch64_sys_ins_reg_supported_p): New check for above.
*** gas/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* testsuite/gas/aarch64/sysreg-4.s: Test IGVAC, IGSW,
CGSW, CIGSW, CGVAC, CGVAP, CGVADP, CIGVAC, GVA,
IGDVAC, IGDSW, CGDSW, CIGDSW, CGDVAC, CGDVAP, CGDVADP,
CIGDVAC and GZVA with DC.
* testsuite/gas/aarch64/sysreg-4.d: Likewise.
* testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions which is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.
This patch adds all the system registers that are part of this
extension and are accessible via the MRS/MSR instructions:
- TCO
- TFSRE0_SL1
- TFSR_EL1
- TFSR_EL2
- TFSR_EL3
- TFSR_EL12
- RGSR_EL1
- GCR_EL1
TCO is also accessible with the MSR(immediate) instruction.
*** opcodes/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.c (aarch64_sys_regs): New entries for TCO,
TFSRE0_SL1, TFSR_EL1, TFSR_EL2, TFSR_EL3, TFSR_EL12,
RGSR_EL1 and GCR_EL1.
(aarch64_sys_reg_supported_p): New check for above.
(aarch64_pstatefields): New entry for TCO.
(aarch64_pstatefield_supported_p): New check for above.
*** gas/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* testsuite/gas/aarch64/sysreg-4.s: Test TCO, TFSRE0_SL1,
TFSR_EL1, TFSR_EL2, TFSR_EL3, TFSR_EL12, RGSR_EL1 and
GCR_EL1 MSR and MRS.
* testsuite/gas/aarch64/sysreg-4.d: Likewise.
* testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
Nick Clifton
Tamar Christina
Jim Wilson
John Darrington
Srinath Parvathaneni
Alan Modra
Andrew Paprocki
Kyrylo Tkachov
Yoshinori Sato
Wu Heng
H.J. Lu
Jeff Law
Sam Tebbs
Andre Vieira
Andrew Burgess
Egeyar Bagcioglu
Fredrik Noring
Thomas Preud'homme
Jozef Lawrynowicz
Sudakshina Das