run_dump_test proposes an ld action but when trying to make use of it in
a gas test it gave me some Tcl error. It turns out that it references
the check_shared_lib_support procedure and ld_elf_shared_opt variable
both only available in ld-lib.exp. I've thus moved the procedure in
binutils-common.exp and defined the variable needed in the various
default.exp of testsuite that seem to be using run_dump_test.
Since check_shared_lib_support itself references the ld variable not
defined in binutils-common I've defined it from LD in run_dump_test and
fixed LD and LDFLAGS to be defined as expected by run_dump_test in the
various default.exp of testsuite using run_dump_test.
2018-11-01 Thomas Preud'homme <thomas.preudhomme@linaro.org>
binutils/
* testsuite/config/default.exp: Define LD, LDFLAGS and
ld_elf_shared_opt.
* testsuite/lib/binutils-common.exp (check_shared_lib_support): Moved
from ld-lib.exp.
(run_dump_test): Set ld to $LD.
gas/
* testsuite/config/default.exp: Define LD, LDFLAGS and
ld_elf_shared_opt.
ld/
* testsuite/lib/ld-lib.exp (check_shared_lib_support): Moved to
binutils-common.exp.
This test never used to test the output of objdump as the old 'error-output'
check would exit after verifying the output in stdout and stderr from the
assembler. Given the use of warning_output now, the objdump runs and expects
its output to be verified. Assuming the correct disassembly of these
instructions is tested elsewhere given we never tested them here, this patch
removes the objdump run.
gas/ChangeLog
2018-10-31 Andre Vieira <andre.simoesdiasvieira@arm.com>
* testsuite/gas/arm/armv8-a+rdma-warning.d: Remove objdump execution.
The old test never checked the objdump output since the 'error-output' directive
would exit and thus never run objdump. When this test was changed to adhere to
use the new warning_output we started to run objdump. The expected objdump
output was old and had bitrotten, this fixes the layout, as the "disassembly"
itself did not change.
gas/ChangeLog
2018-10-31 Andre Vieira <andre.simoesdiasvieira@arm.com>
* testsuite/gas/arm/udf.d: Update expected output.
This test has been failing for a while and it could be argued that since we
started testing 'arm7t' here (and not Armv1) the test itself was wrong. So I
changed the assembly to Armv1. Given the changes to objdump when
"disassembling all" it seemed like a good idea to force the disassembly to
'armv2' instead and actually accept the disassembly of the 26-bit Architecture
variants of tst, teq, cmn and cmp.
gas/ChangeLog
2018-10-31 Andre Vieira <andre.simoesdiasvieira@arm.com>
* testsuite/gas/arm/armv1.d: Assemble for Armv1 and disassemble for
Armv2.
This file was never supposed to be widely used. The fact that it has
found its way into many gas files led to bugs, typically when code
expecting a symbolS* to point at a struct symbol is presented with a
struct local_symbol. Also, commit 158184ac9e changed these structs in
2012 but didn't catch all places where symbol bsym was being used to
test for a local_symbol.
* Makefile.am (HFILES): Delete struc-symbol.h.
* doc/internals.texi: Delete struc-symbol.h reference and out
of date local symbol description.
* struc-symbol.h: Delete. Move contents to..
* symbols.c: ..here.
(symbol_on_chain, symbol_symbolS): New functions.
* symbols.h (symbol_on_chain, symbol_symbolS): Declare.
* cgen.c: Don't #include struc-symbol.h.
(gas_cgen_parse_operand): Don't test for local_symbol using
bsym, instead call symbol_symbolS. Use symbol_get_bfdsym.
(weak_operand_overflow_check, make_right_shifted_expr): Use
symbol accessors.
* config/obj-coff.c: Don't #include struc-symbol.h.
(GET_FILENAME_STRING): Delete.
* config/obj-elf.c: Don't #include struc-symbol.h.
(elf_file_symbol): Use symbol accessors.
(elf_adjust_symtab): Call symbol_on_chain.
* config/obj-evax.c: Don't #include struc-symbol.h.
* config/tc-nds32.c: Likewise.
* config/tc-rl78.c: Likewise.
* config/tc-rx.c: Likewise.
* config/tc-alpha.c: Likewise.
(add_to_link_pool, s_alpha_comm): Use symbol accessors.
* config/tc-arc.c: Don't #include struc-symbol.h.
(arc_check_relocs): Use symbol accessors, testing gas symbol
section rather than bfd symbol section.
* config/tc-avr.c: Don't #include struc-symbol.h.
(avr_patch_gccisr_frag): Use symbol accessors.
* config/tc-bfin.c: Don't #include struc-symbol.h.
(bfin_loop_beginend): Use symbol accessors.
* config/tc-csky.c: Don't #include struc-symbol.h.
(v2_work_movih, v2_work_ori): Use symbol accessors. Check for
absolute symbol as well as O_constant.
* config/tc-riscv.c: Don't #include struc-symbol.h.
(riscv_pre_output_hook): Use symbol accessors.
* config/tc-s390.c: Don't #include struc-symbol.h.
(s390_literals): Use symbol accessors.
* config/tc-score.c (s3_build_la_pic, s3_build_lwst_pic): Use
symbol accessors.
(s3_relax_branch_inst16, s3_relax_cmpbranch_inst32): Don't
test symbol bsym.
* config/tc-score7.c: Don't #include struc-symbol.h.
(s7_build_la_pic, s7_build_lwst_pic): Use symbol accessors.
(s7_b32_relax_to_b16): Don't test symbol bsym.
* config/tc-sh.c: Don't #include struc-symbol.h.
(insert_loop_bounds): Use symbol accessors.
(sh_frob_section): Remove bogus symbol canonicalization.
* config/tc-tic54x.c: Don't #include struc-symbol.h.
(tic54x_bss): Use symbol accessors.
* config/tc-tilegx.c: Don't #include struc-symbol.h.
(emit_tilegx_instruction, tilegx_parse_name): Use symbol accessors.
* config/tc-tilepro.c: Don't #include struc-symbol.h.
(emit_tilepro_instruction, tilepro_parse_name): Use accessors.
* config/tc-xtensa.c: Don't #include struc-symbol.h.
(xg_assemble_vliw_tokens): Use symbol accessors.
(xg_order_trampoline_chain): Likewise.
* ehopt.c: Don't #include struc-symbol.h.
(check_eh_frame): Correct local symbol test. Use symbol accessors.
* write.c: Don't #include struc-symbol.h.
(create_note_reloc, maybe_generate_build_notes): Use symbol accessors.
* Makefile.in: Regenerate.
* po/POTFILES.in: Regenerate.
Local symbols don't have a sy_frag field.
PR 23837
* config/tc-hppa.c: Don't include struc-symbol.h.
(pa_build_unwind_subspace): Call get_symbol_frag rather than
referencing sy_frag.
This patch adds the vector alignment hints to the vector load and
store instructions as documented in the IBM z14 Principles of
Operations manual:
http://publibfi.boulder.ibm.com/epubs/pdf/dz9zr011.pdf
opcodes/ChangeLog:
2018-10-23 Andreas Krebbel <krebbel@linux.ibm.com>
* s390-opc.txt: Add vector load/store instructions with additional
alignment parameter.
gas/ChangeLog:
2018-10-23 Andreas Krebbel <krebbel@linux.ibm.com>
* config/tc-s390.c (md_gather_operands): Fix for optional operands
following memory addresses.
* testsuite/gas/s390/zarch-arch12.d: Add regexp checks for new
instruction variants.
* testsuite/gas/s390/zarch-arch12.s: Emit new instruction
variants.
Commit 1f38083f425e03faf55595414daf291306738222 added a test
to check that the assembler handled fixups with resolved to
constant values. We were not handling this in the case of
16 bit values. This change fixes that.
* gas/config/tc-s12z.c (md_apply_fix): Handle BFD_RELOC_16
Tests that target md_apply_fix can handle fixups that have resolved
down to a constant and thus do not need relocations.
Also a fix for eqv-dot xfails.
* testsuite/gas/all/simple-forward.d,
* testsuite/gas/all/simple-forward.s: New test.
* testsuite/gas/all/gas.exp: Run it.
* testsuite/gas/all/eqv-dot.d: xfail tic30 and tic54x.
* config/tc-alpha.c (md_apply_fix): Handle BFD_RELOC_8 for fixups
without a symbol.
* testsuite/gas/all/gas.exp: Don't xfail forward test here..
* testsuite/gas/all/forward.d: ..do so here, removing alpha.
What a trip down a rabbit hole this bug has been.
First observation: You can't use deferred_expression in s_leb128.
deferred_expression implements the semantics of .eqv or '==', saving
an expression with minimal simplification for assignment to a symbol
so that the expression is evaluated at uses of the symbol. In
particular, the value of "dot" is not evaluated at the .eqv symbol
assignment, but later. When s_leb128 uses deferred_expression,
"later" is at the end of assembly, giving entirely the wrong value of
"dot". There is no way to fix this for the s_leb128 use without
breaking .equ (which incidentally was already somewhat broken, see
commit e4c2619ad1). So, don't use deferred_expression in s_leb128.
But that leads to the gas test elf/dwarf2-17 failing, because view
symbols are calculated with a chain of expression symbols. In the
dwarf2-17 .L1 case there is a "temp_sym_1 > temp_sym_2" expression,
with temp_sym_1 and temp_sym_2 on either side of a ".balign". Since
".balign" and many other directives moving "dot" are not calculated on
the first (and only) pass over source, .L1 cannot be calculated until
final addresses are assigned to frags. However, ".uleb128 .L1" *is*
calculated immediately, resulting in the wrong value.
The reason why .L1 is calculated immediately is that code in
expr.c:operand after the comment
/* If we have an absolute symbol or a reg, then we know its
value now. */
does as it says and fixes the value of .L1, because .L1 is assigned
to absolute_section in dwarf2dbg.c:set_or_check_view. So, correct
that to expr_section.
Unfortunately that fix leads to failure of the elf/dwarf2-5 test with
../gas/elf/dwarf2-5.s: Error: attempt to get value of unresolved symbol `.L5'
../gas/elf/dwarf2-5.s: Error: attempt to get value of unresolved symbol `.L11'
../gas/elf/dwarf2-5.s: Error: attempt to get value of unresolved symbol `.L12'
So why is that? Well, it turns out that .L5 is defined in terms of
.L4, and apparently .L4 is undefined. But .L4 clearly is defined,
otherwise we would hit an error when trying to use .L4 a little
earlier. There are two copies of .L4! So, symbols are cloned when
that should not happen.
Symbol cloning is a technique used by gas to support saving the value
of symbols that change between uses, but that isn't the case with
.L4. Only one value is set and used for .L4, but indeed .L4 was being
cloned by symbol_clone_if_forward_ref. This despite no forward refs
being present. Also, .L4 is a local symbol and a cursory glance at
symbol_clone_if_forward_ref "if (symbolP && !LOCAL_SYMBOL_CHECK (symbolP))"
would seem to prevent cloning of local symbols. All is not as it
seems though, a curse of using macros. LOCAL_SYMBOL_CHECK modifies
its argument if a "struct local_symbol" is converted to the larger
"struct symbol", as happens when assigning a view symbol value.
That fact results in the recursive call to symbol_clone_if_forward_ref
returning a different address for "add_symbol". This problem could
have been fixed by using symbol_same_p rather than comparing symbol
pointers, but I thought it better to use the real symbol throughout.
Note that symbol_find_exact also returns the real symbol for a
converted local symbol.
Finally, this patch does expose lack of support for forward symbol
definitions in various targets. For example:
alpha-linux +ERROR: ../ld/testsuite/ld-elf/pr11138-2.c: compilation failed
This is caused by view symbol uses. On alpha-linux-gcc (GCC) 8.1.1
20180502 they happen to occur in .byte directives so were silently
broken in cases like elf/dwarf2-17 anyway.
/tmp/ccvtsMfU.s: Assembler messages:
/tmp/ccvtsMfU.s: Fatal error: unhandled relocation type BFD_RELOC_8
/tmp/ccvtsMfU.s: Fatal error: unhandled relocation type BFD_RELOC_8
md_apply_fix on those targets needs to handle fixups that resolve down
to a constant.
PR 23040
* symbols.c (get_real_sym): New function.
(symbol_same_p): Use get_real_sym.
(symbol_clone_if_forward_ref): Save real original add_symbol and
op_symbol for comparison against that returned from lookup or
recursive calls.
* dwarf2dbg.c (set_or_check_view): Use expr_section for
expression symbols, not absolute_section.
(dwarf2_directive_loc): Check symbol_equated_p and tidy cloning
of view symbols.
* read.c (s_leb128): Don't use deferred_expression.
.eqv (and ==) ought not simplify expressions involving dot or other
symbols set by .eqv. If such simplification occurs, the value of dot
will be that at the assignment rather than at the place where the
symbol is used.
PR 23800
* expr.c (expr): Don't simplify expressions involving forward_ref
symbols when mode is expr_defer.
* config/tc-spu.c (spu_cons): Parse expression using normal
expression evaluation if @ppu is not detected.
* testsuite/gas/all/eqv-dot.d,
* testsuite/gas/all/eqv-dot.s: New test.
* testsuite/gas/all/gas.exp: Run it.
The two new test I added require the use of the ".inst" directive which the PE
targets don't support. Because of that I excluded *-unknown-pe but the mask needs
to be wider. I am now excluding *-*-pe.
gas/ChangeLog:
* testsuite/gas/arm/undefined-insn-arm.d: Widen pe skip.
* testsuite/gas/arm/undefined-insn-thumb.d: Likewise.
The disassembler for Arm has some aborts in it in places it assumes can never
be reached. Under normal circumstances they indeed cannot be reached because
the right options are selected from the ARM attributes in the ELF file.
However when disassembling with -b binary then if you do not get the options
right the disassembler just aborts. This changes it so it just prints how it
was trying to interpret the instruction and prints UNKNOWN instructions next to it.
This way the user has an idea of what's going.
gas/ChangeLog:
* testsuite/gas/arm/undefined-insn-arm.d: New test.
* testsuite/gas/arm/undefined-insn-thumb.d: New test.
* testsuite/gas/arm/undefined-insn.s: New test.
opcodes/ChangeLog:
* arm-dis.c (UNKNOWN_INSTRUCTION_32BIT): Format specifier for arm mode.
(UNKNOWN_INSTRUCTION_16BIT): Format specifier for thumb mode.
(print_insn_arm, print_insn_thumb16, print_insn_thumb32): Use them.
* testsuite/gas/mips/r5900.s: Extend the R5900 short loop fix
test with border cases.
* testsuite/gas/mips/r5900.d: Add extra expected disassembly.
* config/tc-mips.c (can_swap_branch_p): Clarify the R5900 short
loop hardware bug conditions. Correct note on the R5900
instruction count short loop fix.
Committed on behalf of Matthew Malcomson:
The SIMD UDOT instruction assembly has an unusual operand that selects a single
32 bit element with the mnemonic 4B.
This unusual mnemonic is handled by a special operand qualifier and associated
qualifier data in `aarch64_opnd_qualifiers`.
The current qualifier data describes 4 1-byte elements with the structure
{1, 4, 0x0, "4b", OQK_OPD_VARIANT}
This makes sense, as the instruction does work on 4 1-byte elements, however
some logic in the `operand_general_constraint_met_p` makes assumptions about
the range of index allowed when selecting a SIMD_ELEMENT depending on element
size.
That function reasons that e.g. in order to select a byte-sized element in a 16
byte V register an index must allow selection of one of the 16 elements and
hence its range will be in [0,15].
This reasoning breaks with the above description of a 4 part selection of 1
byte elements and allows an index outside the valid [0,3] range, triggering an
assert later on in the program in `aarch64_ins_reglane`.
vshcmd: > echo 'udot v0.2s, v1.8b, v2.4b[4]' | ../src/binutils-build/gas/as-new -march=armv8.4-a
as-new: ../../binutils-gdb/opcodes/aarch64-asm.c:134: aarch64_ins_reglane: Assertion `reglane_index < 4' failed.
{standard input}: Assembler messages:
{standard input}:1: Internal error (Aborted).
Please report this bug.
This patch changes the operand qualifier data so that it describes a single
32 bit element.
{4, 1, 0x0, "4b", OQK_OPD_VARIANT}
Hence the calculation in `operand_general_constraint_met_p` provides the
correct answer and the usual error checking machinery is used.
vshcmd: > echo 'udot v0.2s, v1.8b, v2.4b[4]' | ../src/binutils-build/gas/as-new -march=armv8.4-a
{standard input}: Assembler messages:
{standard input}:1: Error: register element index out of range 0 to 3 at operand 3 -- `udot v0.2s,v1.8b,v2.4b[4]'
This patch performs a run-time test that a shared libbfd.so has been
compiled with the same size bfd_vma as that of apps using the library.
On a 32-bit host it is easily possible to have one libbfd.so compiled
to support 64-bit targets (or configured with --enable-64-bit-bfd)
while another only supports 32-bit targets. The two libraries will
have differently sized bfd_vma types, and if the wrong one is loaded
all sorts of weird behaviour might be seen.
bfd/
PR 23534
* init.c (BFD_INIT_MAGIC): Define.
(bfd_init): Return BFD_INIT_MAGIC.
bfd-in2.h: Regenerate.
binutils/
PR 23534
* addr2line.c (main): Exit with fatal error if bfd_init
returns an unexpected value.
* ar.c (main): Likewise.
* dlltool.c (identify_dll_for_implib): Likewise.
* nm.c (main): Likewise.
* objcopy.c (main): Likewise.
* objdump.c (main): Likewise.
* size.c (main): Likewise.
* strings.c (main): Likewise.
* windmc.c (main): Likewise.
* windres.c (main): Likewise.
gas/
PR 23534
* as.c (main): Exit with fatal error if bfd_init returns an
unexpected value.
ld/
PR 23534
* ldmain.c (main): Exit with fatal error if bfd_init returns
an unexpected value.
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)
The encodings can be found in the System Register XML.
This patch adds support for the mitigation for Spectre Variant 4 by
adding the PSTATE bit SSBS which are accessible using MSR and MRS
instructions. Although this is a mandatory addition to the ARMv8.5-A,
it is permitted to be added to any version of the ARMv8 architecture.
This is enabled using the command line option of +ssbs for older
versions.
*** include/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_SSBS): New.
(AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_SSBS by default.
*** opcodes/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.c (operand_general_constraint_met_p): Add
SSBS in the check for one-bit immediate.
(aarch64_sys_regs): New entry for SSBS.
(aarch64_sys_reg_supported_p): New check for above.
(aarch64_pstatefields): New entry for SSBS.
(aarch64_pstatefield_supported_p): New check for above.
*** gas/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (aarch64_features): Add new "ssbs".
* doc/c-aarch64.texi: Document the same.
* testsuite/gas/aarch64/ssbs-illegal1.d: New test.
* testsuite/gas/aarch64/ssbs-illegal1.l: New test.
* testsuite/gas/aarch64/ssbs-illegal2.d: New test.
* testsuite/gas/aarch64/ssbs-illegal2.l: New test.
* testsuite/gas/aarch64/ssbs.s: New test.
* testsuite/gas/aarch64/ssbs1.d: Test with +ssbs
* testsuite/gas/aarch64/ssbs2.d: Test with armv8.5-a.
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)
The encodings can be found in the System Register XML.
This patch adds the new system registers SCXTNUM_ELx and ID_PFR2_EL1.
*** include/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_SCXTNUM): New.
(AARCH64_FEATURE_ID_PFR2): New.
(AARCH64_ARCH_V8_5): Add both by default.
*** opcodes/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.c (aarch64_sys_regs): New entries for
scxtnum_el[0,1,2,3,12] and id_pfr2_el1.
(aarch64_sys_reg_supported_p): New checks for above.
*** gas/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* testsuite/gas/aarch64/sysreg-4.s: Test registers
scxtnum_el[0,1,2,3,12] and id_pfr2_el1.
* testsuite/gas/aarch64/sysreg-4.d: Likewise.
* testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order/bti-branch-target-identification)
The Branch Target Identification instructions (BTI) are allocated to
existing HINT space, using HINT numbers 32, 34, 36, 38, such that
bits[7:6] of the instruction identify the compatibility of the BTI
instruction to different branches.
BTI {<targets>}
where <targets> one of the following, specifying which type of
indirection is allowed:
j : Can be a target of any BR Xn isntruction.
c : Can be a target of any BLR Xn and BR {X16|X17}.
jc: Can be a target of any free branch.
A BTI instruction without any <targets> is the strictest of all and
can not be a target of nay free branch.
*** include/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_BTI): New.
(AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_BTI by default.
(aarch64_opnd): Add AARCH64_OPND_BTI_TARGET.
(HINT_OPD_CSYNC, HINT_OPD_C, HINT_OPD_J): New macros to
define HINT #imm values.
(HINT_OPD_JC, HINT_OPD_NULL): Likewise.
*** opcodes/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New.
(HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag
with the hint immediate.
* aarch64-opc.c (aarch64_hint_options): New entries for
c, j, jc and default (with HINT_OPD_F_NOPRINT flag) for BTI.
(aarch64_print_operand): Add case for AARCH64_OPND_BTI_TARGET
while checking for HINT_OPD_F_NOPRINT flag.
* aarch64-dis.c (aarch64_ext_hint): Use new HINT_VALUE to
extract value.
* aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): New.
(aarch64_opcode_table): Add entry for BTI.
(AARCH64_OPERANDS): Add new description for BTI targets.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
*** gas/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (parse_bti_operand): New.
(process_omitted_operand): Add case for AARCH64_OPND_BTI_TARGET.
(parse_operands): Likewise.
* testsuite/gas/aarch64/system.d: Update for BTI.
* testsuite/gas/aarch64/bti.s: New.
* testsuite/gas/aarch64/bti.d: New.
* testsuite/gas/aarch64/illegal-bti.d: New.
* testsuite/gas/aarch64/illegal-bti.l: New.
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)
The encodings can be found in the System Register XML.
This patch adds the following:
MSR Xn, RNDR
MSR Xn, RNDRRS
These are optional instructions in ARMv8.5-A and hence the new
+rng is added.
*** include/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_RNG): New.
*** opcodes/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.c (aarch64_sys_regs): New entries for
rndr and rndrrs.
(aarch64_sys_reg_supported_p): New check for above.
*** gas/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (aarch64_features): New "rng" option.
* doc/c-aarch64.texi: Document the same.
* testsuite/gas/aarch64/sysreg-4.s: Test both instructions.
* testsuite/gas/aarch64/sysreg-4.d: Likewise.
* testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order/dc-data-cache-operation-an-alias-of-sys)
This patch adds the DC CVADP instruction. Since this has a separate
identification mechanism a new feature bit is added.
*** include/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_CVADP): New.
*** opcodes/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp.
(aarch64_sys_ins_reg_supported_p): New check for above.
*** gas/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* testsuite/gas/aarch64/sysreg-4.s: Test instruction.
* testsuite/gas/aarch64/sysreg-4.d: Likewise.
* testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order)
This patch adds the prediction restriction instructions (that is, cfp,
dvp, cpp). These instructions are retrospectively made optional for
all versions of the architecture from ARMv8.0 to ARMv8.4 and is
mandatory from ARMv8.5. Hence adding a new +predres which can be used
by the older architectures.
*** include/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_PREDRES): New.
(AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_PREDRES by default.
(aarch64_opnd): Add AARCH64_OPND_SYSREG_SR.
(aarch64_sys_regs_sr): Declare new table.
*** opcodes/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-dis.c (aarch64_ext_sysins_op): Add case for
AARCH64_OPND_SYSREG_SR.
* aarch64-opc.c (aarch64_print_operand): Likewise.
(aarch64_sys_regs_sr): Define table.
(aarch64_sys_ins_reg_supported_p): Check for RCTX with
AARCH64_FEATURE_PREDRES.
* aarch64-tbl.h (aarch64_feature_predres): New.
(PREDRES, PREDRES_INSN): New.
(aarch64_opcode_table): Add entries for cfp, dvp and cpp.
(AARCH64_OPERANDS): Add new description for SYSREG_SR.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
*** gas/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (aarch64_sys_regs_sr_hsh): New.
(parse_operands): Add entry for AARCH64_OPND_SYSREG_SR.
(md_begin): Allocate and initialize aarch64_sys_regs_sr_hsh
with aarch64_sys_regs_sr.
(aarch64_features): Add new "predres" option for older
architectures.
* doc/c-aarch64.texi: Document the same.
* testsuite/gas/aarch64/sysreg-4.s: New.
* testsuite/gas/aarch64/sysreg-4.d: New.
* testsuite/gas/aarch64/illegal-sysreg-4.d: New.
* testsuite/gas/aarch64/illegal-sysreg-4.l: New.
* testsuite/gas/aarch64/predres.s: New.
* testsuite/gas/aarch64/predres.d: New.
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order)
This instruction is retrospectively made optional for all versions of
the architecture from ARMv8.0 to ARMv8.4 and is mandatory from
ARMv8.5. Hence a new command line option of "+sb" is added for older
architectures.
*** include/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_SB): New.
(AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_SB by default.
*** opcodes/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-tbl.h (aarch64_feature_sb): New.
(SB, SB_INSN): New.
(aarch64_opcode_table): Add entry for sb.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
*** gas/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (aarch64_features): Add new "sb" option
for older architectures.
* doc/c-aarch64.texi: Document the same.
* testsuite/gas/aarch64/sb.s: New.
* testsuite/gas/aarch64/sb.d: New.
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order)
This patch adds the data processing instructions that are new to
ARMv8.5-A.
1) There are 2 instructions: xaflag, axflag, that are added to
manipulate the states of the flag and are used to convert between the
Arm representation and the fcmp representation.
2) The other instructions are rounding instructions which have 8
versions based on whether the floating-point number is a
Single-Precision or Double-Precision number, whether the target
integer is a 32-bit or 64-bit integer and whether the rounding mode is
the ambient rounding mode or to zero. Each of these instruction is
available in both Scalar and Vector forms.
Since both 1) and 2) have separate identification mechanism and it is
permissible that a ARMv8.4 compliant implementation may include any
arbitrary subset of the ARMv8.5 features unless otherwise specified,
new feature bits are added.
*** include/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_FLAGMANIP): New.
(AARCH64_FEATURE_FRINTTS): New.
(AARCH64_ARCH_V8_5): Add both by default.
*** opcodes/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-tbl.h (aarch64_feature_flagmanip): New.
(aarch64_feature_frintts): New.
(FLAGMANIP, FRINTTS): New.
(aarch64_opcode_table): Add entries for xaflag, axflag
and frint[32,64][x,z] instructions.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
*** gas/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* testsuite/gas/aarch64/armv8_5-a-dp.s: New.
* testsuite/gas/aarch64/armv8_5-a-dp.d: New.
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)
This is the first of the patch series and adds -march=armv8.5-a and
other internal feature marcos needed for it.
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (aarch64_archs): New entry for armv8.5-a.
* doc/c-aarch64.texi: Add documentation for the same.
*** include/ChnageLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_V8_5): New.
(AARCH64_ARCH_V8_5): New.
*** opcodes/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-tbl.h (aarch64_feature_set aarch64_feature_v8_5): New.
(ARMV8_5, V8_5_INSN): New.
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)
This patch adds the Execution and Data Prediction Restriction
instructions (that is, cfprctx, dvprxtc, cpprctx). These are all
aliases to MCR and are disassembled as such.
This instruction is retrospectively made optional for all versions of
the architecture from ARMv8.0 to ARMv8.4 and is mandatory from
ARMv8.5. Hence adding a new +predres for older versions of the
architecture.
*** include/ChangeLog ***
2018-10-05 Sudakshina Das <sudi.das@arm.com>
* opcode/arm.h (ARM_EXT2_PREDRES): New.
(ARM_ARCH_V8_5A): Add ARM_EXT2_PREDRES by default.
*** gas/ChangeLog ***
2018-10-05 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (arm_ext_predres): New.
(insns): Add new cfprctx, dvprctx and cpprctx instructions.
(arm_extensions): Add "predres".
* doc/c-arm.texi: Document the above.
* testsuite/gas/arm/predres-bad.d: New test.
* testsuite/gas/arm/predres-bad.l: New test.
* testsuite/gas/arm/predres.s: New test.
* testsuite/gas/arm/predres1.d: New test.
* testsuite/gas/arm/predres2.d: New test.
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)
This patch adds the instruction SB. This instruction is
retrospectively made optional for all versions of the architecture
from ARMv8.0 to ARMv8.4 and is mandatory from ARMv8.5. Hence adding a
new "+sb" for older archtectures.
*** include/ChangeLog ***
2018-10-05 Sudakshina Das <sudi.das@arm.com>
* opcode/arm.h (ARM_EXT2_SB): New.
(ARM_ARCH_V8_5A): Add ARM_EXT2_SB by default.
*** opcodes/ChangeLog ***
2018-10-05 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (arm_opcodes): Add sb.
(thumb32_opcodes): Likewise.
*** gas/ChangeLog ***
2018-10-05 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (arm_ext_sb): New.
(insns): Add new sb instruction.
(arm_extensions): Add "sb".
* doc/c-arm.texi: Document the above.
* testsuite/gas/arm/sb-bad.d: New test.
* testsuite/gas/arm/sb-bad.l: New test.
* testsuite/gas/arm/sb-thumb1.d: New test.
* testsuite/gas/arm/sb-thumb2.d: New test.
* testsuite/gas/arm/sb.s: New test.
* testsuite/gas/arm/sb1.d: New test.
* testsuite/gas/arm/sb2.d: New test.
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)
This is the first of the patch series and adds -march=armv8.5-a and
other internal feature marcos needed for it.
*** gas/ChangeLog ***
2018-10-05 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (arm_archs): New entry for armv8.5-a.
(cpu_arch_ver): Likewise.
* doc/c-arm.texi: Add documentation for the same.
* testsuite/gas/arm/attr-march-armv8_5-a.d: New.
*** include/ChnageLog ***
2018-10-05 Sudakshina Das <sudi.das@arm.com>
* opcode/arm.h (ARM_EXT2_V8_5A): New.
(ARM_AEXT2_V8_5A, ARM_ARCH_V8_5A): New.
Also fix the incorrect definitions of multiply and divide carry and
overflow float.
Changes to the instructions are made in the .cpu file, then we
regenerate the binutils and sim files.
The changes also required a few fixups for tests and additional sim helpers.
cpu/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
Stafford Horne <shorne@gmail.com>
* or1korbis.cpu (insn-opcode-mac): Add opcodes for MACU and MSBU.
(insn-opcode-alu-regreg): Add opcodes for MULD and MULDU.
(l-mul): Fix overflow support and indentation.
(l-mulu): Fix overflow support and indentation.
(l-muld, l-muldu, l-msbu, l-macu): New instructions.
(l-div); Remove incorrect carry behavior.
(l-divu): Fix carry and overflow behavior.
(l-mac): Add overflow support.
(l-msb, l-msbu): Add carry and overflow support.
opcodes/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
Stafford Horne <shorne@gmail.com>
* or1k-desc.c: Regenerate.
* or1k-desc.h: Regenerate.
* or1k-opc.c: Regenerate.
* or1k-opc.h: Regenerate.
* or1k-opinst.c: Regenerate.
sim/common/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* cgen-ops.h (ADDCFDI): New function, add carry flag DI variant.
(ADDOFDI): New function, add overflow flag DI variant.
(SUBCFDI): New function, subtract carry flag DI variant.
(SUBOFDI): New function, subtract overflow flag DI variant.
sim/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* or1k/cpu.h: Regenerate.
* or1k/decode.c: Regenerate.
* or1k/decode.h: Regenerate.
* or1k/model.c: Regenerate.
* or1k/sem-switch.c: Regenerate.
* or1k/sem.c: Regenerate:
sim/testsuite/sim/or1k/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* div.S: Fix tests to match correct overflow/carry semantics.
* mul.S: Likewise.
gas/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* testsuite/gas/or1k/allinsn.s: Add instruction tests for
l.muld, l.muldu, l.macu, l.msb, l.msbu.
* testsuite/gas/or1k/allinsn.d: Add test results for new
instructions.
This patch adds the new instruction and relocation as per proposal:
https://openrisc.io/proposals/ladrp
This is to be added to the spec in an upcoming revision. The new instruction
l.adrp loads the page offset of the current instruction offset by
a 21-bit immediate shifted left 13-bits. This is meant to be used with
a 13-bit lower bit page offset. This allows us to free up the got
register r16.
l.adrp r3, foo
l.ori r4, r3, po(foo)
l.lbz r5, po(foo)(r3)
l.sb po(foo)(r3), r6
The relocations we add are:
- BFD_RELOC_OR1K_PLTA26 For PLT jump relocation with PLT entry
asm: plta() implemented using l.ardp, meaning
no need for r16 (the GOT reg)
- BFD_RELOC_OR1K_GOT_PG21 Upper 21-bit Page offset got address
asm: got()
- BFD_RELOC_OR1K_TLS_GD_PG21 Upper 21-bit Page offset with TLS General
asm: tlsgd() Dynamic calculation
- BFD_RELOC_OR1K_TLS_LDM_PG21 Upper 21-bit Page offset with TLS local
asm: tlsldm() dynamic calculation
- BFD_RELOC_OR1K_TLS_IE_PG21 Upper 21-bit Page offset with TLS Initial
asm: gottp() Executable calculation
- BFD_RELOC_OR1K_PCREL_PG21 Default relocation for disp21 (l.adrp
instructions)
- BFD_RELOC_OR1K_LO13 low 13-bit page offset relocation
asm: po() i.e. mem loads, addi etc
- BFD_RELOC_OR1K_SLO13 low 13-bit page offset relocation
asm: po() i.e. mem stores, with split immediate
- BFD_RELOC_OR1K_GOT_LO13, low 13-bit page offset with GOT calcs
asm: gotpo()
- BFD_RELOC_OR1K_TLS_GD_LO13 Lower 13-bit offset with TLS GD calcs
asm: tlsgdpo()
- BFD_RELOC_OR1K_TLS_LDM_LO13 Lower 13-bit offset with TLS LD calcs
asm: tlsldmpo()
- BFD_RELOC_OR1K_TLS_IE_LO13 Lower 13-bit offset with TLS IE calcs
asm: gottppo()
bfd/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* bfd-in2.h: Regenerated.
* elf32-or1k.c: (or1k_elf_howto_table): Fix formatting for
R_OR1K_PLT26, Add R_OR1K_PCREL_PG21, R_OR1K_GOT_PG21,
R_OR1K_TLS_GD_PG21, R_OR1K_TLS_LDM_PG21, R_OR1K_TLS_IE_PG21,
R_OR1K_LO13, R_OR1K_GOT_LO13, R_OR1K_TLS_GD_LO13, R_OR1K_TLS_LDM_LO13,
R_OR1K_TLS_IE_LO13, R_OR1K_SLO13, R_OR1K_PLTA26.
(or1k_reloc_map): Add BFD_RELOC_OR1K_PCREL_PG21,
BFD_RELOC_OR1K_GOT_PG21, BFD_RELOC_OR1K_TLS_GD_PG21,
BFD_RELOC_OR1K_TLS_LDM_PG21, BFD_RELOC_OR1K_TLS_IE_PG21,
BFD_RELOC_OR1K_LO13, BFD_RELOC_OR1K_GOT_LO13,
BFD_RELOC_OR1K_TLS_GD_LO13, BFD_RELOC_OR1K_TLS_GD_LO13,
BFD_RELOC_OR1K_TLS_LDM_LO13, BFD_RELOC_OR1K_TLS_IE_LO13,
BFD_RELOC_OR1K_SLO13, BFD_RELOC_OR1K_PLTA26.
(elf_or1k_link_hash_table): Add field saw_plta.
(or1k_final_link_relocate): Add value calculations for new relocations.
(or1k_elf_relocate_section): Add section relocations for new
relocations.
(or1k_write_plt_entry): New function.
(or1k_elf_finish_dynamic_sections): Add support for PLTA relocations
using new l.adrp instruction. Cleanup PLT relocation code generation.
* libbfd.h: Regenerated.
* reloc.c: Add BFD_RELOC_OR1K_PCREL_PG21, BFD_RELOC_OR1K_LO13,
BFD_RELOC_OR1K_SLO13, BFD_RELOC_OR1K_GOT_PG21, BFD_RELOC_OR1K_GOT_LO13,
BFD_RELOC_OR1K_PLTA26, BFD_RELOC_OR1K_TLS_GD_PG21,
BFD_RELOC_OR1K_TLS_GD_LO13, BFD_RELOC_OR1K_TLS_LDM_PG21,
BFD_RELOC_OR1K_TLS_LDM_LO13, BFD_RELOC_OR1K_TLS_IE_PG21,
BFD_RELOC_OR1K_TLS_IE_LO13.
cpu/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* or1k.opc (parse_disp26): Add support for plta() relocations.
(parse_disp21): New function.
(or1k_rclass): New enum.
(or1k_rtype): New enum.
(or1k_imm16_relocs): Define new PO and SPO relocation mappings.
(parse_reloc): Add new po(), gotpo() and gottppo() for LO13 relocations.
(parse_imm16): Add support for the new 21bit and 13bit relocations.
* or1korbis.cpu (f-disp26): Don't assume SI.
(f-disp21): New pc-relative 21-bit 13 shifted to right.
(insn-opcode): Add ADRP.
(l-adrp): New instruction.
gas/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* config/tc-or1k.c (or1k_apply_fix): Add BFD_RELOC_OR1K_TLS_GD_PG21,
BFD_RELOC_OR1K_TLS_GD_LO13, BFD_RELOC_OR1K_TLS_LDM_PG21,
BFD_RELOC_OR1K_TLS_LDM_LO13, BFD_RELOC_OR1K_TLS_IE_PG21,
BFD_RELOC_OR1K_TLS_IE_LO13.
* testsuite/gas/or1k/allinsn.s: Add test for l.adrp.
* testsuite/gas/or1k/allinsn.d: Add test results for new
instructions.
* testsuite/gas/or1k/reloc-1.s: Add tests to generate
R_OR1K_PLTA26, R_OR1K_GOT_PG21, R_OR1K_TLS_GD_PG21, R_OR1K_TLS_LDM_PG21,
R_OR1K_TLS_IE_PG21, R_OR1K_LO13, R_OR1K_GOT_LO13, R_OR1K_TLS_GD_LO13,
R_OR1K_TLD_LDM_LO13, R_OR1K_TLS_IE_LO13, R_OR1K_LO13, R_OR1K_SLO13
relocations.
* testsuite/gas/or1k/reloc-1.d: Add relocation results for
tests.
* testsuite/gas/or1k/reloc-2.s: Add negative tests for store to
gotpo().
* testsuite/gas/or1k/reloc-2.l: Add expected error test results.
ld/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* testsuite/ld-or1k/or1k.exp: Add test cases for plt generation.
* testsuite/ld-or1k/plt1.dd: New file.
* testsuite/ld-or1k/plt1.s: New file.
* testsuite/ld-or1k/plt1.x.dd: New file.
* testsuite/ld-or1k/plta1.dd: New file.
* testsuite/ld-or1k/plta1.s: New file.
* testsuite/ld-or1k/pltlib.s: New file.
include/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* elf/or1k.h (elf_or1k_reloc_type): Add R_OR1K_PCREL_PG21,
R_OR1K_GOT_PG21, R_OR1K_TLS_GD_PG21, R_OR1K_TLS_LDM_PG21,
R_OR1K_TLS_IE_PG21, R_OR1K_LO13, R_OR1K_GOT_LO13,
R_OR1K_TLS_GD_LO13, R_OR1K_TLS_LDM_LO13, R_OR1K_TLS_IE_LO13,
R_OR1K_SLO13, R_OR1K_PLTA26.
opcodes/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* or1k-asm.c: Regenerated.
* or1k-desc.c: Regenerated.
* or1k-desc.h: Regenerated.
* or1k-dis.c: Regenerated.
* or1k-ibld.c: Regenerated.
* or1k-opc.c: Regenerated.
* or1k-opc.h: Regenerated.
* or1k-opinst.c: Regenerated.
This patch adds the following target relocations:
- BFD_RELOC_HI16_S High 16-bit relocation, for used with signed
asm: ha() lower.
- BFD_RELOC_HI16_S_GOTOFF High 16-bit GOT offset relocation for local
asm: gotoffha() symbols, for use with signed lower.
- BFD_RELOC_OR1K_TLS_IE_AHI16 High 16-bit TLS relocation with initial
asm: gottpoffha() executable calculation, for use with signed
lower.
- BFD_RELOC_OR1K_TLS_LE_AHI16 High 16-bit TLS relocation for local executable
asm: tpoffha() variables, for use with signed lower.
- BFD_RELOC_OR1K_SLO16 Split lower 16-bit relocation, used with
asm: lo() OpenRISC store instructions.
- BFD_RELOC_OR1K_GOTOFF_SLO16 Split lower 16-bit GOT offset relocation for
asm: gotofflo() local symbols, used with OpenRISC store
instructions.
- BFD_RELOC_OR1K_TLS_LE_SLO16 Split lower 16-bit relocation for TLS local
asm: tpofflo() executable variables, used with OpenRISC store
instructions.
bfd/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
Stafford Horne <shorne@gmail.com>
* bfd-in2.h: Regenerated.
* elf32-or1k.c (N_ONES): New macro.
(or1k_elf_howto_table): Fix R_OR1K_PLT26 to complain on overflow.
Add definitions for R_OR1K_TLS_TPOFF, R_OR1K_TLS_DTPOFF,
R_OR1K_TLS_DTPMOD, R_OR1K_AHI16, R_OR1K_GOTOFF_AHI16,
R_OR1K_TLS_IE_AHI16, R_OR1K_TLS_LE_AHI16, R_OR1K_SLO16,
R_OR1K_GOTOFF_SLO16, R_OR1K_TLS_LE_SLO16.
(or1k_reloc_map): Add entries for BFD_RELOC_HI16_S,
BFD_RELOC_LO16_GOTOFF, BFD_RELOC_HI16_GOTOFF, BFD_RELOC_HI16_S_GOTOFF,
BFD_RELOC_OR1K_TLS_IE_AHI16, BFD_RELOC_OR1K_TLS_LE_AHI16,
BFD_RELOC_OR1K_SLO16, BFD_RELOC_OR1K_GOTOFF_SLO16,
BFD_RELOC_OR1K_TLS_LE_SLO16.
(or1k_reloc_type_lookup): Change search loop to start ad index 0 and
also check results before returning.
(or1k_reloc_name_lookup): Simplify loop to use R_OR1K_max as index
limit.
(or1k_final_link_relocate): New function.
(or1k_elf_relocate_section): Add support for new AHI and SLO
relocations. Use or1k_final_link_relocate instead of generic
_bfd_final_link_relocate.
(or1k_elf_check_relocs): Add support for new AHI and SLO relocations.
* reloc.c: Add new enums for BFD_RELOC_OR1K_SLO16,
BFD_RELOC_OR1K_GOTOFF_SLO16, BFD_RELOC_OR1K_TLS_IE_AHI16,
BFD_RELOC_OR1K_TLS_IE_AHI16, BFD_RELOC_OR1K_TLS_LE_AHI16,
BFD_RELOC_OR1K_TLS_LE_SLO16. Remove unused BFD_RELOC_OR1K_GOTOFF_HI16
and BFD_RELOC_OR1K_GOTOFF_LO16.
* libbfd.h: Regenerated.
cpu/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* or1k.opc: Add RTYPE_ enum.
(INVALID_STORE_RELOC): New string.
(or1k_imm16_relocs): New array array.
(parse_reloc): New static function that just does the parsing.
(parse_imm16): New static function for generic parsing.
(parse_simm16): Change to just call parse_imm16.
(parse_simm16_split): New function.
(parse_uimm16): Change to call parse_imm16.
(parse_uimm16_split): New function.
* or1korbis.cpu (simm16-split): Change to use new simm16_split.
(uimm16-split): Change to use new uimm16_split.
gas/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* testsuite/gas/or1k/allinsn.d (l_ha): Add result for ha() relocation.
* testsuite/gas/or1k/allinsn.s (l_ha): Add test for ha() relocations.
* testsuite/gas/or1k/allinsn.exp: Renamed to or1k.exp.
* testsuite/gas/or1k/or1k.exp: Add reloc-2 list test.
* testsuite/gas/or1k/reloc-1.d: New file.
* testsuite/gas/or1k/reloc-1.s: New file.
* testsuite/gas/or1k/reloc-2.l: New file.
* testsuite/gas/or1k/reloc-2.s: New file.
include/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* elf/or1k.h (elf_or1k_reloc_type): Add R_OR1K_AHI16,
R_OR1K_GOTOFF_AHI16, R_OR1K_TLS_IE_AHI16, R_OR1K_TLS_LE_AHI16,
R_OR1K_SLO16, R_OR1K_GOTOFF_SLO16, R_OR1K_TLS_LE_SLO16.
ld/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* testsuite/ld-or1k/offsets1.d: New file.
* testsuite/ld-or1k/offsets1.s: New file.
* testsuite/ld-or1k/or1k.exp: New file.
opcodes/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* or1k-asm.c: Regenerate.
This patch adds the tests and expected output for each of the conditions where
the MOVPRFX constraint should apply.
The specific test cases are all documented to indicate what the expected
behavior should be.
gas/
* testsuite/gas/aarch64/sve-movprfx_1.d: New test.
* testsuite/gas/aarch64/sve-movprfx_1.s: New test.
* testsuite/gas/aarch64/sve-movprfx_10.d: New test.
* testsuite/gas/aarch64/sve-movprfx_10.l: New test.
* testsuite/gas/aarch64/sve-movprfx_10.s: New test.
* testsuite/gas/aarch64/sve-movprfx_11.d: New test.
* testsuite/gas/aarch64/sve-movprfx_11.s: New test.
* testsuite/gas/aarch64/sve-movprfx_12.d: New test.
* testsuite/gas/aarch64/sve-movprfx_12.s: New test.
* testsuite/gas/aarch64/sve-movprfx_13.d: New test.
* testsuite/gas/aarch64/sve-movprfx_13.l: New test.
* testsuite/gas/aarch64/sve-movprfx_13.s: New test.
* testsuite/gas/aarch64/sve-movprfx_14.d: New test.
* testsuite/gas/aarch64/sve-movprfx_14.l: New test.
* testsuite/gas/aarch64/sve-movprfx_14.s: New test.
* testsuite/gas/aarch64/sve-movprfx_15.d: New test.
* testsuite/gas/aarch64/sve-movprfx_15.l: New test.
* testsuite/gas/aarch64/sve-movprfx_15.s: New test.
* testsuite/gas/aarch64/sve-movprfx_16.d: New test.
* testsuite/gas/aarch64/sve-movprfx_16.s: New test.
* testsuite/gas/aarch64/sve-movprfx_17.d: New test.
* testsuite/gas/aarch64/sve-movprfx_17.l: New test.
* testsuite/gas/aarch64/sve-movprfx_17.s: New test.
* testsuite/gas/aarch64/sve-movprfx_18.d: New test.
* testsuite/gas/aarch64/sve-movprfx_18.l: New test.
* testsuite/gas/aarch64/sve-movprfx_18.s: New test.
* testsuite/gas/aarch64/sve-movprfx_19.d: New test.
* testsuite/gas/aarch64/sve-movprfx_19.s: New test.
* testsuite/gas/aarch64/sve-movprfx_2.d: New test.
* testsuite/gas/aarch64/sve-movprfx_2.l: New test.
* testsuite/gas/aarch64/sve-movprfx_2.s: New test.
* testsuite/gas/aarch64/sve-movprfx_20.d: New test.
* testsuite/gas/aarch64/sve-movprfx_20.l: New test.
* testsuite/gas/aarch64/sve-movprfx_20.s: New test.
* testsuite/gas/aarch64/sve-movprfx_21.d: New test.
* testsuite/gas/aarch64/sve-movprfx_21.s: New test.
* testsuite/gas/aarch64/sve-movprfx_22.d: New test.
* testsuite/gas/aarch64/sve-movprfx_22.l: New test.
* testsuite/gas/aarch64/sve-movprfx_22.s: New test.
* testsuite/gas/aarch64/sve-movprfx_23.d: New test.
* testsuite/gas/aarch64/sve-movprfx_23.l: New test.
* testsuite/gas/aarch64/sve-movprfx_23.s: New test.
* testsuite/gas/aarch64/sve-movprfx_24.d: New test.
* testsuite/gas/aarch64/sve-movprfx_24.l: New test.
* testsuite/gas/aarch64/sve-movprfx_24.s: New test.
* testsuite/gas/aarch64/sve-movprfx_25.d: New test.
* testsuite/gas/aarch64/sve-movprfx_25.l: New test.
* testsuite/gas/aarch64/sve-movprfx_25.s: New test.
* testsuite/gas/aarch64/sve-movprfx_26.d: New test.
* testsuite/gas/aarch64/sve-movprfx_26.l: New test.
* testsuite/gas/aarch64/sve-movprfx_26.s: New test.
* testsuite/gas/aarch64/sve-movprfx_3.d: New test.
* testsuite/gas/aarch64/sve-movprfx_3.l: New test.
* testsuite/gas/aarch64/sve-movprfx_3.s: New test.
* testsuite/gas/aarch64/sve-movprfx_4.d: New test.
* testsuite/gas/aarch64/sve-movprfx_4.l: New test.
* testsuite/gas/aarch64/sve-movprfx_4.s: New test.
* testsuite/gas/aarch64/sve-movprfx_5.d: New test.
* testsuite/gas/aarch64/sve-movprfx_5.s: New test.
* testsuite/gas/aarch64/sve-movprfx_6.d: New test.
* testsuite/gas/aarch64/sve-movprfx_6.l: New test.
* testsuite/gas/aarch64/sve-movprfx_6.s: New test.
* testsuite/gas/aarch64/sve-movprfx_7.d: New test.
* testsuite/gas/aarch64/sve-movprfx_7.l: New test.
* testsuite/gas/aarch64/sve-movprfx_7.s: New test.
* testsuite/gas/aarch64/sve-movprfx_8.d: New test.
* testsuite/gas/aarch64/sve-movprfx_8.l: New test.
* testsuite/gas/aarch64/sve-movprfx_8.s: New test.
* testsuite/gas/aarch64/sve-movprfx_9.d: New test.
* testsuite/gas/aarch64/sve-movprfx_9.l: New test.
* testsuite/gas/aarch64/sve-movprfx_9.s: New test.
This patch wires in the new constraint verifiers into the assembler and
disassembler. Because of this the MOVPRFX tests have to be split out from the
generic SVE tests into their own tests so warnings can be ignored.
These tests are only intended to test the encoding correctness and not the
constraints.
gas/
* testsuite/gas/aarch64/sve-movprfx.d: New test.
* testsuite/gas/aarch64/sve-movprfx.s: New test.
* testsuite/gas/aarch64/sve.d: Refactor.
* testsuite/gas/aarch64/sve.s: Refactor.
* testsuite/gas/aarch64/sysreg-diagnostic.d: Update.
opcodes/
* aarch64-asm.c (aarch64_opcode_encode): Apply constraint verifier.
* aarch64-dis.c (print_operands): Refactor to take notes.
(print_verifier_notes): New.
(print_aarch64_insn): Apply constraint verifier.
(print_insn_aarch64_word): Update call to print_aarch64_insn.
* aarch64-opc.c (aarch64_print_operand): Remove attribute, update notes format.
Any open sequence at the end of a section or assembly is considered an error.
This patch adds a check at the end to ensure that all sequences have been closed
and if not reports a warning.
During disassembly it's not possible to detect this condition in the back-end so
the warning is only emitted from the assembler for now.
gas/
* config/tc-aarch64.c (force_automatic_sequence_close,
aarch64_frob_section): New.
* config/tc-aarch64.h (tc_frob_section, aarch64_frob_section): New.
This patch adds the verification rules for move prefix constraints.
The Arm SVE instruction MOVPRFX introduces[1] constraints on the instruction at
PC+4. Particularly the following constraints are handled by this patch
* MOVPRFX must be followed by an instruction.
* MOVPRFX can only be followed by non-layout altering directives.
* MOVPRFX destination register MUST be used as the destination register in the
instruction at PC+4, and is not allowed to be used in any other position other than
destructive input. This includes registers that architecturally overlap. e.g. x1
should be treated as z1.
* MOVPRFX must be followed by a restricted set of SVE instructions.
* The size of the destination register of MOVPRFX must be equal to that of
the operation at PC+4.
* The predicate register and operation of MOVPRFX must match that of the instruction
at PC+4
* The predicated instruction at PC+4 must use the merging predicate.
* Architectural aliases and pseudo-instructions need to be supported as well.
* MOVPRFX cannot be the last instruction in a sequence
Any failure to adhere to any of these constrains will emit an assembly warning
and a disassembly note.
[1] https://developer.arm.com/docs/ddi0584/latest/arm-architecture-reference-manual-supplement-the-scalable-vector-extension-sve-for-armv8-a
include/
* opcode/aarch64.h (aarch64_inst): Remove.
(enum err_type): Add ERR_VFI.
(aarch64_is_destructive_by_operands): New.
(init_insn_sequence): New.
(aarch64_decode_insn): Remove param name.
opcodes/
* aarch64-opc.c (init_insn_block): New.
(verify_constraints, aarch64_is_destructive_by_operands): New.
* aarch64-opc.h (verify_constraints): New.
gas/
* config/tc-aarch64.c (output_operand_error_report): Order warnings.
This patch introduces aarch64_instr_sequence which is a structure similar to IT
blocks on Arm in order to track instructions that introduce a constraint or
dependency on instruction 1..N positions away from the instruction that opened
the block.
The struct is also wired through to the locations that require it.
gas/
* config/tc-aarch64.c (now_instr_sequence):
(*insn_sequence, now_instr_sequence): New.
(output_operand_error_record, do_encode): Add insn_sequence.
(md_assemble): Update insn_sequence.
(try_to_encode_as_unscaled_ldst, fix_mov_imm_insn, fix_insn):
Pass insn_sequence.
* config/tc-aarch64.h (struct aarch64_segment_info_type):
Add insn_sequence.
include/
* opcode/aarch64.h (struct aarch64_instr_sequence): New.
(aarch64_opcode_encode): Use it.
opcodes/
* aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
* aarch64-dis.c (insn_sequence): New.
The RISC-V memory model has been ratified, and it includes an additional
fence: "fence.tso". This pseudo instruction extends one of the
previously reserved full fence patterns to be less restrictive, and
therefor will execute correctly on all existing microarchitectures.
Thus there is no reason to allow this instruction to be disabled (or
unconverted to a full fence), so it's just unconditionally allowed.
I've added a test case for GAS to check that "fence.tso" correctly
assembles on rv32i-based targets. I checked to see that "fence.tso"
appears in "gas.log", but that's the only testing I've done.
gas/ChangeLog
2018-10-02 Palmer Dabbelt <palmer@sifive.com>
* testsuite/gas/riscv/fence-tso.d: New file.
* testsuite/gas/riscv/fence-tso.s: Likewise.
include/ChangeLog
2018-10-02 Palmer Dabbelt <palmer@sifive.com>
* opcode/riscv-opc.h (MATCH_FENCE_TSO): New define.
(MASK_FENCE_TSO): Likewise.
opcodes/ChangeLog
2018-10-02 Palmer Dabbelt <palmer@sifive.com>
* riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
2018-09-26 Sandra Loosemore <sandra@codesourcery.com>
gas/
* testsuite/gas/all/gas.exp: Skip "Output file must be distinct
from input" test on Windows host.
Increase the fixup length to 4 for the 20 bit displacement.
gas/ChangeLog:
2018-09-25 Andreas Krebbel <krebbel@linux.ibm.com>
* config/tc-s390.c (md_apply_fix): Set fx_size to 4 for 20 bit
displacements.
* testsuite/gas/s390/s390.exp: Run new test.
* testsuite/gas/s390/zarch-z990-symbol-lay.s: New test.
commit b8426d169d3f8ab820f3bdaf45fbc64f8bb827ed
Author: H.J. Lu <hjl.tools@gmail.com>
Date: Fri Sep 21 04:24:40 2018 -0700
gas: Make bfin-parse.c/rl78-parse.c/rx-parse.c depend on bfd/reloc.c
It is for PR gas/23691, not PR gas/23692.
Since bfin-parse.c, rl78-parse.c and rx-parse.c use BFD_RELOC_XXX, we
need to regenerate them when bfd/reloc.c changhes.
PR gas/23692
* Makefile.am (bfin-parse.c): Depend on $(srcdir)/../bfd/reloc.c.
(rl78-parse.c): Likewise.
(rx-parse.c): Likewise.
* Makefile.in: Regenerated.
