As I noted a long time ago in the comment on fixed_reg_p, the real
problem with saving fixed/global regs is that exception frame
unwinding might restore them. So don't emit eh_frame info for any
such reg, and the unwinder won't restore them.
Also, tidy rs6000_savres_strategy. Delaying some checks means we
won't iterate over regs quite so often.
* config/rs6000/rs6000.c (rs6000_savres_strategy): Force inline
restoring when fixed_reg_p, but allow out-of-line or stmw save.
Check for user regs later to avoid unnecessary looping over regs.
Merge user reg check with non-saved reg check. Don't force
inline VR restore when static chain used.
(rs6000_frame_related): Omit eh_frame info for user regs when
saving.
(fixed_regs_p): Delete.
From-SVN: r235672
No functional change here. A single bit becomes two bits, which
always have the same value at the moment.
* config/rs6000/rs6000.c (SAVRES_MULTIPLE): Replace with..
(SAVE_STRATEGY, REST_STRATEGY): ..this. Renumber and sort enum.
Update all uses.
From-SVN: r235671
Treat -ffixed-reg as we do for global asm regs.
PR target/69645
* config/rs6000/rs6000.c (fixed_reg_p): New function.
(fixed_regs_p): Rename from global_regs_p. Call fixed_reg_p.
Update all uses.
From-SVN: r235670
This makes the conditions look the same as other places that deal with
RS6000_PIC_OFFSET_TABLE_REGNUM, eg. first_reg_to_save. No functional
changes.
* config/rs6000/rs6000.c (rs6000_conditional_register_usage):
Remove redundant PIC_OFFSET_TABLE_REGNUM test. Replace with
flag_pic test for Darwin.
From-SVN: r235669
* regs.h (struct reg_info_t): Delete live_length.
(REG_LIVE_LENGTH): Delete macro.
* regstat.c (regstat_bb_compute_ri): Delete artificial_uses,
local_live, local_processed and local_live_last_luid params.
Replace bb_index param with bb. Don't set REG_LIVE_LENGTH.
Formatting fixes.
(regstat_compute_ri): Adjust for above. Don't set
REG_LIVE_LENGTH.
(dump_reg_info): Don't print live length.
* ira.c (update_equiv_regs): Replace test of REG_LIVE_LENGTH
with test of setjmp_crosses. Don't set REG_LIVE_LENGTH.
Localize loop_depth var.
From-SVN: r235663
/cp
2016-04-29 Paolo Carlini <paolo.carlini@oracle.com>
PR c++/66644
* class.c (check_field_decl): Remove final int* parameter, change
the return type to bool; fix logic in order not to reject multiple
initialized fields in anonymous struct.
(check_field_decls): Adjust call.
/testsuite
2016-04-29 Paolo Carlini <paolo.carlini@oracle.com>
PR c++/66644
* g++.dg/cpp0x/nsdmi-anon-struct1.C: New.
From-SVN: r235662
This function is used to validate REG_EQUIV notes generated by ira,
and to validate potential insn combines performed by ira. The two
conditions are not exactly the same, with reload being more
restrictive. Separate them so more combines/moves can occur.
For example, this sequence from cfgexpand.c:expand_gimple_cond
callq _Z18update_bb_for_insnP15basic_block_def
mov 0x10(%rbx),%rdi
mov 0x0(%rip),%rbp # x_rtl+0x34
callq _Z9safe_as_aIP8rtx_insn7rtx_defET_PT0_
mov %r13,%rdx
mov %rbp,%rsi
mov %rax,%rdi
callq _Z18create_basic_blockP7rtx_defS0_P15basic_block_def
becomes
callq _Z18update_bb_for_insnP15basic_block_def
mov 0x10(%rbx),%rdi
callq _Z9safe_as_aIP8rtx_insn7rtx_defET_PT0_
mov 0x0(%rip),%rsi # x_rtl+0x34
mov %r13,%rdx
mov %rax,%rdi
callq _Z18create_basic_blockP7rtx_defS0_P15basic_block_def
* ira.c (enum valid_equiv): New.
(validate_equiv_mem): Return enum.
(update_equiv_mem): Create replacement in more cases.
(add_store_equivs): Update validate_equiv_mem call.
From-SVN: r235661
This patch actually improves generated code, because REG_DEAD notes
used by the old insn scan are not always present. On x86_64, see
gcc/wide-int-print.o:print_hex for an example of a function that is
smaller and uses one less callee saved reg.
* ira.c (combine_and_move_insns): Rather than scanning insns,
use DF infrastucture to find use and def insns.
From-SVN: r235660
Notes added by add_store_equivs are not used directly or indirectly by
combine_and_move_insns. add_store_equivs can therefore run later
without affecting the output of combine_and_move_insns, and thus
add_store_equivs need not take into account potentially moved insns.
Since not all potentially combined/moved insns are in fact combined or
moved, this may allow add_store_equivs to add more REG_EQUIV notes.
grow_reg_equivs isn't needed until the reload reg_equivs array is
changed.
ira.c (combine_and_move_insns): Move invariant conditions..
(ira.c): ..to here. Call combine_and_move_insns before
add_store_equivs. Call grow_reg_equivs later. Allocate
req_equiv later using max_reg_num() rather than global max_regno.
(contains_replace_regs): Delete.
(add_store_equivs): Remove contains_replace_regs test.
From-SVN: r235659
* ira.c (add_store_equivs, combine_and_move_insns): New functions,
split out from..
(update_reg_equivs): ..here. Move allocation and freeing of
reg_equiv, and calls to grow_reg_equivs, init_alias_analysis,
end_alias_analysis to..
(ira): ..here.
From-SVN: r235657
2016-04-29 Patrick Palka <ppalka@gcc.gnu.org>
* tree-ssa-threadedge.c (simplify_control_stmt_condition): Split
out into ...
(simplify_control_stmt_condition_1): ... here. Recurse into
BIT_AND_EXPRs and BIT_IOR_EXPRs.
* gcc.dg/tree-ssa/ssa-thread-14.c: New test.
* gcc.dg/tree-ssa/ssa-thread-11.c: Update expected output.
From-SVN: r235653
Since PIC leads to the *movdi_internal pattern, check for nonexistence
of the *movdi_internal pattern in PR target/70155 tests only if PIC is
off.
* gcc.target/i386/pr70155-1.c: Check for nonexistence of the
*movdi_internal pattern only if PIC off.
* gcc.target/i386/pr70155-2.c: Likewise.
* gcc.target/i386/pr70155-3.c: Likewise.
* gcc.target/i386/pr70155-4.c: Likewise.
* gcc.target/i386/pr70155-5.c: Likewise.
* gcc.target/i386/pr70155-6.c: Likewise.
* gcc.target/i386/pr70155-7.c: Likewise.
* gcc.target/i386/pr70155-8.c: Likewise.
* gcc.target/i386/pr70155-15.c: Likewise.
* gcc.target/i386/pr70155-17.c: Likewise.
* gcc.target/i386/pr70155-22.c: Likewise.
From-SVN: r235647
PR sanitizer/70342
* fold-const.c (tree_single_nonzero_warnv_p): For TARGET_EXPR, use
TARGET_EXPR_SLOT as a base.
* g++.dg/ubsan/null-7.C: New test.
Co-Authored-By: Jakub Jelinek <jakub@redhat.com>
From-SVN: r235637
For performance reasons it is important to write the full 64 bits of
an FPR target reg even when dealing with 32 bit values. So we chose
lder over ler for 32 bit float register moves. lder zero-extends the
32 bit value from the source reg to 64 bit in the target. However,
since it actually doesn't matter whether we write the upper 32 bits
with zeros or with any other garbage we can also use ldr instead. It
is bit shorter and therefore will do good for I-Cache usage.
gcc/ChangeLog:
2016-04-29 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/s390/2964.md ("z13_unit_fxu", "z13_0"): Remove lder.
* config/s390/s390.md ("movsi_larl", "*movsi_esa", "mov<mode>"):
Change lder to ldr.
* config/s390/vector.md ("mov<mode>"): Likewise.
From-SVN: r235627
This fixes an issue with the long displacement memory address
constraints S and T. These were defined to only accept long
displacement addresses. This is wrong since a memory constraint must
not reject an address with a 0 displacement. Reload relies on being
able to turn an invalid memory address into a valid one by reloading
the address into a base register. The S and T constraints would
reject such an address.
This isn't really a problem for the backend since we used the
constraints with that knowledge there but it is a problem for people
writing inline assemblies.
gcc/ChangeLog:
2016-04-29 Ulrich Weigand <uweigand@de.ibm.com>
* config/s390/constraints.md ("U", "W"): Invoke
s390_mem_constraint with "ZR" and "ZT".
* config/s390/s390.c (s390_check_qrst_address): Reject invalid
addresses when using LRA. Accept also short displacements for S
and T constraints. Do not check for long displacement target for
S and T constraints.
(s390_mem_constraint): Remove handling of U and W constraints.
* config/s390/s390.md (various patterns): Remove the short
displacement constraints (Q and R) if a long displacement
constraint is present. Add longdisp as required CPU capability.
* config/s390/vector.md: Likewise.
* config/s390/vx-builtins.md: Likewise.
From-SVN: r235626
The combine pass may conclude umulhisi3_imm pattern can accept also sign
extended 16-bit constants. This patch prohibits the combine in considering
this pattern as suitable.
gcc/
2016-04-29 Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/arc.h (UNSIGNED_INT12, UNSIGNED_INT16): Define.
* config/arc/arc.md (umulhisi3): Use arc_short_operand predicate.
(umulhisi3_imm): Update predicates and constraint letters.
(umulhisi3_reg): Declare instruction as commutative.
* config/arc/constraints.md (J12, J16): New constraints.
* config/arc/predicates.md (short_unsigned_const_operand): New
predicate.
(arc_short_operand): Likewise.
* testsuite/gcc.target/arc/umulsihi3_z.c: New file.
From-SVN: r235623
2016-04-29 Richard Biener <rguenther@suse.de>
PR tree-optimization/13962
PR tree-optimization/65686
* tree-ssa-alias.h (ptrs_compare_unequal): Declare.
* tree-ssa-alias.c (ptrs_compare_unequal): New function
using PTA to compare pointers.
* match.pd: Add pattern for pointer equality compare simplification
using ptrs_compare_unequal.
* gcc.dg/uninit-pr65686.c: New testcase.
From-SVN: r235622
* config/i386/i386.md (Load+RegOp to Mov+MemOp peephole2):
Use SWI mode iterator. Use general_reg_operand predicate.
(Load+RegOp to Mov+MemOp peephole2 with vector regs): Split
peephole to MMX and SSE part. Use mmx_reg_operand and sse_reg_operand
predicates.
From-SVN: r235620
Oleg Endo
Rainer Orth
Alan Modra
GCC Administrator
Paolo Carlini
Bill Schmidt
Patrick Palka
Cesar Philippidis
Chris Manghane
H.J. Lu
David Edelsohn
Chris Gregory
Bin Cheng
Tom Tromey
Uros Bizjak
Uros Bizjak
Ilya Enkovich
Marek Polacek
Andrew Burgess
Claudiu Zissulescu
Dominik Vogt
Andreas Krebbel
Ulrich Weigand
Bernd Schmidt
Richard Biener