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Uros Bizjak 38c84ba5d6 backport: re PR rtl-optimization/83628 (performance regression when accessing arrays on alpha) 
Backport from mainline
	2018-01-12  Uros Bizjak  <ubizjak@gmail.com>

	PR target/83628
	* config/alpha/alpha.md (*saddsi_1): New insn_ans_split pattern.
	(*saddl_se_1): Ditto.
	(*ssubsi_1): Ditto.
	(*ssubl_se_1): Ditto.

	Backport from mainline
	2018-01-09  Uros Bizjak  <ubizjak@gmail.com>

	PR target/83628
	* combine.c (force_int_to_mode) <case ASHIFT>: Use mode instead of
	op_mode in the force_to_mode call.

testsuite/ChangeLog:

	Backport from mainline
	2018-01-12  Uros Bizjak  <ubizjak@gmail.com>

	PR target/83628
	* gcc.target/alpha/pr83628-3.c: New test.

From-SVN: r256665
 		2018-01-14 16:45:38 +01:00
..
aarch64 re PR middle-end/80295 (ICE in __builtin_update_setjmp_buf expander) 2017-10-24 22:46:19 +00:00
alpha backport: re PR rtl-optimization/83628 (performance regression when accessing arrays on alpha) 2018-01-14 16:45:38 +01:00
arc arc: Fix for loop end detection 2017-04-14 22:14:34 +01:00
arm Fix regression on soft float targets for armv8_2-fp16-move-2.c 2017-12-15 09:59:24 +00:00
avr backport: re PR target/81305 ([avr] avrtiny uses LDS for SREG in ISR routines which is out of range of LDS.) 2017-07-05 12:49:08 +00:00
bfin
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cris
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epiphany
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frv
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h8300
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hppa
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i386 re PR target/83467 (ICE: in assign_by_spills, at lra-assigns.c:1476: unable to find a register to spill with -flive-range-shrinkage -m8bit-idiv) 2017-12-21 21:48:34 +01:00
ia64
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m68k
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microblaze
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mips re PR target/74563 (Classic MIPS16 (non-MIPS16e) function return broken) 2017-04-18 22:52:54 -06:00
msp430
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nds32
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nios2
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nvptx
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powerpc backport: re PR target/80210 (ICE in in extract_insn, at recog.c:2311 on ppc64 for with __builtin_pow) 2017-12-14 11:43:32 -06:00
riscv RISC-V: Fix -msave-restore bug with sibcalls. 2018-01-08 17:01:45 -08:00
rl78
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rx Fix numerous typos in comments 2017-04-03 23:30:56 +01:00
s390 S/390: Fix PR81534 2017-07-27 10:42:22 +00:00
sh Use relative line number for subsequent dg directives 2017-04-19 06:55:33 +00:00
sparc Support for the SPARC M8 cpu. 2017-07-07 17:42:43 +02:00
spu
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tic6x
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vax
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visium visium.md (type): Add trap. 2017-02-23 23:04:00 +00:00
x86_64/abi
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xstormy16
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