2011-09-06 01:55:25 +02:00
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/*
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* Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the Open Source and Linux Lab nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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2016-06-29 11:05:55 +02:00
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#ifndef XTENSA_CPU_H
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#define XTENSA_CPU_H
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2011-09-06 01:55:25 +02:00
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2016-03-15 13:49:25 +01:00
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#include "cpu-qom.h"
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2022-03-23 16:57:39 +01:00
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#include "qemu/cpu-float.h"
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2012-12-17 18:19:49 +01:00
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#include "exec/cpu-defs.h"
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2021-10-03 23:31:47 +02:00
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#include "hw/clock.h"
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2017-11-04 02:29:27 +01:00
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#include "xtensa-isa.h"
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2011-09-06 01:55:25 +02:00
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2019-03-22 19:51:19 +01:00
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/* Xtensa processors have a weak memory model */
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#define TCG_GUEST_DEFAULT_MO (0)
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2011-09-06 01:55:25 +02:00
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2011-09-06 01:55:27 +02:00
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enum {
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/* Additional instructions */
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XTENSA_OPTION_CODE_DENSITY,
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XTENSA_OPTION_LOOP,
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XTENSA_OPTION_EXTENDED_L32R,
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XTENSA_OPTION_16_BIT_IMUL,
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XTENSA_OPTION_32_BIT_IMUL,
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2011-10-16 00:56:01 +02:00
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XTENSA_OPTION_32_BIT_IMUL_HIGH,
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2011-09-06 01:55:27 +02:00
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XTENSA_OPTION_32_BIT_IDIV,
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XTENSA_OPTION_MAC16,
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2011-10-16 00:56:01 +02:00
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XTENSA_OPTION_MISC_OP_NSA,
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XTENSA_OPTION_MISC_OP_MINMAX,
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XTENSA_OPTION_MISC_OP_SEXT,
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XTENSA_OPTION_MISC_OP_CLAMPS,
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2011-09-06 01:55:27 +02:00
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XTENSA_OPTION_COPROCESSOR,
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XTENSA_OPTION_BOOLEAN,
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XTENSA_OPTION_FP_COPROCESSOR,
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2020-07-11 11:58:22 +02:00
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XTENSA_OPTION_DFP_COPROCESSOR,
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XTENSA_OPTION_DFPU_SINGLE_ONLY,
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2011-09-06 01:55:27 +02:00
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XTENSA_OPTION_MP_SYNCHRO,
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XTENSA_OPTION_CONDITIONAL_STORE,
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2012-12-05 04:15:20 +01:00
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XTENSA_OPTION_ATOMCTL,
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2015-07-12 01:10:17 +02:00
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XTENSA_OPTION_DEPBITS,
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2011-09-06 01:55:27 +02:00
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/* Interrupts and exceptions */
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XTENSA_OPTION_EXCEPTION,
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XTENSA_OPTION_RELOCATABLE_VECTOR,
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XTENSA_OPTION_UNALIGNED_EXCEPTION,
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XTENSA_OPTION_INTERRUPT,
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XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
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XTENSA_OPTION_TIMER_INTERRUPT,
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/* Local memory */
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XTENSA_OPTION_ICACHE,
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XTENSA_OPTION_ICACHE_TEST,
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XTENSA_OPTION_ICACHE_INDEX_LOCK,
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XTENSA_OPTION_DCACHE,
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XTENSA_OPTION_DCACHE_TEST,
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XTENSA_OPTION_DCACHE_INDEX_LOCK,
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XTENSA_OPTION_IRAM,
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XTENSA_OPTION_IROM,
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XTENSA_OPTION_DRAM,
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XTENSA_OPTION_DROM,
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XTENSA_OPTION_XLMI,
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XTENSA_OPTION_HW_ALIGNMENT,
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XTENSA_OPTION_MEMORY_ECC_PARITY,
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/* Memory protection and translation */
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XTENSA_OPTION_REGION_PROTECTION,
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XTENSA_OPTION_REGION_TRANSLATION,
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2019-03-13 20:40:38 +01:00
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XTENSA_OPTION_MPU,
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2011-09-06 01:55:27 +02:00
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XTENSA_OPTION_MMU,
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2012-12-05 04:15:21 +01:00
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XTENSA_OPTION_CACHEATTR,
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2011-09-06 01:55:27 +02:00
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/* Other */
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XTENSA_OPTION_WINDOWED_REGISTER,
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XTENSA_OPTION_PROCESSOR_INTERFACE,
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XTENSA_OPTION_MISC_SR,
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XTENSA_OPTION_THREAD_POINTER,
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XTENSA_OPTION_PROCESSOR_ID,
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XTENSA_OPTION_DEBUG,
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XTENSA_OPTION_TRACE_PORT,
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2011-11-26 12:48:41 +01:00
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XTENSA_OPTION_EXTERN_REGS,
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2011-09-06 01:55:27 +02:00
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};
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2011-09-06 01:55:33 +02:00
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enum {
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2017-02-18 01:21:36 +01:00
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EXPSTATE = 230,
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2011-09-06 01:55:33 +02:00
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THREADPTR = 231,
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FCR = 232,
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FSR = 233,
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};
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2011-09-06 01:55:35 +02:00
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enum {
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2011-09-06 01:55:44 +02:00
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LBEG = 0,
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LEND = 1,
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LCOUNT = 2,
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2011-09-06 01:55:35 +02:00
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SAR = 3,
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2011-09-06 01:55:54 +02:00
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BR = 4,
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2011-09-06 01:55:45 +02:00
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LITBASE = 5,
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2011-09-06 01:55:36 +02:00
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SCOMPARE1 = 12,
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2011-10-10 04:25:40 +02:00
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ACCLO = 16,
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ACCHI = 17,
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MR = 32,
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2019-02-18 12:11:40 +01:00
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PREFCTL = 40,
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2011-09-06 01:55:43 +02:00
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WINDOW_BASE = 72,
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WINDOW_START = 73,
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2011-09-06 01:55:53 +02:00
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PTEVADDR = 83,
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2017-01-29 12:50:25 +01:00
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MMID = 89,
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2011-09-06 01:55:53 +02:00
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RASID = 90,
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2019-03-13 20:40:38 +01:00
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MPUENB = 90,
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2011-09-06 01:55:53 +02:00
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ITLBCFG = 91,
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DTLBCFG = 92,
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2019-03-13 20:40:38 +01:00
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MPUCFG = 92,
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ERACCESS = 95,
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2012-01-13 06:21:32 +01:00
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IBREAKENABLE = 96,
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2016-11-12 07:40:18 +01:00
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MEMCTL = 97,
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2012-12-05 04:15:21 +01:00
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CACHEATTR = 98,
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2019-03-13 20:40:38 +01:00
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CACHEADRDIS = 98,
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2012-12-05 04:15:20 +01:00
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ATOMCTL = 99,
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2017-01-29 12:50:25 +01:00
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DDR = 104,
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2019-03-13 20:41:13 +01:00
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MEPC = 106,
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MEPS = 107,
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MESAVE = 108,
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MESR = 109,
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MECR = 110,
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MEVADDR = 111,
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2012-01-13 06:21:32 +01:00
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IBREAKA = 128,
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2012-01-29 02:28:21 +01:00
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DBREAKA = 144,
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DBREAKC = 160,
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2014-02-15 17:49:09 +01:00
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CONFIGID0 = 176,
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2011-09-06 01:55:41 +02:00
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EPC1 = 177,
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DEPC = 192,
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2011-09-06 01:55:48 +02:00
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EPS2 = 194,
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2014-02-15 17:49:09 +01:00
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CONFIGID1 = 208,
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2011-09-06 01:55:41 +02:00
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EXCSAVE1 = 209,
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2011-09-06 01:55:50 +02:00
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CPENABLE = 224,
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2011-09-06 01:55:48 +02:00
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INTSET = 226,
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INTCLEAR = 227,
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INTENABLE = 228,
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2011-09-06 01:55:40 +02:00
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PS = 230,
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2011-09-06 01:55:51 +02:00
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VECBASE = 231,
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2011-09-06 01:55:41 +02:00
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EXCCAUSE = 232,
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2011-12-13 23:13:40 +01:00
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DEBUGCAUSE = 233,
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2011-09-06 01:55:48 +02:00
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CCOUNT = 234,
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2011-09-06 01:55:50 +02:00
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PRID = 235,
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2012-01-15 02:40:50 +01:00
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ICOUNT = 236,
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ICOUNTLEVEL = 237,
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2011-09-06 01:55:41 +02:00
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EXCVADDR = 238,
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2011-09-06 01:55:48 +02:00
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CCOMPARE = 240,
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2012-12-05 04:15:24 +01:00
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MISC = 244,
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2011-09-06 01:55:35 +02:00
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};
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2011-09-06 01:55:40 +02:00
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#define PS_INTLEVEL 0xf
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#define PS_INTLEVEL_SHIFT 0
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#define PS_EXCM 0x10
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#define PS_UM 0x20
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#define PS_RING 0xc0
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#define PS_RING_SHIFT 6
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#define PS_OWB 0xf00
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#define PS_OWB_SHIFT 8
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2017-01-25 19:54:11 +01:00
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#define PS_OWB_LEN 4
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2011-09-06 01:55:40 +02:00
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#define PS_CALLINC 0x30000
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#define PS_CALLINC_SHIFT 16
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#define PS_CALLINC_LEN 2
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#define PS_WOE 0x40000
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2011-12-13 23:13:40 +01:00
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#define DEBUGCAUSE_IC 0x1
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#define DEBUGCAUSE_IB 0x2
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#define DEBUGCAUSE_DB 0x4
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#define DEBUGCAUSE_BI 0x8
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#define DEBUGCAUSE_BN 0x10
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#define DEBUGCAUSE_DI 0x20
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#define DEBUGCAUSE_DBNUM 0xf00
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#define DEBUGCAUSE_DBNUM_SHIFT 8
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2012-01-29 02:28:21 +01:00
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#define DBREAKC_SB 0x80000000
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#define DBREAKC_LB 0x40000000
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#define DBREAKC_SB_LB (DBREAKC_SB | DBREAKC_LB)
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#define DBREAKC_MASK 0x3f
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2016-11-12 07:40:18 +01:00
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#define MEMCTL_INIT 0x00800000
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#define MEMCTL_IUSEWAYS_SHIFT 18
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#define MEMCTL_IUSEWAYS_LEN 5
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#define MEMCTL_IUSEWAYS_MASK 0x007c0000
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#define MEMCTL_DALLOCWAYS_SHIFT 13
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#define MEMCTL_DALLOCWAYS_LEN 5
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#define MEMCTL_DALLOCWAYS_MASK 0x0003e000
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#define MEMCTL_DUSEWAYS_SHIFT 8
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#define MEMCTL_DUSEWAYS_LEN 5
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#define MEMCTL_DUSEWAYS_MASK 0x00001f00
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#define MEMCTL_ISNP 0x4
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#define MEMCTL_DSNP 0x2
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#define MEMCTL_IL0EN 0x1
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2017-11-04 02:29:27 +01:00
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#define MAX_INSN_LENGTH 64
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2020-04-07 05:59:54 +02:00
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#define MAX_INSNBUF_LENGTH \
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((MAX_INSN_LENGTH + sizeof(xtensa_insnbuf_word) - 1) / \
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sizeof(xtensa_insnbuf_word))
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2018-08-28 06:43:43 +02:00
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#define MAX_INSN_SLOTS 32
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2017-11-04 02:29:27 +01:00
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#define MAX_OPCODE_ARGS 16
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2011-09-06 01:55:43 +02:00
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#define MAX_NAREG 64
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2011-09-06 01:55:48 +02:00
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#define MAX_NINTERRUPT 32
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#define MAX_NLEVEL 6
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#define MAX_NNMI 1
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#define MAX_NCCOMPARE 3
|
2011-09-06 01:55:53 +02:00
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#define MAX_TLB_WAY_SIZE 8
|
2012-01-29 02:28:21 +01:00
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#define MAX_NDBREAK 2
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2017-02-23 03:59:32 +01:00
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#define MAX_NMEMORY 4
|
2019-03-13 20:40:38 +01:00
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#define MAX_MPU_FOREGROUND_SEGMENTS 32
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2011-09-06 01:55:53 +02:00
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#define REGION_PAGE_MASK 0xe0000000
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2011-09-06 01:55:43 +02:00
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2012-12-05 04:15:20 +01:00
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#define PAGE_CACHE_MASK 0x700
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#define PAGE_CACHE_SHIFT 8
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#define PAGE_CACHE_INVALID 0x000
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#define PAGE_CACHE_BYPASS 0x100
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#define PAGE_CACHE_WT 0x200
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#define PAGE_CACHE_WB 0x400
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#define PAGE_CACHE_ISOLATE 0x600
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2011-09-06 01:55:41 +02:00
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enum {
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/* Static vectors */
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2013-02-17 13:38:09 +01:00
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EXC_RESET0,
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EXC_RESET1,
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2011-09-06 01:55:41 +02:00
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EXC_MEMORY_ERROR,
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/* Dynamic vectors */
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EXC_WINDOW_OVERFLOW4,
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EXC_WINDOW_UNDERFLOW4,
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EXC_WINDOW_OVERFLOW8,
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EXC_WINDOW_UNDERFLOW8,
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EXC_WINDOW_OVERFLOW12,
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EXC_WINDOW_UNDERFLOW12,
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EXC_IRQ,
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EXC_KERNEL,
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EXC_USER,
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EXC_DOUBLE,
|
2012-01-13 06:21:32 +01:00
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EXC_DEBUG,
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2011-09-06 01:55:41 +02:00
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EXC_MAX
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};
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enum {
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ILLEGAL_INSTRUCTION_CAUSE = 0,
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SYSCALL_CAUSE,
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INSTRUCTION_FETCH_ERROR_CAUSE,
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LOAD_STORE_ERROR_CAUSE,
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LEVEL1_INTERRUPT_CAUSE,
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ALLOCA_CAUSE,
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INTEGER_DIVIDE_BY_ZERO_CAUSE,
|
2019-04-19 01:36:36 +02:00
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PC_VALUE_ERROR_CAUSE,
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PRIVILEGED_CAUSE,
|
2011-09-06 01:55:41 +02:00
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LOAD_STORE_ALIGNMENT_CAUSE,
|
2019-04-19 01:36:36 +02:00
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EXTERNAL_REG_PRIVILEGE_CAUSE,
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EXCLUSIVE_ERROR_CAUSE,
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INSTR_PIF_DATA_ERROR_CAUSE,
|
2011-09-06 01:55:41 +02:00
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LOAD_STORE_PIF_DATA_ERROR_CAUSE,
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INSTR_PIF_ADDR_ERROR_CAUSE,
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LOAD_STORE_PIF_ADDR_ERROR_CAUSE,
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INST_TLB_MISS_CAUSE,
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INST_TLB_MULTI_HIT_CAUSE,
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INST_FETCH_PRIVILEGE_CAUSE,
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INST_FETCH_PROHIBITED_CAUSE = 20,
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LOAD_STORE_TLB_MISS_CAUSE = 24,
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LOAD_STORE_TLB_MULTI_HIT_CAUSE,
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LOAD_STORE_PRIVILEGE_CAUSE,
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LOAD_PROHIBITED_CAUSE = 28,
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|
|
STORE_PROHIBITED_CAUSE,
|
|
|
|
|
|
|
|
COPROCESSOR0_DISABLED = 32,
|
|
|
|
};
|
|
|
|
|
2011-09-06 01:55:48 +02:00
|
|
|
typedef enum {
|
|
|
|
INTTYPE_LEVEL,
|
|
|
|
INTTYPE_EDGE,
|
|
|
|
INTTYPE_NMI,
|
|
|
|
INTTYPE_SOFTWARE,
|
|
|
|
INTTYPE_TIMER,
|
|
|
|
INTTYPE_DEBUG,
|
|
|
|
INTTYPE_WRITE_ERR,
|
2014-02-15 16:16:33 +01:00
|
|
|
INTTYPE_PROFILING,
|
2019-03-12 07:11:42 +01:00
|
|
|
INTTYPE_IDMA_DONE,
|
|
|
|
INTTYPE_IDMA_ERR,
|
|
|
|
INTTYPE_GS_ERR,
|
2011-09-06 01:55:48 +02:00
|
|
|
INTTYPE_MAX
|
|
|
|
} interrupt_type;
|
|
|
|
|
2022-02-07 13:35:58 +01:00
|
|
|
typedef struct CPUArchState CPUXtensaState;
|
2013-09-04 02:57:49 +02:00
|
|
|
|
2011-09-06 01:55:53 +02:00
|
|
|
typedef struct xtensa_tlb_entry {
|
|
|
|
uint32_t vaddr;
|
|
|
|
uint32_t paddr;
|
|
|
|
uint8_t asid;
|
|
|
|
uint8_t attr;
|
|
|
|
bool variable;
|
|
|
|
} xtensa_tlb_entry;
|
|
|
|
|
|
|
|
typedef struct xtensa_tlb {
|
|
|
|
unsigned nways;
|
|
|
|
const unsigned way_size[10];
|
|
|
|
bool varway56;
|
|
|
|
unsigned nrefillentries;
|
|
|
|
} xtensa_tlb;
|
|
|
|
|
2019-03-13 20:40:38 +01:00
|
|
|
typedef struct xtensa_mpu_entry {
|
|
|
|
uint32_t vaddr;
|
|
|
|
uint32_t attr;
|
|
|
|
} xtensa_mpu_entry;
|
|
|
|
|
2011-09-06 01:55:52 +02:00
|
|
|
typedef struct XtensaGdbReg {
|
|
|
|
int targno;
|
2018-02-04 08:55:06 +01:00
|
|
|
unsigned flags;
|
2011-09-06 01:55:52 +02:00
|
|
|
int type;
|
|
|
|
int group;
|
2015-06-29 09:50:03 +02:00
|
|
|
unsigned size;
|
2011-09-06 01:55:52 +02:00
|
|
|
} XtensaGdbReg;
|
|
|
|
|
|
|
|
typedef struct XtensaGdbRegmap {
|
|
|
|
int num_regs;
|
|
|
|
int num_core_regs;
|
|
|
|
/* PC + a + ar + sr + ur */
|
|
|
|
XtensaGdbReg reg[1 + 16 + 64 + 256 + 256];
|
|
|
|
} XtensaGdbRegmap;
|
|
|
|
|
2013-09-04 02:57:49 +02:00
|
|
|
typedef struct XtensaCcompareTimer {
|
2022-02-07 13:17:56 +01:00
|
|
|
CPUXtensaState *env;
|
2013-09-04 02:57:49 +02:00
|
|
|
QEMUTimer *timer;
|
|
|
|
} XtensaCcompareTimer;
|
|
|
|
|
2017-02-23 03:59:32 +01:00
|
|
|
typedef struct XtensaMemory {
|
|
|
|
unsigned num;
|
|
|
|
struct XtensaMemoryRegion {
|
|
|
|
uint32_t addr;
|
|
|
|
uint32_t size;
|
|
|
|
} location[MAX_NMEMORY];
|
|
|
|
} XtensaMemory;
|
|
|
|
|
2019-02-12 03:53:19 +01:00
|
|
|
typedef struct opcode_arg {
|
|
|
|
uint32_t imm;
|
|
|
|
uint32_t raw_imm;
|
|
|
|
void *in;
|
|
|
|
void *out;
|
2020-01-25 09:53:39 +01:00
|
|
|
uint32_t num_bits;
|
2019-02-12 03:53:19 +01:00
|
|
|
} OpcodeArg;
|
|
|
|
|
2017-11-04 02:29:27 +01:00
|
|
|
typedef struct DisasContext DisasContext;
|
2019-02-12 03:53:19 +01:00
|
|
|
typedef void (*XtensaOpcodeOp)(DisasContext *dc, const OpcodeArg arg[],
|
2017-11-04 02:29:27 +01:00
|
|
|
const uint32_t par[]);
|
2018-08-29 19:37:29 +02:00
|
|
|
typedef uint32_t (*XtensaOpcodeUintTest)(DisasContext *dc,
|
2019-02-12 03:53:19 +01:00
|
|
|
const OpcodeArg arg[],
|
2018-08-29 19:37:29 +02:00
|
|
|
const uint32_t par[]);
|
2018-08-28 06:43:43 +02:00
|
|
|
|
|
|
|
enum {
|
|
|
|
XTENSA_OP_ILL = 0x1,
|
|
|
|
XTENSA_OP_PRIVILEGED = 0x2,
|
|
|
|
XTENSA_OP_SYSCALL = 0x4,
|
|
|
|
XTENSA_OP_DEBUG_BREAK = 0x8,
|
|
|
|
|
|
|
|
XTENSA_OP_OVERFLOW = 0x10,
|
|
|
|
XTENSA_OP_UNDERFLOW = 0x20,
|
|
|
|
XTENSA_OP_ALLOCA = 0x40,
|
|
|
|
XTENSA_OP_COPROCESSOR = 0x80,
|
|
|
|
|
|
|
|
XTENSA_OP_DIVIDE_BY_ZERO = 0x100,
|
|
|
|
|
2019-01-30 23:48:22 +01:00
|
|
|
/* Postprocessing flags */
|
2018-08-28 06:43:43 +02:00
|
|
|
XTENSA_OP_CHECK_INTERRUPTS = 0x200,
|
|
|
|
XTENSA_OP_EXIT_TB_M1 = 0x400,
|
|
|
|
XTENSA_OP_EXIT_TB_0 = 0x800,
|
2019-01-30 23:48:22 +01:00
|
|
|
XTENSA_OP_SYNC_REGISTER_WINDOW = 0x1000,
|
|
|
|
|
|
|
|
XTENSA_OP_POSTPROCESS =
|
|
|
|
XTENSA_OP_CHECK_INTERRUPTS |
|
|
|
|
XTENSA_OP_EXIT_TB_M1 |
|
|
|
|
XTENSA_OP_EXIT_TB_0 |
|
|
|
|
XTENSA_OP_SYNC_REGISTER_WINDOW,
|
2019-02-10 08:39:10 +01:00
|
|
|
|
|
|
|
XTENSA_OP_NAME_ARRAY = 0x8000,
|
2019-01-30 04:21:10 +01:00
|
|
|
|
|
|
|
XTENSA_OP_CONTROL_FLOW = 0x10000,
|
2019-02-14 02:36:30 +01:00
|
|
|
XTENSA_OP_STORE = 0x20000,
|
|
|
|
XTENSA_OP_LOAD = 0x40000,
|
|
|
|
XTENSA_OP_LOAD_STORE =
|
|
|
|
XTENSA_OP_LOAD | XTENSA_OP_STORE,
|
2018-08-28 06:43:43 +02:00
|
|
|
};
|
2017-11-04 02:29:27 +01:00
|
|
|
|
|
|
|
typedef struct XtensaOpcodeOps {
|
2019-02-10 08:39:10 +01:00
|
|
|
const void *name;
|
2017-11-04 02:29:27 +01:00
|
|
|
XtensaOpcodeOp translate;
|
2020-05-04 23:08:40 +02:00
|
|
|
XtensaOpcodeUintTest test_exceptions;
|
2018-08-29 19:37:29 +02:00
|
|
|
XtensaOpcodeUintTest test_overflow;
|
2017-11-04 02:29:27 +01:00
|
|
|
const uint32_t *par;
|
2018-08-28 06:43:43 +02:00
|
|
|
uint32_t op_flags;
|
2018-08-31 22:57:08 +02:00
|
|
|
uint32_t coprocessor;
|
2017-11-04 02:29:27 +01:00
|
|
|
} XtensaOpcodeOps;
|
|
|
|
|
|
|
|
typedef struct XtensaOpcodeTranslators {
|
|
|
|
unsigned num_opcodes;
|
|
|
|
const XtensaOpcodeOps *opcode;
|
|
|
|
} XtensaOpcodeTranslators;
|
|
|
|
|
|
|
|
extern const XtensaOpcodeTranslators xtensa_core_opcodes;
|
2017-11-04 03:37:13 +01:00
|
|
|
extern const XtensaOpcodeTranslators xtensa_fpu2000_opcodes;
|
2020-07-01 04:27:02 +02:00
|
|
|
extern const XtensaOpcodeTranslators xtensa_fpu_opcodes;
|
2017-11-04 02:29:27 +01:00
|
|
|
|
2016-03-15 13:49:25 +01:00
|
|
|
struct XtensaConfig {
|
2011-09-06 01:55:27 +02:00
|
|
|
const char *name;
|
|
|
|
uint64_t options;
|
2011-09-06 01:55:52 +02:00
|
|
|
XtensaGdbRegmap gdb_regmap;
|
2011-09-06 01:55:43 +02:00
|
|
|
unsigned nareg;
|
2011-09-06 01:55:41 +02:00
|
|
|
int excm_level;
|
|
|
|
int ndepc;
|
2018-04-27 22:07:53 +02:00
|
|
|
unsigned inst_fetch_width;
|
2018-10-04 00:59:11 +02:00
|
|
|
unsigned max_insn_size;
|
2011-09-06 01:55:51 +02:00
|
|
|
uint32_t vecbase;
|
2011-09-06 01:55:41 +02:00
|
|
|
uint32_t exception_vector[EXC_MAX];
|
2011-09-06 01:55:48 +02:00
|
|
|
unsigned ninterrupt;
|
|
|
|
unsigned nlevel;
|
2020-07-06 02:31:59 +02:00
|
|
|
unsigned nmi_level;
|
2011-09-06 01:55:48 +02:00
|
|
|
uint32_t interrupt_vector[MAX_NLEVEL + MAX_NNMI + 1];
|
|
|
|
uint32_t level_mask[MAX_NLEVEL + MAX_NNMI + 1];
|
|
|
|
uint32_t inttype_mask[INTTYPE_MAX];
|
|
|
|
struct {
|
|
|
|
uint32_t level;
|
|
|
|
interrupt_type inttype;
|
|
|
|
} interrupt[MAX_NINTERRUPT];
|
|
|
|
unsigned nccompare;
|
|
|
|
uint32_t timerint[MAX_NCCOMPARE];
|
2011-10-16 00:56:03 +02:00
|
|
|
unsigned nextint;
|
|
|
|
unsigned extint[MAX_NINTERRUPT];
|
2011-12-13 23:13:40 +01:00
|
|
|
|
|
|
|
unsigned debug_level;
|
|
|
|
unsigned nibreak;
|
|
|
|
unsigned ndbreak;
|
|
|
|
|
2016-11-12 07:40:18 +01:00
|
|
|
unsigned icache_ways;
|
|
|
|
unsigned dcache_ways;
|
2019-04-14 23:02:17 +02:00
|
|
|
unsigned dcache_line_bytes;
|
2016-11-12 07:40:18 +01:00
|
|
|
uint32_t memctl_mask;
|
|
|
|
|
2017-02-23 03:59:32 +01:00
|
|
|
XtensaMemory instrom;
|
|
|
|
XtensaMemory instram;
|
|
|
|
XtensaMemory datarom;
|
|
|
|
XtensaMemory dataram;
|
|
|
|
XtensaMemory sysrom;
|
|
|
|
XtensaMemory sysram;
|
|
|
|
|
2020-05-04 13:30:45 +02:00
|
|
|
unsigned hw_version;
|
2014-02-15 17:49:09 +01:00
|
|
|
uint32_t configid[2];
|
|
|
|
|
2017-11-04 02:29:27 +01:00
|
|
|
void *isa_internal;
|
2017-11-04 03:44:46 +01:00
|
|
|
xtensa_isa isa;
|
|
|
|
XtensaOpcodeOps **opcode_ops;
|
|
|
|
const XtensaOpcodeTranslators **opcode_translators;
|
2019-02-10 03:30:00 +01:00
|
|
|
xtensa_regfile a_regfile;
|
2019-02-12 03:53:19 +01:00
|
|
|
void ***regfile;
|
2017-11-04 02:29:27 +01:00
|
|
|
|
2011-09-06 01:55:48 +02:00
|
|
|
uint32_t clock_freq_khz;
|
2011-09-06 01:55:53 +02:00
|
|
|
|
|
|
|
xtensa_tlb itlb;
|
|
|
|
xtensa_tlb dtlb;
|
2019-03-13 20:40:38 +01:00
|
|
|
|
|
|
|
uint32_t mpu_align;
|
|
|
|
unsigned n_mpu_fg_segments;
|
|
|
|
unsigned n_mpu_bg_segments;
|
|
|
|
const xtensa_mpu_entry *mpu_bg;
|
2020-07-01 04:27:02 +02:00
|
|
|
|
|
|
|
bool use_first_nan;
|
2016-03-15 13:49:25 +01:00
|
|
|
};
|
2011-09-06 01:55:27 +02:00
|
|
|
|
2011-10-16 00:56:04 +02:00
|
|
|
typedef struct XtensaConfigList {
|
|
|
|
const XtensaConfig *config;
|
|
|
|
struct XtensaConfigList *next;
|
|
|
|
} XtensaConfigList;
|
|
|
|
|
2022-03-23 16:57:17 +01:00
|
|
|
#if HOST_BIG_ENDIAN
|
2015-06-29 09:50:03 +02:00
|
|
|
enum {
|
|
|
|
FP_F32_HIGH,
|
|
|
|
FP_F32_LOW,
|
|
|
|
};
|
|
|
|
#else
|
|
|
|
enum {
|
|
|
|
FP_F32_LOW,
|
|
|
|
FP_F32_HIGH,
|
|
|
|
};
|
|
|
|
#endif
|
|
|
|
|
2022-02-07 13:35:58 +01:00
|
|
|
struct CPUArchState {
|
2011-09-06 01:55:27 +02:00
|
|
|
const XtensaConfig *config;
|
2011-09-06 01:55:25 +02:00
|
|
|
uint32_t regs[16];
|
|
|
|
uint32_t pc;
|
|
|
|
uint32_t sregs[256];
|
2011-09-06 01:55:33 +02:00
|
|
|
uint32_t uregs[256];
|
2011-09-06 01:55:43 +02:00
|
|
|
uint32_t phys_regs[MAX_NAREG];
|
2015-06-29 09:50:03 +02:00
|
|
|
union {
|
|
|
|
float32 f32[2];
|
|
|
|
float64 f64;
|
|
|
|
} fregs[16];
|
2012-09-19 02:23:54 +02:00
|
|
|
float_status fp_status;
|
2019-01-30 23:56:29 +01:00
|
|
|
uint32_t windowbase_next;
|
2019-04-19 01:37:00 +02:00
|
|
|
uint32_t exclusive_addr;
|
|
|
|
uint32_t exclusive_val;
|
2011-09-06 01:55:25 +02:00
|
|
|
|
2017-01-25 19:54:11 +01:00
|
|
|
#ifndef CONFIG_USER_ONLY
|
2011-09-06 01:55:53 +02:00
|
|
|
xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE];
|
|
|
|
xtensa_tlb_entry dtlb[10][MAX_TLB_WAY_SIZE];
|
2019-03-13 20:40:38 +01:00
|
|
|
xtensa_mpu_entry mpu_fg[MAX_MPU_FOREGROUND_SEGMENTS];
|
2011-09-06 01:55:53 +02:00
|
|
|
unsigned autorefill_idx;
|
2016-12-14 03:52:08 +01:00
|
|
|
bool runstall;
|
2011-11-26 12:48:41 +01:00
|
|
|
AddressSpace *address_space_er;
|
|
|
|
MemoryRegion *system_er;
|
2011-09-06 01:55:48 +02:00
|
|
|
int pending_irq_level; /* level of last raised IRQ */
|
2019-01-26 13:12:30 +01:00
|
|
|
qemu_irq *irq_inputs;
|
|
|
|
qemu_irq ext_irq_inputs[MAX_NINTERRUPT];
|
2019-01-28 02:10:27 +01:00
|
|
|
qemu_irq runstall_irq;
|
2013-09-04 02:57:49 +02:00
|
|
|
XtensaCcompareTimer ccompare[MAX_NCCOMPARE];
|
|
|
|
uint64_t time_base;
|
|
|
|
uint64_t ccount_time;
|
|
|
|
uint32_t ccount_base;
|
2017-01-25 19:54:11 +01:00
|
|
|
#endif
|
2011-09-06 01:55:48 +02:00
|
|
|
|
2013-07-22 06:02:43 +02:00
|
|
|
int yield_needed;
|
2013-02-17 13:38:09 +01:00
|
|
|
unsigned static_vectors;
|
2011-09-06 01:55:41 +02:00
|
|
|
|
2012-01-29 02:28:21 +01:00
|
|
|
/* Watchpoints for DBREAK registers */
|
2013-08-26 18:23:18 +02:00
|
|
|
struct CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK];
|
2022-02-07 13:35:58 +01:00
|
|
|
};
|
2011-09-06 01:55:25 +02:00
|
|
|
|
2016-03-15 13:49:25 +01:00
|
|
|
/**
|
|
|
|
* XtensaCPU:
|
|
|
|
* @env: #CPUXtensaState
|
|
|
|
*
|
|
|
|
* An Xtensa CPU.
|
|
|
|
*/
|
2022-02-14 17:15:16 +01:00
|
|
|
struct ArchCPU {
|
2016-03-15 13:49:25 +01:00
|
|
|
/*< private >*/
|
|
|
|
CPUState parent_obj;
|
|
|
|
/*< public >*/
|
|
|
|
|
2021-10-03 23:31:47 +02:00
|
|
|
Clock *clock;
|
2019-03-23 01:16:06 +01:00
|
|
|
CPUNegativeOffsetState neg;
|
2016-03-15 13:49:25 +01:00
|
|
|
CPUXtensaState env;
|
|
|
|
};
|
|
|
|
|
2017-01-25 19:54:11 +01:00
|
|
|
|
2021-09-15 17:09:38 +02:00
|
|
|
#ifndef CONFIG_USER_ONLY
|
2019-04-03 02:46:30 +02:00
|
|
|
bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
|
|
|
|
MMUAccessType access_type, int mmu_idx,
|
|
|
|
bool probe, uintptr_t retaddr);
|
2016-03-15 13:49:25 +01:00
|
|
|
void xtensa_cpu_do_interrupt(CPUState *cpu);
|
|
|
|
bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request);
|
2018-08-20 04:27:21 +02:00
|
|
|
void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
|
|
|
|
unsigned size, MMUAccessType access_type,
|
|
|
|
int mmu_idx, MemTxAttrs attrs,
|
|
|
|
MemTxResult response, uintptr_t retaddr);
|
2021-09-11 18:54:32 +02:00
|
|
|
#endif
|
2019-04-17 21:18:02 +02:00
|
|
|
void xtensa_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
|
2016-03-15 13:49:25 +01:00
|
|
|
hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
|
2018-08-16 19:34:56 +02:00
|
|
|
void xtensa_count_regs(const XtensaConfig *config,
|
|
|
|
unsigned *n_regs, unsigned *n_core_regs);
|
2020-03-16 18:21:41 +01:00
|
|
|
int xtensa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
|
2016-03-15 13:49:25 +01:00
|
|
|
int xtensa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
|
2022-04-20 15:26:02 +02:00
|
|
|
G_NORETURN void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
|
|
|
|
MMUAccessType access_type, int mmu_idx,
|
|
|
|
uintptr_t retaddr);
|
2012-05-06 12:41:53 +02:00
|
|
|
|
2011-09-06 01:55:25 +02:00
|
|
|
#define cpu_list xtensa_cpu_list
|
|
|
|
|
2017-10-05 15:50:58 +02:00
|
|
|
#define XTENSA_CPU_TYPE_SUFFIX "-" TYPE_XTENSA_CPU
|
|
|
|
#define XTENSA_CPU_TYPE_NAME(model) model XTENSA_CPU_TYPE_SUFFIX
|
2018-02-07 11:40:25 +01:00
|
|
|
#define CPU_RESOLVING_TYPE TYPE_XTENSA_CPU
|
2017-10-05 15:50:58 +02:00
|
|
|
|
2022-03-23 16:57:18 +01:00
|
|
|
#if TARGET_BIG_ENDIAN
|
2012-08-08 12:07:14 +02:00
|
|
|
#define XTENSA_DEFAULT_CPU_MODEL "fsf"
|
2018-01-11 21:56:45 +01:00
|
|
|
#define XTENSA_DEFAULT_CPU_NOMMU_MODEL "fsf"
|
2012-08-08 12:07:14 +02:00
|
|
|
#else
|
|
|
|
#define XTENSA_DEFAULT_CPU_MODEL "dc232b"
|
2018-01-11 21:56:45 +01:00
|
|
|
#define XTENSA_DEFAULT_CPU_NOMMU_MODEL "de212"
|
2012-08-08 12:07:14 +02:00
|
|
|
#endif
|
2018-01-11 21:56:45 +01:00
|
|
|
#define XTENSA_DEFAULT_CPU_TYPE \
|
|
|
|
XTENSA_CPU_TYPE_NAME(XTENSA_DEFAULT_CPU_MODEL)
|
|
|
|
#define XTENSA_DEFAULT_CPU_NOMMU_TYPE \
|
|
|
|
XTENSA_CPU_TYPE_NAME(XTENSA_DEFAULT_CPU_NOMMU_MODEL)
|
2012-08-08 12:07:14 +02:00
|
|
|
|
2019-03-19 01:10:38 +01:00
|
|
|
void xtensa_collect_sr_names(const XtensaConfig *config);
|
2011-09-06 01:55:25 +02:00
|
|
|
void xtensa_translate_init(void);
|
2020-06-28 11:53:32 +02:00
|
|
|
void **xtensa_get_regfile_by_name(const char *name, int entries, int bits);
|
2014-09-12 15:06:48 +02:00
|
|
|
void xtensa_breakpoint_handler(CPUState *cs);
|
2011-10-16 00:56:04 +02:00
|
|
|
void xtensa_register_core(XtensaConfigList *node);
|
2017-05-12 20:09:14 +02:00
|
|
|
void xtensa_sim_open_console(Chardev *chr);
|
2011-09-06 01:55:48 +02:00
|
|
|
void check_interrupts(CPUXtensaState *s);
|
2012-03-14 01:38:23 +01:00
|
|
|
void xtensa_irq_init(CPUXtensaState *env);
|
2019-01-26 13:12:30 +01:00
|
|
|
qemu_irq *xtensa_get_extints(CPUXtensaState *env);
|
2019-01-28 02:10:27 +01:00
|
|
|
qemu_irq xtensa_get_runstall(CPUXtensaState *env);
|
2019-04-17 21:17:57 +02:00
|
|
|
void xtensa_cpu_list(void);
|
2012-03-14 01:38:23 +01:00
|
|
|
void xtensa_sync_window_from_phys(CPUXtensaState *env);
|
|
|
|
void xtensa_sync_phys_from_window(CPUXtensaState *env);
|
2017-01-25 19:54:11 +01:00
|
|
|
void xtensa_rotate_window(CPUXtensaState *env, uint32_t delta);
|
|
|
|
void xtensa_restore_owb(CPUXtensaState *env);
|
2012-03-14 01:38:23 +01:00
|
|
|
void debug_exception_env(CPUXtensaState *new_env, uint32_t cause);
|
2011-09-06 01:55:53 +02:00
|
|
|
|
2013-02-17 13:38:09 +01:00
|
|
|
static inline void xtensa_select_static_vectors(CPUXtensaState *env,
|
|
|
|
unsigned n)
|
|
|
|
{
|
|
|
|
assert(n < 2);
|
|
|
|
env->static_vectors = n;
|
|
|
|
}
|
2016-12-14 03:52:08 +01:00
|
|
|
void xtensa_runstall(CPUXtensaState *env, bool runstall);
|
2011-09-06 01:55:25 +02:00
|
|
|
|
2011-09-06 01:55:27 +02:00
|
|
|
#define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt))
|
2012-12-05 04:15:22 +01:00
|
|
|
#define XTENSA_OPTION_ALL (~(uint64_t)0)
|
2011-09-06 01:55:27 +02:00
|
|
|
|
2011-09-06 01:55:53 +02:00
|
|
|
static inline bool xtensa_option_bits_enabled(const XtensaConfig *config,
|
|
|
|
uint64_t opt)
|
|
|
|
{
|
|
|
|
return (config->options & opt) != 0;
|
|
|
|
}
|
|
|
|
|
2011-09-06 01:55:27 +02:00
|
|
|
static inline bool xtensa_option_enabled(const XtensaConfig *config, int opt)
|
|
|
|
{
|
2011-09-06 01:55:53 +02:00
|
|
|
return xtensa_option_bits_enabled(config, XTENSA_OPTION_BIT(opt));
|
2011-09-06 01:55:27 +02:00
|
|
|
}
|
|
|
|
|
2012-03-14 01:38:23 +01:00
|
|
|
static inline int xtensa_get_cintlevel(const CPUXtensaState *env)
|
2011-09-06 01:55:41 +02:00
|
|
|
{
|
|
|
|
int level = (env->sregs[PS] & PS_INTLEVEL) >> PS_INTLEVEL_SHIFT;
|
|
|
|
if ((env->sregs[PS] & PS_EXCM) && env->config->excm_level > level) {
|
|
|
|
level = env->config->excm_level;
|
|
|
|
}
|
|
|
|
return level;
|
|
|
|
}
|
|
|
|
|
2012-03-14 01:38:23 +01:00
|
|
|
static inline int xtensa_get_ring(const CPUXtensaState *env)
|
2011-09-06 01:55:40 +02:00
|
|
|
{
|
2019-11-04 09:01:27 +01:00
|
|
|
if (xtensa_option_bits_enabled(env->config,
|
|
|
|
XTENSA_OPTION_BIT(XTENSA_OPTION_MMU) |
|
|
|
|
XTENSA_OPTION_BIT(XTENSA_OPTION_MPU))) {
|
2011-09-06 01:55:40 +02:00
|
|
|
return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
|
|
|
|
} else {
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-03-14 01:38:23 +01:00
|
|
|
static inline int xtensa_get_cring(const CPUXtensaState *env)
|
2011-09-06 01:55:40 +02:00
|
|
|
{
|
2019-11-04 09:01:27 +01:00
|
|
|
if (xtensa_option_bits_enabled(env->config,
|
|
|
|
XTENSA_OPTION_BIT(XTENSA_OPTION_MMU) |
|
|
|
|
XTENSA_OPTION_BIT(XTENSA_OPTION_MPU)) &&
|
|
|
|
(env->sregs[PS] & PS_EXCM) == 0) {
|
2011-09-06 01:55:40 +02:00
|
|
|
return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
|
|
|
|
} else {
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-01-25 19:54:11 +01:00
|
|
|
#ifndef CONFIG_USER_ONLY
|
|
|
|
int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb,
|
|
|
|
uint32_t vaddr, int is_write, int mmu_idx,
|
|
|
|
uint32_t *paddr, uint32_t *page_size, unsigned *access);
|
|
|
|
void reset_mmu(CPUXtensaState *env);
|
2019-04-17 21:17:58 +02:00
|
|
|
void dump_mmu(CPUXtensaState *env);
|
2017-01-25 19:54:11 +01:00
|
|
|
|
|
|
|
static inline MemoryRegion *xtensa_get_er_region(CPUXtensaState *env)
|
|
|
|
{
|
|
|
|
return env->system_er;
|
|
|
|
}
|
2019-09-06 18:57:13 +02:00
|
|
|
#else
|
|
|
|
void xtensa_set_abi_call0(void);
|
|
|
|
bool xtensa_abi_call0(void);
|
2017-01-25 19:54:11 +01:00
|
|
|
#endif
|
2011-09-06 01:55:53 +02:00
|
|
|
|
2014-11-07 19:11:07 +01:00
|
|
|
static inline uint32_t xtensa_replicate_windowstart(CPUXtensaState *env)
|
|
|
|
{
|
|
|
|
return env->sregs[WINDOW_START] |
|
|
|
|
(env->sregs[WINDOW_START] << env->config->nareg / 4);
|
|
|
|
}
|
|
|
|
|
2011-09-06 01:55:40 +02:00
|
|
|
/* MMU modes definitions */
|
2017-01-25 19:54:11 +01:00
|
|
|
#define MMU_USER_IDX 3
|
2011-09-06 01:55:40 +02:00
|
|
|
|
2015-08-17 09:34:10 +02:00
|
|
|
static inline int cpu_mmu_index(CPUXtensaState *env, bool ifetch)
|
2011-09-06 01:55:25 +02:00
|
|
|
{
|
2011-09-06 01:55:40 +02:00
|
|
|
return xtensa_get_cring(env);
|
2011-09-06 01:55:25 +02:00
|
|
|
}
|
|
|
|
|
2011-09-06 01:55:40 +02:00
|
|
|
#define XTENSA_TBFLAG_RING_MASK 0x3
|
|
|
|
#define XTENSA_TBFLAG_EXCM 0x4
|
2011-09-06 01:55:45 +02:00
|
|
|
#define XTENSA_TBFLAG_LITBASE 0x8
|
2012-01-13 06:21:32 +01:00
|
|
|
#define XTENSA_TBFLAG_DEBUG 0x10
|
2012-01-15 02:40:50 +01:00
|
|
|
#define XTENSA_TBFLAG_ICOUNT 0x20
|
2012-09-19 02:23:59 +02:00
|
|
|
#define XTENSA_TBFLAG_CPENABLE_MASK 0x3fc0
|
|
|
|
#define XTENSA_TBFLAG_CPENABLE_SHIFT 6
|
2014-10-30 16:07:47 +01:00
|
|
|
#define XTENSA_TBFLAG_WINDOW_MASK 0x18000
|
|
|
|
#define XTENSA_TBFLAG_WINDOW_SHIFT 15
|
2013-07-22 06:02:43 +02:00
|
|
|
#define XTENSA_TBFLAG_YIELD 0x20000
|
2018-08-28 06:43:43 +02:00
|
|
|
#define XTENSA_TBFLAG_CWOE 0x40000
|
2018-08-29 19:37:29 +02:00
|
|
|
#define XTENSA_TBFLAG_CALLINC_MASK 0x180000
|
|
|
|
#define XTENSA_TBFLAG_CALLINC_SHIFT 19
|
2011-09-06 01:55:40 +02:00
|
|
|
|
2018-10-04 00:59:11 +02:00
|
|
|
#define XTENSA_CSBASE_LEND_MASK 0x0000ffff
|
|
|
|
#define XTENSA_CSBASE_LEND_SHIFT 0
|
|
|
|
#define XTENSA_CSBASE_LBEG_OFF_MASK 0x00ff0000
|
|
|
|
#define XTENSA_CSBASE_LBEG_OFF_SHIFT 16
|
|
|
|
|
2019-03-23 03:52:17 +01:00
|
|
|
#include "exec/cpu-all.h"
|
|
|
|
|
2012-03-14 01:38:23 +01:00
|
|
|
static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,
|
2016-04-07 19:19:22 +02:00
|
|
|
target_ulong *cs_base, uint32_t *flags)
|
2011-09-06 01:55:25 +02:00
|
|
|
{
|
|
|
|
*pc = env->pc;
|
|
|
|
*cs_base = 0;
|
|
|
|
*flags = 0;
|
2011-09-06 01:55:40 +02:00
|
|
|
*flags |= xtensa_get_ring(env);
|
|
|
|
if (env->sregs[PS] & PS_EXCM) {
|
|
|
|
*flags |= XTENSA_TBFLAG_EXCM;
|
2018-10-04 00:59:11 +02:00
|
|
|
} else if (xtensa_option_enabled(env->config, XTENSA_OPTION_LOOP)) {
|
|
|
|
target_ulong lend_dist =
|
|
|
|
env->sregs[LEND] - (env->pc & -(1u << TARGET_PAGE_BITS));
|
|
|
|
|
|
|
|
/*
|
|
|
|
* 0 in the csbase_lend field means that there may not be a loopback
|
|
|
|
* for any instruction that starts inside this page. Any other value
|
|
|
|
* means that an instruction that ends at this offset from the page
|
|
|
|
* start may loop back and will need loopback code to be generated.
|
|
|
|
*
|
|
|
|
* lend_dist is 0 when LEND points to the start of the page, but
|
|
|
|
* no instruction that starts inside this page may end at offset 0,
|
|
|
|
* so it's still correct.
|
|
|
|
*
|
|
|
|
* When an instruction ends at a page boundary it may only start in
|
|
|
|
* the previous page. lend_dist will be encoded as TARGET_PAGE_SIZE
|
|
|
|
* for the TB that contains this instruction.
|
|
|
|
*/
|
|
|
|
if (lend_dist < (1u << TARGET_PAGE_BITS) + env->config->max_insn_size) {
|
|
|
|
target_ulong lbeg_off = env->sregs[LEND] - env->sregs[LBEG];
|
|
|
|
|
|
|
|
*cs_base = lend_dist;
|
|
|
|
if (lbeg_off < 256) {
|
|
|
|
*cs_base |= lbeg_off << XTENSA_CSBASE_LBEG_OFF_SHIFT;
|
|
|
|
}
|
|
|
|
}
|
2011-09-06 01:55:40 +02:00
|
|
|
}
|
2011-09-06 01:55:45 +02:00
|
|
|
if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) &&
|
|
|
|
(env->sregs[LITBASE] & 1)) {
|
|
|
|
*flags |= XTENSA_TBFLAG_LITBASE;
|
|
|
|
}
|
2012-01-13 06:21:32 +01:00
|
|
|
if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) {
|
|
|
|
if (xtensa_get_cintlevel(env) < env->config->debug_level) {
|
|
|
|
*flags |= XTENSA_TBFLAG_DEBUG;
|
|
|
|
}
|
2012-01-15 02:40:50 +01:00
|
|
|
if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) {
|
|
|
|
*flags |= XTENSA_TBFLAG_ICOUNT;
|
|
|
|
}
|
2012-01-13 06:21:32 +01:00
|
|
|
}
|
2012-09-19 02:23:59 +02:00
|
|
|
if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) {
|
|
|
|
*flags |= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT;
|
|
|
|
}
|
2014-10-30 16:07:47 +01:00
|
|
|
if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER) &&
|
|
|
|
(env->sregs[PS] & (PS_WOE | PS_EXCM)) == PS_WOE) {
|
|
|
|
uint32_t windowstart = xtensa_replicate_windowstart(env) >>
|
|
|
|
(env->sregs[WINDOW_BASE] + 1);
|
|
|
|
uint32_t w = ctz32(windowstart | 0x8);
|
|
|
|
|
2018-08-28 06:43:43 +02:00
|
|
|
*flags |= (w << XTENSA_TBFLAG_WINDOW_SHIFT) | XTENSA_TBFLAG_CWOE;
|
2018-08-29 19:37:29 +02:00
|
|
|
*flags |= extract32(env->sregs[PS], PS_CALLINC_SHIFT,
|
|
|
|
PS_CALLINC_LEN) << XTENSA_TBFLAG_CALLINC_SHIFT;
|
2014-10-30 16:07:47 +01:00
|
|
|
} else {
|
|
|
|
*flags |= 3 << XTENSA_TBFLAG_WINDOW_SHIFT;
|
|
|
|
}
|
2013-07-22 06:02:43 +02:00
|
|
|
if (env->yield_needed) {
|
|
|
|
*flags |= XTENSA_TBFLAG_YIELD;
|
|
|
|
}
|
2011-09-06 01:55:25 +02:00
|
|
|
}
|
|
|
|
|
2021-10-03 23:31:47 +02:00
|
|
|
XtensaCPU *xtensa_cpu_create_with_clock(const char *cpu_type,
|
|
|
|
Clock *cpu_refclk);
|
|
|
|
|
2011-09-06 01:55:25 +02:00
|
|
|
#endif
|