2006-04-27 23:32:09 +02:00
|
|
|
/*
|
|
|
|
* SH7750 device
|
2007-09-16 23:08:06 +02:00
|
|
|
*
|
2007-10-04 23:53:55 +02:00
|
|
|
* Copyright (c) 2007 Magnus Damm
|
2006-04-27 23:32:09 +02:00
|
|
|
* Copyright (c) 2005 Samuel Tardieu
|
2007-09-16 23:08:06 +02:00
|
|
|
*
|
2006-04-27 23:32:09 +02:00
|
|
|
* Permission is hereby granted, free of charge, to any person obtaining a copy
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|
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
|
2019-08-12 07:23:42 +02:00
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2016-01-26 19:17:20 +01:00
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#include "qemu/osdep.h"
|
2019-08-12 07:23:42 +02:00
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|
#include "hw/irq.h"
|
2013-02-05 17:06:20 +01:00
|
|
|
#include "hw/sh4/sh.h"
|
2012-12-17 18:20:04 +01:00
|
|
|
#include "sysemu/sysemu.h"
|
2013-03-18 17:36:02 +01:00
|
|
|
#include "sh7750_regs.h"
|
|
|
|
#include "sh7750_regnames.h"
|
2013-02-05 17:06:20 +01:00
|
|
|
#include "hw/sh4/sh_intc.h"
|
2020-05-04 10:16:52 +02:00
|
|
|
#include "hw/timer/tmu012.h"
|
2016-03-15 13:18:37 +01:00
|
|
|
#include "exec/exec-all.h"
|
2006-04-27 23:32:09 +02:00
|
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|
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|
|
#define NB_DEVICES 4
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|
|
|
|
|
typedef struct SH7750State {
|
2011-11-17 14:22:58 +01:00
|
|
|
MemoryRegion iomem;
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|
|
MemoryRegion iomem_1f0;
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|
|
MemoryRegion iomem_ff0;
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MemoryRegion iomem_1f8;
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|
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MemoryRegion iomem_ff8;
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|
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MemoryRegion iomem_1fc;
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|
|
|
MemoryRegion iomem_ffc;
|
2011-11-17 14:22:59 +01:00
|
|
|
MemoryRegion mmct_iomem;
|
2006-04-27 23:32:09 +02:00
|
|
|
/* CPU */
|
2013-04-09 16:51:24 +02:00
|
|
|
SuperHCPU *cpu;
|
2006-04-27 23:32:09 +02:00
|
|
|
/* Peripheral frequency in Hz */
|
|
|
|
uint32_t periph_freq;
|
|
|
|
/* SDRAM controller */
|
2008-12-07 20:20:43 +01:00
|
|
|
uint32_t bcr1;
|
2009-02-07 16:18:14 +01:00
|
|
|
uint16_t bcr2;
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|
|
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uint16_t bcr3;
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|
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uint32_t bcr4;
|
2006-04-27 23:32:09 +02:00
|
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|
uint16_t rfcr;
|
2009-02-07 16:18:14 +01:00
|
|
|
/* PCMCIA controller */
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|
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uint16_t pcr;
|
2006-04-27 23:32:09 +02:00
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|
/* IO ports */
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|
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uint16_t gpioic;
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uint32_t pctra;
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|
|
uint32_t pctrb;
|
2021-10-29 23:02:09 +02:00
|
|
|
uint16_t portdira; /* Cached */
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|
|
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uint16_t portpullupa; /* Cached */
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|
|
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uint16_t portdirb; /* Cached */
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|
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|
uint16_t portpullupb; /* Cached */
|
2006-04-27 23:32:09 +02:00
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|
|
uint16_t pdtra;
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|
|
|
uint16_t pdtrb;
|
2021-10-29 23:02:09 +02:00
|
|
|
uint16_t periph_pdtra; /* Imposed by the peripherals */
|
|
|
|
uint16_t periph_portdira; /* Direction seen from the peripherals */
|
|
|
|
uint16_t periph_pdtrb; /* Imposed by the peripherals */
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|
|
|
uint16_t periph_portdirb; /* Direction seen from the peripherals */
|
|
|
|
sh7750_io_device *devices[NB_DEVICES]; /* External peripherals */
|
2007-09-29 21:47:44 +02:00
|
|
|
|
2006-04-27 23:32:09 +02:00
|
|
|
/* Cache */
|
|
|
|
uint32_t ccr;
|
|
|
|
|
2007-10-04 23:53:55 +02:00
|
|
|
struct intc_desc intc;
|
2007-09-29 21:40:09 +02:00
|
|
|
} SH7750State;
|
2006-04-27 23:32:09 +02:00
|
|
|
|
2021-10-29 23:02:09 +02:00
|
|
|
static inline int has_bcr3_and_bcr4(SH7750State *s)
|
2009-02-07 16:18:14 +01:00
|
|
|
{
|
2013-04-09 16:51:24 +02:00
|
|
|
return s->cpu->env.features & SH_FEATURE_BCR3_AND_BCR4;
|
2009-02-07 16:18:14 +01:00
|
|
|
}
|
2021-10-29 23:02:09 +02:00
|
|
|
|
|
|
|
/*
|
|
|
|
* I/O ports
|
|
|
|
*/
|
2006-04-27 23:32:09 +02:00
|
|
|
|
2021-10-29 23:02:09 +02:00
|
|
|
int sh7750_register_io_device(SH7750State *s, sh7750_io_device *device)
|
2006-04-27 23:32:09 +02:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < NB_DEVICES; i++) {
|
2021-10-29 23:02:09 +02:00
|
|
|
if (s->devices[i] == NULL) {
|
|
|
|
s->devices[i] = device;
|
|
|
|
return 0;
|
|
|
|
}
|
2006-04-27 23:32:09 +02:00
|
|
|
}
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
static uint16_t portdir(uint32_t v)
|
|
|
|
{
|
2021-10-29 23:02:09 +02:00
|
|
|
#define EVENPORTMASK(n) ((v & (1 << ((n) << 1))) >> (n))
|
2006-04-27 23:32:09 +02:00
|
|
|
return
|
2021-10-29 23:02:09 +02:00
|
|
|
EVENPORTMASK(15) | EVENPORTMASK(14) | EVENPORTMASK(13) |
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|
EVENPORTMASK(12) | EVENPORTMASK(11) | EVENPORTMASK(10) |
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|
EVENPORTMASK(9) | EVENPORTMASK(8) | EVENPORTMASK(7) |
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EVENPORTMASK(6) | EVENPORTMASK(5) | EVENPORTMASK(4) |
|
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|
|
EVENPORTMASK(3) | EVENPORTMASK(2) | EVENPORTMASK(1) |
|
|
|
|
EVENPORTMASK(0);
|
2006-04-27 23:32:09 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static uint16_t portpullup(uint32_t v)
|
|
|
|
{
|
2021-10-29 23:02:09 +02:00
|
|
|
#define ODDPORTMASK(n) ((v & (1 << (((n) << 1) + 1))) >> (n))
|
2006-04-27 23:32:09 +02:00
|
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|
return
|
2021-10-29 23:02:09 +02:00
|
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|
ODDPORTMASK(15) | ODDPORTMASK(14) | ODDPORTMASK(13) |
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|
ODDPORTMASK(12) | ODDPORTMASK(11) | ODDPORTMASK(10) |
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|
ODDPORTMASK(9) | ODDPORTMASK(8) | ODDPORTMASK(7) | ODDPORTMASK(6) |
|
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|
|
ODDPORTMASK(5) | ODDPORTMASK(4) | ODDPORTMASK(3) | ODDPORTMASK(2) |
|
|
|
|
ODDPORTMASK(1) | ODDPORTMASK(0);
|
2006-04-27 23:32:09 +02:00
|
|
|
}
|
|
|
|
|
2021-10-29 23:02:09 +02:00
|
|
|
static uint16_t porta_lines(SH7750State *s)
|
2006-04-27 23:32:09 +02:00
|
|
|
{
|
2021-10-29 23:02:09 +02:00
|
|
|
return (s->portdira & s->pdtra) | /* CPU */
|
|
|
|
(s->periph_portdira & s->periph_pdtra) | /* Peripherals */
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|
|
(~(s->portdira | s->periph_portdira) & s->portpullupa); /* Pullups */
|
2006-04-27 23:32:09 +02:00
|
|
|
}
|
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|
2021-10-29 23:02:09 +02:00
|
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|
static uint16_t portb_lines(SH7750State *s)
|
2006-04-27 23:32:09 +02:00
|
|
|
{
|
2021-10-29 23:02:09 +02:00
|
|
|
return (s->portdirb & s->pdtrb) | /* CPU */
|
|
|
|
(s->periph_portdirb & s->periph_pdtrb) | /* Peripherals */
|
|
|
|
(~(s->portdirb | s->periph_portdirb) & s->portpullupb); /* Pullups */
|
2006-04-27 23:32:09 +02:00
|
|
|
}
|
|
|
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|
2021-10-29 23:02:09 +02:00
|
|
|
static void gen_port_interrupts(SH7750State *s)
|
2006-04-27 23:32:09 +02:00
|
|
|
{
|
|
|
|
/* XXXXX interrupts not generated */
|
|
|
|
}
|
|
|
|
|
2021-10-29 23:02:09 +02:00
|
|
|
static void porta_changed(SH7750State *s, uint16_t prev)
|
2006-04-27 23:32:09 +02:00
|
|
|
{
|
|
|
|
uint16_t currenta, changes;
|
|
|
|
int i, r = 0;
|
|
|
|
|
|
|
|
#if 0
|
|
|
|
fprintf(stderr, "porta changed from 0x%04x to 0x%04x\n",
|
2021-10-29 23:02:09 +02:00
|
|
|
prev, porta_lines(s));
|
2006-04-27 23:32:09 +02:00
|
|
|
fprintf(stderr, "pdtra=0x%04x, pctra=0x%08x\n", s->pdtra, s->pctra);
|
|
|
|
#endif
|
|
|
|
currenta = porta_lines(s);
|
2021-10-29 23:02:09 +02:00
|
|
|
if (currenta == prev) {
|
2021-10-29 23:02:09 +02:00
|
|
|
return;
|
2021-10-29 23:02:09 +02:00
|
|
|
}
|
2006-04-27 23:32:09 +02:00
|
|
|
changes = currenta ^ prev;
|
|
|
|
|
|
|
|
for (i = 0; i < NB_DEVICES; i++) {
|
2021-10-29 23:02:09 +02:00
|
|
|
if (s->devices[i] && (s->devices[i]->portamask_trigger & changes)) {
|
|
|
|
r |= s->devices[i]->port_change_cb(currenta, portb_lines(s),
|
|
|
|
&s->periph_pdtra,
|
|
|
|
&s->periph_portdira,
|
|
|
|
&s->periph_pdtrb,
|
|
|
|
&s->periph_portdirb);
|
|
|
|
}
|
2006-04-27 23:32:09 +02:00
|
|
|
}
|
|
|
|
|
2021-10-29 23:02:09 +02:00
|
|
|
if (r) {
|
2021-10-29 23:02:09 +02:00
|
|
|
gen_port_interrupts(s);
|
2021-10-29 23:02:09 +02:00
|
|
|
}
|
2006-04-27 23:32:09 +02:00
|
|
|
}
|
|
|
|
|
2021-10-29 23:02:09 +02:00
|
|
|
static void portb_changed(SH7750State *s, uint16_t prev)
|
2006-04-27 23:32:09 +02:00
|
|
|
{
|
|
|
|
uint16_t currentb, changes;
|
|
|
|
int i, r = 0;
|
|
|
|
|
|
|
|
currentb = portb_lines(s);
|
2021-10-29 23:02:09 +02:00
|
|
|
if (currentb == prev) {
|
2021-10-29 23:02:09 +02:00
|
|
|
return;
|
2021-10-29 23:02:09 +02:00
|
|
|
}
|
2006-04-27 23:32:09 +02:00
|
|
|
changes = currentb ^ prev;
|
|
|
|
|
|
|
|
for (i = 0; i < NB_DEVICES; i++) {
|
2021-10-29 23:02:09 +02:00
|
|
|
if (s->devices[i] && (s->devices[i]->portbmask_trigger & changes)) {
|
|
|
|
r |= s->devices[i]->port_change_cb(portb_lines(s), currentb,
|
|
|
|
&s->periph_pdtra,
|
|
|
|
&s->periph_portdira,
|
|
|
|
&s->periph_pdtrb,
|
|
|
|
&s->periph_portdirb);
|
|
|
|
}
|
2006-04-27 23:32:09 +02:00
|
|
|
}
|
|
|
|
|
2021-10-29 23:02:09 +02:00
|
|
|
if (r) {
|
2021-10-29 23:02:09 +02:00
|
|
|
gen_port_interrupts(s);
|
2021-10-29 23:02:09 +02:00
|
|
|
}
|
2006-04-27 23:32:09 +02:00
|
|
|
}
|
|
|
|
|
2021-10-29 23:02:09 +02:00
|
|
|
/*
|
|
|
|
* Memory
|
|
|
|
*/
|
2006-04-27 23:32:09 +02:00
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static void error_access(const char *kind, hwaddr addr)
|
2006-04-27 23:32:09 +02:00
|
|
|
{
|
2008-07-16 14:13:52 +02:00
|
|
|
fprintf(stderr, "%s to %s (0x" TARGET_FMT_plx ") not supported\n",
|
2021-10-29 23:02:09 +02:00
|
|
|
kind, regname(addr), addr);
|
2006-04-27 23:32:09 +02:00
|
|
|
}
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static void ignore_access(const char *kind, hwaddr addr)
|
2006-04-27 23:32:09 +02:00
|
|
|
{
|
2008-07-16 14:13:52 +02:00
|
|
|
fprintf(stderr, "%s to %s (0x" TARGET_FMT_plx ") ignored\n",
|
2021-10-29 23:02:09 +02:00
|
|
|
kind, regname(addr), addr);
|
2006-04-27 23:32:09 +02:00
|
|
|
}
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static uint32_t sh7750_mem_readb(void *opaque, hwaddr addr)
|
2006-04-27 23:32:09 +02:00
|
|
|
{
|
|
|
|
switch (addr) {
|
|
|
|
default:
|
2021-10-29 23:02:09 +02:00
|
|
|
error_access("byte read", addr);
|
2010-03-18 19:41:57 +01:00
|
|
|
abort();
|
2006-04-27 23:32:09 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static uint32_t sh7750_mem_readw(void *opaque, hwaddr addr)
|
2006-04-27 23:32:09 +02:00
|
|
|
{
|
|
|
|
SH7750State *s = opaque;
|
|
|
|
|
|
|
|
switch (addr) {
|
2008-12-07 20:20:43 +01:00
|
|
|
case SH7750_BCR2_A7:
|
2021-10-29 23:02:09 +02:00
|
|
|
return s->bcr2;
|
2009-02-07 16:18:14 +01:00
|
|
|
case SH7750_BCR3_A7:
|
2021-10-29 23:02:09 +02:00
|
|
|
if (!has_bcr3_and_bcr4(s)) {
|
2021-10-29 23:02:09 +02:00
|
|
|
error_access("word read", addr);
|
2021-10-29 23:02:09 +02:00
|
|
|
}
|
2021-10-29 23:02:09 +02:00
|
|
|
return s->bcr3;
|
2007-09-29 21:51:40 +02:00
|
|
|
case SH7750_FRQCR_A7:
|
2021-10-29 23:02:09 +02:00
|
|
|
return 0;
|
2009-02-07 16:18:14 +01:00
|
|
|
case SH7750_PCR_A7:
|
2021-10-29 23:02:09 +02:00
|
|
|
return s->pcr;
|
2006-04-27 23:32:09 +02:00
|
|
|
case SH7750_RFCR_A7:
|
2021-10-29 23:02:09 +02:00
|
|
|
fprintf(stderr,
|
|
|
|
"Read access to refresh count register, incrementing\n");
|
|
|
|
return s->rfcr++;
|
2006-04-27 23:32:09 +02:00
|
|
|
case SH7750_PDTRA_A7:
|
2021-10-29 23:02:09 +02:00
|
|
|
return porta_lines(s);
|
2006-04-27 23:32:09 +02:00
|
|
|
case SH7750_PDTRB_A7:
|
2021-10-29 23:02:09 +02:00
|
|
|
return portb_lines(s);
|
2009-02-07 16:18:14 +01:00
|
|
|
case SH7750_RTCOR_A7:
|
|
|
|
case SH7750_RTCNT_A7:
|
|
|
|
case SH7750_RTCSR_A7:
|
2021-10-29 23:02:09 +02:00
|
|
|
ignore_access("word read", addr);
|
|
|
|
return 0;
|
2006-04-27 23:32:09 +02:00
|
|
|
default:
|
2021-10-29 23:02:09 +02:00
|
|
|
error_access("word read", addr);
|
2010-03-18 19:41:57 +01:00
|
|
|
abort();
|
2006-04-27 23:32:09 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static uint32_t sh7750_mem_readl(void *opaque, hwaddr addr)
|
2006-04-27 23:32:09 +02:00
|
|
|
{
|
|
|
|
SH7750State *s = opaque;
|
2012-11-20 16:15:47 +01:00
|
|
|
SuperHCPUClass *scc;
|
2006-04-27 23:32:09 +02:00
|
|
|
|
|
|
|
switch (addr) {
|
2008-12-07 20:20:43 +01:00
|
|
|
case SH7750_BCR1_A7:
|
2021-10-29 23:02:09 +02:00
|
|
|
return s->bcr1;
|
2008-12-07 20:20:43 +01:00
|
|
|
case SH7750_BCR4_A7:
|
2021-10-29 23:02:09 +02:00
|
|
|
if (!has_bcr3_and_bcr4(s)) {
|
2021-10-29 23:02:09 +02:00
|
|
|
error_access("long read", addr);
|
2021-10-29 23:02:09 +02:00
|
|
|
}
|
2021-10-29 23:02:09 +02:00
|
|
|
return s->bcr4;
|
2008-12-07 20:20:43 +01:00
|
|
|
case SH7750_WCR1_A7:
|
|
|
|
case SH7750_WCR2_A7:
|
|
|
|
case SH7750_WCR3_A7:
|
|
|
|
case SH7750_MCR_A7:
|
|
|
|
ignore_access("long read", addr);
|
|
|
|
return 0;
|
2006-04-27 23:32:09 +02:00
|
|
|
case SH7750_MMUCR_A7:
|
2013-04-09 16:51:24 +02:00
|
|
|
return s->cpu->env.mmucr;
|
2006-04-27 23:32:09 +02:00
|
|
|
case SH7750_PTEH_A7:
|
2013-04-09 16:51:24 +02:00
|
|
|
return s->cpu->env.pteh;
|
2006-04-27 23:32:09 +02:00
|
|
|
case SH7750_PTEL_A7:
|
2013-04-09 16:51:24 +02:00
|
|
|
return s->cpu->env.ptel;
|
2006-04-27 23:32:09 +02:00
|
|
|
case SH7750_TTB_A7:
|
2013-04-09 16:51:24 +02:00
|
|
|
return s->cpu->env.ttb;
|
2006-04-27 23:32:09 +02:00
|
|
|
case SH7750_TEA_A7:
|
2013-04-09 16:51:24 +02:00
|
|
|
return s->cpu->env.tea;
|
2006-04-27 23:32:09 +02:00
|
|
|
case SH7750_TRA_A7:
|
2013-04-09 16:51:24 +02:00
|
|
|
return s->cpu->env.tra;
|
2006-04-27 23:32:09 +02:00
|
|
|
case SH7750_EXPEVT_A7:
|
2013-04-09 16:51:24 +02:00
|
|
|
return s->cpu->env.expevt;
|
2006-04-27 23:32:09 +02:00
|
|
|
case SH7750_INTEVT_A7:
|
2013-04-09 16:51:24 +02:00
|
|
|
return s->cpu->env.intevt;
|
2006-04-27 23:32:09 +02:00
|
|
|
case SH7750_CCR_A7:
|
2021-10-29 23:02:09 +02:00
|
|
|
return s->ccr;
|
|
|
|
case 0x1f000030: /* Processor version */
|
2012-11-20 16:15:47 +01:00
|
|
|
scc = SUPERH_CPU_GET_CLASS(s->cpu);
|
|
|
|
return scc->pvr;
|
2021-10-29 23:02:09 +02:00
|
|
|
case 0x1f000040: /* Cache version */
|
2012-11-20 16:15:47 +01:00
|
|
|
scc = SUPERH_CPU_GET_CLASS(s->cpu);
|
|
|
|
return scc->cvr;
|
2021-10-29 23:02:09 +02:00
|
|
|
case 0x1f000044: /* Processor revision */
|
2012-11-20 16:15:47 +01:00
|
|
|
scc = SUPERH_CPU_GET_CLASS(s->cpu);
|
|
|
|
return scc->prr;
|
2006-04-27 23:32:09 +02:00
|
|
|
default:
|
2021-10-29 23:02:09 +02:00
|
|
|
error_access("long read", addr);
|
2010-03-18 19:41:57 +01:00
|
|
|
abort();
|
2006-04-27 23:32:09 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-02-07 16:18:14 +01:00
|
|
|
#define is_in_sdrmx(a, x) (a >= SH7750_SDMR ## x ## _A7 \
|
2021-10-29 23:02:09 +02:00
|
|
|
&& a <= (SH7750_SDMR ## x ## _A7 + SH7750_SDMR ## x ## _REGNB))
|
2012-10-23 12:30:10 +02:00
|
|
|
static void sh7750_mem_writeb(void *opaque, hwaddr addr,
|
2021-10-29 23:02:09 +02:00
|
|
|
uint32_t mem_value)
|
2006-04-27 23:32:09 +02:00
|
|
|
{
|
2009-02-07 16:18:14 +01:00
|
|
|
|
|
|
|
if (is_in_sdrmx(addr, 2) || is_in_sdrmx(addr, 3)) {
|
2021-10-29 23:02:09 +02:00
|
|
|
ignore_access("byte write", addr);
|
|
|
|
return;
|
2006-04-27 23:32:09 +02:00
|
|
|
}
|
2009-02-07 16:18:14 +01:00
|
|
|
|
|
|
|
error_access("byte write", addr);
|
2010-03-18 19:41:57 +01:00
|
|
|
abort();
|
2006-04-27 23:32:09 +02:00
|
|
|
}
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static void sh7750_mem_writew(void *opaque, hwaddr addr,
|
2021-10-29 23:02:09 +02:00
|
|
|
uint32_t mem_value)
|
2006-04-27 23:32:09 +02:00
|
|
|
{
|
|
|
|
SH7750State *s = opaque;
|
|
|
|
uint16_t temp;
|
|
|
|
|
|
|
|
switch (addr) {
|
2021-10-29 23:02:09 +02:00
|
|
|
/* SDRAM controller */
|
2006-04-27 23:32:09 +02:00
|
|
|
case SH7750_BCR2_A7:
|
2008-12-07 20:20:43 +01:00
|
|
|
s->bcr2 = mem_value;
|
|
|
|
return;
|
2006-04-27 23:32:09 +02:00
|
|
|
case SH7750_BCR3_A7:
|
2021-10-29 23:02:09 +02:00
|
|
|
if (!has_bcr3_and_bcr4(s)) {
|
2021-10-29 23:02:09 +02:00
|
|
|
error_access("word write", addr);
|
2021-10-29 23:02:09 +02:00
|
|
|
}
|
2021-10-29 23:02:09 +02:00
|
|
|
s->bcr3 = mem_value;
|
|
|
|
return;
|
2009-02-07 16:18:14 +01:00
|
|
|
case SH7750_PCR_A7:
|
2021-10-29 23:02:09 +02:00
|
|
|
s->pcr = mem_value;
|
|
|
|
return;
|
2006-04-27 23:32:09 +02:00
|
|
|
case SH7750_RTCNT_A7:
|
2009-02-07 16:18:14 +01:00
|
|
|
case SH7750_RTCOR_A7:
|
2006-04-27 23:32:09 +02:00
|
|
|
case SH7750_RTCSR_A7:
|
2021-10-29 23:02:09 +02:00
|
|
|
ignore_access("word write", addr);
|
|
|
|
return;
|
|
|
|
/* IO ports */
|
2006-04-27 23:32:09 +02:00
|
|
|
case SH7750_PDTRA_A7:
|
2021-10-29 23:02:09 +02:00
|
|
|
temp = porta_lines(s);
|
|
|
|
s->pdtra = mem_value;
|
|
|
|
porta_changed(s, temp);
|
|
|
|
return;
|
2006-04-27 23:32:09 +02:00
|
|
|
case SH7750_PDTRB_A7:
|
2021-10-29 23:02:09 +02:00
|
|
|
temp = portb_lines(s);
|
|
|
|
s->pdtrb = mem_value;
|
|
|
|
portb_changed(s, temp);
|
|
|
|
return;
|
2006-04-27 23:32:09 +02:00
|
|
|
case SH7750_RFCR_A7:
|
2021-10-29 23:02:09 +02:00
|
|
|
fprintf(stderr, "Write access to refresh count register\n");
|
|
|
|
s->rfcr = mem_value;
|
|
|
|
return;
|
2006-04-27 23:32:09 +02:00
|
|
|
case SH7750_GPIOIC_A7:
|
2021-10-29 23:02:09 +02:00
|
|
|
s->gpioic = mem_value;
|
|
|
|
if (mem_value != 0) {
|
|
|
|
fprintf(stderr, "I/O interrupts not implemented\n");
|
2010-03-18 19:41:57 +01:00
|
|
|
abort();
|
2021-10-29 23:02:09 +02:00
|
|
|
}
|
|
|
|
return;
|
2006-04-27 23:32:09 +02:00
|
|
|
default:
|
2021-10-29 23:02:09 +02:00
|
|
|
error_access("word write", addr);
|
2010-03-18 19:41:57 +01:00
|
|
|
abort();
|
2006-04-27 23:32:09 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static void sh7750_mem_writel(void *opaque, hwaddr addr,
|
2021-10-29 23:02:09 +02:00
|
|
|
uint32_t mem_value)
|
2006-04-27 23:32:09 +02:00
|
|
|
{
|
|
|
|
SH7750State *s = opaque;
|
|
|
|
uint16_t temp;
|
|
|
|
|
|
|
|
switch (addr) {
|
2021-10-29 23:02:09 +02:00
|
|
|
/* SDRAM controller */
|
2006-04-27 23:32:09 +02:00
|
|
|
case SH7750_BCR1_A7:
|
2008-12-07 20:20:43 +01:00
|
|
|
s->bcr1 = mem_value;
|
|
|
|
return;
|
2006-04-27 23:32:09 +02:00
|
|
|
case SH7750_BCR4_A7:
|
2021-10-29 23:02:09 +02:00
|
|
|
if (!has_bcr3_and_bcr4(s)) {
|
2021-10-29 23:02:09 +02:00
|
|
|
error_access("long write", addr);
|
2021-10-29 23:02:09 +02:00
|
|
|
}
|
2021-10-29 23:02:09 +02:00
|
|
|
s->bcr4 = mem_value;
|
|
|
|
return;
|
2006-04-27 23:32:09 +02:00
|
|
|
case SH7750_WCR1_A7:
|
|
|
|
case SH7750_WCR2_A7:
|
|
|
|
case SH7750_WCR3_A7:
|
|
|
|
case SH7750_MCR_A7:
|
2021-10-29 23:02:09 +02:00
|
|
|
ignore_access("long write", addr);
|
|
|
|
return;
|
|
|
|
/* IO ports */
|
2006-04-27 23:32:09 +02:00
|
|
|
case SH7750_PCTRA_A7:
|
2021-10-29 23:02:09 +02:00
|
|
|
temp = porta_lines(s);
|
|
|
|
s->pctra = mem_value;
|
|
|
|
s->portdira = portdir(mem_value);
|
|
|
|
s->portpullupa = portpullup(mem_value);
|
|
|
|
porta_changed(s, temp);
|
|
|
|
return;
|
2006-04-27 23:32:09 +02:00
|
|
|
case SH7750_PCTRB_A7:
|
2021-10-29 23:02:09 +02:00
|
|
|
temp = portb_lines(s);
|
|
|
|
s->pctrb = mem_value;
|
|
|
|
s->portdirb = portdir(mem_value);
|
|
|
|
s->portpullupb = portpullup(mem_value);
|
|
|
|
portb_changed(s, temp);
|
|
|
|
return;
|
2006-04-27 23:32:09 +02:00
|
|
|
case SH7750_MMUCR_A7:
|
2010-02-02 19:39:11 +01:00
|
|
|
if (mem_value & MMUCR_TI) {
|
2013-04-09 16:51:24 +02:00
|
|
|
cpu_sh4_invalidate_tlb(&s->cpu->env);
|
2010-02-02 19:39:11 +01:00
|
|
|
}
|
2013-04-09 16:51:24 +02:00
|
|
|
s->cpu->env.mmucr = mem_value & ~MMUCR_TI;
|
2010-02-02 19:39:11 +01:00
|
|
|
return;
|
2006-04-27 23:32:09 +02:00
|
|
|
case SH7750_PTEH_A7:
|
2008-08-22 10:57:52 +02:00
|
|
|
/* If asid changes, clear all registered tlb entries. */
|
2013-04-09 16:51:24 +02:00
|
|
|
if ((s->cpu->env.pteh & 0xff) != (mem_value & 0xff)) {
|
2016-11-14 15:17:28 +01:00
|
|
|
tlb_flush(CPU(s->cpu));
|
2013-04-09 16:51:24 +02:00
|
|
|
}
|
|
|
|
s->cpu->env.pteh = mem_value;
|
|
|
|
return;
|
2006-04-27 23:32:09 +02:00
|
|
|
case SH7750_PTEL_A7:
|
2013-04-09 16:51:24 +02:00
|
|
|
s->cpu->env.ptel = mem_value;
|
|
|
|
return;
|
2008-05-09 20:45:55 +02:00
|
|
|
case SH7750_PTEA_A7:
|
2013-04-09 16:51:24 +02:00
|
|
|
s->cpu->env.ptea = mem_value & 0x0000000f;
|
|
|
|
return;
|
2006-04-27 23:32:09 +02:00
|
|
|
case SH7750_TTB_A7:
|
2013-04-09 16:51:24 +02:00
|
|
|
s->cpu->env.ttb = mem_value;
|
|
|
|
return;
|
2006-04-27 23:32:09 +02:00
|
|
|
case SH7750_TEA_A7:
|
2013-04-09 16:51:24 +02:00
|
|
|
s->cpu->env.tea = mem_value;
|
|
|
|
return;
|
2006-04-27 23:32:09 +02:00
|
|
|
case SH7750_TRA_A7:
|
2013-04-09 16:51:24 +02:00
|
|
|
s->cpu->env.tra = mem_value & 0x000007ff;
|
|
|
|
return;
|
2006-04-27 23:32:09 +02:00
|
|
|
case SH7750_EXPEVT_A7:
|
2013-04-09 16:51:24 +02:00
|
|
|
s->cpu->env.expevt = mem_value & 0x000007ff;
|
|
|
|
return;
|
2006-04-27 23:32:09 +02:00
|
|
|
case SH7750_INTEVT_A7:
|
2013-04-09 16:51:24 +02:00
|
|
|
s->cpu->env.intevt = mem_value & 0x000007ff;
|
|
|
|
return;
|
2006-04-27 23:32:09 +02:00
|
|
|
case SH7750_CCR_A7:
|
2021-10-29 23:02:09 +02:00
|
|
|
s->ccr = mem_value;
|
|
|
|
return;
|
2006-04-27 23:32:09 +02:00
|
|
|
default:
|
2021-10-29 23:02:09 +02:00
|
|
|
error_access("long write", addr);
|
2010-03-18 19:41:57 +01:00
|
|
|
abort();
|
2006-04-27 23:32:09 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-06-15 15:57:13 +02:00
|
|
|
static uint64_t sh7750_mem_readfn(void *opaque, hwaddr addr, unsigned size)
|
|
|
|
{
|
|
|
|
switch (size) {
|
|
|
|
case 1:
|
|
|
|
return sh7750_mem_readb(opaque, addr);
|
|
|
|
case 2:
|
|
|
|
return sh7750_mem_readw(opaque, addr);
|
|
|
|
case 4:
|
|
|
|
return sh7750_mem_readl(opaque, addr);
|
|
|
|
default:
|
|
|
|
g_assert_not_reached();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void sh7750_mem_writefn(void *opaque, hwaddr addr,
|
|
|
|
uint64_t value, unsigned size)
|
|
|
|
{
|
|
|
|
switch (size) {
|
|
|
|
case 1:
|
|
|
|
sh7750_mem_writeb(opaque, addr, value);
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
sh7750_mem_writew(opaque, addr, value);
|
|
|
|
break;
|
|
|
|
case 4:
|
|
|
|
sh7750_mem_writel(opaque, addr, value);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
g_assert_not_reached();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-11-17 14:22:58 +01:00
|
|
|
static const MemoryRegionOps sh7750_mem_ops = {
|
2018-06-15 15:57:13 +02:00
|
|
|
.read = sh7750_mem_readfn,
|
|
|
|
.write = sh7750_mem_writefn,
|
|
|
|
.valid.min_access_size = 1,
|
|
|
|
.valid.max_access_size = 4,
|
2011-11-17 14:22:58 +01:00
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
2006-04-27 23:32:09 +02:00
|
|
|
};
|
|
|
|
|
2021-10-29 23:02:09 +02:00
|
|
|
/*
|
|
|
|
* sh775x interrupt controller tables for sh_intc.c
|
2007-10-04 23:53:55 +02:00
|
|
|
* stolen from linux/arch/sh/kernel/cpu/sh4/setup-sh7750.c
|
|
|
|
*/
|
|
|
|
|
|
|
|
enum {
|
2021-10-29 23:02:09 +02:00
|
|
|
UNUSED = 0,
|
|
|
|
|
|
|
|
/* interrupt sources */
|
|
|
|
IRL_0, IRL_1, IRL_2, IRL_3, IRL_4, IRL_5, IRL_6, IRL_7,
|
|
|
|
IRL_8, IRL_9, IRL_A, IRL_B, IRL_C, IRL_D, IRL_E,
|
|
|
|
IRL0, IRL1, IRL2, IRL3,
|
|
|
|
HUDI, GPIOI,
|
|
|
|
DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, DMAC_DMTE3,
|
|
|
|
DMAC_DMTE4, DMAC_DMTE5, DMAC_DMTE6, DMAC_DMTE7,
|
|
|
|
DMAC_DMAE,
|
|
|
|
PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
|
|
|
|
PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3,
|
|
|
|
TMU3, TMU4, TMU0, TMU1, TMU2_TUNI, TMU2_TICPI,
|
|
|
|
RTC_ATI, RTC_PRI, RTC_CUI,
|
|
|
|
SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI,
|
|
|
|
SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI,
|
|
|
|
WDT,
|
|
|
|
REF_RCMI, REF_ROVI,
|
|
|
|
|
|
|
|
/* interrupt groups */
|
|
|
|
DMAC, PCIC1, TMU2, RTC, SCI1, SCIF, REF,
|
|
|
|
/* irl bundle */
|
|
|
|
IRL,
|
|
|
|
|
|
|
|
NR_SOURCES,
|
2007-10-04 23:53:55 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct intc_vect vectors[] = {
|
2021-10-29 23:02:09 +02:00
|
|
|
INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
|
|
|
|
INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
|
|
|
|
INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460),
|
|
|
|
INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0),
|
|
|
|
INTC_VECT(RTC_CUI, 0x4c0),
|
|
|
|
INTC_VECT(SCI1_ERI, 0x4e0), INTC_VECT(SCI1_RXI, 0x500),
|
|
|
|
INTC_VECT(SCI1_TXI, 0x520), INTC_VECT(SCI1_TEI, 0x540),
|
|
|
|
INTC_VECT(SCIF_ERI, 0x700), INTC_VECT(SCIF_RXI, 0x720),
|
|
|
|
INTC_VECT(SCIF_BRI, 0x740), INTC_VECT(SCIF_TXI, 0x760),
|
|
|
|
INTC_VECT(WDT, 0x560),
|
|
|
|
INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0),
|
2007-10-04 23:53:55 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct intc_group groups[] = {
|
2021-10-29 23:02:09 +02:00
|
|
|
INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI),
|
|
|
|
INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
|
|
|
|
INTC_GROUP(SCI1, SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI),
|
|
|
|
INTC_GROUP(SCIF, SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI),
|
|
|
|
INTC_GROUP(REF, REF_RCMI, REF_ROVI),
|
2007-10-04 23:53:55 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct intc_prio_reg prio_registers[] = {
|
2021-10-29 23:02:09 +02:00
|
|
|
{ 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
|
|
|
|
{ 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } },
|
|
|
|
{ 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } },
|
|
|
|
{ 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
|
|
|
|
{ 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0, TMU4, TMU3,
|
|
|
|
PCIC1, PCIC0_PCISERR } },
|
2007-10-04 23:53:55 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
/* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */
|
|
|
|
|
|
|
|
static struct intc_vect vectors_dma4[] = {
|
2021-10-29 23:02:09 +02:00
|
|
|
INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
|
|
|
|
INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
|
|
|
|
INTC_VECT(DMAC_DMAE, 0x6c0),
|
2007-10-04 23:53:55 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct intc_group groups_dma4[] = {
|
2021-10-29 23:02:09 +02:00
|
|
|
INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
|
|
|
|
DMAC_DMTE3, DMAC_DMAE),
|
2007-10-04 23:53:55 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
/* SH7750R and SH7751R both have 8-channel DMA controllers */
|
|
|
|
|
|
|
|
static struct intc_vect vectors_dma8[] = {
|
2021-10-29 23:02:09 +02:00
|
|
|
INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
|
|
|
|
INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
|
|
|
|
INTC_VECT(DMAC_DMTE4, 0x780), INTC_VECT(DMAC_DMTE5, 0x7a0),
|
|
|
|
INTC_VECT(DMAC_DMTE6, 0x7c0), INTC_VECT(DMAC_DMTE7, 0x7e0),
|
|
|
|
INTC_VECT(DMAC_DMAE, 0x6c0),
|
2007-10-04 23:53:55 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct intc_group groups_dma8[] = {
|
2021-10-29 23:02:09 +02:00
|
|
|
INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
|
|
|
|
DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5,
|
|
|
|
DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE),
|
2007-10-04 23:53:55 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
/* SH7750R, SH7751 and SH7751R all have two extra timer channels */
|
|
|
|
|
|
|
|
static struct intc_vect vectors_tmu34[] = {
|
2021-10-29 23:02:09 +02:00
|
|
|
INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80),
|
2007-10-04 23:53:55 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct intc_mask_reg mask_registers[] = {
|
2021-10-29 23:02:09 +02:00
|
|
|
{ 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
|
|
|
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
|
|
0, 0, 0, 0, 0, 0, TMU4, TMU3,
|
|
|
|
PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
|
|
|
|
PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2,
|
|
|
|
PCIC1_PCIDMA3, PCIC0_PCISERR } },
|
2007-10-04 23:53:55 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
/* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */
|
|
|
|
|
|
|
|
static struct intc_vect vectors_irlm[] = {
|
2021-10-29 23:02:09 +02:00
|
|
|
INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
|
|
|
|
INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
|
2007-10-04 23:53:55 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
/* SH7751 and SH7751R both have PCI */
|
|
|
|
|
|
|
|
static struct intc_vect vectors_pci[] = {
|
2021-10-29 23:02:09 +02:00
|
|
|
INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0),
|
|
|
|
INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0),
|
|
|
|
INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60),
|
|
|
|
INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20),
|
2007-10-04 23:53:55 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct intc_group groups_pci[] = {
|
2021-10-29 23:02:09 +02:00
|
|
|
INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
|
|
|
|
PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3),
|
2007-10-04 23:53:55 +02:00
|
|
|
};
|
|
|
|
|
2008-12-07 19:49:57 +01:00
|
|
|
static struct intc_vect vectors_irl[] = {
|
2021-10-29 23:02:09 +02:00
|
|
|
INTC_VECT(IRL_0, 0x200),
|
|
|
|
INTC_VECT(IRL_1, 0x220),
|
|
|
|
INTC_VECT(IRL_2, 0x240),
|
|
|
|
INTC_VECT(IRL_3, 0x260),
|
|
|
|
INTC_VECT(IRL_4, 0x280),
|
|
|
|
INTC_VECT(IRL_5, 0x2a0),
|
|
|
|
INTC_VECT(IRL_6, 0x2c0),
|
|
|
|
INTC_VECT(IRL_7, 0x2e0),
|
|
|
|
INTC_VECT(IRL_8, 0x300),
|
|
|
|
INTC_VECT(IRL_9, 0x320),
|
|
|
|
INTC_VECT(IRL_A, 0x340),
|
|
|
|
INTC_VECT(IRL_B, 0x360),
|
|
|
|
INTC_VECT(IRL_C, 0x380),
|
|
|
|
INTC_VECT(IRL_D, 0x3a0),
|
|
|
|
INTC_VECT(IRL_E, 0x3c0),
|
2008-12-07 19:49:57 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct intc_group groups_irl[] = {
|
2021-10-29 23:02:09 +02:00
|
|
|
INTC_GROUP(IRL, IRL_0, IRL_1, IRL_2, IRL_3, IRL_4, IRL_5, IRL_6,
|
|
|
|
IRL_7, IRL_8, IRL_9, IRL_A, IRL_B, IRL_C, IRL_D, IRL_E),
|
2008-12-07 19:49:57 +01:00
|
|
|
};
|
|
|
|
|
2021-10-29 23:02:09 +02:00
|
|
|
/*
|
|
|
|
* Memory mapped cache and TLB
|
|
|
|
*/
|
2008-08-22 10:57:43 +02:00
|
|
|
|
|
|
|
#define MM_REGION_MASK 0x07000000
|
|
|
|
#define MM_ICACHE_ADDR (0)
|
|
|
|
#define MM_ICACHE_DATA (1)
|
|
|
|
#define MM_ITLB_ADDR (2)
|
|
|
|
#define MM_ITLB_DATA (3)
|
|
|
|
#define MM_OCACHE_ADDR (4)
|
|
|
|
#define MM_OCACHE_DATA (5)
|
|
|
|
#define MM_UTLB_ADDR (6)
|
|
|
|
#define MM_UTLB_DATA (7)
|
|
|
|
#define MM_REGION_TYPE(addr) ((addr & MM_REGION_MASK) >> 24)
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static uint64_t invalid_read(void *opaque, hwaddr addr)
|
2008-08-22 10:57:43 +02:00
|
|
|
{
|
2010-03-18 19:41:57 +01:00
|
|
|
abort();
|
2008-08-22 10:57:43 +02:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static uint64_t sh7750_mmct_read(void *opaque, hwaddr addr,
|
2011-11-17 14:22:59 +01:00
|
|
|
unsigned size)
|
2008-08-22 10:57:43 +02:00
|
|
|
{
|
2011-01-26 02:16:39 +01:00
|
|
|
SH7750State *s = opaque;
|
2008-08-22 10:57:43 +02:00
|
|
|
uint32_t ret = 0;
|
|
|
|
|
2011-11-17 14:22:59 +01:00
|
|
|
if (size != 4) {
|
|
|
|
return invalid_read(opaque, addr);
|
|
|
|
}
|
|
|
|
|
2008-08-22 10:57:43 +02:00
|
|
|
switch (MM_REGION_TYPE(addr)) {
|
|
|
|
case MM_ICACHE_ADDR:
|
|
|
|
case MM_ICACHE_DATA:
|
|
|
|
/* do nothing */
|
2021-10-29 23:02:09 +02:00
|
|
|
break;
|
2008-08-22 10:57:43 +02:00
|
|
|
case MM_ITLB_ADDR:
|
2013-04-09 16:51:24 +02:00
|
|
|
ret = cpu_sh4_read_mmaped_itlb_addr(&s->cpu->env, addr);
|
2011-01-26 02:16:39 +01:00
|
|
|
break;
|
2008-08-22 10:57:43 +02:00
|
|
|
case MM_ITLB_DATA:
|
2013-04-09 16:51:24 +02:00
|
|
|
ret = cpu_sh4_read_mmaped_itlb_data(&s->cpu->env, addr);
|
2011-01-26 02:16:39 +01:00
|
|
|
break;
|
2008-08-22 10:57:43 +02:00
|
|
|
case MM_OCACHE_ADDR:
|
|
|
|
case MM_OCACHE_DATA:
|
|
|
|
/* do nothing */
|
2021-10-29 23:02:09 +02:00
|
|
|
break;
|
2008-08-22 10:57:43 +02:00
|
|
|
case MM_UTLB_ADDR:
|
2013-04-09 16:51:24 +02:00
|
|
|
ret = cpu_sh4_read_mmaped_utlb_addr(&s->cpu->env, addr);
|
2011-01-26 02:16:39 +01:00
|
|
|
break;
|
2008-08-22 10:57:43 +02:00
|
|
|
case MM_UTLB_DATA:
|
2013-04-09 16:51:24 +02:00
|
|
|
ret = cpu_sh4_read_mmaped_utlb_data(&s->cpu->env, addr);
|
2011-01-26 02:16:39 +01:00
|
|
|
break;
|
2008-08-22 10:57:43 +02:00
|
|
|
default:
|
2010-03-18 19:41:57 +01:00
|
|
|
abort();
|
2008-08-22 10:57:43 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static void invalid_write(void *opaque, hwaddr addr,
|
2011-11-17 14:22:59 +01:00
|
|
|
uint64_t mem_value)
|
2008-08-22 10:57:43 +02:00
|
|
|
{
|
2010-03-18 19:41:57 +01:00
|
|
|
abort();
|
2008-08-22 10:57:43 +02:00
|
|
|
}
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static void sh7750_mmct_write(void *opaque, hwaddr addr,
|
2011-11-17 14:22:59 +01:00
|
|
|
uint64_t mem_value, unsigned size)
|
2008-08-22 10:57:43 +02:00
|
|
|
{
|
|
|
|
SH7750State *s = opaque;
|
|
|
|
|
2011-11-17 14:22:59 +01:00
|
|
|
if (size != 4) {
|
|
|
|
invalid_write(opaque, addr, mem_value);
|
|
|
|
}
|
|
|
|
|
2008-08-22 10:57:43 +02:00
|
|
|
switch (MM_REGION_TYPE(addr)) {
|
|
|
|
case MM_ICACHE_ADDR:
|
|
|
|
case MM_ICACHE_DATA:
|
|
|
|
/* do nothing */
|
2021-10-29 23:02:09 +02:00
|
|
|
break;
|
2008-08-22 10:57:43 +02:00
|
|
|
case MM_ITLB_ADDR:
|
2013-04-09 16:51:24 +02:00
|
|
|
cpu_sh4_write_mmaped_itlb_addr(&s->cpu->env, addr, mem_value);
|
2011-01-09 23:53:45 +01:00
|
|
|
break;
|
2008-08-22 10:57:43 +02:00
|
|
|
case MM_ITLB_DATA:
|
2013-04-09 16:51:24 +02:00
|
|
|
cpu_sh4_write_mmaped_itlb_data(&s->cpu->env, addr, mem_value);
|
2010-03-18 19:41:57 +01:00
|
|
|
abort();
|
2021-10-29 23:02:09 +02:00
|
|
|
break;
|
2008-08-22 10:57:43 +02:00
|
|
|
case MM_OCACHE_ADDR:
|
|
|
|
case MM_OCACHE_DATA:
|
|
|
|
/* do nothing */
|
2021-10-29 23:02:09 +02:00
|
|
|
break;
|
2008-08-22 10:57:43 +02:00
|
|
|
case MM_UTLB_ADDR:
|
2013-04-09 16:51:24 +02:00
|
|
|
cpu_sh4_write_mmaped_utlb_addr(&s->cpu->env, addr, mem_value);
|
2021-10-29 23:02:09 +02:00
|
|
|
break;
|
2008-08-22 10:57:43 +02:00
|
|
|
case MM_UTLB_DATA:
|
2013-04-09 16:51:24 +02:00
|
|
|
cpu_sh4_write_mmaped_utlb_data(&s->cpu->env, addr, mem_value);
|
2021-10-29 23:02:09 +02:00
|
|
|
break;
|
2008-08-22 10:57:43 +02:00
|
|
|
default:
|
2010-03-18 19:41:57 +01:00
|
|
|
abort();
|
2021-10-29 23:02:09 +02:00
|
|
|
break;
|
2008-08-22 10:57:43 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-02-25 13:37:13 +01:00
|
|
|
static const MemoryRegionOps sh7750_mmct_ops = {
|
2011-11-17 14:22:59 +01:00
|
|
|
.read = sh7750_mmct_read,
|
|
|
|
.write = sh7750_mmct_write,
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
2008-08-22 10:57:43 +02:00
|
|
|
};
|
|
|
|
|
2013-04-09 16:51:24 +02:00
|
|
|
SH7750State *sh7750_init(SuperHCPU *cpu, MemoryRegion *sysmem)
|
2006-04-27 23:32:09 +02:00
|
|
|
{
|
|
|
|
SH7750State *s;
|
|
|
|
|
2011-08-21 05:09:37 +02:00
|
|
|
s = g_malloc0(sizeof(SH7750State));
|
2006-04-27 23:32:09 +02:00
|
|
|
s->cpu = cpu;
|
2021-10-29 23:02:09 +02:00
|
|
|
s->periph_freq = 60000000; /* 60MHz */
|
2013-06-06 11:41:28 +02:00
|
|
|
memory_region_init_io(&s->iomem, NULL, &sh7750_mem_ops, s,
|
2011-11-17 14:22:58 +01:00
|
|
|
"memory", 0x1fc01000);
|
|
|
|
|
2013-06-06 11:41:28 +02:00
|
|
|
memory_region_init_alias(&s->iomem_1f0, NULL, "memory-1f0",
|
2011-11-17 14:22:58 +01:00
|
|
|
&s->iomem, 0x1f000000, 0x1000);
|
|
|
|
memory_region_add_subregion(sysmem, 0x1f000000, &s->iomem_1f0);
|
|
|
|
|
2013-06-06 11:41:28 +02:00
|
|
|
memory_region_init_alias(&s->iomem_ff0, NULL, "memory-ff0",
|
2011-11-17 14:22:58 +01:00
|
|
|
&s->iomem, 0x1f000000, 0x1000);
|
|
|
|
memory_region_add_subregion(sysmem, 0xff000000, &s->iomem_ff0);
|
|
|
|
|
2013-06-06 11:41:28 +02:00
|
|
|
memory_region_init_alias(&s->iomem_1f8, NULL, "memory-1f8",
|
2011-11-17 14:22:58 +01:00
|
|
|
&s->iomem, 0x1f800000, 0x1000);
|
|
|
|
memory_region_add_subregion(sysmem, 0x1f800000, &s->iomem_1f8);
|
|
|
|
|
2013-06-06 11:41:28 +02:00
|
|
|
memory_region_init_alias(&s->iomem_ff8, NULL, "memory-ff8",
|
2011-11-17 14:22:58 +01:00
|
|
|
&s->iomem, 0x1f800000, 0x1000);
|
|
|
|
memory_region_add_subregion(sysmem, 0xff800000, &s->iomem_ff8);
|
|
|
|
|
2013-06-06 11:41:28 +02:00
|
|
|
memory_region_init_alias(&s->iomem_1fc, NULL, "memory-1fc",
|
2011-11-17 14:22:58 +01:00
|
|
|
&s->iomem, 0x1fc00000, 0x1000);
|
|
|
|
memory_region_add_subregion(sysmem, 0x1fc00000, &s->iomem_1fc);
|
|
|
|
|
2013-06-06 11:41:28 +02:00
|
|
|
memory_region_init_alias(&s->iomem_ffc, NULL, "memory-ffc",
|
2011-11-17 14:22:58 +01:00
|
|
|
&s->iomem, 0x1fc00000, 0x1000);
|
|
|
|
memory_region_add_subregion(sysmem, 0xffc00000, &s->iomem_ffc);
|
2007-09-29 21:43:54 +02:00
|
|
|
|
2013-06-06 11:41:28 +02:00
|
|
|
memory_region_init_io(&s->mmct_iomem, NULL, &sh7750_mmct_ops, s,
|
2011-11-17 14:22:59 +01:00
|
|
|
"cache-and-tlb", 0x08000000);
|
|
|
|
memory_region_add_subregion(sysmem, 0xf0000000, &s->mmct_iomem);
|
2008-08-22 10:57:43 +02:00
|
|
|
|
2011-11-17 14:23:01 +01:00
|
|
|
sh_intc_init(sysmem, &s->intc, NR_SOURCES,
|
2021-10-29 23:02:09 +02:00
|
|
|
_INTC_ARRAY(mask_registers),
|
|
|
|
_INTC_ARRAY(prio_registers));
|
2007-10-04 23:53:55 +02:00
|
|
|
|
2008-09-02 18:18:28 +02:00
|
|
|
sh_intc_register_sources(&s->intc,
|
2021-10-29 23:02:09 +02:00
|
|
|
_INTC_ARRAY(vectors),
|
|
|
|
_INTC_ARRAY(groups));
|
2007-10-04 23:53:55 +02:00
|
|
|
|
2013-04-09 16:51:24 +02:00
|
|
|
cpu->env.intc_handle = &s->intc;
|
2007-12-02 07:18:24 +01:00
|
|
|
|
2011-11-17 14:23:02 +01:00
|
|
|
sh_serial_init(sysmem, 0x1fe00000,
|
2018-04-20 16:52:43 +02:00
|
|
|
0, s->periph_freq, serial_hd(0),
|
2011-11-17 14:23:02 +01:00
|
|
|
s->intc.irqs[SCI1_ERI],
|
|
|
|
s->intc.irqs[SCI1_RXI],
|
|
|
|
s->intc.irqs[SCI1_TXI],
|
|
|
|
s->intc.irqs[SCI1_TEI],
|
|
|
|
NULL);
|
|
|
|
sh_serial_init(sysmem, 0x1fe80000,
|
|
|
|
SH_SERIAL_FEAT_SCIF,
|
2018-04-20 16:52:43 +02:00
|
|
|
s->periph_freq, serial_hd(1),
|
2011-11-17 14:23:02 +01:00
|
|
|
s->intc.irqs[SCIF_ERI],
|
|
|
|
s->intc.irqs[SCIF_RXI],
|
|
|
|
s->intc.irqs[SCIF_TXI],
|
|
|
|
NULL,
|
|
|
|
s->intc.irqs[SCIF_BRI]);
|
2007-09-29 21:40:09 +02:00
|
|
|
|
2011-11-17 14:23:00 +01:00
|
|
|
tmu012_init(sysmem, 0x1fd80000,
|
2021-10-29 23:02:09 +02:00
|
|
|
TMU012_FEAT_TOCR | TMU012_FEAT_3CHAN | TMU012_FEAT_EXTCLK,
|
|
|
|
s->periph_freq,
|
|
|
|
s->intc.irqs[TMU0],
|
|
|
|
s->intc.irqs[TMU1],
|
|
|
|
s->intc.irqs[TMU2_TUNI],
|
|
|
|
s->intc.irqs[TMU2_TICPI]);
|
2007-10-04 23:53:55 +02:00
|
|
|
|
2013-04-09 16:51:24 +02:00
|
|
|
if (cpu->env.id & (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7751)) {
|
2008-09-02 18:18:28 +02:00
|
|
|
sh_intc_register_sources(&s->intc,
|
2021-10-29 23:02:09 +02:00
|
|
|
_INTC_ARRAY(vectors_dma4),
|
|
|
|
_INTC_ARRAY(groups_dma4));
|
2007-10-04 23:53:55 +02:00
|
|
|
}
|
|
|
|
|
2013-04-09 16:51:24 +02:00
|
|
|
if (cpu->env.id & (SH_CPU_SH7750R | SH_CPU_SH7751R)) {
|
2008-09-02 18:18:28 +02:00
|
|
|
sh_intc_register_sources(&s->intc,
|
2021-10-29 23:02:09 +02:00
|
|
|
_INTC_ARRAY(vectors_dma8),
|
|
|
|
_INTC_ARRAY(groups_dma8));
|
2007-10-04 23:53:55 +02:00
|
|
|
}
|
|
|
|
|
2013-04-09 16:51:24 +02:00
|
|
|
if (cpu->env.id & (SH_CPU_SH7750R | SH_CPU_SH7751 | SH_CPU_SH7751R)) {
|
2008-09-02 18:18:28 +02:00
|
|
|
sh_intc_register_sources(&s->intc,
|
2021-10-29 23:02:09 +02:00
|
|
|
_INTC_ARRAY(vectors_tmu34),
|
|
|
|
NULL, 0);
|
2011-11-17 14:23:00 +01:00
|
|
|
tmu012_init(sysmem, 0x1e100000, 0, s->periph_freq,
|
2021-10-29 23:02:09 +02:00
|
|
|
s->intc.irqs[TMU3],
|
|
|
|
s->intc.irqs[TMU4],
|
|
|
|
NULL, NULL);
|
2007-10-04 23:53:55 +02:00
|
|
|
}
|
|
|
|
|
2013-04-09 16:51:24 +02:00
|
|
|
if (cpu->env.id & (SH_CPU_SH7751_ALL)) {
|
2008-09-02 18:18:28 +02:00
|
|
|
sh_intc_register_sources(&s->intc,
|
2021-10-29 23:02:09 +02:00
|
|
|
_INTC_ARRAY(vectors_pci),
|
|
|
|
_INTC_ARRAY(groups_pci));
|
2007-10-04 23:53:55 +02:00
|
|
|
}
|
|
|
|
|
2013-04-09 16:51:24 +02:00
|
|
|
if (cpu->env.id & (SH_CPU_SH7750S | SH_CPU_SH7750R | SH_CPU_SH7751_ALL)) {
|
2008-09-02 18:18:28 +02:00
|
|
|
sh_intc_register_sources(&s->intc,
|
2021-10-29 23:02:09 +02:00
|
|
|
_INTC_ARRAY(vectors_irlm),
|
|
|
|
NULL, 0);
|
2007-10-04 23:53:55 +02:00
|
|
|
}
|
|
|
|
|
2008-12-07 19:49:57 +01:00
|
|
|
sh_intc_register_sources(&s->intc,
|
2021-10-29 23:02:09 +02:00
|
|
|
_INTC_ARRAY(vectors_irl),
|
|
|
|
_INTC_ARRAY(groups_irl));
|
2006-04-27 23:32:09 +02:00
|
|
|
return s;
|
|
|
|
}
|
2008-12-07 19:49:57 +01:00
|
|
|
|
|
|
|
qemu_irq sh7750_irl(SH7750State *s)
|
|
|
|
{
|
|
|
|
sh_intc_toggle_source(sh_intc_source(&s->intc, IRL), 1, 0); /* enable */
|
2014-06-18 09:55:18 +02:00
|
|
|
return qemu_allocate_irq(sh_intc_set_irl, sh_intc_source(&s->intc, IRL), 0);
|
2008-12-07 19:49:57 +01:00
|
|
|
}
|