Commit Graph

198 Commits

Author SHA1 Message Date
Alexandre Courbot e3f114f761 target-sh4: update PTEH upon MMU exception
Update the PTEH register to contain the VPN at which an MMU
exception occured as specified by the SH4 reference.

Signed-off-by: Alexandre Courbot <gnurou@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-26 14:30:24 +01:00
Aurelien Jarno bc656a2968 sh4: implement missing mmaped TLB read functions
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-26 14:30:24 +01:00
Aurelien Jarno 9f97309a70 sh4: implement missing mmaped TLB write functions
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-26 14:30:24 +01:00
Alexandre Courbot bec43cc3b6 target-sh4: fix index of address read error exception
Exception index of address read error should be 0x0e0.

Signed-off-by: Alexandre Courbot <gnurou@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-25 08:36:30 +01:00
Alexandre Courbot e40a67beed target-sh4: fix TLB invalidation code
In cpu_sh4_invalidate_tlb, the UTLB was invalidated twice and the
ITLB left unchaged, probably because of some unfortunate copy/paste.

Signed-off-by: Alexandre Courbot <gnurou@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-25 08:36:29 +01:00
Aurelien Jarno b2d9eda5d4 target-sh4: implement negc using TCG
Using setcond it's now possible to generate a relatively short negc
instruction in TCG.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-16 13:19:20 +01:00
Aurelien Jarno 2411fde9a4 target-sh4: use rotl/rotr when possible
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-16 13:19:20 +01:00
Aurelien Jarno 0c16e71e6a target-sh4: correct use of ! and &
Fix wrong usage of ! and & in MMU related functions. Thanks to Blue
Swirl for reporting the issue.

Reported-by: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-15 13:50:38 +01:00
Aurelien Jarno c5c191370e target-sh4: use setcond when possible
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14 20:39:18 +01:00
Aurelien Jarno be15c50d8e target-sh4: log instructions start in TCG code
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14 20:39:18 +01:00
Aurelien Jarno 6f396c8f38 target-sh4: simplify comparisons after a 'and' op
When a TCG variable is anded with a value and the compared with the same
value, we can simply invert the comparison and compare it with 0. The
generated code is smaller.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14 20:39:18 +01:00
Aurelien Jarno 4f6493ff8a target-sh4: fix reset on r2d
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14 20:39:18 +01:00
Aurelien Jarno fd4bab102c target-sh4: optimize exceptions
As exception is not the normal path, don't bother saving PC, before
raising one, instead rely on code retranslation to get the CPU state.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14 20:39:18 +01:00
Aurelien Jarno 17075f10ff target-sh4: add ftrv instruction
Add the ftrv XMTRX,FVn instruction, which computes the 4-row x 4-column
matrix XMTRX by the 4-dimensional vector FVn.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14 20:39:18 +01:00
Aurelien Jarno af8c2bde4b target-sh4: add fipr instruction
Add the fipr FVm,FVn instruction, which computes the inner products of
a 4-dimensional single precision floating-point vector.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14 20:39:18 +01:00
Aurelien Jarno 21829e9b39 target-sh4: implement FPU exceptions
FPU exception support where not implemented on SH4. Implement them by
clearing the softfloat exceptions flags before an FP instruction (the
SH4 FPU also clear them before an instruction), and calling a function
to update the FPSCR register after an FP instruction. This function
update the corresponding FPSCR bits (both flags and cumulative flags)
and trigger exception if enabled.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14 20:39:18 +01:00
Aurelien Jarno a0d4ac333a target-sh4: implement flush-to-zero
When the FPSCR.DN bit is set, the SH4 FPU treat denormalized numbers as
zero. Enable the corresponding softfloat option when this bit is set.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14 20:39:18 +01:00
Aurelien Jarno 26ac1ea559 target-sh4: define FPSCR constants
Define FPSCR constants for all field and use them instead of hardcoded
values.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14 20:39:18 +01:00
Aurelien Jarno 442599a340 target-sh4: use default-NaN mode
SH4 FPU doesn't propagate NaN, and instead always regenerate new ones.
Enable the default-NaN mode by default.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14 20:39:17 +01:00
Aurelien Jarno 86865c5ff1 target-sh4: fix fpu disabled/illegal exception
Illegal instructions in a slot delay should generate a slot illegal
instruction exception instead of an illegal instruction exception.

The current PC should be saved before generating such an exception,
but should not be corrected if in a delay slot, given it's already
done in the exception handler do_interrupt().

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-11 17:25:24 +01:00
Aurelien Jarno 829a49274f target-sh4: improve TLB
SH4 is using 16-bit instructions which means most of the constants are
loaded through a constant pool at the end of the subroutine. The same
memory page is therefore accessed in exec and read mode.

With the current implementation, a QEMU TLB entry is set to read or
read/write mode after an UTLB search and to exec mode after an ITLB
search, which causes a lot of TLB exceptions to switch from read or
read/write to exec and vice versa.

This patch optimizes that by already setting the QEMU TLB entry in read
or read/write mode when an UTLB entry is copied into ITLB (during an
ITLB miss). This improve the emulation speed by about 14%.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-10 00:02:16 +01:00
Aurelien Jarno c0f809c46a target-sh4: implement writes to mmaped ITLB
Some Linux kernels seems to implement ITLB/UTLB flushing through by
writing all TLB entries through the memory mapped interface instead
of writing one to MMUCR.TI.

Implement memory mapped ITLB write interface so that such kernels can
boot. This fixes https://bugs.launchpad.net/bugs/700774 .

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-09 23:59:12 +01:00
Stefan Weil 9a78eead0c target-xxx: Use fprintf_function (format checking)
fprintf_function uses format checking with GCC_FMT_ATTR.

Format errors were fixed in
* target-i386/helper.c
* target-mips/translate.c
* target-ppc/translate.c

Cc: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-10-30 08:01:59 +00:00
Alexandre Courbot 935fc17559 target-sh4: Add support for ldc & stc with sgr
Add support for the following missing priviledged intructions:

For SH4:
- stc sgr, Rn
- stc.l sgr, @-Rn

For SH4A:
- ldc Rm, sgr
- ldc.l @Rm+, sgr

Signed-off-by: Alexandre Courbot <gnurou@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-07-12 10:20:31 +02:00
Alexandre Courbot 8e9b06787b target-sh4: Split the LDST macro into 2 sub-macros
The LDST macro is used to generate ldc and stc instructions that work with a
specific register. However, the SGR register only supports stc up to SH4A,
which supports both stc and ldc. This patch creates two sub-macros named LD
and ST that handle generating ldc and stc instructions separately, and
redeclares LDST to use these sub-macro.

Signed-off-by: Alexandre Courbot <gnurou@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-07-12 10:20:29 +02:00
Paolo Bonzini a88790a14f remove exec-all.h inclusion from cpu.h
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-07-03 09:48:24 +03:00
Paolo Bonzini 10eb0cc03c move cpu_pc_from_tb to target-*/exec.h
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-07-03 09:48:12 +03:00
Richard Henderson 6f0f607f96 target-sh4: Remove duplicate CPU log.
Logging for -d cpu is done in generic code.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-05 12:20:05 +02:00
Paolo Bonzini 1a7ff92218 remove TARGET_* defines from translate-all.c
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-08 21:34:12 +02:00
Blue Swirl 43dc2a645e Replace assert(0) with abort() or cpu_abort()
When building with -DNDEBUG, assert(0) will not stop execution
so it must not be used for abnormal termination.

Use cpu_abort() when in CPU context, abort() otherwise.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-03-18 18:41:57 +00:00
Paul Brook d4c430a80f Large page TLB flush
QEMU uses a fixed page size for the CPU TLB.  If the guest uses large
pages then we effectively split these into multiple smaller pages, and
populate the corresponding TLB entries on demand.

When the guest invalidates the TLB by virtual address we must invalidate
all entries covered by the large page.  However the address used to
invalidate the entry may not be present in the QEMU TLB, so we do not
know which regions to clear.

Implementing a full vaiable size TLB is hard and slow, so just keep a
simple address/mask pair to record which addresses may have been mapped by
large pages.  If the guest invalidates this region then flush the
whole TLB.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-03-17 02:44:41 +00:00
Paul Brook 3c7b48b74c Target specific usermode cleanup
Disable various target specific code that is only relevant to system emulation.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-03-12 18:44:24 +00:00
Paul Brook 4fcc562bff Remove cpu_get_phys_page_debug from userspace emulation
cpu_get_phys_page_debug makes no sense for userspace emulation, so remove it.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-03-12 18:34:25 +00:00
Richard Henderson 5270589032 Move TARGET_PHYS_ADDR_SPACE_BITS to target-*/cpu.h.
Removes a set of ifdefs from exec.c.

Introduce TARGET_VIRT_ADDR_SPACE_BITS for all targets other
than Alpha.  This will be used for page_find_alloc, which is
supposed to be using virtual addresses in the first place.

Signed-off-by: Richard Henderson <rth@twiddle.net>
2010-03-12 16:28:24 +00:00
Blue Swirl ee0dc6d393 Fix incorrect exception_index use
env->exception_index should be cleared with -1, not 0.

See also 821b19fe92.

Spotted by Igor Kovalenko.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-14 07:23:50 +00:00
Aurelien Jarno 5a25cc2b5c target-sh4: MMU: separate execute and read/write permissions
On SH4, the ITLB and UTLB configurations are memory mapped, so loading
ITLB entries from UTLB has to be simulated correctly. For that the QEMU
TLB has to be handle the execute (ITLB) and read/write permissions
(UTLB) seperately.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-09 21:08:06 +01:00
Aurelien Jarno 03e3b61e4f target-sh4: MMU: fix store queue addresses
The store queues are located from 0xe0000000 to 0xe3ffffff.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-09 21:08:05 +01:00
Aurelien Jarno 55ff33a435 target-sh4: MMU: remove dead code
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-09 21:08:05 +01:00
Aurelien Jarno af090497c6 target-sh4: MMU: reduce the size of a TLB entry
Reduce the size of the TLB entry from 32 to 16 bytes, reorganising
members and using a bit field.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-09 21:08:05 +01:00
Aurelien Jarno 628b61a072 target-sh4: MMU: optimize UTLB accesses
With the current code, the QEMU TLB is setup to match the read/write
mode of the MMU fault. This means when read access is done, the page
is setup in read-only mode. When the page is later accessed in write
mode, an MMU fault happened, and the page is switch in write-only
mode. This flip-flop causes a lot of calls to the MMU code and slow
down the emulation.

This patch changes the MMU emulation, so that the QEMU TLB is setup
to match the UTLB protection key. This impressively increase the
speed of the emulation.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-09 21:08:05 +01:00
Aurelien Jarno 4d1e4ff63c target-sh4: MMU: fix ITLB priviledge check
There is an ITLB access violation if SR_MD=0 (user mode) while
the high bit of the protection key is 0 (priviledge mode).

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-09 21:08:05 +01:00
Aurelien Jarno 0f3f1ec787 target-sh4: MMU: simplify call to tlb_set_page()
tlb_set_page() doesn't need addresses with offset, but simply the
page aligned addresses.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-09 21:08:05 +01:00
Aurelien Jarno 1f486815ae target-sh4: MMU: fix mem_idx computation
The mem_idx is wrongly computed. As written in target-sh4/cpu.h, mode 0
corresponds to kernel mode (SR_MD = 1), while mode 1 corresponds to user
mode (SR_MD = 0).

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-09 21:08:05 +01:00
Aurelien Jarno e0bcb9ca36 sh7750: handle MMUCR TI bit
When the MMUCR TI bit is set, all the UTLB and ITLB entries should be
flushed.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-09 21:07:03 +01:00
Aurelien Jarno 3101e99c21 target-sh4: minor optimisations
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-08 12:21:22 +01:00
Paolo Bonzini 49a945a3c0 kill regs_to_env and env_to_regs
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2010-01-19 16:31:02 -06:00
Anthony Liguori c227f0995e Revert "Get rid of _t suffix"
In the very least, a change like this requires discussion on the list.

The naming convention is goofy and it causes a massive merge problem.  Something
like this _must_ be presented on the list first so people can provide input
and cope with it.

This reverts commit 99a0949b72.

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-01 16:12:16 -05:00
malc 99a0949b72 Get rid of _t suffix
Some not so obvious bits, slirp and Xen were left alone for the time
being.

Signed-off-by: malc <av1474@comtv.ru>
2009-10-01 22:45:02 +04:00
Blue Swirl b9d38e9510 Fix Sparse warnings about using plain integer as NULL pointer
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-09-21 18:11:34 +00:00
Blue Swirl 72cf2d4f0e Fix sys-queue.h conflict for good
Problem: Our file sys-queue.h is a copy of the BSD file, but there are
some additions and it's not entirely compatible. Because of that, there have
been conflicts with system headers on BSD systems. Some hacks have been
introduced in the commits 15cc923584,
f40d753718,
96555a96d7 and
3990d09adf but the fixes were fragile.

Solution: Avoid the conflict entirely by renaming the functions and the
file. Revert the previous hacks.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-09-12 07:36:22 +00:00