Anup Patel 881df35d3d target/riscv: Implement SGEIP bit in hip and hie CSRs ... A hypervisor can optionally take guest external interrupts using SGEIP bit of hip and hie CSRs. Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <anup@brainfault.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Message-id: 20220204174700.534953-3-anup@brainfault.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2022-02-16 12:24:18 +10:00
..
insn_trans	target/riscv: Add XVentanaCondOps custom extension	2022-02-16 12:24:18 +10:00
arch_dump.c
bitmanip_helper.c	target/riscv: Add rev8 instruction, removing grev/grevi	2021-10-07 08:41:33 +10:00
cpu_bits.h	target/riscv: Implement SGEIP bit in hip and hie CSRs	2022-02-16 12:24:18 +10:00
cpu_helper.c	target/riscv: Split out the vill from vtype	2022-01-21 15:52:57 +10:00
cpu_user.h
cpu-param.h
cpu.c	target/riscv: Implement SGEIP bit in hip and hie CSRs	2022-02-16 12:24:18 +10:00
cpu.h	target/riscv: Add XVentanaCondOps custom extension	2022-02-16 12:24:18 +10:00
csr.c	target/riscv: Implement SGEIP bit in hip and hie CSRs	2022-02-16 12:24:18 +10:00
fpu_helper.c	target/riscv: add "set round to odd" rounding mode helper function	2021-12-20 14:53:31 +10:00
gdbstub.c	target/riscv: correct "code should not be reached" for x-rv128	2022-02-16 12:24:18 +10:00
helper.h	target/riscv: Don't save pc when exception return	2022-01-21 15:52:57 +10:00
insn16.decode	target/riscv: accessors to registers upper part and 128-bit load/store	2022-01-08 15:46:10 +10:00
insn32.decode	target/riscv: support for 128-bit M extension	2022-01-08 15:46:10 +10:00
instmap.h
internals.h	target/riscv: add "set round to odd" rounding mode helper function	2021-12-20 14:53:31 +10:00
Kconfig
kvm_riscv.h	target/riscv: Support setting external interrupt by KVM	2022-01-21 15:52:56 +10:00
kvm-stub.c	target/riscv: Support setting external interrupt by KVM	2022-01-21 15:52:56 +10:00
kvm.c	target/riscv: Implement virtual time adjusting with vm state changing	2022-01-21 15:52:56 +10:00
m128_helper.c	target/riscv: support for 128-bit M extension	2022-01-08 15:46:10 +10:00
machine.c	target/riscv: Split out the vill from vtype	2022-01-21 15:52:57 +10:00
meson.build	target/riscv: Add XVentanaCondOps custom extension	2022-02-16 12:24:18 +10:00
monitor.c	target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl	2021-10-22 07:47:51 +10:00
op_helper.c	target/riscv: Adjust csr write mask with XLEN	2022-01-21 15:52:57 +10:00
pmp.c	target/riscv: Adjust pmpcfg access with mxl	2022-01-21 15:52:57 +10:00
pmp.h
sbi_ecall_interface.h	target/riscv: Handle KVM_EXIT_RISCV_SBI exit	2022-01-21 15:52:56 +10:00
trace-events
trace.h
translate.c	target/riscv: Add XVentanaCondOps custom extension	2022-02-16 12:24:18 +10:00
vector_helper.c	target/riscv: Fix vill field write in vtype	2022-02-16 12:24:18 +10:00
XVentanaCondOps.decode	target/riscv: Add XVentanaCondOps custom extension	2022-02-16 12:24:18 +10:00