We got a report from the linux-arm-kernel folks about getting spurious
warnings when building the kernel with binutils 2.29. See
https://www.spinics.net/lists/arm-kernel/msg599929.html
which boils down to this testcase.
$> cat /tmp/tst.s
lr .req x30
/tmp/tst.s: Assembler messages:
/tmp/tst.s:1: Warning: ignoring attempt to redefine built-in register 'lr'
Instead let's treat this as a proper alias at startup time thus
avoiding the problem and treating these as proper aliases
rather than new registers. This means that attempts to redefine
the alias with the same "name" will provoke no warning and attempts
to redefine the alias to something else will provoke the above mentioned
warning.
Tested make check-gas and no regressions.
Ok to apply to trunk (and backport to 2.29 branch)?
Regards
Ramana
With IBM z14 officially announced I can add z14 as CPU name.
No regressions with that patch on s390x.
gas/ChangeLog:
2017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/tc-s390.c (s390_parse_cpu): Add z14 as alternate CPU
name.
* doc/as.texinfo: Add z14 to CPU string list.
* doc/c-s390.texi: Likewise.
opcodes/ChangeLog:
2017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* s390-mkopc.c (main): Enable z14 as CPU string in the opcode
table.
This patch adds support for the ARM Cortex-A55 and
Cortex-A75 processors.
The ARM Cortex-A55 and Cortex-A75 procsessors implement the ARMv8-A
architecture, with support for the ARMv8.1-A and ARMv8.2-A extensions,
including support for the 16-bit floating point extensions.
The 16-bit floating-point extensions are optional, and we haven't defined
an option mapping straight to them thus far, so this patch first needs to
add one of those in include/opcode/arm.h, then we can simply add the CPU names
as usual in config/tc-arm.c .
Tested on arm-none-eabi.
2017-07-05 James Greenhalgh <james.greenhalgh@arm.com>
* config/tc-arm.c (arm_cpus): Add Cortex-A55 and Cortex-A75.
* doc/c-arm.texi (-mcpu): Document Cortex-A55 and Cortex-A75.
PR gas/21683
include * opcode/avr.h (AVR_INSN): Add one for __gcc_isr.
gas * doc/c-avr.texi (AVR Options) <-mgcc-isr>: Document it.
(AVR Pseudo Instructions): New node.
* config/tc-avr.h (md_pre_output_hook): Define to avr_pre_output_hook.
(md_undefined_symbol): Define to avr_undefined_symbol.
(avr_pre_output_hook, avr_undefined_symbol): New protos.
* config/tc-avr.c (struc-symbol.h): Include it.
(ISR_CHUNK_Done, ISR_CHUNK_Prologue, ISR_CHUNK_Epilogue): New enums.
(avr_isr, avr_gccisr_opcode)
(avr_no_sreg_hash, avr_no_sreg): New static variables.
(avr_opt_s) <have_gccisr>: Add field.
(avr_opt): Add initializer for have_gccisr.
(enum options) <OPTION_HAVE_GCCISR>: Add enum.
(md_longopts) <"mgcc-isr">: Add entry.
(md_show_usage): Document -mgcc-isr.
(md_parse_option) [OPTION_HAVE_GCCISR]: Handle it.
(md_undefined_symbol): Remove.
(avr_undefined_symbol, avr_pre_output_hook): New fuctions.
(md_begin) <avr_no_sreg_hash, avr_gccisr_opcode>: Initialize them.
(avr_operand) <pregno>: Add argument and set *pregno if function
is called for a register constraint.
[N]: Handle constraint.
(avr_operands) <avr_operand>: Pass 5th parameter to calls.
[avr_opt.have_gccisr]: Call avr_update_gccisr. Call
avr_gccisr_operands instead of avr_operands.
(avr_update_gccisr, avr_emit_insn, avr_patch_gccisr_frag)
(avr_gccisr_operands, avr_check_gccisr_done): New static functions.
* testsuite/gas/avr/gccisr-01.d: New test.
* testsuite/gas/avr/gccisr-01.s: New test.
* testsuite/gas/avr/gccisr-02.d: New test.
* testsuite/gas/avr/gccisr-02.s: New test.
* testsuite/gas/avr/gccisr-03.d: New test.
* testsuite/gas/avr/gccisr-03.s: New test.
This patch add assembler and disassembler support for new Dot Product
Extension.
The support can be enabled through the new "+dotprod" extension.
include/
* opcode/arm.h (FPU_NEON_EXT_DOTPROD): New macro.
(FPU_ARCH_DOTPROD_NEON_VFP_ARMV8): New macro.
gas/
* config/tc-arm.c (fpu_neon_ext_dotprod): New variable.
(neon_scalar_for_mul): Improve comments.
(do_neon_dotproduct): New function to encode Dot Product instructions.
(do_neon_dotproduct_s): Wrapper function for signed Dot Product
instructions.
(do_neon_dotproduct_u): Wrapper function for unsigned Dot Product
instructions.
(insns): New entries for vsdot and vudot.
(arm_extensions): New entry for "dotprod".
* doc/c-arm.texi: Document new "dotprod" extension.
* testsuite/gas/arm/dotprod.s: New test source.
* testsuite/gas/arm/dotprod-illegal.s: New test source.
* testsuite/gas/arm/dotprod.d: New test.
* testsuite/gas/arm/dotprod-thumb2.d: New test.
* testsuite/gas/arm/dotprod-illegal.d: New test.
* testsuite/gas/arm/dotprod-legacy-arch.d: New test.
* testsuite/gas/arm/dotprod-illegal.l: New error file.
* testsuite/gas/arm/dotprod-legacy-arch.l: New error file.
opcodes/
* arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
Add support for the Imagination interAptiv MR2 MIPS32r3 processor with
the MIPS16e2 ASE as per documentation, including in particular:
1. Support for implementation-specific interAptiv MR2 COPYW and UCOPYW
MIPS16e2 instructions[1], for assembly and disassembly,
2. Support for implementation-specific interAptiv MR2 SAVE and RESTORE
regular MIPS instructions[2], for assembly and disassembly,
3. ELF binary file annotation for the interAptiv MR2 MIPS architecture
extension.
4. Support for interAptiv MR2 architecture selection for assembly, in
the form of the `-march=interaptiv-mr2' command-line option and its
corresponding `arch=interaptiv-mr2' setting for the `.set' and
`.module' pseudo-ops.
5. Support for interAptiv MR2 architecture selection for disassembly,
in the form of the `mips:interaptiv-mr2' target architecture, for
use e.g. with the `-m' command-line option for `objdump'.
Parts of this change by Matthew Fortune and Andrew Bennett.
References:
[1] "MIPS32 interAptiv Multiprocessing System Software User's Manual",
Imagination Technologies Ltd., Document Number: MD00904, Revision
02.01, June 15, 2016, Section 24.3 "MIPS16e2 Implementation Specific
Instructions", pp. 878-883
[2] same, Chapter 25 "Implementation-specific Instructions", pp. 911-917
include/
* elf/mips.h (E_MIPS_MACH_IAMR2): New macro.
(AFL_EXT_INTERAPTIV_MR2): Likewise.
* opcode/mips.h: Document new operand codes defined.
(INSN_INTERAPTIV_MR2): New macro.
(INSN_CHIP_MASK): Adjust accordingly.
(CPU_INTERAPTIV_MR2): New macro.
(cpu_is_member) <CPU_INTERAPTIV_MR2>: New case.
(MIPS16_ALL_ARGS): Rename to...
(MIPS_SVRS_ALL_ARGS): ... this.
(MIPS16_ALL_STATICS): Rename to...
(MIPS_SVRS_ALL_STATICS): ... this.
bfd/
* archures.c (bfd_mach_mips_interaptiv_mr2): New macro.
* cpu-mips.c (I_interaptiv_mr2): New enum value.
(arch_info_struct): Add "mips:interaptiv-mr2" entry.
* elfxx-mips.c (_bfd_elf_mips_mach) <E_MIPS_MACH_IAMR2>: New
case.
(mips_set_isa_flags) <bfd_mach_mips_interaptiv_mr2>: Likewise.
(bfd_mips_isa_ext) <bfd_mach_mips_interaptiv_mr2>: Likewise.
(print_mips_isa_ext) <AFL_EXT_INTERAPTIV_MR2>: Likewise.
(mips_mach_extensions): Add `bfd_mach_mipsisa32r3' and
`bfd_mach_mips_interaptiv_mr2' entries.
* bfd-in2.h: Regenerate.
opcodes/
* mips-formats.h (INT_BIAS): New macro.
(INT_ADJ): Redefine in INT_BIAS terms.
* mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
(mips_print_save_restore): New function.
(print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
(validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
call.
(print_insn_args): Handle OP_SAVE_RESTORE_LIST.
(print_mips16_insn_arg): Call `mips_print_save_restore' for
OP_SAVE_RESTORE_LIST handling, factored out from here.
* mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
(RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
(mips_builtin_opcodes): Add "restore" and "save" entries.
* mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
(IAMR2): New macro.
(mips16_opcodes): Add "copyw" and "ucopyw" entries.
binutils/
* readelf.c (get_machine_flags) <E_MIPS_MACH_IAMR2>: New case.
(print_mips_isa_ext) <AFL_EXT_INTERAPTIV_MR2>: Likewise.
* NEWS: Mention Imagination interAptiv MR2 processor support.
gas/
* config/tc-mips.c (validate_mips_insn): Handle
OP_SAVE_RESTORE_LIST specially.
(mips_encode_save_restore, mips16_encode_save_restore): New
functions.
(match_save_restore_list_operand): Factor out SAVE/RESTORE
operand insertion into the instruction word or halfword to these
new functions.
(mips_cpu_info_table): Add "interaptiv-mr2" entry.
* doc/c-mips.texi (MIPS Options): Add `interaptiv-mr2' to the
`-march=' argument list.
=== Context ===
This patch is part of a patch series to add support for ARMv8-R
architecture. Its purpose is to add support for ARM Cortex-R52
processor.
=== Patch description ===
This patch adds support for Cortex-R52 as an ARMv8-R processor with CRC
extensions.
2017-06-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
gas/
* NEWS: Mention support of ARM Cortex-R52 processor.
* config/tc-arm.c (arm_cpus): Add entry for ARM Cortex-R52 processor.
* doc/c-arm.texi: Mention support for -mcpu=cortex-r52.
=== Context ===
This patch is part of a patch series to add support for ARMv8-R
architecture. Its purpose is to add support for ARMv8-R in GAS:
instructions, build attributes and readelf.
=== Patch description ===
Although some differences exist for system registers, from GAS point of
view ARMv8-R supports the same instructions as ARMv8-A Aarch32 state
and a subset of its extensions. This patch therefore introduce a new
feature bit to distinguish the availability of the pan, ras and rdma
extensions between ARMv8-A and ARMv8-R and allow crypto, fp and simd
extensions to be used by ARMv8-R.
Most of the changes are then in the testsuite to (i) rename source files
and error output to be shared between ARMv8-A and ARMv8-R, (ii) rename
files with expected output for ARMv8-A build attributes and (iii) add
new files with expected output for ARMv8-R build attributes.
2017-06-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
binutils/
* readelf.c (arm_attr_tag_CPU_arch): Fill value for ARMv8-R.
gas/
* NEWS: Mention support for ARMv8-R architecture.
* config/tc-arm.c (arm_archs): Add entry for ARMv8-R.
(arm_extensions): Restrict pan, ras and rdma extension to
ARMv8-A and make crypto, fp and simd extensions available to
ARMv8-R.
(cpu_arch_ver): Add entry for ARMv8-R.
(aeabi_set_public_attributes): Update gas_assert for Tag_DIV_use
logic.
* testsuite/gas/arm/armv8-a+fp.s: Rename into ...
* testsuite/gas/arm/armv8-ar+fp.s: This. Remove .arch directive.
* testsuite/gas/arm/armv8-a+fp.d: Specify source to assemble and
architecture to assemble for.
* testsuite/gas/arm/armv8-r+fp.d: New.
* testsuite/gas/arm/armv8-a+simd.s: Rename into ...
* testsuite/gas/arm/armv8-ar+simd.s: This. Remove .arch directive.
* testsuite/gas/arm/armv8-a+simd.d: Specify source to assemble and
architecture to assemble for.
* testsuite/gas/arm/armv8-r+simd.d: New.
* testsuite/gas/arm/armv8-a-bad.s: Rename into ...
* testsuite/gas/arm/armv8-ar-bad.s: This. Remove .arch directive.
* testsuite/gas/arm/armv8-a-bad.l: Rename into ...
* testsuite/gas/arm/armv8-ar-bad.l: This. Decrement line number by 1.
* testsuite/gas/arm/armv8-a-bad.d: Specify source to assemble,
architecture to assemble for and adjust error output file.
* testsuite/gas/arm/armv8-r-bad.d: New.
* testsuite/gas/arm/armv8-a-barrier.s: Rename into ...
* testsuite/gas/arm/armv8-ar-barrier.s: This.
* testsuite/gas/arm/armv8-a-barrier-arm.d: Adjust source.
* testsuite/gas/arm/armv8-a-barrier-thumb.d: Likewise.
* testsuite/gas/arm/armv8-r-barrier-arm.d: New.
* testsuite/gas/arm/armv8-r-barrier-thumb.d: New.
* testsuite/gas/arm/armv8-a-it-bad.s: Rename into ...
* testsuite/gas/arm/armv8-ar-it-bad.s: This. Remove .arch directive.
* testsuite/gas/arm/armv8-a-it-bad.l: Rename into ...
* testsuite/gas/arm/armv8-ar-it-bad.l: This. Decrement line number
by 1.
* testsuite/gas/arm/armv8-a-it-bad.d: Specify source to assemble,
architecture to assemble for and adjust error output file.
* testsuite/gas/arm/armv8-r-it-bad.d: New.
* testsuite/gas/arm/armv8-a.s: Rename into ...
* testsuite/gas/arm/armv8-ar.s: This. Remove .arch directive.
* testsuite/gas/arm/armv8-a.d: Specify source to assemble and
architecture to assemble for.
* testsuite/gas/arm/armv8-r.d: New.
* testsuite/gas/arm/attr-march-armv8-r+crypto.d: New.
* testsuite/gas/arm/attr-march-armv8-r+fp.d: New.
* testsuite/gas/arm/attr-march-armv8-r+simd.d: New.
* testsuite/gas/arm/attr-march-armv8-r.d: New.
* testsuite/gas/arm/crc32.s: Rename into ...
* testsuite/gas/arm/crc32-armv8-ar.s: This.
* testsuite/gas/arm/crc32.d: Rename into ...
* testsuite/gas/arm/crc32-armv8-a.d: This. Specify source to assemble.
* testsuite/gas/arm/crc32-armv8-r.d: New.
* testsuite/gas/arm/crc32-bad.s: Rename into ...
* testsuite/gas/arm/crc32-armv8-ar-bad.s: This.
* testsuite/gas/arm/crc32-bad.d: Rename into ...
* testsuite/gas/arm/crc32-armv8-a-bad.d: This. Specify source to
assemble.
* testsuite/gas/arm/crc32-armv8-r-bad.d: New.
* testsuite/gas/arm/mask_1.s: Rename into ...
* testsuite/gas/arm/mask_1-armv8-ar.s: This.
* testsuite/gas/arm/mask_1.d: Rename into ...
* testsuite/gas/arm/mask_1-armv8-a.d: This. Specify source to
assemble.
* testsuite/gas/arm/mask_1-armv8-r.d: new.
include/
* elf/arm.h (TAG_CPU_ARCH_V8R): New macro.
* opcode/arm.h (ARM_EXT2_V8A): New macro.
(ARM_AEXT2_V8A): Rename into ...
(ARM_AEXT2_V8AR): This.
(ARM_AEXT2_V8A): New macro.
(ARM_AEXT_V8R): New macro.
(ARM_AEXT2_V8R): New macro.
(ARM_ARCH_V8R): New macro.
Add MIPS16e2 ASE support as per the architecture specification[1],
including in particular:
1. A new ELF ASE flag to mark MIPS16e2 binaries.
2. MIPS16e2 instruction assembly support, including a relaxation update
to use LUI rather than an LI/SLL instruction pair for loading the
high part of 32-bit addresses.
3. MIPS16e2 instruction disassembly support, including updated rules for
extended forms of instructions that are now subdecoded and therefore
do not alias to the original MIPS16 ISA revision instructions even
for encodings that are not valid in the MIPS16e2 instruction set.
Add `-mmips16e2' and `-mno-mips16e2' GAS command-line options and their
corresponding `mips16e2' and `no-mips16e2' settings for the `.set' and
`.module' pseudo-ops. Control the availability of the MT ASE subset of
the MIPS16e2 instruction set with a combination of these controls and
the preexisting MT ASE controls.
Parts of this change by Matthew Fortune and Andrew Bennett.
References:
[1] "MIPS32 Architecture for Programmers: MIPS16e2 Application-Specific
Extension Technical Reference Manual", Imagination Technologies
Ltd., Document Number: MD01172, Revision 01.00, April 26, 2016
include/
* elf/mips.h (AFL_ASE_MIPS16E2): New macro.
(AFL_ASE_MASK): Adjust accordingly.
* opcode/mips.h: Document new operand codes defined.
(mips_operand_type): Add OP_REG28 enum value.
(INSN2_SHORT_ONLY): Update description.
(ASE_MIPS16E2, ASE_MIPS16E2_MT): New macros.
bfd/
* elfxx-mips.c (print_mips_ases): Handle MIPS16e2 ASE.
opcodes/
* mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
(mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
(print_insn_arg) <OP_REG28>: Add handler.
(validate_insn_args) <OP_REG28>: Handle.
(print_mips16_insn_arg): Handle MIPS16 instructions that require
32-bit encoding and 9-bit immediates.
(print_insn_mips16): Handle MIPS16 instructions that require
32-bit encoding and MFC0/MTC0 operand decoding.
* mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
<'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
(RD_C0, WR_C0, E2, E2MT): New macros.
(mips16_opcodes): Add entries for MIPS16e2 instructions:
GP-relative "addiu" and its "addu" spelling, "andi", "cache",
"di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
"lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
"movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
"pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
instructions, "swl", "swr", "sync" and its "sync_acquire",
"sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
"xori", "dmt", "dvpe", "emt" and "evpe". Add split
regular/extended entries for original MIPS16 ISA revision
instructions whose extended forms are subdecoded in the MIPS16e2
ISA revision: "li", "sll" and "srl".
binutils/
* readelf.c (print_mips_ases): Handle MIPS16e2 ASE.
* NEWS: Mention MIPS16e2 ASE support.
gas/
* config/tc-mips.c (RELAX_MIPS16_ENCODE): Add `e2' flag.
(RELAX_MIPS16_E2): New macro.
(RELAX_MIPS16_PIC, RELAX_MIPS16_SYM32, RELAX_MIPS16_NOMACRO)
(RELAX_MIPS16_USER_SMALL, RELAX_MIPS16_USER_EXT)
(RELAX_MIPS16_DSLOT, RELAX_MIPS16_JAL_DSLOT)
(RELAX_MIPS16_EXTENDED, RELAX_MIPS16_MARK_EXTENDED)
(RELAX_MIPS16_CLEAR_EXTENDED, RELAX_MIPS16_ALWAYS_EXTENDED)
(RELAX_MIPS16_MARK_ALWAYS_EXTENDED)
(RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED, RELAX_MIPS16_MACRO)
(RELAX_MIPS16_MARK_MACRO, RELAX_MIPS16_CLEAR_MACRO): Shift bits.
(mips16_immed_extend): New prototype.
(options): Add OPTION_MIPS16E2 and OPTION_NO_MIPS16E2 enum
values.
(md_longopts): Add "mmips16e2" and "mno-mips16e2" options.
(mips_ases): Add "mips16e2" entry.
(mips_set_ase): Handle MIPS16e2 ASE.
(insn_insert_operand): Explicitly handle immediates with MIPS16
instructions that require 32-bit encoding.
(is_opcode_valid_16): Pass enabled ASE bitmask on to
`opcode_is_member'.
(validate_mips_insn): Explicitly handle immediates with MIPS16
instructions that require 32-bit encoding.
(operand_reg_mask) <OP_REG28>: Add handler.
(match_reg28_operand): New function.
(match_operand) <OP_REG28>: Add handler.
(append_insn): Pass ASE_MIPS16E2 setting to RELAX_MIPS16_ENCODE.
(match_mips16_insn): Handle MIPS16 instructions that require
32-bit encoding and `V' and `u' operand codes.
(mips16_ip): Allow any characters except from `.' in opcodes.
(mips16_immed_extend): Handle 9-bit immediates. Do not shuffle
immediates whose width is not one of these listed.
(md_estimate_size_before_relax): Handle MIPS16e2 relaxation.
(mips_relax_frag): Likewise.
(md_convert_frag): Likewise.
(mips_convert_ase_flags): Handle MIPS16e2 ASE.
* doc/as.texinfo (Target MIPS options): Add `-mmips16e2' and
`-mno-mips16e2' options.
(-mmips16e2, -mno-mips16e2): New options.
* doc/c-mips.texi (MIPS Options): Add `-mmips16e2' and
`-mno-mips16e2' options.
(MIPS ASE Instruction Generation Overrides): Add `.set mips16e2'
and `.set nomips16e2'.
Complement commit 919731affb ("Add MIPS .module directive") and update
the GAS manual to refer to the `.module' rather than `.set' directive in
command-line option descriptions, following an observation that unlike
`.set' and like the respective command-line option the use of the
`.module' directive affects the ISA and ASE flags recorded in the object
file produced, and therefore it is `.module' rather than `.set' that
corresponds to the respective command-line option.
gas/
* doc/as.texinfo (-mips16, -no-mips16): Refer to `.module
mips16' rather than `.set mips16'.
(-mmicromips, -mno-micromips): Refer to `.module micromips' and
`.module nomicromips' rather than `.set micromips' and `.set
nomicromips'.
(-msmartmips, -mno-smartmips): Refer to `.module smartmips'
rather than `.set smartmips'.
* doc/c-mips.texi (MIPS Options): Refer to `.module mips16',
`.module micromips', `.module nomicromips' and `.module
smartmips' rather than `.set mips16', `.set micromips', `.set
nomicromips' and `.set smartmips' respectively.
Mark an ALLOC section, which should be placed in special memory area,
with SHF_GNU_MBIND. Its sh_info field indicates the special memory
type. GNU_MBIND section names start with ".mbind" so that they are
placed as orphan sections by linker. All input GNU_MBIND sections
with the same sh_type, sh_flags and sh_info are placed in one output
GNU_MBIND section. In executable and shared object, create a
GNU_MBIND segment for each GNU_MBIND section and its segment type is
PT_GNU_MBIND_LO plus the sh_info value. Each GNU_MBIND segment is
aligned at page boundary.
The assembler syntax:
.section .mbind.foo,"adx",%progbits
^ 0: Special memory type.
|
'd' for SHF_GNU_MBIND.
.section .mbind.foo,"adx",%progbits,0x1
^ 1: Special memory type.
|
'd' for SHF_GNU_MBIND.
.section .mbind.bar,"adG",%progbits,.foo_group,comdat,0x2
^ 2: Special memory type.
|
'd' for SHF_GNU_MBIND.
bfd/
* elf.c (get_program_header_size): Add a GNU_MBIND segment for
each GNU_MBIND section and align GNU_MBIND section to page size.
(_bfd_elf_map_sections_to_segments): Create a GNU_MBIND
segment for each GNU_MBIND section.
(_bfd_elf_init_private_section_data): Copy sh_info from input
for GNU_MBIND section.
binutils/
* NEWS: Mention support for ELF SHF_GNU_MBIND and
PT_GNU_MBIND_XXX.
* readelf.c (get_segment_type): Handle PT_GNU_MBIND_XXX.
(get_elf_section_flags): Handle SHF_GNU_MBIND.
(process_section_headers): Likewise.
* testsuite/binutils-all/mbind1.s: New file.
* testsuite/binutils-all/objcopy.exp: Run readelf test on
mbind1.s.
gas/
* NEWS: Mention support for ELF SHF_GNU_MBIND.
* config/obj-elf.c (section_match): New.
(get_section): Match both sh_info and group name.
(obj_elf_change_section): Add argument for sh_info. Pass both
sh_info and group name to get_section. Issue an error for
SHF_GNU_MBIND section without SHF_ALLOC. Set sh_info.
(obj_elf_parse_section_letters): Set SHF_GNU_MBIND for 'd'.
(obj_elf_section): Support SHF_GNU_MBIND section info.
* config/obj-elf.h (obj_elf_change_section): Add argument for
sh_info.
* config/tc-arm.c (start_unwind_section): Pass 0 as sh_info to
obj_elf_change_section.
* config/tc-ia64.c (obj_elf_vms_common): Likewise.
* config/tc-microblaze.c (microblaze_s_data): Likewise.
(microblaze_s_sdata): Likewise.
(microblaze_s_rdata): Likewise.
(microblaze_s_bss): Likewise.
* config/tc-mips.c (s_change_section): Likewise.
* config/tc-msp430.c (msp430_profiler): Likewise.
* config/tc-rx.c (parse_rx_section): Likewise.
* config/tc-tic6x.c (tic6x_start_unwind_section): Likewise.
* doc/as.texinfo: Document 'd' for SHF_GNU_MBIND.
* testsuite/gas/elf/elf.exp: Run section12a, section12b and
section13.
* testsuite/gas/elf/section10.d: Updated.
* testsuite/gas/elf/section10.s: Likewise.
* testsuite/gas/elf/section12.s: New file.
* testsuite/gas/elf/section12a.d: Likewise.
* testsuite/gas/elf/section12b.d: Likewise.
* testsuite/gas/elf/section13.l: Likewise.
* testsuite/gas/elf/section13.d: Likewise.
* testsuite/gas/elf/section13.s: Likewise.
include/
* elf/common.h (PT_GNU_MBIND_NUM): New.
(PT_GNU_MBIND_LO): Likewise.
(PT_GNU_MBIND_HI): Likewise.
(SHF_GNU_MBIND): Likewise.
ld/
* NEWS: Mention support for ELF SHF_GNU_MBIND and
PT_GNU_MBIND_XXX.
* emultempl/elf32.em (gld${EMULATION_NAME}_place_orphan): Place
input GNU_MBIND sections with the same type, attributes and
sh_info field into a single output GNU_MBIND section.
* testsuite/ld-elf/elf.exp: Run mbind2a and mbind2b.
* testsuite/ld-elf/mbind1.s: New file.
* testsuite/ld-elf/mbind1a.d: Likewise.
* testsuite/ld-elf/mbind1b.d: Likewise.
* testsuite/ld-elf/mbind1c.d: Likewise.
* testsuite/ld-elf/mbind2a.s: Likewise.
* testsuite/ld-elf/mbind2b.c: Likewise.
It looks like I missed the GAS help text when going through all the
documentation last time, so it printed some of the old-format (never
upstream) arguments. I fixed this, and when I went to check doc/ I
noticed it was missing the '-fpic'/'-fno-pic' options.
* doc/as.texinfo (2byte): Note that if no expressions are present
the directive does nothing. Emphasize that the output is
unaligned, and that this can have an effect on the relocations
generated.
(4byte): Simplify description. Refer back to the 2byte
description.
(8byte): Likewise.
Nick pointed out that I hadn't documented the new -mfpu option
neon-vfpv3 and mentioned that some others were missing.
Having looked through the list only one (neon-fp16) really should be
documented; the other two entries in the real table should not be
documented as they are aliases kept for legacy compatibility reasons.
This patch adds the missing entries and notes in the main table that
the other two entries should not be documented.
I've also fixed a small spelling error in the accompanying text.
* config/tc-arm.c (arm_fpus): Note entires that should not be
documented.
* doc/c-arm.texi (-mfpu): Add missing FPU entries for neon-vfpv3 and
neon-fp16. Fix spelling error.
Many x86 instructions have more than one encodings. Assembler picks
the default one, usually the shortest one. Although the ".s", ".d8"
and ".d32" suffixes can be used to swap register operands or specify
displacement size, they aren't very flexible. This patch adds pseudo
prefixes, {xxx}, to control instruction encoding. The available
pseudo prefixes are {disp8}, {disp32}, {load}, {store}, {vex2}, {vex3}
and {evex}. Pseudo prefixes are preferred over the ".s", ".d8" and
".d32" suffixes, which are deprecated.
gas/
* config/tc-i386.c (_i386_insn): Add dir_encoding and
vec_encoding. Remove swap_operand and need_vrex.
(extra_symbol_chars): Add '}'.
(md_begin): Mark '}' with LEX_BEGIN_NAME. Allow '}' in
mnemonic.
(build_vex_prefix): Don't use 2-byte VEX encoding with
{vex3}. Check dir_encoding and load.
(parse_insn): Check pseudo prefixes. Set dir_encoding.
(VEX_check_operands): Likewise.
(match_template): Check dir_encoding and load.
(parse_real_register): Set vec_encoding instead of need_vrex.
(parse_register): Likewise.
* doc/c-i386.texi: Document {disp8}, {disp32}, {load}, {store},
{vex2}, {vex3} and {evex}. Remove ".s", ".d8" and ".d32"
* testsuite/gas/i386/i386.exp: Run pseudos and x86-64-pseudos.
* testsuite/gas/i386/pseudos.d: New file.
* testsuite/gas/i386/pseudos.s: Likewise.
* testsuite/gas/i386/x86-64-pseudos.d: Likewise.
* testsuite/gas/i386/x86-64-pseudos.s: Likewise.
opcodes/
* i386-gen.c (opcode_modifiers): Replace S with Load.
* i386-opc.h (S): Removed.
(Load): New.
(i386_opcode_modifier): Replace s with load.
* i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
and {evex}. Replace S with Load.
* i386-tbl.h: Regenerated.
This patch supports some additions to the SVE architecture prior to
its public release.
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4x16)
(AARCH64_OPND_SVE_IMM_ROT1, AARCH64_OPND_SVE_IMM_ROT2)
(AARCH64_OPND_SVE_Zm3_INDEX, AARCH64_OPND_SVE_Zm3_22_INDEX)
(AARCH64_OPND_SVE_Zm4_INDEX): New aarch64_opnds.
opcodes/
* aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
(OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
(OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
(OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
(OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
(OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
(OP_SVE_V_HSD): New macros.
(OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
(OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
(OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
(aarch64_opcode_table): Add new SVE instructions.
(aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
for rotation operands. Add new SVE operands.
* aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
(ins_sve_quad_index): Likewise.
(ins_imm_rotate): Split into...
(ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
* aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
(aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
functions.
(aarch64_ins_sve_addr_ri_s4): New function.
(aarch64_ins_sve_quad_index): Likewise.
(do_misc_encoding): Handle "MOV Zn.Q, Qm".
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
(ext_sve_quad_index): Likewise.
(ext_imm_rotate): Split into...
(ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
* aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
(aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
functions.
(aarch64_ext_sve_addr_ri_s4): New function.
(aarch64_ext_sve_quad_index): Likewise.
(aarch64_ext_sve_index): Allow quad indices.
(do_misc_decoding): Likewise.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
aarch64_field_kinds.
(OPD_F_OD_MASK): Widen by one bit.
(OPD_F_NO_ZR): Bump accordingly.
(get_operand_field_width): New function.
* aarch64-opc.c (fields): Add new SVE fields.
(operand_general_constraint_met_p): Handle new SVE operands.
(aarch64_print_operand): Likewise.
* aarch64-opc-2.c: Regenerate.
gas/
* doc/c-aarch64.texi: Document that sve implies fp16, simd and compnum.
* config/tc-aarch64.c (parse_vector_type_for_operand): Allow .q
to be used with SVE registers.
(parse_operands): Handle new SVE operands.
(aarch64_features): Make "sve" require F16 rather than FP. Also
require COMPNUM.
* testsuite/gas/aarch64/sve.s: Add tests for new instructions.
Include compnum tests.
* testsuite/gas/aarch64/sve.d: Update accordingly.
* testsuite/gas/aarch64/sve-invalid.s: Add tests for new instructions.
* testsuite/gas/aarch64/sve-invalid.l: Update accordingly. Also
update expected output for new FMOV and MOV alternatives.
This patch adds a named "compnum" feature for the ARMv8.3-A FCADD
and FCMLA extensions.
include/
* opcode/aarch64.h (AARCH64_FEATURE_COMPNUM): New macro.
(AARCH64_ARCH_V8_3): Include AARCH64_FEATURE_COMPNUM.
opcodes/
* aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
(aarch64_feature_compnum): ...this.
(SIMD_V8_3): Replace with...
(COMPNUM): ...this.
(CNUM_INSN): New macro.
(aarch64_opcode_table): Use it for the complex number instructions.
gas/
* doc/c-aarch64.texi: Add a "compnum" entry.
* config/tc-aarch64.c (aarch64_features): Likewise,
* testsuite/gas/aarch64/advsimd-compnum.s: New test.
* testsuite/gas/aarch64/advsimd-compnum.d: Likewise.
This adds support of new instructions to the S/390 specific parts.
The important feature of the new instruction set is the support of
single and extended precision floating point vector operations.
Note: arch12 is NOT the official name of the new CPU. It just
continues the series of archXX options supported as alternate names.
The archXX terminology refers to the edition number of the Principle
of Operations manual. The official CPU name will be added later while
keeping support of the arch12 for backwards compatibility.
No testsuite regressions.
Committed to mainline.
Bye,
-Andreas-
opcodes/ChangeLog:
2017-02-23 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* s390-mkopc.c (main): Accept arch12 as cpu string and vx2 as
facility.
* s390-opc.c: Add new operand description macros, new instruction
types, instruction masks, and new .insn instruction types.
* s390-opc.txt: Add new arch12 instructions.
include/ChangeLog:
2017-02-23 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* opcode/s390.h (enum s390_opcode_cpu_val): New value
S390_OPCODE_ARCH12.
(S390_INSTR_FLAG_VX2): New macro definition.
gas/ChangeLog:
2017-02-23 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/tc-s390.c (s390_parse_cpu): New entry for arch12.
* doc/as.texinfo: Document arch12 as cpu type.
* doc/c-s390.texi: Likewise.
* testsuite/gas/s390/s390.exp: Run arch12 specific tests.
* testsuite/gas/s390/zarch-arch12.d: New test.
* testsuite/gas/s390/zarch-arch12.s: New test.
* testsuite/gas/s390/zarch-z13.d: Rename some mnemonics in the
output patterns.
The documentation entry for the SVE feature incorrectly said that
it was enabled by default for ARMv8-A or later. This patch fixes
that and also mentions that +sve implies +simd. (It also implies
+fp, but that follows by transitivity.)
gas/
* doc/c-aarch64.texi: Fix sve entry.
Include the detailed MIPS option description in the man page along with
other target descriptions and complementing the terse list earlier on.
gas/
* doc/as.texinfo (Overview): Select MIPS options for man page
inclusion.
Complement commit 9d862524f6 ("MIPS: Verify the ISA mode and alignment
of branch and jump targets") and add GAS and LD options to control the
checks for invalid branches between ISA modes introduced there, to help
with some handwritten code lacking `.insn' annotation for labels used as
branch targets and code produced by older versions of GCC which suffers
from the issue with branches to code that has been optimized away,
addressed with GCC commit 242424 ("MIPS/GCC: Mark trailing labels with
`.insn'"), <https://gcc.gnu.org/ml/gcc-patches/2016-11/msg01061.html>.
bfd/
* elfxx-mips.h (_bfd_mips_elf_insn32): Rename prototype to...
(_bfd_mips_elf_linker_flags): ... this. Add another parameter.
* elfxx-mips.c (mips_elf_link_hash_table): Add
`ignore_branch_isa' member.
(mips_elf_perform_relocation): Do not treat an ISA mode mismatch
in branch relocation calculation as an error if
`ignore_branch_isa' has been set.
(_bfd_mips_elf_insn32): Rename to...
(_bfd_mips_elf_linker_flags): ... this. Rename the `on'
parameter to `insn32' and add an `ignore_branch_isa' parameter.
Handle the new parameter.
gas/
* config/tc-mips.c (mips_ignore_branch_isa): New variable.
(options): Add OPTION_IGNORE_BRANCH_ISA and
OPTION_NO_IGNORE_BRANCH_ISA enum values.
(md_longopts): Add "mignore-branch-isa" and
"mno-ignore-branch-isa" options.
(md_parse_option): Handle OPTION_IGNORE_BRANCH_ISA and
OPTION_NO_IGNORE_BRANCH_ISA.
(fix_bad_cross_mode_branch_p): Return FALSE if
`mips_ignore_branch_isa' has been set.
(md_show_usage): Add `-mignore-branch-isa' and
`-mno-ignore-branch-isa'.
* doc/as.texinfo (Target MIPS options): Add
`-mignore-branch-isa' and `-mno-ignore-branch-isa' options.
(-mignore-branch-isa, -mno-ignore-branch-isa): New options.
* doc/c-mips.texi (MIPS Options): Add `-mignore-branch-isa' and
`-mno-ignore-branch-isa' options.
* testsuite/gas/mips/branch-local-ignore-2.d: New test.
* testsuite/gas/mips/branch-local-ignore-3.d: New test.
* testsuite/gas/mips/branch-local-ignore-n32-2.d: New test.
* testsuite/gas/mips/branch-local-ignore-n32-3.d: New test.
* testsuite/gas/mips/branch-local-ignore-n64-2.d: New test.
* testsuite/gas/mips/branch-local-ignore-n64-3.d: New test.
* testsuite/gas/mips/mips.exp: Run the new tests.
ld/
* emultempl/mipself.em (ignore_branch_isa): New variable.
(mips_create_output_section_statements): Rename
`_bfd_mips_elf_insn32' called to `_bfd_mips_elf_linker_flags',
add `ignore_branch_isa' argument.
(PARSE_AND_LIST_PROLOGUE): Add OPTION_IGNORE_BRANCH_ISA and
OPTION_NO_IGNORE_BRANCH_ISA enum values.
(PARSE_AND_LIST_LONGOPTS): Add "ignore-branch-isa" and
"no-ignore-branch-isa" options.
(PARSE_AND_LIST_OPTIONS): Add `--ignore-branch-isa' and
`--no-ignore-branch-isa'.
(PARSE_AND_LIST_ARGS_CASES): Handle OPTION_IGNORE_BRANCH_ISA and
OPTION_NO_IGNORE_BRANCH_ISA.
* ld.texinfo (Options specific to MIPS targets): Add
`--ignore-branch-isa' and `--no-ignore-branch-isa' options.
(ld and the MIPS family): Likewise.
* testsuite/ld-mips-elf/bal-jalx-pic-ignore.d: New test.
* testsuite/ld-mips-elf/bal-jalx-pic-ignore-n32.d: New test.
* testsuite/ld-mips-elf/bal-jalx-pic-ignore-n64.d: New test.
* testsuite/ld-mips-elf/unaligned-branch-ignore-2.d: New test.
* testsuite/ld-mips-elf/unaligned-branch-ignore-r6-1: New test.
* testsuite/ld-mips-elf/unaligned-branch-ignore-mips16: New
test.
* testsuite/ld-mips-elf/unaligned-branch-ignore-micromips: New
test.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
gas/
* doc/c-lm32.texi: Fix chars with high bit set.
* testsuite/gas/bfin/vector2.s: Likewise.
gold/
* arm.cc: Fix comment chars with high bit set.
include/
* coff/pe.h: Fix comment chars with high bit set.
* opcode/xgate.h: Likewise.
ld/
* testsuite/ld-scripts/sysroot-prefix.exp: Fix chars with high bit set.
We've decided to standardize on two flags for RISC-V: "-march" sets the
target architecture (which determines which instructions can be
generated), and "-mabi" sets the target ABI. We needed to rework this
because the old flag set didn't support soft-float or single-float ABIs,
and didn't support an x32-style ABI on RISC-V.
Additionally, we've changed the behavior of the -march flag: it's now a
lot stricter and only parses things we can actually understand.
Additionally, it's now lowercase-only: the rationale is that while the
RISC-V ISA manual specifies that ISA strings are case-insensitive, in
Linux-land things are usually case-sensitive. Since this flag can be
used to determine library paths, we didn't want to bake some
case-insensitivity in there that would case trouble later.
This patch implements these two new flags and removes the old flags that
could conflict with these. There wasn't a RISC-V release before, so we
want to just support a clean flag set.
include/
* elf/riscv.h (EF_RISCV_SOFT_FLOAT): Don't define.
(EF_RISCV_FLOAT_ABI, EF_RISCV_FLOAT_ABI_SOFT): Define.
(EF_RISCV_FLOAT_ABI_SINGLE, EF_RISCV_FLOAT_ABI_DOUBLE): Define.
(EF_RISCV_FLOAT_ABI_QUAD): Define.
bfd/
* elfnn-riscv.c (_bfd_riscv_elf_merge_private_bfd_data): Use
EF_RISCV_FLOAT_ABI_SOFT instead of EF_RISCV_SOFT_FLOAT.
binutils/
* readelf.c (get_machine_flags): Use
EF_RISCV_FLOAT_ABI_{SOFT,SINGLE,DOBULE,QUAD) instead of
EF_RISCV_{SOFT,HARD}_FLOAT.
gas/
* config/tc-riscv.h (xlen): Delete.
* config/tc-riscv.c (xlen): Make static.
(abi_xlen): New variable.
(options): Replace OPTION_{M32,M64,MSOFT_FLOAT,MHARD_FLOAT,MRVC}
with OPTION_MABI.
(md_longopts): Likewise.
(md_parse_option): Likewise.
(riscv_elf_final_processing): Likewise.
* doc/as.texinfo (Target RISC-V options): Likewise.
* doc/c-riscv.texi (OPTIONS): Likewise.
* config/tc-riscv.c (float_mode): Removed.
(float_abi): New type, specifies the floating-point ABI.
(riscv_set_abi): New function.
(riscv_add_subset): Only allow lower-case ISA names and require
them to start with "rv".
(riscv_after_parse_args): Likewise.
opcodes/
* riscv-dis.c (riscv_disassemble_insn): Default to the ELF's
XLEN when none is provided.
ARMv8.3 is an architectural extension of ARMv8. Add the
feature macro and -march=armv8.3-a gas command line option
for the ARM target.
https://community.arm.com/groups/processors/blog/2016/10/27/armv8-a-architecture-2016-additions
gas/
* config/tc-arm.c (arm_archs): Add "armv8.3-a".
* doc/c-arm.texi (-march): Add "armv8.3-a".
include/
* opcode/arm.h (ARM_EXT2_V8_3A, ARM_AEXT2_V8_3A): New.
(ARM_ARCH_V8_3A): New.
ARMv8.3 can be selected with -march=armv8.3-a command line option.
An overview of the ARMv8.3 architecture extension is at
https://community.arm.com/groups/processors/blog/2016/10/27/armv8-a-architecture-2016-additions
gas/
2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
* config/tc-aarch64.c (aarch64_archs): Add "armv8.3-a".
* doc/c-aarch64.texi (-march): Likewise.
include/
2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_V8_3): Define.
(AARCH64_ARCH_V8_3): Define.
(AARCH64_ARCH_V8_1, AARCH64_ARCH_V8_2): Simplify.
2016-11-04 Thomas Preud'homme <thomas.preudhomme@arm.com>
gas/
* config/tc-arm.c (cortex-m33): Declare new processor.
* doc/c-arm.texi (-mcpu ARM command line option): Document new
Cortex-M33 processor.
* NEWS: Mention ARM Cortex-M33 support.
2016-11-04 Thomas Preud'homme <thomas.preudhomme@arm.com>
gas/
* config/tc-arm.c (cortex-m23): Declare new processor.
* doc/c-arm.texi (-mcpu ARM command line option): Document new
Cortex-M23 processor.
* NEWS: Mention ARM Cortex-M23 support.
This adds an option for the Qualcomm falkor core, the corresponding
gcc patch is here:
https://gcc.gnu.org/ml/gcc-patches/2016-11/msg00262.html
This was tested with aarch64 and armhf builds and make check and also
by building and running SPEC2006.
* config/tc-aarch64.c (aarch64_cpus): Add falkor.
* config/tc-arm.c (arm_cpus): Likewise.
* doc/c-aarch64.texi: Likewise.
* doc/c-arm.texi: Likewise.
Alexander Fedotov
Ramana Radhakrishnan
Alexandre Oliva
Andreas Krebbel
Georg-Johann Lay
James Greenhalgh
Tamar Christina
Jiong Wang
Maciej W. Rozycki
Thomas Preud'homme
Jim Wilson
Jose E. Marchesi
Claudiu Zissulescu
H.J. Lu
Pip Cet
Palmer Dabbelt
Nick Clifton
Richard Earnshaw
Alan Modra
Szabolcs Nagy
Richard Sandiford
Igor Tsimbalist
Dimitar Dimitrov
Andrew Waterman
Siddhesh Poyarekar