Commit Graph

185 Commits

Author SHA1 Message Date
Mike Frysinger ab04c00066 sim: bfin: more parallel insn checks
Now that we keep track of the exact parallel insn slot we're in, we can
make sure that the current insn being decoded is valid for that slot.
This brings us much closer to the hardware in flagging invalid parallel
insn combinations.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-04-09 03:59:10 +00:00
Mike Frysinger 99265d6b00 sim: bfin: keep track of the exact position of parallel insns
Some insns need to know which slot they're in to determine whether they
are valid.  So add an enum for each slot, and check that rather than the
overall insn len.  This makes tracking things in the code much clearer.
However, this code is functionally the same, so a follow up patch will
leverage this more to properly flag invalid parallel insn combos.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-04-09 03:49:30 +00:00
Mike Frysinger a8a0e37c8b sim: bfin: drop excess space in negation insn
The amod1 helper includes a leading space so it can expand into the empty
string when need be, which means the caller need not add spacing itself.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-04-08 20:48:20 +00:00
Mike Frysinger 1d18e9892e sim: bfin: throw VEC_ILGAL_I with 32bit insn in group1/group2 slots
Parallel insns can only do one 32bit, then two 16bits.  So if we see
a 2nd 32bit insn after the first 32bit in a parallel insn, abort.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-04-01 04:31:46 +00:00
Mike Frysinger 2fa7a0570b sim: bfin: simplify field width processing and fix build warnings
This fix the build time warning:
warning: format not a string literal, argument types not checked [-Wformat-nonliteral]

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-04-01 04:23:40 +00:00
Mike Frysinger 02bb38cc80 sim: bfin: fix unused bfrom handling for BF535
machs.c: In function 'bfin_model_cpu_init':
machs.c:1657:1: warning: 'bfrom' may be used uninitialized
	in this function [-Wuninitialized]

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-04-01 04:21:03 +00:00
Mike Frysinger e4967d72f9 sim: bfin: fix build warning/style with auxvt_size
Fix warning about mixing decls and code by moving auxvt_size decl
down to the scope where it is used.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-04-01 02:39:12 +00:00
Mike Frysinger 8d72c97073 sim: bfin: fix typo in BF54x SIC init
The current code triggers a warning:
dv-bfin_sic.c: In function 'bfin_sic_finish':
dv-bfin_sic.c:930:41: warning: operation on 'sic-><U78e8>.bf54x.iwr1'
	may be undefined [-Wsequence-point]

This points out the IWR2 register was not being setup because of a typo.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-03-31 18:48:20 +00:00
Mike Frysinger a4a66f7132 sim: bfin: include devices.h to fix build warnings
The place where these funcs get defined do not include the header that
declares their prototypes.  Add that to fix -Wmissing-prototypes:

devices.c:59:1: warning: no previous prototype for 'dv_bfin_mmr_invalid'
devices.c:66:1: warning: no previous prototype for 'dv_bfin_mmr_require'
devices.c:99:1: warning: no previous prototype for 'dv_bfin_mmr_check'
devices.c:159:14: warning: no previous prototype for 'dv_get_bus_num'

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-03-31 18:44:43 +00:00
Mike Frysinger 2232061b1c [PATCH] sim: make sure to include strsignal prototype
Before POSIX standardized strsignal(), old systems would hide the
prototype unless the normal extension defines were enabled.  So use
the AC_USE_SYSTEM_EXTENSIONS helper for that.

Then make sure we include string.h ourselves in nrun.c rather than
relying on implicit includes via other sim headers.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-03-24 05:38:43 +00:00
Mike Frysinger e62bb22a4b sim: bfin: fix corner case Logical shift issues
From: Robin Getz <robin.getz@analog.com>

Overflow with shift operations happens independently of saturation, but
we have the logic merged.  Extend the lshift function so that callers
can tell it when to handle each independently, and then do so when it's
needed.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-03-19 05:06:23 +00:00
Mike Frysinger 8dbfaed8e2 sim: bfin: ebiu_amc: push down hardcoded base addresses
To make it easier to support ebiu banks at other addresses, move the base to
a runtime parameter rather than structure.  Future work will make this more
dynamic, but I'm waiting for more details first.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-03-19 03:09:20 +00:00
Mike Frysinger 410bbc9498 sim: bfin: use ARRAY_SIZE
Rather than hardcode the constant, use ARRAY_SIZE to get it.  Should be no
functional changes here.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-03-19 01:16:25 +00:00
Mike Frysinger 84de2f06d8 sim: bfin: drop old linux/mii.h workarounds
We had some workarounds for old linux/mii.h headers, but it breaks with
newer ones.  So tweak the checks a bit to work with newer ones.  We'll
worry about older systems once someone complains.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-03-04 19:56:57 +00:00
Joel Brobecker c5a5708100 Copyright year update in most files of the GDB Project.
gdb/ChangeLog:

        Copyright year update in most files of the GDB Project.
2012-01-04 08:28:28 +00:00
Mike Frysinger cc5add8c1c sim: bfin: lookup target strings when tracing system calls
Parsing target addresses is hard if not generally useless, so use the new
cb_get_string function to lookup the associated strings as well.  Now the
trace output is quickly useful instead of just marginally so.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-12-03 19:05:15 +00:00
Mike Frysinger db2e4d67e7 sim: generate build dependencies on the fly
Lift the code that GDB is using to generate dependencies on the fly and
port it over to the sim.  Now people shouldn't have to manually maintain
these in their Makefile's.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-12-03 18:23:51 +00:00
Mike Frysinger 4399a56be2 sim: dv-cfi: check for log2 support in libm when enabled
The dv-cfi model uses log2() internally, so make sure we automatically
link in libm when required.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-10-19 21:28:27 +00:00
Mike Frysinger 9c082ca86e sim: rename common/aclocal.m4 to common/acinclude.m4
Automake likes to dump macros automatically used into the aclocal.m4
file, but the common/aclocal.m4 naming prevents that.  So rename it
to the more normal "acinclude.m4" so the aclocal tool can work.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-10-18 00:31:00 +00:00
Mike Frysinger 6ffe910a7e sim: move from common.m4 to SIM_AC_COMMON
Now that the sourceware tree generally requires autoconf-2.64, update
the sim tree to require that too.

This allows us to drop the long standing SIM_AC_COMMON/common.m4
workaround as autoconf 2.64+ seems to work for me.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-10-18 00:17:24 +00:00
Mike Frysinger 39c1f96aef sim: bfin: use store buffer for VIT_MAX insns
The VIT_MAX insns can be used in parallel, so we need to use the store
buffer so we don't clobber the output register before we get a chance
to do a memory store with it.

Reported-by: Kai Iskratsch <kai@stella.at>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-09-29 03:19:47 +00:00
Mike Frysinger 2419798b80 sim: start a unified sim_do_command
Since sim_do_command for many people simply calls sim_args_command, start
a unified version of it.  For people who handle their own options, they
could switch to this by using sim_add_option_table instead.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-07-05 19:06:38 +00:00
Mike Frysinger a931db6a07 sim: bfin: implement stat_map for virtual environments (libgloss)
The stat syscalls cannot work without a stat map, so declare one that
matches libgloss for virtual environments.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-07-01 21:53:03 +00:00
Mike Frysinger ce2486ab20 sim: bfin: pass up result2/errcode with libgloss syscalls
Now that the Blackfin libgloss code extracts the 2nd result and the
error code from the R1/R2 registers, have the sim fill them up.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-22 04:21:29 +00:00
Mike Frysinger 1f20b1457b sim: bfin: set ASTAT AV/AVS when shifting accumulators overflow
The LSHIFT/ASHIFT insns that work with accumulators lacked AV/AVS
handling in the ASTAT register, so add it to match the hardware.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-18 22:03:10 +00:00
Mike Frysinger b4876e0485 sim: bfin: do not touch ASTAT[V] when shifting accumulators
If we're shifting accumulators, we don't want to touch the V bit in
ASTAT, so add size checks to the ashiftrt/lshiftrt helpers.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-18 21:59:38 +00:00
Mike Frysinger d5fcd950e4 sim: bfin: do not extend accumulator in LSHIFT insns
The logical shift insn does not sign extend before shifting, so
we shouldn't either.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-18 21:58:08 +00:00
Mike Frysinger a56a195412 sim: bfin: tweak saturation handling with TFU/FU modes and MM bit
This too should have been squashed into an earlier change.  It covers
a few more cases in the V/VS saturation patch when working with TFU
and FU modes of dsp insns.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-18 21:22:50 +00:00
Mike Frysinger 90e13d65c1 sim: bfin: handle large shift values with accumulator shift insns
When the shift magnitude exceeds 32 bits, the values rotate around (since
the hardware is actually a barrel shifter).  So handle this edge case,
update the corresponding AV bit in ASTAT which was missing previously,
and tweak the AZ setting based on how the hardware behaves.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-18 20:59:54 +00:00
Mike Frysinger 99dcc4dc65 sim: bfin: handle odd shift values with shift insns
The shift magnitude is a 5-bit signed value.  When it is between 0 and
15, then we do the requested shift, but when it is outside of that, we
have to do the opposite.

That means we flip between lshift and ashiftrt to match the hardware.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-18 20:59:24 +00:00
Mike Frysinger a0a71a7f8b sim: bfin: fix M_IH saturation size
This reverts the previous commit and does it right.  This change got
lost in the shuffle of patches I have pending.

Basically the logic is to change the 32bit saturation (and then masked
to 16bits) to a proper 16bit saturation.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-18 20:10:57 +00:00
Mike Frysinger 388aa9fe20 sim: bfin: handle V/VS saturation in dsp mac insns
Some saturation cases with dsp mac insns were not setting the V flag.
So implement that part and split up the logic between the dual macs.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-18 20:04:32 +00:00
Mike Frysinger f2a56d0ad7 sim: bfin: handle the MM flag in M_IU/M_TFU modes with dsp insns
Our handling of the M_IU/M_TFU modes are missing signed saturation when
the MM flag is set, so add it to match the hardware behavior.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-18 19:44:14 +00:00
Mike Frysinger ef26d60eba sim: bfin: fix sign extension in dsp insns with MM flag
After testing the hardware with all the different dsp flags, the MM flag
triggers sign extension in all modes.  So drop the limited use of it, and
the local custom helper that was also extending unsigned values.  We also
can see that the flag checks in the mult/mac insns have the same behavior
with sign extending, so add a helper func to keep the logic the same in
both places.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-18 19:42:55 +00:00
Mike Frysinger 075a845a92 sim: bfin: fix dsp insns IH saturation/rounding behavior
When using the IH modifier, we need to first saturate the value before
rounding it, and then further saturate it a bit more.  This makes the
sim match the hardware behavior with these insns.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-18 19:24:57 +00:00
Mike Frysinger b02cc5b9df sim: bfin: fix inverted changelog entry 2011-06-18 18:09:35 +00:00
Mike Frysinger 73aae8efb2 sim: bfin: fix accumulator edge case saturation
When the accumulator saturates, it needs to be greater than, but not
equal to, the largest unsigned value as this is what the hardware does.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-18 17:27:01 +00:00
Mike Frysinger 886ea33b69 sim: bfin: use freeargv for freeing argvs
Since the argv array was allocated with dupargv, it needs to be freed
with freeargv to avoid leaks.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-18 17:20:38 +00:00
Mike Frysinger eb3243445a sim: bfin: add support for glued SIC interrupt lines
The BF537 family glues a bunch of peripherals into single interrupt lines
that run into the SIC.  To model this same behavior in the sim, we need to
use the glue-or device, and in order to use that, we need to tweak things
a bit in the mach code to allow declaring of these new devices.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-04 17:18:04 +00:00
Mike Frysinger 082e1c4a87 sim: bfin: push SIC mappings to device tree
The machs.c file is the best place for holding cpu-specific details, so
restructure the way the SIC manages its ports to do just that.  Now the
SIC's have a standard set of input pins and the different line routing
from peripherals is kept in the device tree only.  This better models
the hardware where the SIC doesn't care about the exact peripheral that
is sending it stuff, just which input pin it gets it on.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-04 17:11:19 +00:00
Mike Frysinger 36f3e98103 sim: bfin: dma: fix indentation 2011-06-03 05:03:31 +00:00
Mike Frysinger ea1f7d4c8e sim: bfin: switch to new syscall trace level
Now that the common code supports the syscall trace level, change the
Blackfin code from using the event level to the syscall level.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-05-26 00:14:43 +00:00
Mike Frysinger f2db709f4f sim: bfin: move model data into machs.h
Pull the model data (register addresses/sizes) out of the different model
files and into the machs.h header.  The models themselves don't care about
where they're mapped, only the mach code does.  This allows us to keep the
model headers from being included in the mach code which can cause issues
with model-specific names colliding.  Such as when a newer device model is
created, but with incompatible register names/layouts.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-05-25 12:54:19 +00:00
Mike Frysinger c43aadcaa6 sim: bfin: add a performance monitor stub
No counters get updated, but there is enough here for software to
poke things and work.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-05-25 12:41:29 +00:00
Mike Frysinger dfb61fb66f sim: bfin: add bf526-0.2/bf54x-0.4 rom regions
Add regions for the on-chip roms on some newer Blackfin parts.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-05-25 12:35:05 +00:00
Mike Frysinger efac2223c4 sim: bfin: allow pushing of SP
The hardware respects this insn, and some code (like the on-chip bootrom)
uses it, so allow it.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-05-14 16:00:37 +00:00
Mike Frysinger 28fe96b798 sim: bfin: implement loop back support in the UARTs
The UART has a LOOP_ENA bit in its MCR register where writes to the THR
go to the RBR.  Implement support for this mode.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-05-14 15:59:09 +00:00
Mike Frysinger b44f3f638e sim: bfin: fix UART LSR read-only bit saturation
A few bits in the newer UART LSR register are not sticky, so make sure
we clear them when returning updated status rather than leaving them
always set.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-05-09 18:14:01 +00:00
Mike Frysinger 2613074f8f sim: bfin: constify dmac pmap arrays
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-27 21:29:03 +00:00
Mike Frysinger 054c055baf sim: gpio: add output support
Make all of the pins bidirectional, and support sending signals when
software drives the pins as outputs.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-26 05:47:14 +00:00
Mike Frysinger 5e0ba1a39e sim: gpio: update mask a/b signals better
When the mask a/b MMRs are written, the output signal might change levels
(as pins are [un]masked), so make sure we update the output level.

Further, make sure we handle edge ints correctly by first sending a high
signal followed by a low signal.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-26 05:46:02 +00:00
Mike Frysinger 0427acfba0 sim: bfin: use store buffer with more 32bit insns
A bunch of 32bit insns were not using the store buffer, so when they were
used in parallel insns, they would incorrectly clobber a register early.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-16 17:37:55 +00:00
Mike Frysinger d2cfa400a1 sim: bfin: handle implicit DISALGNEXCPT with video insns
When most video related insns are used in parallel with Ireg loads, the
DISALGNEXCPT insn behavior is implicitly in effect.

Reported-by: Anton Shokurov <shokurov.anton.v@yandex.ru>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-15 01:21:21 +00:00
Mike Frysinger e10d6db33d sim: bfin: respect the port level on signals to the SIC
The SIC latches ints from peripherals to the CEC, but the peripherals
need to be able to tell the SIC when to stop.  So use the incoming level
to figure out when to set the int bits and when to clear it.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-11 05:23:26 +00:00
Mike Frysinger 8aacdaf48d sim: bfin: add missing GPIO pin 15
Each GPIO block has 16 pins, and I only added 15 in the original
port list.  So add the missing 16th.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-11 05:22:23 +00:00
Mike Frysinger 2b12772f43 sim: bfin: add OTP output port
This doesn't currently generate any interrupts (as there doesn't appear
to be any documentation to *when* it would even do so), but since the
HRM does say an interrupt line exists between the OTP and the SIC, add
one for completeness sake.  This will make a follow up patch easier.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-01 22:32:04 +00:00
Mike Frysinger 6294f8ea1e sim: bfin: regen configure to include new cfi device 2011-03-29 18:39:51 +00:00
Mike Frysinger 1a3af0bfc3 sim: bfin: fix sign extension with 16bit acc add insns
The current implementation attempts to handle the 16bit sign extension
itself.  Unfortunately, it gets it right in some cases.  So rather than
fix that logic, just drop it in favor of using 16bit signed casts.  Now
gcc will take care of getting the logic right.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-29 01:41:49 +00:00
Mike Frysinger 36aef94270 sim: bfin: handle saturation with RND12 sub insns
The current handling of the subtraction insn with the RND12 modifier
works when saturation isn't involved.  So add handling for this edge
case to match the hardware.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-27 04:03:05 +00:00
Mike Frysinger fcd1ee07d3 sim: bfin: add missing VS set with add/sub insns
The 16bit add/sub insns missed setting the VS bit in ASTAT whenever the
V bit was also set.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-26 06:02:41 +00:00
Mike Frysinger a31d4fd99d sim: bfin: add hw tracing to gpio/sic port events
Makes it a lot easier to find out what's going on with interrupt lines
if the ports have tracing output.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-25 00:13:57 +00:00
Mike Frysinger b72cc8e145 sim: bfin: fix GPIO logic bugs when processing events
We need the DIR bit cleared, not set, in order for the pin to be treated
as an input.

When looking up the data value, we need to shift the "level" value over by
"my_port" rather than "bit" as the latter has already been shifted over.
We also should normalize the "level" coming in from the outside worlds to
the set of {0,1} since those are the only values that matter to GPIOs.

We need the BOTH bit set, not cleared, in order for the pin to trigger
on both edges.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-25 00:13:23 +00:00
Mike Frysinger eaf863cd1e sim: bfin: fix clear/set/toggle GPIO handling
The clear/set/toggle MMRs aren't backed by "real" data; they implicitly
perform bit operations on the associated data register.  So when we go
to process writes to them, we need to adjust the pointer accordingly so
that the actual backing data is modified.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-25 00:12:47 +00:00
Mike Frysinger b16a1f4c4f sim: bfin: document SIC limitation
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-24 03:18:17 +00:00
Mike Frysinger 9922f80319 sim: bfin: fix inverted W1C logic
When I originally wrote the w1c helper funcs, I used it in a few places.
Then I forgot how it worked and when I later documented it, I described
the 3rd arg in the exact opposite way it is actually used.  This error
propagated to a bunch of devices registers that were not explicitly
tested (a bunch of the devices are stubs which merely exist to say "no
device is connected" to make device drivers happy).

So once the documentation is unscrewed, fix all of the broken call sites.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-24 03:17:14 +00:00
Mike Frysinger 2d2bab5b21 sim: bfin: define more UART LSR bits
We'll need these bits in an upcoming patch, so map out the whole
LSR MMR now.

Fix up indentation style while we're here.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-24 03:16:50 +00:00
Mike Frysinger 972dbc8ade sim: bfin: fix typo in TWI stat reg
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-24 03:16:22 +00:00
Mike Frysinger 8e670c0a3f sim: bfin: update VIT_MAX behavior to match hardware when Acc.X bits are set
The Blackfin PRM says that the top 8 bits of the accumulator must be
cleared when using the VIT_MAX insn, so the sim has followed this spec.
Matching the hardware behavior though when the high bits are not cleared
is easy to do and doesn't break existing behavior, so go for it.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-24 03:14:20 +00:00
Mike Frysinger de0addfbef sim: bfin: always do 16bit sign extension with the SEARCH insn
The Blackfin PRM does not cover this case, but the hardware is clear: even
if the search criteria is not met (and thus a new 16bit value is loaded up
into the accumulator), the accumulator undergoes 16bit sign extension.  So
simply reload the low signed 16bits in that case.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-24 03:13:32 +00:00
Mike Frysinger beb378a5f2 sim: bfin: update AV and AC ASTAT bits with acc negation
The Acc=-Acc insn can overflow or carry with edge values, so make sure
we update the ASTAT bits accordingly to match the hardware.  Also fix
a thinko where we always updated AC0 even when working with A1 regs.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-24 03:12:16 +00:00
Mike Frysinger e4a861d14b sim: bfin: fix thinko in SIC pin encoding
When encoding the SIC/pin info into unique input port ids, I used bases
of 100 when I meant to use 0x100.  Rather than simply fix the decoding
math in the different functions, create a few helper macros to simplify
the SIC/pin encoding and decoding steps.  This makes the resulting tables
nice & clear.

And now that pins are clear, the 533 and 537 port_event handlers may
easily be merged into one.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-24 03:11:08 +00:00
Mike Frysinger 8d8a97461a sim: bfin: allow byteop[123]p src regs to be the same
The hardware allows the byteop[123]p insns to use the same src reg pair,
so remove the combination check in the sim.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-24 03:08:15 +00:00
Mike Frysinger a9c3ef4760 sim: bfin: fix thinko in bfin_gpio bus addresses
The bus addresses have to be valid numbers, so 'g' and 'h' won't work.
Oddly, the common code silently ignored this which is why I didn't notice
in the first place.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-24 03:07:33 +00:00
Mike Frysinger 9e6584c9a0 sim: bfin: check for kill/pread
If the host system (like Windows) doesn't support these functions,
then make sure we don't use them.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-17 19:03:30 +00:00
Mike Frysinger b5215db0ff sim: bfin: add GPIO device simulation
This takes care of the MMR interface and pushing up interrupts.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-15 21:01:45 +00:00
Mike Frysinger 81d126c3be sim: bfin: fix brace style 2011-03-15 20:55:11 +00:00
Mike Frysinger 990d19fd6d sim: bfin: fix brace style 2011-03-15 20:44:11 +00:00
Mike Frysinger 227d265839 sim: bfin: handle AZ updates with 16bit adds/subs
We weren't updating AZ when doing a 16bit add or sub insn.  Implement it.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-15 20:10:40 +00:00
Mike Frysinger e3809a37d4 sim: bfin: skip acc/ASTAT updates for moves
No point in moving unchanged acc values to the acc regs, and avoid
updating the acc ASTAT bits when only reading.  This fixes incorrect
changing of the ASTAT bits when they're only being read.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-15 20:10:12 +00:00
Mike Frysinger 86d3d8de68 sim: bfin: handle AN (negative overflows) in dsp mult insns
The current dsp mult handler does not take care of overflows which turn
values negative (and thus set AN in ASTAT).  So implement it.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-15 20:09:39 +00:00
Mike Frysinger 9b7509d900 sim: bfin: handle V overflows in dsp mult insns
The current dsp mult handler does not take care of overflows and updating
the V ASTAT bit.  So implement it.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-15 20:09:09 +00:00
Mike Frysinger bf416ccded sim: bfin: decode ASTAT on failure
When testing ASTAT regs, specific bit differences carry a lot more meaning
than when checking the value of a data register.  So automatically decode
the bits of the two values and print things out so that people don't have
to manually do it themselves every time.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-15 20:08:27 +00:00
Mike Frysinger c9329594d4 sim: bfin: handle saturation with fract multiplications
The saturation behavior with fract modes differs from non-fract modes.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-15 20:04:04 +00:00
Mike Frysinger f4e33aa6c5 sim: bfin: forgot to cvs add the changelog 2011-03-14 22:24:30 +00:00
Mike Frysinger ef016f835f sim: bfin: new port
This can boot Das U-Boot and a Linux kernel.  It also supports Linux
userspace FLAT and FDPIC (dynamic and static) ELFs.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-06 00:20:21 +00:00